gcc-2.5.8/ 40777 22011 13 0 5520736507 10705 5ustar kennerusergcc-2.5.8/config/ 40777 22011 13 0 5502603110 12131 5ustar kennerusergcc-2.5.8/config/README100666 22011 13 406 5322741130 13073 0ustar kenneruserThis directory contains machine-specific files for the GNU C compiler. It has a subdirectory for each basic CPU type. The only files in this directory itself are some .h files that pertain to particular operating systems and are used for more than one CPU type. gcc-2.5.8/config/a29k/ 40777 22011 13 0 5515224210 12703 5ustar kennerusergcc-2.5.8/config/a29k/a29k.c100444 22011 13 114255 5514641014 13760 0ustar kenneruser/* Subroutines used for code generation on AMD Am29000. Copyright (C) 1987, 88, 90, 91, 92, 1993 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@nyu.edu) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include "config.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "output.h" #include "insn-attr.h" #include "flags.h" #include "recog.h" #include "expr.h" #include "obstack.h" #include "tree.h" #include "reload.h" #define min(A,B) ((A) < (B) ? (A) : (B)) /* This gives the size in words of the register stack for the current procedure. */ static int a29k_regstack_size; /* This points to the last insn of the insn prologue. It is set when an insn without a filled delay slot is found near the start of the function. */ static char *a29k_last_prologue_insn; /* This points to the first insn that will be in the epilogue. It is null if no epilogue is required. */ static char *a29k_first_epilogue_insn; /* This is nonzero if a a29k_first_epilogue_insn was put in a delay slot. It indicates that an intermediate label needs to be written. */ static int a29k_first_epilogue_insn_used; /* Location to hold the name of the current function. We need this prolog to contain the tag words prior to the declaration. So the name must be stored away. */ char *a29k_function_name; /* Mapping of registers to debug register numbers. The only change is for the frame pointer and the register numbers used for the incoming arguments. */ int a29k_debug_reg_map[FIRST_PSEUDO_REGISTER]; /* Save information from a "cmpxx" operation until the branch or scc is emitted. */ rtx a29k_compare_op0, a29k_compare_op1; int a29k_compare_fp_p; /* Gives names for registers. */ extern char *reg_names[]; /* Returns 1 if OP is a 8-bit constant. */ int cint_8_operand (op, mode) register rtx op; enum machine_mode mode; { return GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffffff00) == 0; } /* Returns 1 if OP is a 16-bit constant. */ int cint_16_operand (op, mode) rtx op; enum machine_mode mode; { return GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0; } /* Returns 1 if OP is a constant that cannot be moved in a single insn. */ int long_const_operand (op, mode) register rtx op; enum machine_mode mode; { if (! CONSTANT_P (op)) return 0; if (TARGET_29050 && GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0) return 0; return (GET_CODE (op) != CONST_INT || ((INTVAL (op) & 0xffff0000) != 0 && (INTVAL (op) & 0xffff0000) != 0xffff0000 && INTVAL (op) != 0x80000000)); } /* The following four functions detect constants of 0, 8, 16, and 24 used as a position in ZERO_EXTRACT operations. They can either be the appropriate constant integer or a shift (which will be produced by combine). */ static int shift_constant_operand (op, mode, val) rtx op; enum machine_mode mode; int val; { return ((GET_CODE (op) == CONST_INT && INTVAL (op) == val) || (GET_CODE (op) == ASHIFT && GET_CODE (XEXP (op, 0)) == CONST_INT && INTVAL (XEXP (op, 0)) == val / 8 && GET_CODE (XEXP (op, 1)) == CONST_INT && INTVAL (XEXP (op, 1)) == 3)); } int const_0_operand (op, mode) rtx op; enum machine_mode mode; { return shift_constant_operand (op, mode, 0); } int const_8_operand (op, mode) rtx op; enum machine_mode mode; { return shift_constant_operand (op, mode, 8); } int const_16_operand (op, mode) rtx op; enum machine_mode mode; { return shift_constant_operand (op, mode, 16); } int const_24_operand (op, mode) rtx op; enum machine_mode mode; { return shift_constant_operand (op, mode, 24); } /* Returns 1 if OP is a floating-point constant of the proper mode. */ int float_const_operand (op, mode) rtx op; enum machine_mode mode; { return GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == mode; } /* Returns 1 if OP is a floating-point constant of the proper mode or a general-purpose register. */ int gpc_reg_or_float_constant_operand (op, mode) rtx op; enum machine_mode mode; { return float_const_operand (op, mode) || gpc_reg_operand (op, mode); } /* Returns 1 if OP is an integer constant of the proper mode or a general-purpose register. */ int gpc_reg_or_integer_constant_operand (op, mode) rtx op; enum machine_mode mode; { return ((GET_MODE (op) == VOIDmode && (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)) || gpc_reg_operand (op, mode)); } /* Returns 1 if OP is a special machine register. */ int spec_reg_operand (op, mode) rtx op; enum machine_mode mode; { if (GET_CODE (op) != REG || GET_MODE (op) != mode) return 0; switch (GET_MODE_CLASS (mode)) { case MODE_PARTIAL_INT: return REGNO (op) >= R_BP && REGNO (op) <= R_CR; case MODE_INT: return REGNO (op) >= R_Q && REGNO (op) <= R_EXO; detault: return 0; } } /* Returns 1 if OP is an accumulator register. */ int accum_reg_operand (op, mode) rtx op; enum machine_mode mode; { return (GET_CODE (op) == REG && REGNO (op) >= R_ACC (0) && REGNO (op) <= R_ACC (3)); } /* Returns 1 if OP is a normal data register. */ int gpc_reg_operand (op, mode) rtx op; enum machine_mode mode; { int regno; if (GET_MODE (op) != mode && mode != VOIDmode) return 0; if (GET_CODE (op) == REG) regno = REGNO (op); else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG) { regno = REGNO (SUBREG_REG (op)); if (regno < FIRST_PSEUDO_REGISTER) regno += SUBREG_WORD (op); } else return 0; return (regno >= FIRST_PSEUDO_REGISTER || regno < R_BP || (regno >= R_KR (0) && regno <= R_KR (31))); } /* Returns 1 if OP is either an 8-bit constant integer or a general register. If a register, it must be in the proper mode unless MODE is VOIDmode. */ int srcb_operand (op, mode) register rtx op; enum machine_mode mode; { if (GET_CODE (op) == CONST_INT && (mode == QImode || (INTVAL (op) & 0xffffff00) == 0)) return 1; if (GET_MODE (op) != mode && mode != VOIDmode) return 0; return gpc_reg_operand (op, mode); } /* Return 1 if OP is either an immediate or a general register. This is used for the input operand of mtsr/mtrsim. */ int gpc_reg_or_immediate_operand (op, mode) rtx op; enum machine_mode mode; { return gpc_reg_operand (op, mode) || immediate_operand (op, mode); } /* Return 1 if OP can be used as the second operand of and AND insn. This includes srcb_operand and a constant whose complement fits in 8 bits. */ int and_operand (op, mode) rtx op; enum machine_mode mode; { return (srcb_operand (op, mode) || (GET_CODE (op) == CONST_INT && ((unsigned) ((~ INTVAL (op)) & GET_MODE_MASK (mode)) < 256))); } /* Return 1 if OP can be used as the second operand of an ADD insn. This is the same as above, except we use negative, rather than complement. */ int add_operand (op, mode) rtx op; enum machine_mode mode; { return (srcb_operand (op, mode) || (GET_CODE (op) == CONST_INT && ((unsigned) ((- INTVAL (op)) & GET_MODE_MASK (mode)) < 256))); } /* Return 1 if OP is a valid address in a CALL_INSN. These are a SYMBOL_REF to the current function, all SYMBOL_REFs if TARGET_SMALL_MEMORY, or a sufficiently-small constant. */ int call_operand (op, mode) rtx op; enum machine_mode mode; { switch (GET_CODE (op)) { case SYMBOL_REF: return (TARGET_SMALL_MEMORY || (! TARGET_LARGE_MEMORY && ((GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_FLAG (op)) || ! strcmp (XSTR (op, 0), current_function_name)))); case CONST_INT: return (unsigned HOST_WIDE_INT) INTVAL (op) < 0x40000; default: return 0; } } /* Return 1 if OP can be used as the input operand for a move insn. */ int in_operand (op, mode) rtx op; enum machine_mode mode; { rtx orig_op = op; if (! general_operand (op, mode)) return 0; while (GET_CODE (op) == SUBREG) op = SUBREG_REG (op); switch (GET_CODE (op)) { case REG: return 1; case MEM: return (GET_MODE_SIZE (mode) >= UNITS_PER_WORD || TARGET_DW_ENABLE); case CONST_INT: if (GET_MODE_CLASS (mode) != MODE_INT && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) return 0; return 1; case CONST: case SYMBOL_REF: case LABEL_REF: return (GET_MODE (op) == mode || mode == SImode || mode == HImode || mode == QImode); case CONST_DOUBLE: return ((GET_MODE_CLASS (mode) == MODE_FLOAT && mode == GET_MODE (op)) || (GET_MODE (op) == VOIDmode && GET_MODE_CLASS (mode) == MODE_INT)); default: return 0; } } /* Return 1 if OP can be used as the output operand for a move insn. */ int out_operand (op, mode) rtx op; enum machine_mode mode; { rtx orig_op = op; if (! general_operand (op, mode)) return 0; while (GET_CODE (op) == SUBREG) op = SUBREG_REG (op); if (GET_CODE (op) == REG) return (gpc_reg_operand (orig_op, mode) || spec_reg_operand (orig_op, mode) || (GET_MODE_CLASS (mode) == MODE_FLOAT && accum_reg_operand (orig_op, mode))); else if (GET_CODE (op) == MEM) return (GET_MODE_SIZE (mode) >= UNITS_PER_WORD || TARGET_DW_ENABLE); else return 0; } /* Return 1 if OP is an item in memory, given that we are in reload. */ int reload_memory_operand (op, mode) rtx op; enum machine_mode mode; { int regno = true_regnum (op); return (! CONSTANT_P (op) && (regno == -1 || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER))); } /* Given an object for which reload_memory_operand is true, return the address of the operand, taking into account anything that reload may do. */ rtx a29k_get_reloaded_address (op) rtx op; { if (GET_CODE (op) == SUBREG) { if (SUBREG_WORD (op) != 0) abort (); op = SUBREG_REG (op); } if (GET_CODE (op) == REG) op = reg_equiv_mem[REGNO (op)]; return find_replacement (&XEXP (op, 0)); } /* Subfunction of the following function. Update the flags of any MEM found in part of X. */ static void a29k_set_memflags_1 (x, in_struct_p, volatile_p, unchanging_p) rtx x; int in_struct_p, volatile_p, unchanging_p; { int i; switch (GET_CODE (x)) { case SEQUENCE: case PARALLEL: for (i = XVECLEN (x, 0) - 1; i >= 0; i--) a29k_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, volatile_p, unchanging_p); break; case INSN: a29k_set_memflags_1 (PATTERN (x), in_struct_p, volatile_p, unchanging_p); break; case SET: a29k_set_memflags_1 (SET_DEST (x), in_struct_p, volatile_p, unchanging_p); a29k_set_memflags_1 (SET_SRC (x), in_struct_p, volatile_p, unchanging_p); break; case MEM: MEM_IN_STRUCT_P (x) = in_struct_p; MEM_VOLATILE_P (x) = volatile_p; RTX_UNCHANGING_P (x) = unchanging_p; break; } } /* Given INSN, which is either an INSN or a SEQUENCE generated to perform a memory operation, look for any MEMs in either a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and volatile flags from REF into each of the MEMs found. If REF is not a MEM, don't do anything. */ void a29k_set_memflags (insn, ref) rtx insn; rtx ref; { /* Note that it is always safe to get these flags, though they won't be what we think if REF is not a MEM. */ int in_struct_p = MEM_IN_STRUCT_P (ref); int volatile_p = MEM_VOLATILE_P (ref); int unchanging_p = RTX_UNCHANGING_P (ref); if (GET_CODE (ref) != MEM || (! in_struct_p && ! volatile_p && ! unchanging_p)) return; a29k_set_memflags_1 (insn, in_struct_p, volatile_p, unchanging_p); } /* Return 1 if OP is a comparison operator that we have in floating-point. */ int fp_comparison_operator (op, mode) rtx op; enum machine_mode mode; { return ((mode == VOIDmode || mode == GET_MODE (op)) && (GET_CODE (op) == EQ || GET_CODE (op) == GT || GET_CODE (op) == GE)); } /* Return 1 if OP is a valid branch comparison. */ int branch_operator (op, mode) rtx op; enum machine_mode mode; { return ((mode == VOIDmode || mode == GET_MODE (op)) && (GET_CODE (op) == GE || GET_CODE (op) == LT)); } /* Return 1 if OP is a load multiple operation. It is known to be a PARALLEL and the first three sections will be tested. */ int load_multiple_operation (op, mode) rtx op; enum machine_mode mode; { int count = XVECLEN (op, 0) - 2; int dest_regno; rtx src_addr; int i; /* Perform a quick check so we don't blow up below. */ if (count <= 1 || GET_CODE (XVECEXP (op, 0, 0)) != SET || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) return 0; dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); for (i = 1; i < count; i++) { rtx elt = XVECEXP (op, 0, i + 2); if (GET_CODE (elt) != SET || GET_CODE (SET_DEST (elt)) != REG || GET_MODE (SET_DEST (elt)) != SImode || REGNO (SET_DEST (elt)) != dest_regno + i || GET_CODE (SET_SRC (elt)) != MEM || GET_MODE (SET_SRC (elt)) != SImode || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) return 0; } return 1; } /* Similar, but tests for store multiple. */ int store_multiple_operation (op, mode) rtx op; enum machine_mode mode; { int num_special = TARGET_NO_STOREM_BUG ? 2 : 1; int count = XVECLEN (op, 0) - num_special; int src_regno; rtx dest_addr; int i; /* Perform a quick check so we don't blow up below. */ if (count <= 1 || GET_CODE (XVECEXP (op, 0, 0)) != SET || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) return 0; src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); for (i = 1; i < count; i++) { rtx elt = XVECEXP (op, 0, i + num_special); if (GET_CODE (elt) != SET || GET_CODE (SET_SRC (elt)) != REG || GET_MODE (SET_SRC (elt)) != SImode || REGNO (SET_SRC (elt)) != src_regno + i || GET_CODE (SET_DEST (elt)) != MEM || GET_MODE (SET_DEST (elt)) != SImode || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) return 0; } return 1; } /* Given a special register REG and MASK, a value being masked against a quantity to which the special register is set, return 1 if the masking operation is built-in to the setting of that special register. */ int masks_bits_for_special (reg, mask) rtx reg; rtx mask; { int needed_mask_value; if (GET_CODE (reg) != REG || GET_CODE (mask) != CONST_INT) abort (); switch (REGNO (reg)) { case R_BP: case R_INT: needed_mask_value = 3; break; case R_FC: needed_mask_value = 31; break; case R_CR: case R_LRU: needed_mask_value = 255; break; case R_FPE: needed_mask_value = 511; break; case R_MMU: needed_mask_value = 0x3ff; break; case R_OPS: case R_CPS: case R_RBP: case R_FPS: needed_mask_value = 0xffff; break; case R_VAB: needed_mask_value = 0xffff0000; break; case R_Q: case R_CFG: case R_CHA: case R_CHD: case R_CHC: case R_TMC: case R_TMR: case R_PC0: case R_PC1: case R_PC2: return 0; default: abort (); } return (INTVAL (mask) & ~ needed_mask_value) == 0; } /* Return nonzero if this label is that of the return point, but there is a non-null epilogue. */ int epilogue_operand (op, mode) rtx op; enum machine_mode mode; { return next_active_insn (op) == 0 && a29k_first_epilogue_insn != 0; } /* Return the register class of a scratch register needed to copy IN into or out of a register in CLASS in MODE. If it can be done directly, NO_REGS is returned. */ enum reg_class secondary_reload_class (class, mode, in) enum reg_class class; enum machine_mode mode; rtx in; { int regno = -1; enum rtx_code code = GET_CODE (in); if (! CONSTANT_P (in)) { regno = true_regnum (in); /* A pseudo is the same as memory. */ if (regno == -1 || regno >= FIRST_PSEUDO_REGISTER) code = MEM; } /* If we are transferring between memory and a multi-word mode, we need CR. */ if (code == MEM && GET_MODE_SIZE (mode) > UNITS_PER_WORD) return CR_REGS; /* If between memory and a mode smaller than a word without DW being enabled, we need BP. */ if (code == MEM && ! TARGET_DW_ENABLE && GET_MODE_SIZE (mode) < UNITS_PER_WORD) return BP_REGS; /* Otherwise, we can place anything into GENERAL_REGS and can put GENERAL_REGS into anything. */ if (class == GENERAL_REGS || (regno != -1 && (regno < R_BP || (regno >= R_KR (0) && regno <= R_KR (31))))) return NO_REGS; /* We can place 16-bit constants into a special register. */ if (code == CONST_INT && (GET_MODE_BITSIZE (mode) <= 16 || (unsigned) INTVAL (in) <= 65535) && (class == BP_REGS || class == Q_REGS || class == SPECIAL_REGS)) return NO_REGS; /* Otherwise, we need GENERAL_REGS. */ return GENERAL_REGS; } /* START is the zero-based incoming argument register index used (0 is 160, i.e., the first incoming argument register) and COUNT is the number used. Mark the corresponding incoming registers as neither fixed nor call used. For each register used for incoming arguments, we have one less local register that can be used. So also mark some high-numbered registers as fixed. Return the first register number to use for the argument. */ int incoming_reg (start, count) int start; int count; { int i; /* We only use 16 argument registers, so truncate at the end of the area. */ if (start + count > 16) count = 16 - start; if (! TARGET_NO_REUSE_ARGS) /* Mark all the used registers as not fixed and saved over calls. */ for (i = R_AR (start); i < R_AR (start + count); i++) { fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 0; CLEAR_HARD_REG_BIT (fixed_reg_set, i); CLEAR_HARD_REG_BIT (call_used_reg_set, i); CLEAR_HARD_REG_BIT (call_fixed_reg_set, i); } /* Shorten the maximum size of the frame. */ for (i = R_AR (0) - start - count; i < R_AR (0) - start; i++) { fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; SET_HARD_REG_BIT (fixed_reg_set, i); SET_HARD_REG_BIT (call_used_reg_set, i); SET_HARD_REG_BIT (call_fixed_reg_set, i); } return R_AR (start); } /* These routines are used in finding insns to fill delay slots in the epilogue. */ /* Return 1 if the current function will adjust the register stack. */ int needs_regstack_p () { int i; rtx insn; if (frame_pointer_needed) return 1; /* If any local register is used, we need to adjust the regstack. */ for (i = R_LR (127); i >= R_LR (0); i --) if (regs_ever_live[i]) return 1; /* We need a register stack if we make any calls. */ for (insn = get_insns (); insn; insn = next_insn (insn)) if (GET_CODE (insn) == CALL_INSN || (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == CALL_INSN)) return 1; /* Otherwise, we don't. */ return 0; } /* Return 1 if X uses a local register. */ int uses_local_reg_p (x) rtx x; { char *fmt; int i, j; switch (GET_CODE (x)) { case REG: return REGNO (x) >= R_LR (0) && REGNO (x) <= R_FP; case CONST_INT: case CONST: case PC: case CC0: case LABEL_REF: case SYMBOL_REF: return 0; } fmt = GET_RTX_FORMAT (GET_CODE (x)); for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) { if (fmt[i] == 'e') { if (uses_local_reg_p (XEXP (x, i))) return 1; } else if (fmt[i] == 'E') { for (j = XVECLEN (x, i) - 1; j >= 0; j--) if (uses_local_reg_p (XVECEXP (x, i, j))) return 1; } } return 0; } /* Returns 1 if this function is known to have a null epilogue. */ int null_epilogue () { return (reload_completed && ! needs_regstack_p () && get_frame_size () == 0 && current_function_pretend_args_size == 0); } /* Write out the assembler form of an operand. Recognize the following special options: %N means write the low-order 8 bits of the negative of the constant %Q means write a QImode operand (truncate constants to 8 bits) %M means write the low-order 16 bits of the constant %m means write the low-order 16 bits shifted left 16 bits %C means write the low-order 8 bits of the complement of the constant %b means write `f' is this is a reversed condition, `t' otherwise %B means write `t' is this is a reversed condition, `f' otherwise %J means write the 29k opcode part for a comparison operation %e means write the label with an extra `X' is this is the epilogue otherwise the normal label name %E means write nothing if this insn has a delay slot, a nop unless this is the epilogue label, in which case write the first epilogue insn %F means write just the normal operand if the insn has a delay slot; otherwise, this is a recursive call so output the symbol + 4 and write the first prologue insn in the delay slot. %L means write the register number plus one ("low order" register) or the low-order part of a multi-word constant %O means write the register number plus two %P means write the register number plus three ("low order" of TImode) %S means write the number of words in the mode of the operand, minus one (for CR) %V means write the number of elements in a PARALLEL minus 1 %# means write nothing if we have a delay slot, "\n\tnop" otherwise %* means write the register name for TPC. */ void print_operand (file, x, code) FILE *file; rtx x; char code; { char buf[100]; /* These macros test for integers and extract the low-order bits. */ #define INT_P(X) \ ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ && GET_MODE (X) == VOIDmode) #define INT_LOWPART(X) \ (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) switch (code) { case 'Q': if (GET_CODE (x) == REG) break; else if (! INT_P (x)) output_operand_lossage ("invalid %%Q value"); fprintf (file, "%d", INT_LOWPART (x) & 0xff); return; case 'C': if (! INT_P (x)) output_operand_lossage ("invalid %%C value"); fprintf (file, "%d", (~ INT_LOWPART (x)) & 0xff); return; case 'N': if (! INT_P (x)) output_operand_lossage ("invalid %%N value"); fprintf (file, "%d", (- INT_LOWPART (x)) & 0xff); return; case 'M': if (! INT_P (x)) output_operand_lossage ("invalid %%M value"); fprintf (file, "%d", INT_LOWPART (x) & 0xffff); return; case 'm': if (! INT_P (x)) output_operand_lossage ("invalid %%m value"); fprintf (file, "%d", (INT_LOWPART (x) & 0xffff) << 16); return; case 'b': if (GET_CODE (x) == GE) fprintf (file, "f"); else fprintf (file, "t"); return; case 'B': if (GET_CODE (x) == GE) fprintf (file, "t"); else fprintf (file, "f"); return; case 'J': /* It so happens that the RTX names for the conditions are the same as the 29k's insns except for "ne", which requires "neq". */ fprintf (file, GET_RTX_NAME (GET_CODE (x))); if (GET_CODE (x) == NE) fprintf (file, "q"); return; case 'e': if (optimize && flag_delayed_branch && a29k_last_prologue_insn == 0 && epilogue_operand (x, VOIDmode) && dbr_sequence_length () == 0) { /* We need to output the label number of the last label in the function, which is not necessarily X since there might be a USE insn in between. First go forward to the last insn, then back up to a label. */ while (NEXT_INSN (x) != 0) x = NEXT_INSN (x); while (GET_CODE (x) != CODE_LABEL) x = PREV_INSN (x); ASM_GENERATE_INTERNAL_LABEL (buf, "LX", CODE_LABEL_NUMBER (x)); assemble_name (file, buf); } else output_asm_label (x); return; case 'E': if (dbr_sequence_length ()) ; else if (a29k_last_prologue_insn) { fprintf (file, "\n\t%s", a29k_last_prologue_insn); a29k_last_prologue_insn = 0; } else if (optimize && flag_delayed_branch && epilogue_operand (x, VOIDmode)) { fprintf (file, "\n\t%s", a29k_first_epilogue_insn); a29k_first_epilogue_insn_used = 1; } else fprintf (file, "\n\tnop"); return; case 'F': output_addr_const (file, x); if (dbr_sequence_length () == 0) { /* If this doesn't have its delay slot filled, see if we need to put the last insn of the prolog in it. If not, see if this is a recursive call. If so, we can put the first insn of its prolog in the delay slot. Otherwise, write a nop. */ if (a29k_last_prologue_insn) { fprintf (file, "\n\t%s", a29k_last_prologue_insn); a29k_last_prologue_insn = 0; } else if (GET_CODE (x) == SYMBOL_REF && ! strcmp (XSTR (x, 0), current_function_name)) fprintf (file, "+4\n\t%s,%d", a29k_regstack_size >= 64 ? "const gr121" : "sub gr1,gr1", a29k_regstack_size * 4); else fprintf (file, "\n\tnop"); } return; case 'L': if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) { union real_extract u; bcopy (&CONST_DOUBLE_LOW (x), &u, sizeof u); fprintf (file, "$double1(%.20e)", u.d); } else if (GET_CODE (x) == REG) fprintf (file, "%s", reg_names[REGNO (x) + 1]); else output_operand_lossage ("invalid %%L value"); return; case 'O': if (GET_CODE (x) != REG) output_operand_lossage ("invalid %%O value"); fprintf (file, "%s", reg_names[REGNO (x) + 2]); return; case 'P': if (GET_CODE (x) != REG) output_operand_lossage ("invalid %%P value"); fprintf (file, "%s", reg_names[REGNO (x) + 3]); return; case 'S': fprintf (file, "%d", (GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD)-1); return; case 'V': if (GET_CODE (x) != PARALLEL) output_operand_lossage ("invalid %%V value"); fprintf (file, "%d", XVECLEN (x, 0) - 2); return; case '#': if (dbr_sequence_length () == 0) { if (a29k_last_prologue_insn) { fprintf (file, "\n\t%s", a29k_last_prologue_insn); a29k_last_prologue_insn = 0; } else fprintf (file, "\n\tnop"); } return; case '*': fprintf (file, "%s", reg_names [R_TPC]); return; } if (GET_CODE (x) == REG) fprintf (file, "%s", reg_names [REGNO (x)]); else if (GET_CODE (x) == MEM) output_address (XEXP (x, 0)); else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == SUBREG && GET_CODE (SUBREG_REG (XEXP (x, 0))) == CONST_DOUBLE) { union real_extract u; if (GET_MODE (SUBREG_REG (XEXP (x, 0))) == SFmode) fprintf (file, "$float"); else fprintf (file, "$double%d", SUBREG_WORD (XEXP (x, 0))); bcopy (&CONST_DOUBLE_LOW (SUBREG_REG (XEXP (x, 0))), &u, sizeof u); fprintf (file, "(%.20e)", u.d); } else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) { union real_extract u; bcopy (&CONST_DOUBLE_LOW (x), &u, sizeof u); fprintf (file, "$%s(%.20e)", GET_MODE (x) == SFmode ? "float" : "double0", u.d); } else output_addr_const (file, x); } /* This page contains routines to output function prolog and epilog code. */ /* Output function prolog code to file FILE. Memory stack size is SIZE. Also sets register names for incoming arguments and frame pointer. */ void output_prolog (file, size) FILE *file; int size; { int makes_calls = 0; int arg_count = 0; rtx insn; int i; unsigned int tag_word; /* See if we make any calls. We need to set lr1 if so. */ for (insn = get_insns (); insn; insn = next_insn (insn)) if (GET_CODE (insn) == CALL_INSN || (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == CALL_INSN)) { makes_calls = 1; break; } /* Find the highest local register used. */ for (i = R_LR (127); i >= R_LR (0); i--) if (regs_ever_live[i]) break; a29k_regstack_size = i - (R_LR (0) - 1); /* If calling routines, ensure we count lr0 & lr1. */ if (makes_calls && a29k_regstack_size < 2) a29k_regstack_size = 2; /* Count frame pointer and align to 8 byte boundary (even number of registers). */ a29k_regstack_size += frame_pointer_needed; if (a29k_regstack_size & 1) a29k_regstack_size++; /* See how many incoming arguments we have in registers. */ for (i = R_AR (0); i < R_AR (16); i++) if (! fixed_regs[i]) arg_count++; /* The argument count includes the caller's lr0 and lr1. */ arg_count += 2; /* Set the names and numbers of the frame pointer and incoming argument registers. */ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) a29k_debug_reg_map[i] = i; reg_names[FRAME_POINTER_REGNUM] = reg_names[R_LR (a29k_regstack_size - 1)]; a29k_debug_reg_map[FRAME_POINTER_REGNUM] = R_LR (a29k_regstack_size - 1); for (i = 0; i < 16; i++) { reg_names[R_AR (i)] = reg_names[R_LR (a29k_regstack_size + i + 2)]; a29k_debug_reg_map[R_AR (i)] = R_LR (a29k_regstack_size + i + 2); } /* If using kernel register map, swap numbers for kernel and user registers. */ if (TARGET_KERNEL_REGISTERS) for (i = 0; i < 32; i++) { int tem = a29k_debug_reg_map[i]; a29k_debug_reg_map[i] = a29k_debug_reg_map[R_KR (i)]; a29k_debug_reg_map[R_KR (i)] = tem; } /* Compute memory stack size. Add in number of bytes that the we should push and pretend the caller did and the size of outgoing arguments. Then round to a doubleword boundary. */ size += (current_function_pretend_args_size + current_function_outgoing_args_size); size = (size + 7) & ~7; /* Write header words. See if one or two word form. */ tag_word = (frame_pointer_needed ? 0x400000 : 0) + (arg_count << 16); if (size / 8 > 0xff) fprintf (file, "\t.word %d, 0x%0x\n", (size / 8) << 2, 0x800000 + tag_word); else fprintf (file, "\t.word 0x%0x\n", tag_word + ((size / 8) << 3)); /* Define the function name. */ assemble_name (file, a29k_function_name); fprintf (file, ":\n"); /* Push the register stack by the proper amount. There are two possible ways to do this. */ if (a29k_regstack_size >= 256/4) fprintf (file, "\tconst %s,%d\n\tsub gr1,gr1,%s\n", reg_names[R_TAV], a29k_regstack_size * 4, reg_names[R_TAV]); else if (a29k_regstack_size) fprintf (file, "\tsub gr1,gr1,%d\n", a29k_regstack_size * 4); /* Test that the registers are available. */ if (a29k_regstack_size) fprintf (file, "\tasgeu V_%sSPILL,gr1,%s\n", TARGET_KERNEL_REGISTERS ? "K" : "", reg_names[R_RAB]); /* Set up frame pointer, if one is needed. */ if (frame_pointer_needed) fprintf (file, "\tsll %s,%s,0\n", reg_names[FRAME_POINTER_REGNUM], reg_names[R_MSP]); /* Make room for any frame space. There are three ways to do this. */ if (size >= 256) { fprintf (file, "\tconst %s,%d\n", reg_names[R_TAV], size); if (size >= 65536) fprintf (file, "\tconsth %s,%d\n", reg_names[R_TAV], size); if (TARGET_STACK_CHECK) fprintf (file, "\tcall %s,__msp_check\n", reg_names[R_TPC]); fprintf (file, "\tsub %s,%s,%s\n", reg_names[R_MSP], reg_names[R_MSP], reg_names[R_TAV]); } else if (size) { if (TARGET_STACK_CHECK) fprintf (file, "\tcall %s,__msp_check\n", reg_names[R_TPC]); fprintf (file, "\tsub %s,%s,%d\n", reg_names[R_MSP], reg_names[R_MSP], size); } /* If this routine will make calls, set lr1. If we see an insn that can use a delay slot before a call or jump, save this insn for that slot (this condition is equivalent to seeing if we have an insn that needs delay slots before an insn that has a filled delay slot). */ a29k_last_prologue_insn = 0; if (makes_calls) { i = (a29k_regstack_size + arg_count) * 4; if (i >= 256) fprintf (file, "\tconst %s,%d\n\tadd lr1,gr1,%s\n", reg_names[R_TAV], i, reg_names[R_TAV]); else { if (optimize && flag_delayed_branch) for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) { if (GET_CODE (insn) == CODE_LABEL || (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)) break; if (GET_CODE (insn) == NOTE || (GET_CODE (insn) == INSN && (GET_CODE (PATTERN (insn)) == USE || GET_CODE (PATTERN (insn)) == CLOBBER))) continue; if (num_delay_slots (insn) > 0) { a29k_last_prologue_insn = (char *) oballoc (100); sprintf (a29k_last_prologue_insn, "add lr1,gr1,%d", i); break; } } if (a29k_last_prologue_insn == 0) fprintf (file, "\tadd lr1,gr1,%d\n", i); } } /* Compute the first insn of the epilogue. */ a29k_first_epilogue_insn_used = 0; if (size == 0 && a29k_regstack_size == 0 && ! frame_pointer_needed) a29k_first_epilogue_insn = 0; else a29k_first_epilogue_insn = (char *) oballoc (100); if (frame_pointer_needed) sprintf (a29k_first_epilogue_insn, "sll %s,%s,0", reg_names[R_MSP], reg_names[FRAME_POINTER_REGNUM]); else if (a29k_regstack_size) { if (a29k_regstack_size >= 256 / 4) sprintf (a29k_first_epilogue_insn, "const %s,%d", reg_names[R_TAV], a29k_regstack_size * 4); else sprintf (a29k_first_epilogue_insn, "add gr1,gr1,%d", a29k_regstack_size * 4); } else if (size) { if (size >= 256) sprintf (a29k_first_epilogue_insn, "const %s,%d", reg_names[R_TAV], size); else sprintf (a29k_first_epilogue_insn, "add %s,%s,%d", reg_names[R_MSP], reg_names[R_MSP], size); } } /* Call this after writing what might be the first instruction of the epilogue. If that first insn was used in a delay slot, an intermediate label is written. */ static void check_epilogue_internal_label (file) FILE *file; { rtx insn; if (! a29k_first_epilogue_insn_used) return; for (insn = get_last_insn (); GET_CODE (insn) != CODE_LABEL; insn = PREV_INSN (insn)) ; ASM_OUTPUT_INTERNAL_LABEL (file, "LX", CODE_LABEL_NUMBER (insn)); a29k_first_epilogue_insn_used = 0; } /* Output the epilog of the last procedure to file FILE. SIZE is the memory stack size. The register stack size is in the variable A29K_REGSTACK_SIZE. */ void output_epilog (file, size) FILE *file; int size; { rtx insn; int locals_unavailable = 0; /* True until after first insn after gr1 update. */ /* If we hit a BARRIER before a real insn or CODE_LABEL, we don't need to do anything because we are never jumped to. */ insn = get_last_insn (); if (GET_CODE (insn) == NOTE) insn = prev_nonnote_insn (insn); if (insn && GET_CODE (insn) == BARRIER) return; /* If a frame pointer was needed we must restore the memory stack pointer before adjusting the register stack. */ if (frame_pointer_needed) { fprintf (file, "\tsll %s,%s,0\n", reg_names[R_MSP], reg_names[FRAME_POINTER_REGNUM]); check_epilogue_internal_label (file); } /* Restore the register stack. There are two ways to do this. */ if (a29k_regstack_size) { if (a29k_regstack_size >= 256/4) { fprintf (file, "\tconst %s,%d\n", reg_names[R_TAV], a29k_regstack_size * 4); check_epilogue_internal_label (file); fprintf (file, "\tadd gr1,gr1,%s\n", reg_names[R_TAV]); } else { fprintf (file, "\tadd gr1,gr1,%d\n", a29k_regstack_size * 4); check_epilogue_internal_label (file); } locals_unavailable = 1; } /* Restore the memory stack pointer if there is no frame pointer. Adjust the size to include any pretend arguments and pushed arguments and round to doubleword boundary. */ size += (current_function_pretend_args_size + current_function_outgoing_args_size); size = (size + 7) & ~7; if (size && ! frame_pointer_needed) { if (size >= 256) { fprintf (file, "\tconst %s,%d\n", reg_names[R_TAV], size); check_epilogue_internal_label (file); locals_unavailable = 0; if (size >= 65536) fprintf (file, "\tconsth %s,%d\n", reg_names[R_TAV], size); fprintf (file, "\tadd %s,%s,%s\n", reg_names[R_MSP], reg_names[R_MSP], reg_names[R_TAV]); } else { fprintf (file, "\tadd %s,%s,%d\n", reg_names[R_MSP], reg_names[R_MSP], size); check_epilogue_internal_label (file); locals_unavailable = 0; } } if (locals_unavailable) { /* If we have an insn for this delay slot, write it. */ if (current_function_epilogue_delay_list) final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), file, 1, -2, 1); else fprintf (file, "\tnop\n"); } fprintf (file, "\tjmpi lr0\n"); if (a29k_regstack_size) fprintf (file, "\tasleu V_%sFILL,lr1,%s\n", TARGET_KERNEL_REGISTERS ? "K" : "", reg_names[R_RFB]); else if (current_function_epilogue_delay_list) final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), file, 1, -2, 1); else fprintf (file, "\tnop\n"); } gcc-2.5.8/config/a29k/a29k.h100444 22011 13 173570 5477354234 14007 0ustar kenneruser/* Definitions of target machine for GNU compiler, for AMD Am29000 CPU. Copyright (C) 1988, 1990, 1991, 1992, 1993 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@nyu.edu) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-D_AM29K -D_AM29000 -D_EPI -Acpu(a29k) -Amachine(a29k)" /* Print subsidiary information on the compiler version in use. */ #define TARGET_VERSION /* Pass -w to assembler. */ #define ASM_SPEC "-w" /* Run-time compilation parameters selecting different hardware subsets. */ extern int target_flags; /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */ /* This means that the DW bit will be enabled, to allow direct loads of bytes. */ #define TARGET_DW_ENABLE (target_flags & 1) /* This means that the external hardware does supports byte writes. */ #define TARGET_BYTE_WRITES (target_flags & 2) /* This means that a "small memory model" has been selected where all function addresses are known to be within 256K. This allows CALL to be used. */ #define TARGET_SMALL_MEMORY (target_flags & 4) /* This means that we must always used on indirect call, even when calling a function in the same file, since the file might be > 256KB. */ #define TARGET_LARGE_MEMORY (target_flags & 8) /* This means that we are compiling for a 29050. */ #define TARGET_29050 (target_flags & 16) /* This means that we are compiling for the kernel which means that we use gr64-gr95 instead of gr96-126. */ #define TARGET_KERNEL_REGISTERS (target_flags & 32) /* This means that a call to "__msp_check" should be inserted after each stack adjustment to check for stack overflow. */ #define TARGET_STACK_CHECK (target_flags & 64) /* This handles 29k processors which cannot handle the separation of a mtsrim insns and a storem insn (most 29000 chips to date, but not the 29050. */ #define TARGET_NO_STOREM_BUG (target_flags & 128) /* This forces the compiler not to use incoming argument registers except for copying out arguments. It helps detect problems when a function is called with fewer arguments than it is declared with. */ #define TARGET_NO_REUSE_ARGS (target_flags & 256) #define TARGET_SWITCHES \ { {"dw", 1}, \ {"ndw", -1}, \ {"bw", 2}, \ {"nbw", - (1|2)}, \ {"small", 4}, \ {"normal", - (4|8)}, \ {"large", 8}, \ {"29050", 16+128}, \ {"29000", -16}, \ {"kernel-registers", 32}, \ {"user-registers", -32}, \ {"stack-check", 64}, \ {"no-stack-check", - 74}, \ {"storem-bug", -128}, \ {"no-storem-bug", 128}, \ {"reuse-arg-regs", -256}, \ {"no-reuse-arg-regs", 256}, \ {"", TARGET_DEFAULT}} #define TARGET_DEFAULT 3 /* Define this to change the optimizations performed by default. */ #define OPTIMIZATION_OPTIONS(LEVEL) \ { \ if ((LEVEL) > 0) \ { \ flag_force_addr = 1; \ flag_force_mem = 1; \ flag_omit_frame_pointer = 1; \ } \ } /* target machine storage layout */ /* Define the types for size_t, ptrdiff_t, and wchar_t. These are the same as those used by EPI. The type for wchar_t does not make much sense, but is what is used. */ #define SIZE_TYPE "unsigned int" #define PTRDIFF_TYPE "int" #define WCHAR_TYPE "char" #define WCHAR_TYPE_SIZE BITS_PER_UNIT /* Define this macro if it is advisable to hold scalars in registers in a wider mode than that declared by the program. In such cases, the value is constrained to be within the bounds of the declared type, but kept valid in the wider mode. The signedness of the extension may differ from that of the type. */ #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ if (GET_MODE_CLASS (MODE) == MODE_INT \ && GET_MODE_SIZE (MODE) < 4) \ (MODE) = SImode; /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. This is arbitrary on the 29k since it has no actual bit-field insns. It is better to define this as TRUE because BYTES_BIG_ENDIAN is TRUE and we want to be able to convert BP position to bit position with just a shift. */ #define BITS_BIG_ENDIAN 1 /* Define this if most significant byte of a word is the lowest numbered. This is true on 29k. */ #define BYTES_BIG_ENDIAN 1 /* Define this if most significant word of a multiword number is lowest numbered. For 29k we can decide arbitrarily since there are no machine instructions for them. Might as well be consistent with bytes. */ #define WORDS_BIG_ENDIAN 1 /* number of bits in an addressable storage unit */ #define BITS_PER_UNIT 8 /* Width in bits of a "word", which is the contents of a machine register. Note that this is not necessarily the width of data type `int'; if using 16-bit ints on a 68000, this would still be 32. But on a machine with 16-bit registers, this would be 16. */ #define BITS_PER_WORD 32 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 4 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ #define POINTER_SIZE 32 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ #define PARM_BOUNDARY 32 /* Boundary (in *bits*) on which stack pointer should be aligned. */ #define STACK_BOUNDARY 64 /* Allocation boundary (in *bits*) for the code of a function. */ #define FUNCTION_BOUNDARY 32 /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 32 /* Every structure's size must be a multiple of this. */ #define STRUCTURE_SIZE_BOUNDARY 8 /* A bitfield declared as `int' forces `int' alignment for the struct. */ #define PCC_BITFIELD_TYPE_MATTERS 1 /* No data type wants to be aligned rounder than this. */ #define BIGGEST_ALIGNMENT 32 /* Make strings word-aligned so strcpy from constants will be faster. */ #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ (TREE_CODE (EXP) == STRING_CST \ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) /* Make arrays of chars word-aligned for the same reasons. */ #define DATA_ALIGNMENT(TYPE, ALIGN) \ (TREE_CODE (TYPE) == ARRAY_TYPE \ && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) /* Set this non-zero if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 0 /* Set this non-zero if unaligned move instructions are extremely slow. On the 29k, they trap. */ #define SLOW_UNALIGNED_ACCESS 1 /* Standard register usage. */ /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. 29k has 256 registers, of which 62 are not defined. gr0 and gr1 are not produced in generated RTL so we can start at gr96, and call it register zero. So 0-31 are gr96-gr127, lr0-lr127 are 32-159. To represent the input arguments, whose register numbers we won't know until we are done, use register 160-175. They cannot be modified. Similarly, 176 is used for the frame pointer. It is assigned the last local register number once the number of registers used is known. We use 177, 178, 179, and 180 for the special registers BP, FC, CR, and Q, respectively. Registers 181 through 199 are used for the other special registers that may be used by the programmer, but are never used by the compiler. Registers 200-203 are the four floating-point accumulator register in the 29050. Registers 204-235 are the 32 global registers for kernel mode when -mkernel-registers is not specified, and the 32 global user registers when it is. When -mkernel-registers is specified, we still use the same register map but change the names so 0-31 print as gr64-gr95. */ #define FIRST_PSEUDO_REGISTER 236 /* Because of the large number of registers on the 29k, we define macros to refer to each group of registers and then define the number for some registers used in the calling sequence. */ #define R_GR(N) ((N) - 96) /* gr96 is register number 0 */ #define R_LR(N) ((N) + 32) /* lr0 is register number 32 */ #define R_FP 176 /* frame pointer is register 176 */ #define R_AR(N) ((N) + 160) /* first incoming arg reg is 160 */ #define R_KR(N) ((N) + 204) /* kernel registers (gr64 to gr95) */ /* Define the numbers of the special registers. */ #define R_BP 177 #define R_FC 178 #define R_CR 179 #define R_Q 180 /* These special registers are not used by the compiler, but may be referenced by the programmer via asm declarations. */ #define R_VAB 181 #define R_OPS 182 #define R_CPS 183 #define R_CFG 184 #define R_CHA 185 #define R_CHD 186 #define R_CHC 187 #define R_RBP 188 #define R_TMC 189 #define R_TMR 190 #define R_PC0 191 #define R_PC1 192 #define R_PC2 193 #define R_MMU 194 #define R_LRU 195 #define R_FPE 196 #define R_INT 197 #define R_FPS 198 #define R_EXO 199 /* Define the number for floating-point accumulator N. */ #define R_ACC(N) ((N) + 200) /* Now define the registers used in the calling sequence. */ #define R_TAV R_GR (121) #define R_TPC R_GR (122) #define R_LRP R_GR (123) #define R_SLP R_GR (124) #define R_MSP R_GR (125) #define R_RAB R_GR (126) #define R_RFB R_GR (127) /* 1 for registers that have pervasive standard uses and are not available for the register allocator. */ #define FIXED_REGISTERS \ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \ 0, 0, 0, 0, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. */ #define CALL_USED_REGISTERS \ {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } /* List the order in which to allocate registers. Each register must be listed once, even those in FIXED_REGISTERS. We allocate in the following order: gr116-gr120 (not used for anything but temps) gr96-gr111 (function return values, reverse order) argument registers (160-175) lr0-lr127 (locals, saved) acc3-0 (acc0 special) everything else */ #define REG_ALLOC_ORDER \ {R_GR (116), R_GR (117), R_GR (118), R_GR (119), R_GR (120), \ R_GR (111), R_GR (110), R_GR (109), R_GR (108), R_GR (107), \ R_GR (106), R_GR (105), R_GR (104), R_GR (103), R_GR (102), \ R_GR (101), R_GR (100), R_GR (99), R_GR (98), R_GR (97), R_GR (96), \ R_AR (0), R_AR (1), R_AR (2), R_AR (3), R_AR (4), R_AR (5), \ R_AR (6), R_AR (7), R_AR (8), R_AR (9), R_AR (10), R_AR (11), \ R_AR (12), R_AR (13), R_AR (14), R_AR (15), \ R_LR (0), R_LR (1), R_LR (2), R_LR (3), R_LR (4), R_LR (5), \ R_LR (6), R_LR (7), R_LR (8), R_LR (9), R_LR (10), R_LR (11), \ R_LR (12), R_LR (13), R_LR (14), R_LR (15), R_LR (16), R_LR (17), \ R_LR (18), R_LR (19), R_LR (20), R_LR (21), R_LR (22), R_LR (23), \ R_LR (24), R_LR (25), R_LR (26), R_LR (27), R_LR (28), R_LR (29), \ R_LR (30), R_LR (31), R_LR (32), R_LR (33), R_LR (34), R_LR (35), \ R_LR (36), R_LR (37), R_LR (38), R_LR (39), R_LR (40), R_LR (41), \ R_LR (42), R_LR (43), R_LR (44), R_LR (45), R_LR (46), R_LR (47), \ R_LR (48), R_LR (49), R_LR (50), R_LR (51), R_LR (52), R_LR (53), \ R_LR (54), R_LR (55), R_LR (56), R_LR (57), R_LR (58), R_LR (59), \ R_LR (60), R_LR (61), R_LR (62), R_LR (63), R_LR (64), R_LR (65), \ R_LR (66), R_LR (67), R_LR (68), R_LR (69), R_LR (70), R_LR (71), \ R_LR (72), R_LR (73), R_LR (74), R_LR (75), R_LR (76), R_LR (77), \ R_LR (78), R_LR (79), R_LR (80), R_LR (81), R_LR (82), R_LR (83), \ R_LR (84), R_LR (85), R_LR (86), R_LR (87), R_LR (88), R_LR (89), \ R_LR (90), R_LR (91), R_LR (92), R_LR (93), R_LR (94), R_LR (95), \ R_LR (96), R_LR (97), R_LR (98), R_LR (99), R_LR (100), R_LR (101), \ R_LR (102), R_LR (103), R_LR (104), R_LR (105), R_LR (106), \ R_LR (107), R_LR (108), R_LR (109), R_LR (110), R_LR (111), \ R_LR (112), R_LR (113), R_LR (114), R_LR (115), R_LR (116), \ R_LR (117), R_LR (118), R_LR (119), R_LR (120), R_LR (121), \ R_LR (122), R_LR (123), R_LR (124), R_LR (124), R_LR (126), \ R_LR (127), \ R_ACC (3), R_ACC (2), R_ACC (1), R_ACC (0), \ R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (121), \ R_GR (122), R_GR (123), R_GR (124), R_GR (125), R_GR (126), \ R_GR (127), \ R_FP, R_BP, R_FC, R_CR, R_Q, \ R_VAB, R_OPS, R_CPS, R_CFG, R_CHA, R_CHD, R_CHC, R_RBP, R_TMC, \ R_TMR, R_PC0, R_PC1, R_PC2, R_MMU, R_LRU, R_FPE, R_INT, R_FPS, \ R_EXO, \ R_KR (0), R_KR (1), R_KR (2), R_KR (3), R_KR (4), R_KR (5), \ R_KR (6), R_KR (7), R_KR (8), R_KR (9), R_KR (10), R_KR (11), \ R_KR (12), R_KR (13), R_KR (14), R_KR (15), R_KR (16), R_KR (17), \ R_KR (18), R_KR (19), R_KR (20), R_KR (21), R_KR (22), R_KR (23), \ R_KR (24), R_KR (25), R_KR (26), R_KR (27), R_KR (28), R_KR (29), \ R_KR (30), R_KR (31) } /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ ((REGNO) >= R_ACC (0) && (REGNO) <= R_ACC (3)? 1 \ : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On 29k, the cpu registers can hold any mode. But a double-precision floating-point value should start at an even register. The special registers cannot hold floating-point values, BP, CR, and FC cannot hold integer or floating-point values, and the accumulators cannot hold integer values. DImode and larger values should start at an even register just like DFmode values, even though the instruction set doesn't require it, in order to prevent reload from aborting due to a modes_equiv_for_class_p failure. (I'd like to use the "?:" syntax to make this more readable, but Sun's compiler doesn't seem to accept it.) */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ (((REGNO) >= R_ACC (0) && (REGNO) <= R_ACC (3) \ && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)) \ || ((REGNO) >= R_BP && (REGNO) <= R_CR \ && GET_MODE_CLASS (MODE) == MODE_PARTIAL_INT) \ || ((REGNO) >= R_Q && (REGNO) < R_ACC (0) \ && GET_MODE_CLASS (MODE) != MODE_FLOAT \ && GET_MODE_CLASS (MODE) != MODE_COMPLEX_FLOAT) \ || (((REGNO) < R_BP || (REGNO) >= R_KR (0)) \ && ((((REGNO) & 1) == 0) \ || GET_MODE_UNIT_SIZE (MODE) <= UNITS_PER_WORD))) /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. On the 29k, normally we'd just have problems with DFmode because of the even alignment. However, we also have to be a bit concerned about the special register's restriction to non-floating and the floating-point accumulator's restriction to only floating. This probably won't cause any great inefficiencies in practice. */ #define MODES_TIEABLE_P(MODE1, MODE2) \ ((MODE1) == (MODE2) \ || (GET_MODE_CLASS (MODE1) == MODE_INT \ && GET_MODE_CLASS (MODE2) == MODE_INT)) /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ /* 29k pc isn't overloaded on a register that the compiler knows about. */ /* #define PC_REGNUM */ /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM R_GR (125) /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM R_FP /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */ #define FRAME_POINTER_REQUIRED 0 /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM R_FP /* Register in which static-chain is passed to a function. */ #define STATIC_CHAIN_REGNUM R_SLP /* Register in which address to store a structure value is passed to a function. */ #define STRUCT_VALUE_REGNUM R_LRP /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. One of the classes must always be named ALL_REGS and include all hard regs. If there is more than one class, another class must be named NO_REGS and contain no registers. The name GENERAL_REGS must be the name of a class (or an alias for another name such as ALL_REGS). This is the class of registers that is allowed by "g" or "r" in a register constraint. Also, registers outside this class are allocated only when instructions express preferences for them. The classes must be numbered in nondecreasing order; that is, a larger-numbered class must never be contained completely in a smaller-numbered class. For any two classes, it is very desirable that there be another class that represents their union. The 29k has nine registers classes: LR0_REGS, GENERAL_REGS, SPECIAL_REGS, BP_REGS, FC_REGS, CR_REGS, Q_REGS, ACCUM_REGS, and ACCUM0_REGS. LR0_REGS, BP_REGS, FC_REGS, CR_REGS, and Q_REGS contain just the single register. The latter two classes are used to represent the floating-point accumulator registers in the 29050. We also define the union class FLOAT_REGS to represent any register that can be used to hold a floating-point value. The union of SPECIAL_REGS and ACCUM_REGS isn't useful as the former cannot contain floating-point and the latter can only contain floating-point. */ enum reg_class { NO_REGS, LR0_REGS, GENERAL_REGS, BP_REGS, FC_REGS, CR_REGS, Q_REGS, SPECIAL_REGS, ACCUM0_REGS, ACCUM_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ {"NO_REGS", "LR0_REGS", "GENERAL_REGS", "BP_REGS", "FC_REGS", "CR_REGS", \ "Q_REGS", "SPECIAL_REGS", "ACCUM0_REGS", "ACCUM_REGS", "FLOAT_REGS", \ "ALL_REGS" } /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS \ { {0, 0, 0, 0, 0, 0, 0, 0}, \ {0, 1, 0, 0, 0, 0, 0, 0}, \ {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xfff, 0xfffff}, \ {0, 0, 0, 0, 0, 0x20000, 0, 0}, \ {0, 0, 0, 0, 0, 0x40000, 0, 0}, \ {0, 0, 0, 0, 0, 0x80000, 0, 0}, \ {0, 0, 0, 0, 0, 0x100000, 0, 0}, \ {0, 0, 0, 0, 0, 0xfffe0000, 0xff, 0}, \ {0, 0, 0, 0, 0, 0, 0x100, 0}, \ {0, 0, 0, 0, 0, 0, 0xf00, 0}, \ {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xff, ~0}, \ {~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0} } /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ #define REGNO_REG_CLASS(REGNO) \ ((REGNO) == R_BP ? BP_REGS \ : (REGNO) == R_FC ? FC_REGS \ : (REGNO) == R_CR ? CR_REGS \ : (REGNO) == R_Q ? Q_REGS \ : (REGNO) > R_BP && (REGNO) <= R_EXO ? SPECIAL_REGS \ : (REGNO) == R_ACC (0) ? ACCUM0_REGS \ : (REGNO) >= R_KR (0) ? GENERAL_REGS \ : (REGNO) > R_ACC (0) ? ACCUM_REGS \ : (REGNO) == R_LR (0) ? LR0_REGS \ : GENERAL_REGS) /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS NO_REGS #define BASE_REG_CLASS GENERAL_REGS /* Get reg_class from a letter such as appears in the machine description. */ #define REG_CLASS_FROM_LETTER(C) \ ((C) == 'r' ? GENERAL_REGS \ : (C) == 'l' ? LR0_REGS \ : (C) == 'b' ? BP_REGS \ : (C) == 'f' ? FC_REGS \ : (C) == 'c' ? CR_REGS \ : (C) == 'q' ? Q_REGS \ : (C) == 'h' ? SPECIAL_REGS \ : (C) == 'a' ? ACCUM_REGS \ : (C) == 'A' ? ACCUM0_REGS \ : (C) == 'f' ? FLOAT_REGS \ : NO_REGS) /* Define this macro to change register usage conditional on target flags. On the 29k, we use this to change the register names for kernel mapping. */ #define CONDITIONAL_REGISTER_USAGE \ { \ char *p; \ int i; \ \ if (TARGET_KERNEL_REGISTERS) \ for (i = 0; i < 32; i++) \ { \ p = reg_names[i]; \ reg_names[i] = reg_names[R_KR (i)]; \ reg_names[R_KR (i)] = p; \ } \ } /* The letters I, J, K, L, M, N, O, and P in a register constraint string can be used to stand for particular ranges of immediate operands. This macro defines what the ranges are. C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. For 29k: `I' is used for the range of constants most insns can contain. `J' is for the few 16-bit insns. `K' is a constant whose high-order 24 bits are all one `L' is a HImode constant whose high-order 8 bits are all one `M' is a 32-bit constant whose high-order 16 bits are all one (for CONSTN) `N' is a 32-bit constant whose negative is 8 bits `O' is the 32-bit constant 0x80000000, any constant with low-order 16 bits zero for 29050. `P' is a HImode constant whose negative is 8 bits */ #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? (unsigned) (VALUE) < 0x100 \ : (C) == 'J' ? (unsigned) (VALUE) < 0x10000 \ : (C) == 'K' ? ((VALUE) & 0xffffff00) == 0xffffff00 \ : (C) == 'L' ? ((VALUE) & 0xff00) == 0xff00 \ : (C) == 'M' ? ((VALUE) & 0xffff0000) == 0xffff0000 \ : (C) == 'N' ? ((VALUE) < 0 && (VALUE) > -256) \ : (C) == 'O' ? ((VALUE) == 0x80000000 \ || (TARGET_29050 && ((VALUE) & 0xffff) == 0)) \ : (C) == 'P' ? (((VALUE) | 0xffff0000) < 0 \ && ((VALUE) | 0xffff0000) > -256) \ : 0) /* Similar, but for floating constants, and defining letters G and H. Here VALUE is the CONST_DOUBLE rtx itself. All floating-point constants are valid on 29k. */ #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1 /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. */ #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS /* Return the register class of a scratch register needed to copy IN into or out of a register in CLASS in MODE. If it can be done directly, NO_REGS is returned. */ #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ secondary_reload_class (CLASS, MODE, IN) /* This function is used to get the address of an object. */ extern struct rtx_def *a29k_get_reloaded_address (); /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. On 29k, this is the size of MODE in words except that the floating-point accumulators only require one word for anything they can hold. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ (((CLASS) == ACCUM_REGS || (CLASS) == ACCUM0_REGS) ? 1 \ : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* Define the cost of moving between registers of various classes. Everything involving a general register is cheap, but moving between the other types (even within a class) is two insns. */ #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ ((CLASS1) == GENERAL_REGS || (CLASS2) == GENERAL_REGS ? 2 : 4) /* A C statement (sans semicolon) to update the integer variable COST based on the relationship between INSN that is dependent on DEP_INSN through the dependence LINK. The default is to make no adjustment to COST. On the a29k, ignore the cost of anti- and output-dependencies. */ #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \ if (REG_NOTE_KIND (LINK) != 0) \ (COST) = 0; /* Anti or output dependence. */ /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack makes the stack pointer a smaller address. */ #define STACK_GROWS_DOWNWARD /* Define this if the nominal address of the stack frame is at the high-address end of the local variables; that is, each additional local variable allocated goes at a more negative offset in the frame. */ #define FRAME_GROWS_DOWNWARD /* Offset within stack frame to start allocating local variables at. If FRAME_GROWS_DOWNWARD, this is the offset to the END of the first local allocated. Otherwise, it is the offset to the BEGINNING of the first local allocated. */ #define STARTING_FRAME_OFFSET (- current_function_pretend_args_size) /* If we generate an insn to push BYTES bytes, this says how many the stack pointer really advances by. On 29k, don't define this because there are no push insns. */ /* #define PUSH_ROUNDING(BYTES) */ /* Define this if the maximum size of all the outgoing args is to be accumulated and pushed during the prologue. The amount can be found in the variable current_function_outgoing_args_size. */ #define ACCUMULATE_OUTGOING_ARGS /* Offset of first parameter from the argument pointer register value. */ #define FIRST_PARM_OFFSET(FNDECL) (- current_function_pretend_args_size) /* Define this if stack space is still allocated for a parameter passed in a register. */ /* #define REG_PARM_STACK_SPACE */ /* Value is the number of bytes of arguments automatically popped when returning from a subroutine call. FUNTYPE is the data type of the function (as a tree), or for a library call it is an identifier node for the subroutine name. SIZE is the number of bytes of arguments passed on the stack. */ #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0 /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. On 29k the value is found in gr96. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ gen_rtx (REG, TYPE_MODE (VALTYPE), R_GR (96)) /* Define how to find the value returned by a library function assuming the value has mode MODE. */ #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, R_GR (96)) /* 1 if N is a possible register number for a function value as seen by the caller. On 29k, gr96-gr111 are used. */ #define FUNCTION_VALUE_REGNO_P(N) ((N) == R_GR (96)) /* 1 if N is a possible register number for function argument passing. On 29k, these are lr2-lr17. */ #define FUNCTION_ARG_REGNO_P(N) ((N) <= R_LR (17) && (N) >= R_LR (2)) /* Define a data type for recording info about an argument list during the scan of that argument list. This data type should hold all necessary information about the function itself and about the args processed so far, enough to enable macros such as FUNCTION_ARG to determine where the next arg should go. On 29k, this is a single integer, which is a number of words of arguments scanned so far. Thus 16 or more means all following args should go on the stack. */ #define CUMULATIVE_ARGS int /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) (CUM) = 0 /* Same, but called for incoming args. On the 29k, we use this to set all argument registers to fixed and set the last 16 local regs (lr112-lr127) to available. Some will later be changed to call-saved by FUNCTION_INCOMING_ARG. */ #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \ { int i; \ for (i = R_AR (0); i < R_AR (16); i++) \ { \ fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; \ SET_HARD_REG_BIT (fixed_reg_set, i); \ SET_HARD_REG_BIT (call_used_reg_set, i); \ SET_HARD_REG_BIT (call_fixed_reg_set, i); \ } \ for (i = R_LR (112); i < R_LR (128); i++) \ { \ fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 0; \ CLEAR_HARD_REG_BIT (fixed_reg_set, i); \ CLEAR_HARD_REG_BIT (call_used_reg_set, i); \ CLEAR_HARD_REG_BIT (call_fixed_reg_set, i); \ } \ (CUM) = 0; \ } /* Define intermediate macro to compute the size (in registers) of an argument for the 29k. */ #define A29K_ARG_SIZE(MODE, TYPE, NAMED) \ (! (NAMED) ? 0 \ : (MODE) != BLKmode \ ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \ : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ if (MUST_PASS_IN_STACK (MODE, TYPE)) \ (CUM) = 16; \ else \ (CUM) += A29K_ARG_SIZE (MODE, TYPE, NAMED) /* Determine where to put an argument to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. MODE is the argument's machine mode. TYPE is the data type of the argument (as a tree). This is null for libcalls where that information may not be available. CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called. NAMED is nonzero if this argument is a named parameter (otherwise it is an extra parameter matching an ellipsis). On 29k the first 16 words of args are normally in registers and the rest are pushed. */ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ ((CUM) < 16 && (NAMED) && ! MUST_PASS_IN_STACK (MODE, TYPE) \ ? gen_rtx(REG, (MODE), R_LR (2) + (CUM)) : 0) /* Define where a function finds its arguments. This is different from FUNCTION_ARG because of register windows. On the 29k, we hack this to call a function that sets the used registers as non-fixed and not used by calls. */ #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ ((CUM) < 16 && (NAMED) && ! MUST_PASS_IN_STACK (MODE, TYPE) \ ? gen_rtx (REG, MODE, \ incoming_reg (CUM, A29K_ARG_SIZE (MODE, TYPE, NAMED))) \ : 0) /* This indicates that an argument is to be passed with an invisible reference (i.e., a pointer to the object is passed). On the 29k, we do this if it must be passed on the stack. */ #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ (MUST_PASS_IN_STACK (MODE, TYPE)) /* Specify the padding direction of arguments. On the 29k, we must pad upwards in order to be able to pass args in registers. */ #define FUNCTION_ARG_PADDING(MODE, TYPE) upward /* For an arg passed partly in registers and partly in memory, this is the number of registers used. For args passed entirely in registers or entirely in memory, zero. */ #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ ((CUM) < 16 && 16 < (CUM) + A29K_ARG_SIZE (MODE, TYPE, NAMED) && (NAMED) \ ? 16 - (CUM) : 0) /* Perform any needed actions needed for a function that is receiving a variable number of arguments. CUM is as above. MODE and TYPE are the mode and type of the current parameter. PRETEND_SIZE is a variable that should be set to the amount of stack that must be pushed by the prolog to pretend that our caller pushed it. Normally, this macro will push all remaining incoming registers on the stack and set PRETEND_SIZE to the length of the registers pushed. */ #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ { if ((CUM) < 16) \ { \ int first_reg_offset = (CUM); \ \ if (MUST_PASS_IN_STACK (MODE, TYPE)) \ first_reg_offset += A29K_ARG_SIZE (TYPE_MODE (TYPE), TYPE, 1); \ \ if (first_reg_offset > 16) \ first_reg_offset = 16; \ \ if (! (NO_RTL) && first_reg_offset != 16) \ move_block_from_reg \ (R_AR (0) + first_reg_offset, \ gen_rtx (MEM, BLKmode, virtual_incoming_args_rtx), \ 16 - first_reg_offset, (16 - first_reg_offset) * UNITS_PER_WORD); \ PRETEND_SIZE = (16 - first_reg_offset) * UNITS_PER_WORD; \ } \ } /* Define the information needed to generate branch and scc insns. This is stored from the compare operation. Note that we can't use "rtx" here since it hasn't been defined! */ extern struct rtx_def *a29k_compare_op0, *a29k_compare_op1; extern int a29k_compare_fp_p; /* This macro produces the initial definition of a function name. For the 29k, we need the prolog to contain one or two words prior to the declaration of the function name. So just store away the name and write it as part of the prolog. */ extern char *a29k_function_name; #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ a29k_function_name = NAME; /* This macro generates the assembly code for function entry. FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. Refer to the array `regs_ever_live' to determine which registers to save; `regs_ever_live[I]' is nonzero if register number I is ever used in the function. This macro is responsible for knowing which registers should not be saved even if used. */ #define FUNCTION_PROLOGUE(FILE, SIZE) output_prolog (FILE, SIZE) /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ #define FUNCTION_PROFILER(FILE, LABELNO) /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, the stack pointer does not matter. The value is tested only in functions that have frame pointers. No definition is equivalent to always zero. */ #define EXIT_IGNORE_STACK 1 /* This macro generates the assembly code for function exit, on machines that need it. If FUNCTION_EPILOGUE is not defined then individual return instructions are generated for each return statement. Args are same as for FUNCTION_PROLOGUE. The function epilogue should not depend on the current stack pointer! It should use the frame pointer only. This is mandatory because of alloca; we also take advantage of it to omit stack adjustments before returning. */ #define FUNCTION_EPILOGUE(FILE, SIZE) output_epilog (FILE, SIZE) /* Define the number of delay slots needed for the function epilogue. On the 29k, we need a slot except when we have a register stack adjustment, have a memory stack adjustment, and have no frame pointer. */ #define DELAY_SLOTS_FOR_EPILOGUE \ (! (needs_regstack_p () \ && (get_frame_size () + current_function_pretend_args_size \ + current_function_outgoing_args_size) != 0 \ && ! frame_pointer_needed)) /* Define whether INSN can be placed in delay slot N for the epilogue. On the 29k, we must be able to place it in a delay slot, it must not use sp if the frame pointer cannot be eliminated, and it cannot use local regs if we need to push the register stack. */ #define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN,N) \ (get_attr_in_delay_slot (INSN) == IN_DELAY_SLOT_YES \ && ! (frame_pointer_needed \ && reg_mentioned_p (stack_pointer_rtx, PATTERN (INSN))) \ && ! (needs_regstack_p () && uses_local_reg_p (PATTERN (INSN)))) /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. The trampoline should set the static chain pointer to value placed into the trampoline and should branch to the specified routine. We use gr121 (tav) as a temporary. */ #define TRAMPOLINE_TEMPLATE(FILE) \ { \ fprintf (FILE, "\tconst %s,0\n", reg_names[R_TAV]); \ fprintf (FILE, "\tconsth %s,0\n", reg_names[R_TAV]); \ fprintf (FILE, "\tconst %s,0\n", reg_names[R_SLP]); \ fprintf (FILE, "\tjmpi %s\n", reg_names[R_TAV]); \ fprintf (FILE, "\tconsth %s,0\n", reg_names[R_SLP]); \ } /* Length in units of the trampoline for entering a nested function. */ #define TRAMPOLINE_SIZE 20 /* Emit RTL insns to initialize the variable parts of a trampoline. FNADDR is an RTX for the address of the function's pure code. CXT is an RTX for the static chain value for the function. We do this on the 29k by writing the bytes of the addresses into the trampoline one byte at a time. */ #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ INITIALIZE_TRAMPOLINE_VALUE (TRAMP, FNADDR, 0, 4); \ INITIALIZE_TRAMPOLINE_VALUE (TRAMP, CXT, 8, 16); \ } /* Define a sub-macro to initialize one value into the trampoline. We specify the offsets of the CONST and CONSTH instructions, respectively and copy the value a byte at a time into these instructions. */ #define INITIALIZE_TRAMPOLINE_VALUE(TRAMP, VALUE, CONST, CONSTH) \ { \ rtx _addr, _temp; \ rtx _val = force_reg (SImode, VALUE); \ \ _addr = memory_address (QImode, plus_constant (TRAMP, (CONST) + 3)); \ emit_move_insn (gen_rtx (MEM, QImode, _addr), \ gen_lowpart (QImode, _val)); \ \ _temp = expand_shift (RSHIFT_EXPR, SImode, _val, \ build_int_2 (8, 0), 0, 1); \ _addr = memory_address (QImode, plus_constant (TRAMP, (CONST) + 1)); \ emit_move_insn (gen_rtx (MEM, QImode, _addr), \ gen_lowpart (QImode, _temp)); \ \ _temp = expand_shift (RSHIFT_EXPR, SImode, _temp, \ build_int_2 (8, 0), _temp, 1); \ _addr = memory_address (QImode, plus_constant (TRAMP, (CONSTH) + 3)); \ emit_move_insn (gen_rtx (MEM, QImode, _addr), \ gen_lowpart (QImode, _temp)); \ \ _temp = expand_shift (RSHIFT_EXPR, SImode, _temp, \ build_int_2 (8, 0), _temp, 1); \ _addr = memory_address (QImode, plus_constant (TRAMP, (CONSTH) + 1)); \ emit_move_insn (gen_rtx (MEM, QImode, _addr), \ gen_lowpart (QImode, _temp)); \ } /* Addressing modes, and classification of registers for them. */ /* #define HAVE_POST_INCREMENT */ /* #define HAVE_POST_DECREMENT */ /* #define HAVE_PRE_DECREMENT */ /* #define HAVE_PRE_INCREMENT */ /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. */ #define REGNO_OK_FOR_INDEX_P(REGNO) 0 #define REGNO_OK_FOR_BASE_P(REGNO) 1 /* Given the value returned from get_frame_size, compute the actual size of the frame we will allocate. We include the pretend and outgoing arg sizes and round to a doubleword. */ #define ACTUAL_FRAME_SIZE(SIZE) \ (((SIZE) + current_function_pretend_args_size \ + current_function_outgoing_args_size + 7) & ~7) /* Define the initial offset between the frame and stack pointer. */ #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ (DEPTH) = ACTUAL_FRAME_SIZE (get_frame_size ()) /* Maximum number of registers that can appear in a valid memory address. */ #define MAX_REGS_PER_ADDRESS 1 /* Recognize any constant value that is a valid address. None are on the 29K. */ #define CONSTANT_ADDRESS_P(X) 0 /* Include all constant integers and constant doubles */ #define LEGITIMATE_CONSTANT_P(X) 1 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. The usual definition accepts all pseudo regs; the other rejects them unless they have been allocated suitable hard regs. The symbol REG_OK_STRICT causes the latter definition to be used. Most source files want to accept pseudo regs in the hope that they will get allocated to the class that the insn wants them to be in. Source files for reload pass need to be strict. After reload, it makes no difference, since pseudo regs have been eliminated by then. */ #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ #define REG_OK_FOR_INDEX_P(X) 0 /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ #define REG_OK_FOR_BASE_P(X) 1 #else /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) #endif /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. On the 29k, a legitimate address is a register and so is a constant of less than 256. */ #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \ goto ADDR; \ if (GET_CODE (X) == CONST_INT \ && (unsigned) INTVAL (X) < 0x100) \ goto ADDR; \ } /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. OLDX is the address as it was before break_out_memory_refs was called. In some cases it is useful to look at this to decide what needs to be done. MODE and WIN are passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. It is always safe for this macro to do nothing. It exists to recognize opportunities to optimize the output. For the 29k, we need not do anything. However, if we don't, `memory_address' will try lots of things to get a valid address, most of which will result in dead code and extra pseudos. So we make the address valid here. This is easy: The only valid addresses are an offset from a register and we know the address isn't valid. So just call either `force_operand' or `force_reg' unless this is a (plus (reg ...) (const_int 0)). */ #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ { if (GET_CODE (X) == PLUS && XEXP (X, 1) == const0_rtx) \ X = XEXP (x, 0); \ if (GET_CODE (X) == MULT || GET_CODE (X) == PLUS) \ X = force_operand (X, 0); \ else \ X = force_reg (Pmode, X); \ goto WIN; \ } /* Go to LABEL if ADDR (a legitimate address expression) has an effect that depends on the machine mode it is used for. On the 29k this is never true. */ #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) /* Compute the cost of an address. For the 29k, all valid addresses are the same cost. */ #define ADDRESS_COST(X) 0 /* Define this if some processing needs to be done immediately before emitting code for an insn. */ /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */ /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE SImode /* Define this if the tablejump instruction expects the table to contain offsets from the address of the table. Do not define this if the table should contain absolute addresses. */ /* #define CASE_VECTOR_PC_RELATIVE */ /* Specify the tree operation to be used to convert reals to integers. */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR /* This is the kind of divide that is easiest to do in the general case. */ #define EASY_DIV_EXPR TRUNC_DIV_EXPR /* Define this as 1 if `char' should by default be signed; else as 0. */ #define DEFAULT_SIGNED_CHAR 0 /* This flag, if defined, says the same insns that convert to a signed fixnum also convert validly to an unsigned one. We actually lie a bit here as overflow conditions are different. But they aren't being checked anyway. */ #define FIXUNS_TRUNC_LIKE_FIX_TRUNC /* Max number of bytes we can move to of from memory in one reasonably fast instruction. For the 29k, we will define movti, so put this at 4 words. */ #define MOVE_MAX 16 /* Largest number of bytes of an object that can be placed in a register. On the 29k we have plenty of registers, so use TImode. */ #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) /* Nonzero if access to memory by bytes is no faster than for words. Also non-zero if doing byte operations (specifically shifts) in registers is undesirable. On the 29k, large masks are expensive, so we want to use bytes to manipulate fields. */ #define SLOW_BYTE_ACCESS 0 /* Define if operations between registers always perform the operation on the full register even if a narrower mode is specified. */ #define WORD_REGISTER_OPERATIONS /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly done, NIL if none. */ #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Define if the object format being used is COFF or a superset. */ #define OBJECT_FORMAT_COFF /* This uses COFF, so it wants SDB format. */ #define SDB_DEBUGGING_INFO /* Define this to be the delimiter between SDB sub-sections. The default is ";". */ #define SDB_DELIM "\n" /* Do not break .stabs pseudos into continuations. */ #define DBX_CONTIN_LENGTH 0 /* Don't try to use the `x' type-cross-reference character in DBX data. Also has the consequence of putting each struct, union or enum into a separate .stabs, containing only cross-refs to the others. */ #define DBX_NO_XREFS /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 /* We assume that the store-condition-codes instructions store 0 for false and some other value for true. This is the value stored for true. */ #define STORE_FLAG_VALUE 0x80000000 /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ #define Pmode SImode /* Mode of a function address in a call instruction (for indexing purposes). Doesn't matter on 29k. */ #define FUNCTION_MODE SImode /* Define this if addresses of constant functions shouldn't be put through pseudo regs where they can be cse'd. Desirable on machines where ordinary constants are expensive but a CALL with constant address is cheap. */ #define NO_FUNCTION_CSE /* Define this to be nonzero if shift instructions ignore all but the low-order few bits. */ #define SHIFT_COUNT_TRUNCATED 1 /* Compute the cost of computing a constant rtl expression RTX whose rtx-code is CODE. The body of this macro is a portion of a switch statement. If the code is computed here, return it with a return statement. Otherwise, break from the switch. We only care about the cost if it is valid in an insn. The only constants that cause an insn to generate more than one machine instruction are those involving floating-point or address. So only these need be expensive. */ #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ return 0; \ case CONST: \ case LABEL_REF: \ case SYMBOL_REF: \ return 6; \ case CONST_DOUBLE: \ return GET_MODE (RTX) == SFmode ? 6 : 8; /* Provide the costs of a rtl expression. This is in the body of a switch on CODE. All MEMs cost the same if they are valid. This is used to ensure that (mem (symbol_ref ...)) is placed into a CALL when valid. The multiply cost depends on whether this is a 29050 or not. */ #define RTX_COSTS(X,CODE,OUTER_CODE) \ case MULT: \ return TARGET_29050 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (40); \ case DIV: \ case UDIV: \ case MOD: \ case UMOD: \ return COSTS_N_INSNS (50); \ case MEM: \ return COSTS_N_INSNS (2); /* Control the assembler format that we output. */ /* Output at beginning of assembler file. */ #define ASM_FILE_START(FILE) \ { char *p, *after_dir = main_input_filename; \ if (TARGET_29050) \ fprintf (FILE, "\t.cputype 29050\n"); \ for (p = main_input_filename; *p; p++) \ if (*p == '/') \ after_dir = p + 1; \ fprintf (FILE, "\t.file "); \ output_quoted_string (FILE, after_dir); \ fprintf (FILE, "\n"); \ fprintf (FILE, "\t.sect .lit,lit\n"); } /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ #define ASM_APP_ON "" /* Output to assembler file text saying following lines no longer contain unusual constructs. */ #define ASM_APP_OFF "" /* The next few macros don't have tabs on most machines, but at least one 29K assembler wants them. */ /* Output before instructions. */ #define TEXT_SECTION_ASM_OP "\t.text" /* Output before read-only data. */ #define READONLY_DATA_SECTION_ASM_OP "\t.use .lit" /* Output before writable data. */ #define DATA_SECTION_ASM_OP "\t.data" /* Define an extra section for read-only data, a routine to enter it, and indicate that it is for read-only data. */ #define EXTRA_SECTIONS readonly_data #define EXTRA_SECTION_FUNCTIONS \ void \ literal_section () \ { \ if (in_section != readonly_data) \ { \ fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \ in_section = readonly_data; \ } \ } \ #define READONLY_DATA_SECTION literal_section /* If we are referencing a function that is static or is known to be in this file, make the SYMBOL_REF special. We can use this to indicate that we can branch to this function without emitting a no-op after the call. */ #define ENCODE_SECTION_INFO(DECL) \ if (TREE_CODE (DECL) == FUNCTION_DECL \ && (TREE_ASM_WRITTEN (DECL) || ! TREE_PUBLIC (DECL))) \ SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ #define REGISTER_NAMES \ {"gr96", "gr97", "gr98", "gr99", "gr100", "gr101", "gr102", "gr103", "gr104", \ "gr105", "gr106", "gr107", "gr108", "gr109", "gr110", "gr111", "gr112", \ "gr113", "gr114", "gr115", "gr116", "gr117", "gr118", "gr119", "gr120", \ "gr121", "gr122", "gr123", "gr124", "gr125", "gr126", "gr127", \ "lr0", "lr1", "lr2", "lr3", "lr4", "lr5", "lr6", "lr7", "lr8", "lr9", \ "lr10", "lr11", "lr12", "lr13", "lr14", "lr15", "lr16", "lr17", "lr18", \ "lr19", "lr20", "lr21", "lr22", "lr23", "lr24", "lr25", "lr26", "lr27", \ "lr28", "lr29", "lr30", "lr31", "lr32", "lr33", "lr34", "lr35", "lr36", \ "lr37", "lr38", "lr39", "lr40", "lr41", "lr42", "lr43", "lr44", "lr45", \ "lr46", "lr47", "lr48", "lr49", "lr50", "lr51", "lr52", "lr53", "lr54", \ "lr55", "lr56", "lr57", "lr58", "lr59", "lr60", "lr61", "lr62", "lr63", \ "lr64", "lr65", "lr66", "lr67", "lr68", "lr69", "lr70", "lr71", "lr72", \ "lr73", "lr74", "lr75", "lr76", "lr77", "lr78", "lr79", "lr80", "lr81", \ "lr82", "lr83", "lr84", "lr85", "lr86", "lr87", "lr88", "lr89", "lr90", \ "lr91", "lr92", "lr93", "lr94", "lr95", "lr96", "lr97", "lr98", "lr99", \ "lr100", "lr101", "lr102", "lr103", "lr104", "lr105", "lr106", "lr107", \ "lr108", "lr109", "lr110", "lr111", "lr112", "lr113", "lr114", "lr115", \ "lr116", "lr117", "lr118", "lr119", "lr120", "lr121", "lr122", "lr123", \ "lr124", "lr125", "lr126", "lr127", \ "AI0", "AI1", "AI2", "AI3", "AI4", "AI5", "AI6", "AI7", "AI8", "AI9", \ "AI10", "AI11", "AI12", "AI13", "AI14", "AI15", "FP", \ "bp", "fc", "cr", "q", \ "vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr", \ "pc0", "pc1", "pc2", "mmu", "lru", "fpe", "int", "fps", "exo", \ "0", "1", "2", "3", \ "gr64", "gr65", "gr66", "gr67", "gr68", "gr69", "gr70", "gr71", \ "gr72", "gr73", "gr74", "gr75", "gr76", "gr77", "gr78", "gr79", \ "gr80", "gr81", "gr82", "gr83", "gr84", "gr85", "gr86", "gr87", \ "gr88", "gr89", "gr90", "gr91", "gr92", "gr93", "gr94", "gr95" } /* How to renumber registers for dbx and gdb. */ extern int a29k_debug_reg_map[]; #define DBX_REGISTER_NUMBER(REGNO) a29k_debug_reg_map[REGNO] /* This is how to output the definition of a user-level label named NAME, such as the label on a static function or variable NAME. */ #define ASM_OUTPUT_LABEL(FILE,NAME) \ do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) /* This is how to output a command to make the user-level label named NAME defined for reference from other files. */ #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) /* This is how to output a reference to a user-level label named NAME. `assemble_name' uses this. */ #define ASM_OUTPUT_LABELREF(FILE,NAME) \ fprintf (FILE, "_%s", NAME) /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, "%s%d:\n", PREFIX, NUM) /* This is how to output a label for a jump table. Arguments are the same as for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is passed. */ #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \ { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); } /* This is how to store into the string LABEL the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ sprintf (LABEL, "*%s%d", PREFIX, NUM) /* This is how to output an assembler line defining a `double' constant. */ #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ fprintf (FILE, "\t.double %.20e\n", (VALUE)) /* This is how to output an assembler line defining a `float' constant. */ #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ fprintf (FILE, "\t.float %.20e\n", (VALUE)) /* This is how to output an assembler line defining an `int' constant. */ #define ASM_OUTPUT_INT(FILE,VALUE) \ ( fprintf (FILE, "\t.word "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* Likewise for `char' and `short' constants. */ #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "\t.hword "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ( fprintf (FILE, "\t.byte "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tsub %s,%s,4\n\tstore 0,0,%s,%s\n", \ reg_names[R_MSP], reg_names[R_MSP], reg_names[REGNO], \ reg_names[R_MSP]); /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tload 0,0,%s,%s\n\tadd %s,%s,4\n", \ reg_names[REGNO], reg_names[R_MSP], reg_names[R_MSP], \ reg_names[R_MSP]); /* This is how to output an assembler line for a numeric constant byte. */ #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) /* This is how to output an element of a case-vector that is absolute. */ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "\t.word L%d\n", VALUE) /* This is how to output an element of a case-vector that is relative. (29k does not use such vectors, but we must define this macro anyway.) */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) abort () /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG) != 0) \ fprintf (FILE, "\t.align %d\n", 1 << (LOG)) #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t.block %d\n", (SIZE)) /* This says how to output an assembler line to define a global common symbol. */ #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fputs ("\t.comm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%d\n", (SIZE))) /* This says how to output an assembler line to define a local common symbol. */ #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \ ( fputs ("\t.lcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%d\n", (SIZE))) /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) /* Define the parentheses used to group arithmetic operations in assembler code. */ #define ASM_OPEN_PAREN "(" #define ASM_CLOSE_PAREN ")" /* Define results of standard character escape sequences. */ #define TARGET_BELL 007 #define TARGET_BS 010 #define TARGET_TAB 011 #define TARGET_NEWLINE 012 #define TARGET_VT 013 #define TARGET_FF 014 #define TARGET_CR 015 /* Print operand X (an rtx) in assembler syntax to file FILE. CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. For `%' followed by punctuation, CODE is the punctuation and X is null. */ #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) /* Determine which codes are valid without a following integer. These must not be alphabetic. We support `#' which is null if a delay slot exists, otherwise "\n\tnop" and `*' which prints the register name for TPC (gr122). */ #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#' || (CODE) == '*') /* Print a memory address as an operand to reference that memory location. */ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ { register rtx addr = ADDR; \ if (!REG_P (addr) \ && ! (GET_CODE (addr) == CONST_INT \ && INTVAL (addr) >= 0 && INTVAL (addr) < 256)) \ abort (); \ output_operand (addr, 0); \ } /* Define the codes that are matched by predicates in a29k.c. */ #define PREDICATE_CODES \ {"cint_8_operand", {CONST_INT}}, \ {"cint_16_operand", {CONST_INT}}, \ {"long_const_operand", {CONST_INT, CONST, CONST_DOUBLE, \ LABEL_REF, SYMBOL_REF}}, \ {"shift_constant_operand", {CONST_INT, ASHIFT}}, \ {"const_0_operand", {CONST_INT, ASHIFT}}, \ {"const_8_operand", {CONST_INT, ASHIFT}}, \ {"const_16_operand", {CONST_INT, ASHIFT}}, \ {"const_24_operand", {CONST_INT, ASHIFT}}, \ {"float_const_operand", {CONST_DOUBLE}}, \ {"gpc_reg_operand", {SUBREG, REG}}, \ {"gpc_reg_or_float_constant_operand", {SUBREG, REG, CONST_DOUBLE}}, \ {"gpc_reg_or_integer_constant_operand", {SUBREG, REG, \ CONST_INT, CONST_DOUBLE}}, \ {"gpc_reg_or_immediate_operand", {SUBREG, REG, CONST_INT, \ CONST_DOUBLE, CONST, \ SYMBOL_REF, LABEL_REF}}, \ {"spec_reg_operand", {REG}}, \ {"accum_reg_operand", {REG}}, \ {"srcb_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_immediate_operand", {SUBREG, REG, CONST_INT, CONST, \ CONST_DOUBLE, CONST, SYMBOL_REF, LABEL_REF}}, \ {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \ {"and_operand", {SUBREG, REG, CONST_INT}}, \ {"add_operand", {SUBREG, REG, CONST_INT}}, \ {"call_operand", {SYMBOL_REF, CONST_INT}}, \ {"in_operand", {SUBREG, MEM, REG, CONST_INT, CONST, SYMBOL_REF, \ LABEL_REF, CONST_DOUBLE}}, \ {"out_operand", {SUBREG, REG, MEM}}, \ {"reload_memory_operand", {SUBREG, REG, MEM}}, \ {"fp_comparison_operator", {EQ, GT, GE}}, \ {"branch_operator", {GE, LT}}, \ {"load_multiple_operation", {PARALLEL}}, \ {"store_multiple_operation", {PARALLEL}}, \ {"epilogue_operand", {CODE_LABEL}}, gcc-2.5.8/config/a29k/a29k.md100444 22011 13 244427 5477354052 14156 0ustar kenneruser;;- Machine description for AMD Am29000 for GNU C compiler ;; Copyright (C) 1991, 1992 Free Software Foundation, Inc. ;; Contributed by Richard Kenner (kenner@nyu.edu) ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ;; The insns in this file are presented in the same order as the AMD 29000 ;; User's Manual (i.e., alphabetical by machine op-code). ;; ;; DEFINE_EXPAND's are located near the first occurrence of the major insn ;; that they generate. ;; The only attribute we have is the type. We only care about calls, branches, ;; loads, stores, floating-point operations, and multi-word insns. ;; Everything else is miscellaneous. (define_attr "type" "call,branch,load,store,fadd,fmul,fam,fdiv,fsqrt,dmul,dam,ddiv,dsqrt,multi,misc" (const_string "misc")) ;; ASM insns cannot go into a delay slot, so call them "multi". (define_asm_attributes [(set_attr "type" "multi")]) (define_attr "in_delay_slot" "yes,no" (if_then_else (eq_attr "type" "call,branch,multi") (const_string "no") (const_string "yes"))) ;; Branch and call insns require a single delay slot. Annulling is not ;; supported. (define_delay (eq_attr "type" "call,branch") [(eq_attr "in_delay_slot" "yes") (nil) (nil)]) ;; Define the function unit usages. We first define memory as a unit. (define_function_unit "memory" 1 0 (eq_attr "type" "load") 6 5 [(eq_attr "type" "load")]) (define_function_unit "memory" 1 0 (eq_attr "type" "load") 6 6 [(eq_attr "type" "store")]) (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0) ;; Now define the function units for the floating-point support. Most ;; units are pipelined and can accept an input every cycle. ;; ;; Note that we have an inaccuracy here. If a fmac insn is issued, followed ;; 2 cycles later by a fadd, there will be a conflict for the floating ;; adder that we can't represent. Also, all insns will conflict for the ;; floating-point rounder. It isn't clear how to represent this. (define_function_unit "multiplier" 1 0 (eq_attr "type" "fmul") 3 0) (define_function_unit "multiplier" 1 0 (eq_attr "type" "dmul") 6 4) (define_function_unit "multiplier" 1 0 (eq_attr "type" "fam") 6 0) (define_function_unit "multiplier" 1 0 (eq_attr "type" "dam") 9 4) (define_function_unit "adder" 1 0 (eq_attr "type" "fadd,fam,dam") 3 0) (define_function_unit "divider" 1 0 (eq_attr "type" "fdiv") 11 10) (define_function_unit "divider" 1 0 (eq_attr "type" "fsqrt") 28 27) (define_function_unit "divider" 1 0 (eq_attr "type" "ddiv") 18 17) (define_function_unit "divider" 1 0 (eq_attr "type" "dsqrt") 57 56) ;; ADD (define_insn "addsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") (match_operand:SI 2 "add_operand" "rI,N")))] "" "@ add %0,%1,%2 sub %0,%1,%n2") (define_insn "adddi3" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r") (match_operand:DI 2 "gpc_reg_operand" "r")))] "" "add %L0,%L1,%L2\;addc %0,%1,%2" [(set_attr "type" "multi")]) ;; AND/ANDN (define_insn "andsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") (match_operand:SI 2 "and_operand" "rI,K")))] "" "@ and %0,%1,%2 andn %0,%1,%C2") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (not:SI (match_operand:SI 1 "srcb_operand" "rI")) (match_operand:SI 2 "gpc_reg_operand" "r")))] "" "andn %0,%2,%1") ;; CALLI ;; ;; Start with a subroutine to write out CLOBBERs starting at lr2 up to, ;; but not including, the next parameter register. If operand[0] is null, ;; it means that all the argument registers have been used. (define_expand "clobbers_to" [(clobber (match_operand:SI 0 "" ""))] "" " { int i; int high_regno; if (operands[0] == 0) high_regno = R_LR (18); else if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) < R_LR (0) || REGNO (operands[0]) > R_LR (18)) abort (); else high_regno = REGNO (operands[0]); for (i = R_LR (2); i < high_regno; i++) emit_insn (gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, i))); DONE; }") ;; We indicate that LR0 is clobbered in the CALL_INSN itself. Otherwise, ;; reorg will think it is just clobbered by the called function. (define_expand "call" [(parallel [(call (match_operand:SI 0 "" "") (match_operand 1 "" "")) (clobber (scratch:SI))]) (match_operand 2 "" "")] "" " { if (GET_CODE (operands[0]) != MEM) abort (); /* We tell here whether this is a recursive call, since this insn may later be inlined into another function. */ if (! TARGET_SMALL_MEMORY && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) operands[0] = gen_rtx (MEM, SImode, force_reg (Pmode, XEXP (operands[0], 0))); operands[2] = gen_clobbers_to (operands[2]); }") (define_expand "call_value" [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") (call (match_operand:SI 1 "" "") (match_operand 2 "" ""))) (clobber (scratch:SI))]) (match_operand 3 "" "")] "" " { if (GET_CODE (operands[1]) != MEM) abort (); /* We tell here whether this is a recursive call, since this insn may later be inlined into another function. */ if (! TARGET_SMALL_MEMORY && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) operands[1] = gen_rtx (MEM, SImode, force_reg (Pmode, XEXP (operands[1], 0))); operands[3] = gen_clobbers_to (operands[3]); }") (define_insn "" [(call (match_operand:SI 0 "memory_operand" "m") (match_operand 1 "" "")) (clobber (match_scratch:SI 2 "=&l"))] "GET_CODE (XEXP (operands[0], 0)) != CONST_INT" "calli lr0,%0%#" [(set_attr "type" "call")]) (define_insn "" [(call (mem:SI (match_operand:SI 0 "call_operand" "i")) (match_operand:SI 1 "general_operand" "g")) (clobber (match_scratch:SI 2 "=&l"))] "" "call lr0,%F0" [(set_attr "type" "call")]) (define_insn "" [(set (match_operand 0 "gpc_reg_operand" "=r") (call (match_operand:SI 1 "memory_operand" "m") (match_operand 2 "" ""))) (clobber (match_scratch:SI 3 "=&l"))] "GET_CODE (XEXP (operands[1], 0)) != CONST_INT" "calli lr0,%1%#" [(set_attr "type" "call")]) (define_insn "" [(set (match_operand 0 "gpc_reg_operand" "=r") (call (mem:SI (match_operand:SI 1 "call_operand" "i")) (match_operand:SI 2 "general_operand" "g"))) (clobber (match_scratch:SI 3 "=&l"))] "" "call lr0,%F1" [(set_attr "type" "call")]) (define_expand "probe" [(call (mem:SI (symbol_ref:SI "_msp_check")) (const_int 1))] "TARGET_STACK_CHECK" "") ;; This is used for internal routine calls via TPC. Currently used only ;; in probe, above. (define_insn "" [(call (mem:SI (match_operand:SI 0 "immediate_operand" "s")) (const_int 1))] "" "call %*,%0" [(set_attr "type" "call")]) ;; CONST, CONSTH, CONSTN ;; ;; Many of these are generated from move insns. (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (match_operand:SI 1 "immediate_operand" "i") (const_int 65535)))] "" "const %0,%1") (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 16) (match_operand:SI 1 "const_0_operand" "")) (ashiftrt:SI (match_operand:SI 2 "immediate_operand" "i") (const_int 16)))] "" "consth %0,%2") (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 16) (match_operand:SI 1 "const_0_operand" "")) (match_operand:SI 2 "cint_16_operand" "J"))] "" "consth %0,%m2") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")) (match_operand:SI 2 "const_int_operand" "n")))] "(INTVAL (operands[2]) & 0xffff) == 0" "consth %0,%2") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")) (and:SI (match_operand:SI 2 "immediate_operand" "i") (const_int -65536))))] "" "consth %0,%2") ;; CONVERT (define_insn "fix_truncsfsi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (fix:SI (match_operand:SF 1 "register_operand" "r")))] "" "convert %0,%1,0,3,0,1") (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (fix:SI (match_operand:DF 1 "register_operand" "r")))] "" "convert %0,%1,0,3,0,2") (define_insn "fixuns_truncsfsi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))] "" "convert %0,%1,1,3,0,1") (define_insn "fixuns_truncdfsi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))] "" "convert %0,%1,1,3,0,2") (define_insn "truncdfsf2" [(set (match_operand:SF 0 "register_operand" "=r") (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))] "" "convert %0,%1,0,4,1,2") (define_insn "extendsfdf2" [(set (match_operand:DF 0 "register_operand" "=r") (float_extend:DF (match_operand:SF 1 "register_operand" "r")))] "" "convert %0,%1,0,4,2,1") (define_insn "floatsisf2" [(set (match_operand:SF 0 "register_operand" "=r") (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "convert %0,%1,0,4,1,0") (define_insn "floatsidf2" [(set (match_operand:DF 0 "register_operand" "=r") (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "convert %0,%1,0,4,2,0") (define_insn "floatunssisf2" [(set (match_operand:SF 0 "register_operand" "=r") (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "convert %0,%1,1,4,1,0") (define_insn "floatunssidf2" [(set (match_operand:DF 0 "register_operand" "=r") (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "convert %0,%1,1,4,2,0") ;; CPxxx, DEQ, DGT, DGE, FEQ, FGT, FGE (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_operator 3 "comparison_operator" [(match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "srcb_operand" "rI")]))] "" "cp%J3 %0,%1,%2") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_operator 3 "fp_comparison_operator" [(match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r")]))] "" "f%J3 %0,%1,%2" [(set_attr "type" "fadd")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_operator 3 "fp_comparison_operator" [(match_operand:DF 1 "register_operand" "r") (match_operand:DF 2 "register_operand" "r")]))] "" "d%J3 %0,%1,%2" [(set_attr "type" "fadd")]) ;; DADD (define_expand "adddf3" [(set (match_operand:DF 0 "register_operand" "") (plus:DF (match_operand:DF 1 "register_operand" "") (match_operand:DF 2 "register_operand" "")))] "" "") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r") (plus:DF (match_operand:DF 1 "register_operand" "%r") (match_operand:DF 2 "register_operand" "r")))] "! TARGET_29050 " "dadd %0,%1,%2" [(set_attr "type" "fadd")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,a") (plus:DF (match_operand:DF 1 "register_operand" "%r,r") (match_operand:DF 2 "register_operand" "r,0")))] "TARGET_29050" "@ dadd %0,%1,%2 dmac 8,%0,%1,%1" [(set_attr "type" "fadd,dam")]) ;; DDIV (define_insn "divdf3" [(set (match_operand:DF 0 "register_operand" "=r") (div:DF (match_operand:DF 1 "register_operand" "=r") (match_operand:DF 2 "register_operand" "r")))] "" "ddiv %0,%1,%2" [(set_attr "type" "ddiv")]) ;; DIVIDE ;; ;; We must set Q to the sign extension of the dividend first. For MOD, we ;; must get the remainder from Q. ;; ;; For divmod: operand 1 is divided by operand 2; quotient goes to operand ;; 0 and remainder to operand 3. (define_expand "divmodsi4" [(set (match_dup 4) (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") (const_int 31))) (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") (div:SI (match_dup 1) (match_operand:SI 2 "gpc_reg_operand" ""))) (set (match_operand:SI 3 "gpc_reg_operand" "") (mod:SI (match_dup 1) (match_dup 2))) (use (match_dup 4))])] "" " { operands[4] = gen_reg_rtx (SImode); }") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "gpc_reg_operand" "r"))) (set (match_operand:SI 3 "register_operand" "=q") (mod:SI (match_dup 1) (match_dup 2))) (use (match_operand:SI 4 "register_operand" "3"))] "" "divide %0,%1,%2") ;; DIVIDU ;; ;; Similar to DIVIDE. (define_expand "udivmodsi4" [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "gpc_reg_operand" ""))) (set (match_operand:SI 3 "gpc_reg_operand" "") (umod:SI (match_dup 1) (match_dup 2))) (use (const_int 0))])] "" "") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "gpc_reg_operand" "r"))) (set (match_operand:SI 3 "register_operand" "=q") (umod:SI (match_dup 1) (match_dup 2))) (use (match_operand:SI 4 "const_int_operand" "3"))] "" "dividu %0,%1,%2") ;; DMAC/DMSM (define_insn "" [(set (match_operand:DF 0 "register_operand" "=a,*r") (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r,A") (match_operand:DF 2 "register_operand" "r,r")) (match_operand:DF 3 "register_operand" "0,*r")))] "TARGET_29050" "@ dmac 0,%0,%1,%2 dmsm %0,%2,%3" [(set_attr "type" "dam")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=a") (plus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r")) (match_operand:DF 2 "register_operand" "r")) (match_operand:DF 3 "register_operand" "0")))] "TARGET_29050" "dmac 1,%0,%2,%1" [(set_attr "type" "dam")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=a") (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r") (match_operand:DF 2 "register_operand" "r")) (match_operand:DF 3 "register_operand" "0")))] "TARGET_29050" "dmac 2,%0,%1,%2" [(set_attr "type" "dam")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=a") (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "r") (neg:DF (match_operand:DF 2 "register_operand" "r"))) (match_operand:DF 3 "register_operand" "0")))] "TARGET_29050" "dmac 3,%0,%1,%2" [(set_attr "type" "dam")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=a") (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r")) (match_operand:DF 2 "register_operand" "r")))] "TARGET_29050" "dmac 5,%0,%2,%1" [(set_attr "type" "dam")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=a") (minus:DF (neg:DF (match_operand:DF 1 "register_operand" "r")) (match_operand:DF 2 "register_operand" "0")))] "TARGET_29050" "dmac 11,%0,%1,%1" [(set_attr "type" "dam")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=a") (neg:DF (plus:DF (match_operand:DF 1 "register_operand" "%r") (match_operand:DF 2 "register_operand" "0"))))] "TARGET_29050" "dmac 11,%0,%1,%1" [(set_attr "type" "dam")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,r,a") (neg:DF (match_operand:DF 1 "register_operand" "0,r,r"))) (clobber (match_scratch:SI 2 "=&r,&r,X"))] "TARGET_29050" "@ cpeq %2,gr1,gr1\;xor %0,%1,%2 cpeq %2,gr1,gr1\;xor %0,%1,%2\;sll %L0,%L1,0 dmac 13,%0,%1,%1" [(set_attr "type" "multi,multi,dam")]) ;; DMUL (define_expand "muldf3" [(set (match_operand:DF 0 "register_operand" "") (mult:DF (match_operand:DF 1 "register_operand" "") (match_operand:DF 2 "register_operand" "")))] "" "") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r") (mult:DF (match_operand:DF 1 "register_operand" "%r") (match_operand:DF 2 "register_operand" "r")))] "! TARGET_29050" "dmul %0,%1,%2" [(set_attr "type" "dmul")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,a") (mult:DF (match_operand:DF 1 "register_operand" "%r,r") (match_operand:DF 2 "register_operand" "r,r")))] "TARGET_29050" "@ dmul %0,%1,%2 dmac 4,%0,%1,%2" [(set_attr "type" "dmul,dam")]) ;; DSUB (define_expand "subdf3" [(set (match_operand:DF 0 "register_operand" "=r") (minus:DF (match_operand:DF 1 "register_operand" "r") (match_operand:DF 2 "register_operand" "r")))] "" "") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r") (minus:DF (match_operand:DF 1 "register_operand" "r") (match_operand:DF 2 "register_operand" "r")))] "! TARGET_29050" "dsub %0,%1,%2" [(set_attr "type" "fadd")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,a,a") (minus:DF (match_operand:DF 1 "register_operand" "r,0,r") (match_operand:DF 2 "register_operand" "r,r,0")))] "TARGET_29050" "@ dsub %0,%1,%2 dmac 9,%0,%2,%2 dmac 10,%0,%1,%1" [(set_attr "type" "fadd,dam,dam")]) ;; EXBYTE (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI") (const_int -256)) (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") (const_int 8) (ashift:PSI (match_operand:PSI 3 "register_operand" "b") (const_int 3)))))] "" "exbyte %0,%2,%1") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 8) (ashift:PSI (match_operand:PSI 2 "register_operand" "b") (const_int 3))))] "" "exbyte %0,%1,0") (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 8) (match_operand:PSI 1 "const_24_operand" "")) (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") (const_int 8) (ashift:PSI (match_operand:PSI 3 "register_operand" "b") (const_int 3))))] "" "exbyte %0,%2,%0") (define_expand "extzv" [(set (match_operand:SI 0 "gpc_reg_operand" "") (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "general_operand" "") (match_operand:SI 3 "general_operand" "")))] "" " { int size, pos; if (GET_CODE (operands[2]) != CONST_INT || GET_CODE (operands[3]) != CONST_INT) FAIL; size = INTVAL (operands[2]); pos = INTVAL (operands[3]); /* Can't do this unless a byte extraction. If extracting the high or low byte, don't do this because a shift or AND is shorter. Don't do 16-bit extracts, since the only two are the high and low ends, and it is faster to do them with CONSTH and SRL. */ if (size != 8 || (pos != 8 && pos != 16)) FAIL; operands[3] = gen_rtx (ASHIFT, PSImode, force_reg (PSImode, GEN_INT (pos / 8)), GEN_INT (3)); }") ;; EXHW (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI") (const_int -65536)) (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") (const_int 16) (ashift:PSI (match_operand:PSI 3 "register_operand" "b") (const_int 3)))))] "" "exhw %0,%2,%1") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 16) (ashift:PSI (match_operand:PSI 2 "register_operand" "b") (const_int 3))))] "" "exhw %0,%1,0") (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 16) (match_operand:PSI 1 "const_16_operand" "")) (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") (const_int 16) (ashift:PSI (match_operand:PSI 3 "register_operand" "b") (const_int 3))))] "" "exhw %0,%2,%0") ;; EXHWS ;; ;; This is probably unused. The high-order 16-bits are obtained with an SRA ;; insn. The low-order 16 bits are a sign-extend, which is a pair of ;; shifts. Setting BP followed by the insn is equivalent, so we don't ;; bother going to any trouble to generate this insn. (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (sign_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 16) (ashift:PSI (match_operand:PSI 2 "register_operand" "b") (const_int 3))))] "" "exhws %0,%1") ;; EXTRACT (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:PSI 2 "register_operand" "f")))] "" "extract %0,%1,%1") (define_expand "rotlsi3" [(set (match_dup 3) (match_operand:SI 2 "gpc_reg_or_immediate_operand" "")) (set (match_operand:SI 0 "gpc_reg_operand" "") (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_dup 3)))] "" " { operands[2] = gen_lowpart (PSImode, operands[2]); operands[3] = gen_reg_rtx (PSImode); }") ;; It would be nice to be able to have a define_split corresponding to the ;; above, but there is no way to tell combine we need a PSImode temporary. ;; If we put a (clobber (scratch:PSI)) there, combine would merge the above ;; two insns. This is bad because it then thinks only one insn is needed. ;; FADD (define_expand "addsf3" [(set (match_operand:SF 0 "register_operand" "") (plus:SF (match_operand:SF 1 "register_operand" "") (match_operand:SF 2 "register_operand" "")))] "" "") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=r") (plus:SF (match_operand:SF 1 "register_operand" "%r") (match_operand:SF 2 "register_operand" "r")))] "! TARGET_29050" "fadd %0,%1,%2" [(set_attr "type" "fadd")]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=r,a") (plus:SF (match_operand:SF 1 "register_operand" "%r,r") (match_operand:SF 2 "register_operand" "r,0")))] "TARGET_29050" "@ fadd %0,%1,%2 fmac 8,%0,%1,%1" [(set_attr "type" "fadd,fam")]) ;; FDIV (define_insn "divsf3" [(set (match_operand:SF 0 "register_operand" "=r") (div:SF (match_operand:SF 1 "register_operand" "=r") (match_operand:SF 2 "register_operand" "r")))] "" "fdiv %0,%1,%2" [(set_attr "type" "fdiv")]) ;; FDMUL (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r") (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "%r")) (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))] "" "fdmul %0,%1,%2") ;; FMAC/FMSM (define_insn "" [(set (match_operand:SF 0 "register_operand" "=a,*r") (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r,A") (match_operand:SF 2 "register_operand" "r,r")) (match_operand:SF 3 "register_operand" "0,*r")))] "TARGET_29050" "@ fmac 0,%0,%1,%2 fmsm %0,%2,%3" [(set_attr "type" "fam")]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=a") (plus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) (match_operand:SF 2 "register_operand" "r")) (match_operand:SF 3 "register_operand" "0")))] "TARGET_29050" "fmac 1,%0,%2,%1" [(set_attr "type" "fam")]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=a") (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r") (match_operand:SF 2 "register_operand" "r")) (match_operand:SF 3 "register_operand" "0")))] "TARGET_29050" "fmac 2,%0,%1,%2" [(set_attr "type" "fam")]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=a") (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) (match_operand:SF 2 "register_operand" "r")) (match_operand:SF 3 "register_operand" "0")))] "TARGET_29050" "fmac 3,%0,%2,%1" [(set_attr "type" "fam")]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=a") (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) (match_operand:SF 2 "register_operand" "r")))] "TARGET_29050" "fmac 5,%0,%2,%1" [(set_attr "type" "fam")]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=a") (minus:SF (neg:SF (match_operand:SF 1 "register_operand" "%r")) (match_operand:SF 2 "register_operand" "0")))] "TARGET_29050" "fmac 11,%0,%1,%1" [(set_attr "type" "fam")]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=a") (neg:SF (plus:SF (match_operand:SF 1 "register_operand" "%r") (match_operand:SF 2 "register_operand" "0"))))] "TARGET_29050" "fmac 11,%0,%1,%1" [(set_attr "type" "fam")]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=r,a") (neg:SF (match_operand:SF 1 "register_operand" "r,r"))) (clobber (match_scratch:SI 2 "=&r,X"))] "TARGET_29050" "@ cpeq %2,gr1,gr1\;xor %0,%1,%2 fmac 13,%0,%1,%1" [(set_attr "type" "multi,fam")]) ;; FMUL (define_expand "mulsf3" [(set (match_operand:SF 0 "register_operand" "") (mult:SF (match_operand:SF 1 "register_operand" "") (match_operand:SF 2 "register_operand" "")))] "" "") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=r") (mult:SF (match_operand:SF 1 "register_operand" "%r") (match_operand:SF 2 "register_operand" "r")))] "! TARGET_29050" "fmul %0,%1,%2" [(set_attr "type" "fmul")]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=r,a") (mult:SF (match_operand:SF 1 "register_operand" "%r,r") (match_operand:SF 2 "register_operand" "r,r")))] "TARGET_29050" "@ fmul %0,%1,%2 fmac 4,%0,%1,%2" [(set_attr "type" "fmul,fam")]) ;; FSUB (define_expand "subsf3" [(set (match_operand:SF 0 "register_operand" "") (minus:SF (match_operand:SF 1 "register_operand" "") (match_operand:SF 2 "register_operand" "")))] "" "") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=r") (minus:SF (match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r")))] "! TARGET_29050" "fsub %0,%1,%2" [(set_attr "type" "fadd")]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=r,a,a") (minus:SF (match_operand:SF 1 "register_operand" "r,0,r") (match_operand:SF 2 "register_operand" "r,r,0")))] "TARGET_29050" "@ fsub %0,%1,%2 fmac 9,%0,%2,%2 fmac 10,%0,%1,%1" [(set_attr "type" "fadd,fam,fam")]) ;; INBYTE (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 8) (ashift:PSI (match_operand:PSI 2 "register_operand" "b") (const_int 3))) (match_operand:SI 1 "srcb_operand" "rI"))] "" "inbyte %0,%0,%1") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (not:SI (ashift:SI (const_int 255) (ashift:PSI (match_operand:PSI 3 "register_operand" "b") (const_int 3)))) (match_operand:SI 1 "gpc_reg_operand" "r")) (ashift:SI (zero_extend:SI (match_operand:QI 2 "srcb_operand" "rI")) (ashift:PSI (match_dup 3) (const_int 3)))))] "" "inbyte %0,%1,%2") ;; INHW (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 16) (ashift:PSI (match_operand:PSI 2 "register_operand" "b") (const_int 3))) (match_operand:SI 1 "srcb_operand" "rI"))] "" "inhw %0,%0,%1") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (not:SI (ashift:SI (const_int 65535) (ashift:PSI (match_operand:PSI 3 "register_operand" "b") (const_int 3)))) (match_operand:SI 1 "gpc_reg_operand" "r")) (ashift:SI (zero_extend:SI (match_operand:HI 2 "srcb_operand" "rI")) (ashift:PSI (match_dup 3) (const_int 3)))))] "" "inhw %0,%1,%2") (define_expand "insv" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "") (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" "")) (match_operand:SI 3 "srcb_operand" ""))] "" " { int size, pos; if (GET_CODE (operands[1]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT) FAIL; size = INTVAL (operands[1]); pos = INTVAL (operands[2]); if ((size != 8 && size != 16) || pos % size != 0) FAIL; operands[2] = gen_rtx (ASHIFT, PSImode, force_reg (PSImode, GEN_INT (pos / 8)), GEN_INT (3)); }") ;; LOAD (also used by move insn). (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int -4)))) (set (match_operand:PSI 2 "register_operand" "=b") (truncate:PSI (match_dup 1)))] "! TARGET_DW_ENABLE" "load 0,16,%0,%1" [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] "TARGET_DW_ENABLE" "load 0,1,%0,%1" [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:HI 0 "gpc_reg_operand" "=r") (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] "TARGET_DW_ENABLE" "load 0,1,%0,%1" [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] "TARGET_DW_ENABLE" "load 0,2,%0,%1" [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))) (clobber (match_scratch:PSI 2 "=&b"))] "TARGET_DW_ENABLE" "load 0,17,%0,%1" [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:HI 0 "gpc_reg_operand" "=r") (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))) (clobber (match_scratch:PSI 2 "=&b"))] "TARGET_DW_ENABLE" "load 0,17,%0,%1" [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))) (clobber (match_scratch:PSI 2 "=&b"))] "TARGET_DW_ENABLE" "load 0,18,%0,%1" [(set_attr "type" "load")]) ;; LOADM (define_expand "load_multiple" [(set (match_dup 4) (match_operand:PSI 2 "const_int_operand" "")) (match_par_dup 3 [(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))])] "" " { int regno; int count; rtx from; int i; /* Support only loading a constant number of hard registers from memory. */ if (GET_CODE (operands[2]) != CONST_INT || operands[2] == const1_rtx || GET_CODE (operands[1]) != MEM || GET_CODE (operands[0]) != REG || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER) FAIL; count = INTVAL (operands[2]); regno = REGNO (operands[0]); /* CR gets set to the number of registers minus one. */ operands[2] = GEN_INT(count - 1); operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2)); from = memory_address (SImode, XEXP (operands[1], 0)); XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno), gen_rtx (MEM, SImode, from)); operands[4] = gen_reg_rtx (PSImode); XVECEXP (operands[3], 0, 1) = gen_rtx (USE, VOIDmode, operands[4]); XVECEXP (operands[3], 0, 2) = gen_rtx (CLOBBER, VOIDmode, operands[4]); for (i = 1; i < count; i++) XVECEXP (operands[3], 0, i + 2) = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i), gen_rtx (MEM, SImode, plus_constant (from, i * 4))); }") ;; Indicate that CR is used and is then clobbered. (define_insn "" [(set (match_operand 0 "gpc_reg_operand" "=r") (match_operand 1 "memory_operand" "m")) (use (match_operand:PSI 2 "register_operand" "+c")) (clobber (match_dup 2))] "GET_MODE (operands[0]) == GET_MODE (operands[1]) && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD" "loadm 0,0,%0,%1" [(set_attr "type" "load")]) (define_insn "" [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 1 "gpc_reg_operand" "=r") (match_operand:SI 2 "memory_operand" "m")) (use (match_operand:PSI 3 "register_operand" "+c")) (clobber (match_dup 3))])] "" "loadm 0,0,%1,%2" [(set_attr "type" "load")]) ;; MTSR (used also by move insn) (define_insn "" [(set (match_operand:SI 0 "spec_reg_operand" "=*h,*h") (and:SI (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i") (match_operand:SI 2 "const_int_operand" "n,n")))] "masks_bits_for_special (operands[0], operands[2])" "@ mtsr %0,%1 mtsrim %0,%1") (define_insn "" [(set (match_operand:PSI 0 "register_operand" "=h,h") (truncate:PSI (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i")))] "" "@ mtsr %0,%1 mtsrim %0,%1") ;; MULTIPLY, MULTM, MULTMU (define_insn "mulsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 3 "=&q"))] "" "multiply %0,%1,%2") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (subreg:SI (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0)) (clobber (match_scratch:SI 3 "=&q"))] "" "multm %0,%1,%2") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (subreg:SI (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0)) (clobber (match_scratch:SI 3 "=&q"))] "" "multmu %0,%1,%2") (define_insn "mulsidi3" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) (clobber (match_scratch:SI 3 "=&q"))] "" "multiply %L0,%1,%2\;multm %0,%1,%2" [(set_attr "type" "multi")]) (define_split [(set (match_operand:DI 0 "gpc_reg_operand" "") (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "")))) (clobber (reg:SI 180))] "reload_completed" [(parallel [(set (match_dup 3) (mult:SI (match_dup 1) (match_dup 2))) (clobber (reg:SI 180))]) (parallel [(set (match_dup 4) (subreg:SI (mult:DI (sign_extend:DI (match_dup 1)) (sign_extend:DI (match_dup 2))) 0)) (clobber (reg:SI 180))])] " { operands[3] = operand_subword (operands[0], 1, 1, DImode); operands[4] = operand_subword (operands[1], 0, 1, DImode); } ") (define_insn "umulsidi3" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) (clobber (match_scratch:SI 3 "=&q"))] "" "multiplu %L0,%1,%2\;multmu %0,%1,%2" [(set_attr "type" "multi")]) (define_split [(set (match_operand:DI 0 "gpc_reg_operand" "") (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "")))) (clobber (reg:SI 180))] "reload_completed" [(parallel [(set (match_dup 3) (mult:SI (match_dup 1) (match_dup 2))) (clobber (reg:SI 180))]) (parallel [(set (match_dup 4) (subreg:SI (mult:DI (zero_extend:DI (match_dup 1)) (zero_extend:DI (match_dup 2))) 0)) (clobber (reg:SI 180))])] " { operands[3] = operand_subword (operands[0], 1, 1, DImode); operands[4] = operand_subword (operands[1], 0, 1, DImode); } ") ;; NAND (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) (not:SI (match_operand:SI 2 "srcb_operand" "rI"))))] "" "nand %0,%1,%2") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (match_operand:SI 2 "const_int_operand" "K")))] "((unsigned) ~ INTVAL (operands[2])) < 256" "nand %0,%1,%C2") ;; NOR (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) (not:SI (match_operand:SI 2 "srcb_operand" "rI"))))] "" "nor %0,%1,%2") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (match_operand:SI 2 "const_int_operand" "K")))] "((unsigned) ~ INTVAL (operands[2])) < 256" "nor %0,%1,%C2") (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "nor %0,%1,0") ;; OR/ORN (define_expand "iorsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "") (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "srcb_operand" "")))] "" "") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "srcb_operand" "rI")))] "! TARGET_29050" "or %0,%1,%2") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") (match_operand:SI 2 "srcb_operand" "rI,K")))] "TARGET_29050" "@ or %0,%1,%2 orn %0,%1,%C2") ;; SLL (also used by move insn) (define_insn "nop" [(const_int 0)] "" "aseq 0x40,gr1,gr1") (define_insn "ashlsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:QI 2 "srcb_operand" "rn")))] "" "sll %0,%1,%Q2") ;; SQRT (define_insn "sqrtsf2" [(set (match_operand:SF 0 "gpc_reg_operand" "=r") (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] "TARGET_29050" "sqrt %0,%1,1" [(set_attr "type" "fsqrt")]) (define_insn "sqrtdf2" [(set (match_operand:DF 0 "gpc_reg_operand" "=r") (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "r")))] "TARGET_29050" "sqrt %0,%1,2" [(set_attr "type" "dsqrt")]) ;; SRA (define_insn "ashrsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:QI 2 "srcb_operand" "rn")))] "" "sra %0,%1,%Q2") ;; SRL (define_insn "lshrsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:QI 2 "srcb_operand" "rn")))] "" "srl %0,%1,%Q2") ;; STORE ;; ;; These somewhat bogus patterns exist to set OPT = 001/010 for partial-word ;; stores on systems with DW not set. (define_insn "" [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r") (const_int -4))) (match_operand:SI 1 "gpc_reg_operand" "r"))] "! TARGET_DW_ENABLE" "store 0,1,%1,%0" [(set_attr "type" "store")]) (define_insn "" [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r") (const_int -3))) (match_operand:SI 1 "gpc_reg_operand" "r"))] "! TARGET_DW_ENABLE" "store 0,2,%1,%0" [(set_attr "type" "store")]) ;; STOREM (define_expand "store_multiple" [(use (match_operand 0 "" "")) (use (match_operand 1 "" "")) (use (match_operand 2 "" ""))] "" " { rtx pat; if (TARGET_NO_STOREM_BUG) pat = gen_store_multiple_no_bug (operands[0], operands[1], operands[2]); else pat = gen_store_multiple_bug (operands[0], operands[1], operands[2]); if (pat) emit_insn (pat); else FAIL; DONE; }") (define_expand "store_multiple_no_bug" [(set (match_dup 4) (match_operand:PSI 2 "const_int_operand" "")) (match_par_dup 3 [(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))])] "" " { int regno; int count; rtx from; int i; /* Support only storing a constant number of hard registers to memory. */ if (GET_CODE (operands[2]) != CONST_INT || operands[2] == const1_rtx || GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != REG || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) FAIL; count = INTVAL (operands[2]); regno = REGNO (operands[1]); /* CR gets set to the number of registers minus one. */ operands[2] = GEN_INT(count - 1); operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2)); from = memory_address (SImode, XEXP (operands[0], 0)); XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, from), gen_rtx (REG, SImode, regno)); operands[4] = gen_reg_rtx (PSImode); XVECEXP (operands[3], 0, 1) = gen_rtx (USE, VOIDmode, operands[4]); XVECEXP (operands[3], 0, 2) = gen_rtx (CLOBBER, VOIDmode, operands[4]); for (i = 1; i < count; i++) XVECEXP (operands[3], 0, i + 2) = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, plus_constant (from, i * 4)), gen_rtx (REG, SImode, regno + i)); }") (define_expand "store_multiple_bug" [(match_par_dup 3 [(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" "")) (use (match_operand:SI 2 "" ""))])] "" " { int regno; int count; rtx from; int i; /* Support only storing a constant number of hard registers to memory. */ if (GET_CODE (operands[2]) != CONST_INT || operands[2] == const1_rtx || GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != REG || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) FAIL; count = INTVAL (operands[2]); regno = REGNO (operands[1]); operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1)); from = memory_address (SImode, XEXP (operands[0], 0)); XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, from), gen_rtx (REG, SImode, regno)); XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, PSImode)); for (i = 1; i < count; i++) XVECEXP (operands[3], 0, i + 1) = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, plus_constant (from, i * 4)), gen_rtx (REG, SImode, regno + i)); }") (define_insn "" [(set (match_operand 0 "memory_operand" "=m") (match_operand 1 "gpc_reg_operand" "r")) (clobber (match_scratch:PSI 2 "=&c"))] "!TARGET_NO_STOREM_BUG && GET_MODE (operands[0]) == GET_MODE (operands[1]) && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD" "mtsrim cr,%S1\;storem 0,0,%1,%0" [(set_attr "type" "multi")]) (define_insn "" [(match_parallel 0 "store_multiple_operation" [(set (match_operand:SI 1 "memory_operand" "=m") (match_operand:SI 2 "gpc_reg_operand" "r")) (clobber (match_scratch:PSI 3 "=&c"))])] "!TARGET_NO_STOREM_BUG" "mtsrim cr,%V0\;storem 0,0,%2,%1" [(set_attr "type" "multi")]) (define_insn "" [(set (match_operand 0 "memory_operand" "=m") (match_operand 1 "gpc_reg_operand" "r")) (use (match_operand:PSI 2 "register_operand" "+c")) (clobber (match_dup 2))] "TARGET_NO_STOREM_BUG && GET_MODE (operands[0]) == GET_MODE (operands[1]) && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD" "storem 0,0,%1,%0" [(set_attr "type" "store")]) (define_insn "" [(match_parallel 0 "store_multiple_operation" [(set (match_operand:SI 1 "memory_operand" "=m") (match_operand:SI 2 "gpc_reg_operand" "r")) (use (match_operand:PSI 3 "register_operand" "+c")) (clobber (match_dup 3))])] "TARGET_NO_STOREM_BUG" "storem 0,0,%2,%1" [(set_attr "type" "store")]) ;; SUB ;; ;; Either operand can be a register or an 8-bit constant, but both cannot be ;; constants (can't usually occur anyway). (define_expand "subsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "") (minus:SI (match_operand:SI 1 "srcb_operand" "") (match_operand:SI 2 "srcb_operand" "")))] "" " { if (GET_CODE (operands[0]) == CONST_INT && GET_CODE (operands[1]) == CONST_INT) operands[1] = force_reg (SImode, operands[1]); }") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (minus:SI (match_operand:SI 1 "srcb_operand" "r,I") (match_operand:SI 2 "srcb_operand" "rI,r")))] "register_operand (operands[1], SImode) || register_operand (operands[2], SImode)" "@ sub %0,%1,%2 subr %0,%2,%1") (define_insn "subdi3" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") (match_operand:DI 2 "gpc_reg_operand" "r")))] "" "sub %L0,%L1,%L2\;subc %0,%1,%2" [(set_attr "type" "multi")]) ;; SUBR (also used above in SUB) (define_insn "negdi2" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] "" "subr %L0,%L1,0\;subrc %0,%1,0" [(set_attr "type" "multi")]) (define_insn "negsi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "subr %0,%1,0") ;; XNOR (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "srcb_operand" "rI"))))] "" "xnor %0,%1,%2") ;; XOR (define_insn "xorsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "srcb_operand" "rI")))] "" "xor %0,%1,%2") ;; Can use XOR to negate floating-point values, but we are better off not doing ;; it that way on the 29050 so it can combine with the fmac insns. (define_expand "negsf2" [(parallel [(set (match_operand:SF 0 "register_operand" "") (neg:SF (match_operand:SF 1 "register_operand" ""))) (clobber (match_scratch:SI 2 ""))])] "" " { rtx result; rtx target; if (! TARGET_29050) { target = operand_subword_force (operands[0], 0, SFmode); result = expand_binop (SImode, xor_optab, operand_subword_force (operands[1], 0, SFmode), GEN_INT(0x80000000), target, 0, OPTAB_WIDEN); if (result == 0) abort (); if (result != target) emit_move_insn (result, target); /* Make a place for REG_EQUAL. */ emit_move_insn (operands[0], operands[0]); DONE; } }") (define_expand "negdf2" [(parallel [(set (match_operand:DF 0 "register_operand" "") (neg:DF (match_operand:DF 1 "register_operand" ""))) (clobber (match_scratch:SI 2 ""))])] "" " { rtx result; rtx target; rtx insns; if (! TARGET_29050) { start_sequence (); target = operand_subword (operands[0], 0, 1, DFmode); result = expand_binop (SImode, xor_optab, operand_subword_force (operands[1], 0, DFmode), GEN_INT(0x80000000), target, 0, OPTAB_WIDEN); if (result == 0) abort (); if (result != target) emit_move_insn (result, target); emit_move_insn (operand_subword (operands[0], 1, 1, DFmode), operand_subword_force (operands[1], 1, DFmode)); insns = get_insns (); end_sequence (); emit_no_conflict_block (insns, operands[0], operands[1], 0, 0); DONE; } }") ;; Sign extend and truncation operations. (define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "gpc_reg_operand" "=r") (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] "" "and %0,%1,255") (define_insn "zero_extendqisi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] "" "and %0,%1,255") (define_insn "zero_extendhisi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")))] "" "consth %0,0") (define_expand "extendqihi2" [(set (match_dup 2) (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") (const_int 24))) (set (match_operand:HI 0 "gpc_reg_operand" "") (ashiftrt:SI (match_dup 2) (const_int 24)))] "" " { operands[0] = gen_lowpart (SImode, operands[0]); operands[1] = gen_lowpart (SImode, operands[1]); operands[2] = gen_reg_rtx (SImode); }") (define_expand "extendqisi2" [(set (match_dup 2) (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") (const_int 24))) (set (match_operand:SI 0 "gpc_reg_operand" "") (ashiftrt:SI (match_dup 2) (const_int 24)))] "" " { operands[1] = gen_lowpart (SImode, operands[1]); operands[2] = gen_reg_rtx (SImode); }") (define_expand "extendhisi2" [(set (match_dup 2) (ashift:SI (match_operand:HI 1 "gpc_reg_operand" "") (const_int 16))) (set (match_operand:SI 0 "gpc_reg_operand" "") (ashiftrt:SI (match_dup 2) (const_int 16)))] "" " { operands[1] = gen_lowpart (SImode, operands[1]); operands[2] = gen_reg_rtx (SImode); }") ;; Define the methods used to move data around. ;; ;; movsi: ;; ;; If storing into memory, force source into register. (define_expand "movsi" [(set (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))] "" " { if (GET_CODE (operands[0]) == MEM && ! gpc_reg_operand (operands[1], SImode)) operands[1] = copy_to_mode_reg (SImode, operands[1]); else if (spec_reg_operand (operands[0], SImode) && ! (register_operand (operands[1], SImode) || cint_16_operand (operands[1], SImode))) operands[1] = force_reg (SImode, operands[1]); }") (define_expand "movpsi" [(set (match_operand:PSI 0 "general_operand" "") (match_operand:PSI 1 "general_operand" ""))] "" " { if (GET_CODE (operands[0]) == MEM && ! gpc_reg_operand (operands[1], PSImode)) operands[1] = copy_to_mode_reg (PSImode, operands[1]); else if (spec_reg_operand (operands[0], PSImode) && ! (register_operand (operands[1], PSImode) || cint_16_operand (operands[1], PSImode))) operands[1] = force_reg (PSImode, operands[1]); }") (define_split [(set (match_operand:SI 0 "gpc_reg_operand" "") (match_operand:SI 1 "long_const_operand" ""))] "" [(set (match_dup 0) (and:SI (match_dup 1) (const_int 65535))) (set (match_dup 0) (ior:SI (zero_extend:SI (match_dup 2)) (and:SI (match_dup 1) (const_int -65536))))] " operands[2] = gen_lowpart (HImode, operands[0]); ") ;; Subroutines to load/store halfwords. Operands 0 and 1 are the output and ;; input, respectively, except that the address is passed for a MEM instead ;; of the MEM itself and the short item is passed in QImode. ;; ;; Operand 2 is a scratch general register and operand 3 is a scratch register ;; used for BP. When called before reload, pseudos are passed for both ;; operands. During reload, R_TAV is used for the general register, and ;; a reload register of class BR_REGS (R_VP) for BP. ;; ;; We have two versions of the store operations, for when halfword writes are ;; supported and when they are not. (define_expand "loadhi" [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "") (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "") (const_int -4)))) (set (match_operand:PSI 3 "register_operand" "") (truncate:PSI (match_dup 1)))]) (set (match_operand:SI 0 "gpc_reg_operand" "") (zero_extract:SI (match_dup 2) (const_int 16) (ashift:PSI (match_dup 3) (const_int 3))))] "" "") (define_expand "storehinhww" [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "") (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "") (const_int -4)))) (set (match_operand:PSI 3 "register_operand" "") (truncate:PSI (match_dup 0)))]) (set (zero_extract:SI (match_dup 2) (const_int 16) (ashift:PSI (match_dup 3) (const_int 3))) (match_operand:SI 1 "gpc_reg_operand" "")) (set (mem:SI (match_dup 0)) (match_dup 2))] "" "") (define_expand "storehihww" [(set (match_operand:PSI 3 "register_operand" "") (truncate:PSI (match_operand:SI 0 "gpc_reg_operand" ""))) (set (match_operand:SI 2 "gpc_reg_operand" "") (ior:SI (and:SI (not:SI (ashift:SI (const_int 65535) (ashift:PSI (match_dup 3) (const_int 3)))) (match_operand:SI 1 "gpc_reg_operand" "")) (ashift:SI (zero_extend:SI (match_dup 4)) (ashift:PSI (match_dup 3) (const_int 3))))) (set (mem:SI (and:SI (match_dup 0) (const_int -3))) (match_dup 2))] "" " { operands[4] = gen_lowpart (HImode, operands[1]); }") (define_expand "movhi" [(set (match_operand:HI 0 "general_operand" "") (match_operand:HI 1 "general_operand" ""))] "" " { if (GET_CODE (operands[0]) == MEM) { if (! gpc_reg_operand (operands[1], HImode)) operands[1] = copy_to_mode_reg (HImode, operands[1]); if (! TARGET_DW_ENABLE) { rtx general = gen_reg_rtx (SImode); rtx bp = gen_reg_rtx (PSImode); rtx (*fcn) () = TARGET_BYTE_WRITES ? gen_storehihww : gen_storehinhww; rtx seq = (*fcn) (XEXP (operands[0], 0), gen_lowpart (SImode, operands[1]), general, bp); a29k_set_memflags (seq, operands[0]); emit_insn (seq); DONE; } } else if (GET_CODE (operands[1]) == MEM) { if (! TARGET_DW_ENABLE) { rtx general = gen_reg_rtx (SImode); rtx bp = gen_reg_rtx (PSImode); rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]), XEXP (operands[1], 0), general, bp); a29k_set_memflags (seq, operands[1]); emit_insn (seq); DONE; } } }") (define_expand "reload_inhi" [(parallel [(match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "reload_memory_operand" "m") (match_operand:PSI 2 "register_operand" "=b")])] "! TARGET_DW_ENABLE" " { rtx seq = gen_loadhi (gen_lowpart (SImode, operands[0]), a29k_get_reloaded_address (operands[1]), gen_rtx (REG, SImode, R_TAV), operands[2]); a29k_set_memflags (seq, operands[1]); emit_insn (seq); DONE; }") (define_expand "reload_outhi" [(parallel [(match_operand:SI 0 "reload_memory_operand" "=m") (match_operand:SI 1 "register_operand" "m") (match_operand:PSI 2 "register_operand" "=b")])] "! TARGET_DW_ENABLE" " { rtx (*fcn) () = TARGET_BYTE_WRITES ? gen_storehihww : gen_storehinhww; rtx seq = (*fcn) (a29k_get_reloaded_address (operands[0]), gen_lowpart (SImode, operands[1]), gen_rtx (REG, SImode, R_TAV), operands[2]); a29k_set_memflags (seq, operands[0]); emit_insn (seq); DONE; }") ;; Subroutines to load/store bytes. Operands 0 and 1 are the output and ;; input, respectively, except that the address is passed for a MEM instead ;; of the MEM itself and the short item is passed in QImode. ;; ;; Operand 2 is a scratch general register and operand 3 is a scratch register ;; used for BP. When called before reload, pseudos are passed for both ;; operands. During reload, R_TAV is used for the general register, and ;; a reload register of class BR_REGS (R_VP) for BP. ;; ;; We have two versions of the store operations, for when byte writes are ;; supported and when they are not. (define_expand "loadqi" [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "") (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "") (const_int -4)))) (set (match_operand:PSI 3 "register_operand" "") (truncate:PSI (match_dup 1)))]) (set (match_operand:SI 0 "gpc_reg_operand" "") (zero_extract:SI (match_dup 2) (const_int 8) (ashift:PSI (match_dup 3) (const_int 3))))] "" "") (define_expand "storeqinhww" [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "") (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "") (const_int -4)))) (set (match_operand:PSI 3 "register_operand" "") (truncate:PSI (match_dup 0)))]) (set (zero_extract:SI (match_dup 2) (const_int 8) (ashift:PSI (match_dup 3) (const_int 3))) (match_operand:SI 1 "gpc_reg_operand" "")) (set (mem:SI (match_dup 0)) (match_dup 2))] "" "") (define_expand "storeqihww" [(set (match_operand:PSI 3 "register_operand" "") (truncate:PSI (match_operand:SI 0 "gpc_reg_operand" ""))) (set (match_operand:SI 2 "gpc_reg_operand" "") (ior:SI (and:SI (not:SI (ashift:SI (const_int 255) (ashift:PSI (match_dup 3) (const_int 3)))) (match_operand:SI 1 "gpc_reg_operand" "")) (ashift:SI (zero_extend:SI (match_dup 4)) (ashift:PSI (match_dup 3) (const_int 3))))) (set (mem:SI (and:SI (match_dup 0) (const_int -4))) (match_dup 2))] "" " { operands[4] = gen_lowpart (QImode, operands[1]); }") (define_expand "movqi" [(set (match_operand:QI 0 "general_operand" "") (match_operand:QI 1 "general_operand" ""))] "" " { if (GET_CODE (operands[0]) == MEM) { if (! gpc_reg_operand (operands[1], QImode)) operands[1] = copy_to_mode_reg (QImode, operands[1]); if (! TARGET_DW_ENABLE) { rtx general = gen_reg_rtx (SImode); rtx bp = gen_reg_rtx (PSImode); rtx (*fcn) () = TARGET_BYTE_WRITES ? gen_storeqihww : gen_storeqinhww; rtx seq = (*fcn) (XEXP (operands[0], 0), gen_lowpart (SImode, operands[1]), general, bp); a29k_set_memflags (seq, operands[0]); emit_insn (seq); } } else if (GET_CODE (operands[1]) == MEM) { if (! TARGET_DW_ENABLE) { rtx general = gen_reg_rtx (SImode); rtx bp = gen_reg_rtx (PSImode); rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]), XEXP (operands[1], 0), general, bp); a29k_set_memflags (seq, operands[1]); emit_insn (seq); DONE; } } }") (define_expand "reload_inqi" [(parallel [(match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "reload_memory_operand" "m") (match_operand:PSI 2 "register_operand" "=b")])] "! TARGET_DW_ENABLE" " { rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]), a29k_get_reloaded_address (operands[1]), gen_rtx (REG, SImode, R_TAV), operands[2]); a29k_set_memflags (seq, operands[1]); emit_insn (seq); DONE; }") (define_expand "reload_outqi" [(parallel [(match_operand:SI 0 "reload_memory_operand" "=m") (match_operand:SI 1 "register_operand" "m") (match_operand:PSI 2 "register_operand" "=b")])] "! TARGET_DW_ENABLE" " { rtx (*fcn) () = TARGET_BYTE_WRITES ? gen_storeqihww : gen_storeqinhww; rtx seq = (*fcn) (a29k_get_reloaded_address (operands[0]), gen_lowpart (SImode, operands[1]), gen_rtx (REG, SImode, R_TAV), operands[2]); a29k_set_memflags (seq, operands[0]); emit_insn (seq); DONE; }") ;; Now the actual insns used to move data around. We include here the ;; DEFINE_SPLITs that may be needed. In some cases these will be ;; split again. For floating-point, if we can look inside the constant, ;; always split it. This can eliminate unnecessary insns. (define_insn "" [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m") (match_operand:SF 1 "in_operand" "r,E,F,m,r"))] "(gpc_reg_operand (operands[0], SFmode) || gpc_reg_operand (operands[1], SFmode)) && ! TARGET_29050" "@ sll %0,%1,0 # const %0,%1\;consth %0,%1 load 0,0,%0,%1 store 0,0,%1,%0" [(set_attr "type" "misc,multi,multi,load,store")]) (define_insn "" [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m,*a,r") (match_operand:SF 1 "in_operand" "r,E,F,m,r,r,*a"))] "(gpc_reg_operand (operands[0], SFmode) || gpc_reg_operand (operands[1], SFmode)) && TARGET_29050" "@ sll %0,%1,0 # const %0,%1\;consth %0,%1 load 0,0,%0,%1 store 0,0,%1,%0 mtacc %1,1,%0 mfacc %0,1,%1" [(set_attr "type" "misc,multi,multi,load,store,fadd,fadd")]) ;; Turn this into SImode. It will then be split up that way. (define_split [(set (match_operand:SF 0 "register_operand" "") (match_operand:SF 1 "float_const_operand" ""))] "HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT" [(set (match_dup 0) (match_dup 1))] " { operands[0] = operand_subword (operands[0], 0, 0, SFmode); operands[1] = operand_subword (operands[1], 0, 0, SFmode); if (operands[0] == 0 || operands[1] == 0) FAIL; }") (define_insn "" [(set (match_operand:DF 0 "out_operand" "=?r,?r,r,m") (match_operand:DF 1 "in_operand" "rE,F,m,r")) (clobber (match_scratch:PSI 2 "=X,X,&c,&c"))] "(gpc_reg_operand (operands[0], DFmode) || gpc_reg_operand (operands[1], DFmode)) && ! TARGET_29050" "@ # const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1 mtsrim cr,1\;loadm 0,0,%0,%1 mtsrim cr,1\;storem 0,0,%1,%0" [(set_attr "type" "multi")]) (define_insn "" [(set (match_operand:DF 0 "out_operand" "=?r,?r,r,m,?*a,?r") (match_operand:DF 1 "in_operand" "rE,F,m,r,r,*a")) (clobber (match_scratch:PSI 2 "=X,X,&c,&c,X,X"))] "(gpc_reg_operand (operands[0], DFmode) || gpc_reg_operand (operands[1], DFmode)) && TARGET_29050" "@ # const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1 mtsrim cr,1\;loadm 0,0,%0,%1 mtsrim cr,1\;storem 0,0,%1,%0 mtacc %1,2,%0 mfacc %0,2,%1" [(set_attr "type" "multi,multi,multi,multi,fadd,fadd")]) ;; Split register-register copies and constant loads into two SImode loads, ;; one for each word. In the constant case, they will get further split. ;; Don't so this until register allocation, though, since it will ;; interfere with register allocation. Normally copy the lowest-addressed ;; word first; the exception is if we are copying register to register and ;; the lowest register of the first operand is the highest register of the ;; second operand. (define_split [(set (match_operand:DF 0 "gpc_reg_operand" "") (match_operand:DF 1 "gpc_reg_or_float_constant_operand" "")) (clobber (match_scratch:PSI 2 ""))] "reload_completed" [(set (match_dup 3) (match_dup 4)) (set (match_dup 5) (match_dup 6))] " { if (GET_CODE (operands[1]) == REG && REGNO (operands[0]) == REGNO (operands[1]) + 1) { operands[3] = operand_subword (operands[0], 1, 1, DFmode); operands[4] = operand_subword (operands[1], 1, 1, DFmode); operands[5] = operand_subword (operands[0], 0, 1, DFmode); operands[6] = operand_subword (operands[1], 0, 1, DFmode); } else { operands[3] = operand_subword (operands[0], 0, 1, DFmode); operands[4] = operand_subword (operands[1], 0, 1, DFmode); operands[5] = operand_subword (operands[0], 1, 1, DFmode); operands[6] = operand_subword (operands[1], 1, 1, DFmode); } if (operands[3] == 0 || operands[4] == 0 || operands[5] == 0 || operands[6] == 0) FAIL; }") ;; Split memory loads and stores into the MTSR and LOADM/STOREM. (define_split [(set (match_operand:DF 0 "out_operand" "") (match_operand:DF 1 "in_operand" "")) (clobber (reg:PSI 179))] "TARGET_NO_STOREM_BUG && (memory_operand (operands[0], DFmode) || memory_operand (operands[1], DFmode))" [(set (reg:PSI 179) (const_int 1)) (parallel [(set (match_dup 0) (match_dup 1)) (use (reg:PSI 179)) (clobber (reg:PSI 179))])] "") ;; DI move is similar to DF move. (define_insn "" [(set (match_operand:DI 0 "out_operand" "=?r,r,m") (match_operand:DI 1 "in_operand" "rn,m,r")) (clobber (match_scratch:PSI 2 "=X,&c,&c"))] "(gpc_reg_operand (operands[0], DImode) || gpc_reg_operand (operands[1], DImode))" "@ # mtsrim cr,1\;loadm 0,0,%0,%1 mtsrim cr,1\;storem 0,0,%1,%0" [(set_attr "type" "multi")]) (define_split [(set (match_operand:DI 0 "gpc_reg_operand" "") (match_operand:DI 1 "gpc_reg_or_integer_constant_operand" "")) (clobber (match_scratch:PSI 2 ""))] "reload_completed" [(set (match_dup 3) (match_dup 4)) (set (match_dup 5) (match_dup 6))] " { if (GET_CODE (operands[1]) == REG && REGNO (operands[0]) == REGNO (operands[1]) + 1) { operands[3] = operand_subword (operands[0], 1, 1, DImode); operands[4] = operand_subword (operands[1], 1, 1, DImode); operands[5] = operand_subword (operands[0], 0, 1, DImode); operands[6] = operand_subword (operands[1], 0, 1, DImode); } else { operands[3] = operand_subword (operands[0], 0, 1, DImode); operands[4] = operand_subword (operands[1], 0, 1, DImode); operands[5] = operand_subword (operands[0], 1, 1, DImode); operands[6] = operand_subword (operands[1], 1, 1, DImode); } }") (define_split [(set (match_operand:DI 0 "out_operand" "") (match_operand:DI 1 "in_operand" "")) (clobber (reg:PSI 179))] "TARGET_NO_STOREM_BUG && (memory_operand (operands[0], DImode) || memory_operand (operands[1], DImode))" [(set (reg:PSI 179) (const_int 1)) (parallel [(set (match_dup 0) (match_dup 1)) (use (reg:PSI 179)) (clobber (reg:PSI 179))])] "") ;; TImode moves are very similar to DImode moves, except that we can't ;; have constants. (define_insn "" [(set (match_operand:TI 0 "out_operand" "=?r,r,m") (match_operand:TI 1 "in_operand" "r,m,r")) (clobber (match_scratch:PSI 2 "=X,&c,&c"))] "(gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" "@ # mtsrim cr,3\;loadm 0,0,%0,%1 mtsrim cr,3\;storem 0,0,%1,%0" [(set_attr "type" "multi,multi,multi")]) (define_split [(set (match_operand:TI 0 "gpc_reg_operand" "") (match_operand:TI 1 "gpc_reg_operand" "")) (clobber (match_scratch:PSI 2 ""))] "reload_completed" [(set (match_dup 3) (match_dup 4)) (set (match_dup 5) (match_dup 6)) (set (match_dup 7) (match_dup 8)) (set (match_dup 9) (match_dup 10))] " { if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 && REGNO (operands[0]) <= REGNO (operands[1]) + 3) { operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 3); operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 3); operands[5] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2); operands[6] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); operands[7] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); operands[8] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); operands[9] = gen_rtx (REG, SImode, REGNO (operands[0])); operands[10] = gen_rtx (REG, SImode, REGNO (operands[1])); } else { operands[3] = gen_rtx (REG, SImode, REGNO (operands[0])); operands[4] = gen_rtx (REG, SImode, REGNO (operands[1])); operands[5] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); operands[6] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); operands[7] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2); operands[8] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); operands[9] = gen_rtx (REG, SImode, REGNO (operands[0]) + 3); operands[10] = gen_rtx (REG, SImode, REGNO (operands[1]) + 3); } }") (define_split [(set (match_operand:TI 0 "out_operand" "") (match_operand:TI 1 "in_operand" "")) (clobber (reg:PSI 179))] "TARGET_NO_STOREM_BUG && (memory_operand (operands[0], TImode) || memory_operand (operands[1], TImode))" [(set (reg:PSI 179) (const_int 3)) (parallel [(set (match_dup 0) (match_dup 1)) (use (reg:PSI 179)) (clobber (reg:PSI 179))])] "") (define_insn "" [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h") (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))] "(gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode) || (spec_reg_operand (operands[0], SImode) && cint_16_operand (operands[1], SImode))) && ! TARGET_29050" "@ sll %0,%1,0 const %0,%1 constn %0,%M1 cpeq %0,gr1,gr1 # load 0,0,%0,%1 mfsr %0,%1 store 0,0,%1,%0 mtsr %0,%1 mtsrim %0,%1" [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")]) (define_insn "" [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h") (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))] "(gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode) || (spec_reg_operand (operands[0], SImode) && cint_16_operand (operands[1], SImode))) && TARGET_29050" "@ sll %0,%1,0 const %0,%1 constn %0,%M1 consthz %0,%1 # load 0,0,%0,%1 mfsr %0,%1 store 0,0,%1,%0 mtsr %0,%1 mtsrim %0,%1" [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")]) (define_insn "" [(set (match_operand:PSI 0 "out_operand" "=*r,*r,*r,*r,m,h,h") (match_operand:PSI 1 "in_operand" "r,i,m,h,r,r,J"))] "(gpc_reg_operand (operands[0], PSImode) || gpc_reg_operand (operands[1], PSImode) || (spec_reg_operand (operands[0], PSImode) && cint_16_operand (operands[1], PSImode)))" "@ sll %0,%1,0 const %0,%1 load 0,0,%0,%1 mfsr %0,%1 store 0,0,%1,%0 mtsr %0,%1 mtsrim %0,%1" [(set_attr "type" "misc,multi,load,misc,store,misc,misc")]) (define_insn "" [(set (match_operand:HI 0 "out_operand" "=r,r,r,m,r,*h,*h") (match_operand:HI 1 "in_operand" "r,i,m,r,*h,r,i"))] "gpc_reg_operand (operands[0], HImode) || gpc_reg_operand (operands[1], HImode) || (spec_reg_operand (operands[0], HImode) && cint_16_operand (operands[1], HImode))" "@ sll %0,%1,0 const %0,%1 load 0,2,%0,%1 store 0,2,%1,%0 mfsr %0,%1 mtsr %0,%1 mtsrim %0,%1" [(set_attr "type" "misc,misc,load,store,misc,misc,misc")]) (define_insn "" [(set (match_operand:QI 0 "out_operand" "=r,r,r,m,r,*h,*h") (match_operand:QI 1 "in_operand" "r,i,m,r,*h,r,i"))] "gpc_reg_operand (operands[0], QImode) || gpc_reg_operand (operands[1], QImode) || (spec_reg_operand (operands[0], HImode) && cint_16_operand (operands[1], HImode))" "@ sll %0,%1,0 const %0,%1 load 0,1,%0,%1 store 0,1,%1,%0 mfsr %0,%1 mtsr %0,%1 mtsrim %0,%1" [(set_attr "type" "misc,misc,load,store,misc,misc,misc")]) ;; Define move insns for DI, TI, SF, and DF. ;; ;; In no case do we support mem->mem directly. ;; ;; For DI move of constant to register, split apart at this time since these ;; can require anywhere from 2 to 4 insns and determining which is complex. ;; ;; In other cases, handle similarly to SImode moves. ;; ;; However, indicate that DI, TI, and DF moves may clobber CR (reg 179). (define_expand "movdi" [(parallel [(set (match_operand:DI 0 "general_operand" "") (match_operand:DI 1 "general_operand" "")) (clobber (scratch:PSI))])] "" " { if (GET_CODE (operands[0]) == MEM) operands[1] = force_reg (DImode, operands[1]); }") (define_expand "movsf" [(set (match_operand:SF 0 "general_operand" "") (match_operand:SF 1 "general_operand" ""))] "" " { if (GET_CODE (operands[0]) == MEM) operands[1] = force_reg (SFmode, operands[1]); }") (define_expand "movdf" [(parallel [(set (match_operand:DF 0 "general_operand" "") (match_operand:DF 1 "general_operand" "")) (clobber (scratch:PSI))])] "" " { if (GET_CODE (operands[0]) == MEM) operands[1] = force_reg (DFmode, operands[1]); }") (define_expand "movti" [(parallel [(set (match_operand:TI 0 "general_operand" "") (match_operand:TI 1 "general_operand" "")) (clobber (scratch:PSI))])] "" " { if (GET_CODE (operands[0]) == MEM) operands[1] = force_reg (TImode, operands[1]); /* We can't handle constants in general because there is no rtl to represent 128 bit constants. Splitting happens to work for CONST_INTs so we split them for good code. Other constants will get forced to memory. */ if (GET_CODE (operands[1]) == CONST_INT) { rtx part0, part1, part2, part3; part0 = operand_subword (operands[0], 0, 1, TImode); part1 = operand_subword (operands[0], 1, 1, TImode); part2 = operand_subword (operands[0], 2, 1, TImode); part3 = operand_subword (operands[0], 3, 1, TImode); emit_move_insn (part0, const0_rtx); emit_move_insn (part1, const0_rtx); emit_move_insn (part2, const0_rtx); emit_move_insn (part3, const0_rtx); DONE; } else if (CONSTANT_P (operands[1])) { operands[1] = force_const_mem (TImode, operands[1]); if (! memory_address_p (TImode, XEXP (operands[1], 0)) && ! reload_in_progress) operands[1] = change_address (operands[1], TImode, XEXP (operands[1], 0)); } }") ;; Here are the variants of the above for use during reload. (define_expand "reload_indf" [(parallel [(set (match_operand:DF 0 "register_operand" "=r") (match_operand:DF 1 "reload_memory_operand" "m")) (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] "" "") (define_expand "reload_outdf" [(parallel [(set (match_operand:DF 0 "reload_memory_operand" "=m") (match_operand:DF 1 "register_operand" "r")) (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] "" "") (define_expand "reload_indi" [(parallel [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "reload_memory_operand" "m")) (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] "" "") (define_expand "reload_outdi" [(parallel [(set (match_operand:DI 0 "reload_memory_operand" "=m") (match_operand:DI 1 "register_operand" "r")) (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] "" "") (define_expand "reload_inti" [(parallel [(set (match_operand:TI 0 "register_operand" "=r") (match_operand:TI 1 "reload_memory_operand" "m")) (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] "" "") (define_expand "reload_outti" [(parallel [(set (match_operand:TI 0 "reload_memory_operand" "=m") (match_operand:TI 1 "register_operand" "r")) (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] "" "") ;; For compare operations, we simply store the comparison operands and ;; do nothing else. The following branch or scc insn will output whatever ;; is needed. (define_expand "cmpsi" [(set (cc0) (compare (match_operand:SI 0 "gpc_reg_operand" "") (match_operand:SI 1 "srcb_operand" "")))] "" " { a29k_compare_op0 = operands[0]; a29k_compare_op1 = operands[1]; a29k_compare_fp_p = 0; DONE; }") (define_expand "cmpsf" [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") (match_operand:SF 1 "gpc_reg_operand" "")))] "" " { a29k_compare_op0 = operands[0]; a29k_compare_op1 = operands[1]; a29k_compare_fp_p = 1; DONE; }") (define_expand "cmpdf" [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") (match_operand:DF 1 "gpc_reg_operand" "")))] "" " { a29k_compare_op0 = operands[0]; a29k_compare_op1 = operands[1]; a29k_compare_fp_p = 1; DONE; }") ;; We can generate bit-tests better if we use NE instead of EQ, but we ;; don't have an NE for floating-point. So we have to have two patterns ;; for EQ and two for NE. (define_expand "beq" [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3))) (set (pc) (if_then_else (ge (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT) { emit_insn (gen_beq_fp (operands[0])); DONE; } operands[1] = gen_reg_rtx (SImode); operands[2] = a29k_compare_op0; operands[3] = a29k_compare_op1; }") (define_expand "beq_fp" [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3))) (set (pc) (if_then_else (lt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_reg_rtx (SImode); operands[2] = a29k_compare_op0; operands[3] = a29k_compare_op1; }") (define_expand "bne" [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3))) (set (pc) (if_then_else (lt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT) { emit_insn (gen_bne_fp (operands[0])); DONE; } operands[1] = gen_reg_rtx (SImode); operands[2] = a29k_compare_op0; operands[3] = a29k_compare_op1; }") (define_expand "bne_fp" [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3))) (set (pc) (if_then_else (ge (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_reg_rtx (SImode); operands[2] = a29k_compare_op0; operands[3] = a29k_compare_op1; }") ;; We don't have a floating-point "lt" insn, so we have to use "gt" in that ;; case with the operands swapped. The operands must both be registers in ;; the floating-point case, so we know that swapping them is OK. (define_expand "blt" [(set (match_dup 1) (match_dup 2)) (set (pc) (if_then_else (lt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_reg_rtx (SImode); if (a29k_compare_fp_p) operands[2] = gen_rtx (GT, SImode, a29k_compare_op1, a29k_compare_op0); else operands[2] = gen_rtx (LT, SImode, a29k_compare_op0, a29k_compare_op1); }") ;; Similarly for "le". (define_expand "ble" [(set (match_dup 1) (match_dup 2)) (set (pc) (if_then_else (lt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_reg_rtx (SImode); if (a29k_compare_fp_p) operands[2] = gen_rtx (GE, SImode, a29k_compare_op1, a29k_compare_op0); else operands[2] = gen_rtx (LE, SImode, a29k_compare_op0, a29k_compare_op1); }") (define_expand "bltu" [(set (match_dup 1) (ltu:SI (match_dup 2) (match_dup 3))) (set (pc) (if_then_else (lt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_reg_rtx (SImode); operands[2] = a29k_compare_op0; operands[3] = a29k_compare_op1; }") (define_expand "bleu" [(set (match_dup 1) (leu:SI (match_dup 2) (match_dup 3))) (set (pc) (if_then_else (lt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_reg_rtx (SImode); operands[2] = a29k_compare_op0; operands[3] = a29k_compare_op1; }") (define_expand "bgt" [(set (match_dup 1) (gt:SI (match_dup 2) (match_dup 3))) (set (pc) (if_then_else (lt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_reg_rtx (SImode); operands[2] = a29k_compare_op0; operands[3] = a29k_compare_op1; }") (define_expand "bge" [(set (match_dup 1) (ge:SI (match_dup 2) (match_dup 3))) (set (pc) (if_then_else (lt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_reg_rtx (SImode); operands[2] = a29k_compare_op0; operands[3] = a29k_compare_op1; }") (define_expand "bgtu" [(set (match_dup 1) (gtu:SI (match_dup 2) (match_dup 3))) (set (pc) (if_then_else (lt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_reg_rtx (SImode); operands[2] = a29k_compare_op0; operands[3] = a29k_compare_op1; }") (define_expand "bgeu" [(set (match_dup 1) (geu:SI (match_dup 2) (match_dup 3))) (set (pc) (if_then_else (lt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_reg_rtx (SImode); operands[2] = a29k_compare_op0; operands[3] = a29k_compare_op1; }") (define_expand "seq" [(set (match_operand:SI 0 "gpc_reg_operand" "") (eq:SI (match_dup 1) (match_dup 2)))] "" " { operands[1] = a29k_compare_op0; operands[2] = a29k_compare_op1; }") ;; This is the most complicated case, because we don't have a floating-point ;; "ne" insn. If integer, handle normally. If floating-point, write the ;; compare and then write an insn to reverse the test. (define_expand "sne_fp" [(set (match_dup 3) (eq:SI (match_operand 1 "gpc_reg_operand" "") (match_operand 2 "gpc_reg_operand" ""))) (set (match_operand:SI 0 "gpc_reg_operand" "") (ge:SI (match_dup 3) (const_int 0)))] "" " { operands[3] = gen_reg_rtx (SImode); }"); (define_expand "sne" [(set (match_operand:SI 0 "gpc_reg_operand" "") (ne:SI (match_dup 1) (match_dup 2)))] "" " { operands[1] = a29k_compare_op0; operands[2] = a29k_compare_op1; if (a29k_compare_fp_p) { emit_insn (gen_sne_fp (operands[0], operands[1], operands[2])); DONE; } }") ;; We don't have a floating-point "lt" insn, so use "gt" and swap the ;; operands, the same as we do "blt". (define_expand "slt" [(set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] "" " { if (a29k_compare_fp_p) operands[1] = gen_rtx (GT, SImode, a29k_compare_op1, a29k_compare_op0); else operands[1] = gen_rtx (LT, SImode, a29k_compare_op0, a29k_compare_op1); }") ;; Similarly for "le" (define_expand "sle" [(set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] "" " { if (a29k_compare_fp_p) operands[1] = gen_rtx (GE, SImode, a29k_compare_op1, a29k_compare_op0); else operands[1] = gen_rtx (LE, SImode, a29k_compare_op0, a29k_compare_op1); }") (define_expand "sltu" [(set (match_operand:SI 0 "gpc_reg_operand" "") (ltu:SI (match_dup 1) (match_dup 2)))] "" " { operands[1] = a29k_compare_op0; operands[2] = a29k_compare_op1; }") (define_expand "sleu" [(set (match_operand:SI 0 "gpc_reg_operand" "") (leu:SI (match_dup 1) (match_dup 2)))] "" " { operands[1] = a29k_compare_op0; operands[2] = a29k_compare_op1; }") (define_expand "sgt" [(set (match_operand:SI 0 "gpc_reg_operand" "") (gt:SI (match_dup 1) (match_dup 2)))] "" " { operands[1] = a29k_compare_op0; operands[2] = a29k_compare_op1; }") (define_expand "sge" [(set (match_operand:SI 0 "gpc_reg_operand" "") (ge:SI (match_dup 1) (match_dup 2)))] "" " { operands[1] = a29k_compare_op0; operands[2] = a29k_compare_op1; }") (define_expand "sgtu" [(set (match_operand:SI 0 "gpc_reg_operand" "") (gtu:SI (match_dup 1) (match_dup 2)))] "" " { operands[1] = a29k_compare_op0; operands[2] = a29k_compare_op1; }") (define_expand "sgeu" [(set (match_operand:SI 0 "gpc_reg_operand" "") (geu:SI (match_dup 1) (match_dup 2)))] "" " { operands[1] = a29k_compare_op0; operands[2] = a29k_compare_op1; }") ;; Now define the actual jump insns. (define_insn "" [(set (pc) (if_then_else (match_operator 0 "branch_operator" [(match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "" "jmp%b0 %1,%l2%#" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (match_operator 0 "branch_operator" [(match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)]) (return) (pc)))] "null_epilogue ()" "jmp%b0i %1,lr0%#" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (match_operator 0 "branch_operator" [(match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)]) (pc) (label_ref (match_operand 2 "" ""))))] "" "jmp%B0 %1,%l2%#" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (match_operator 0 "branch_operator" [(match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)]) (pc) (return)))] "null_epilogue ()" "jmp%B0i %1,lr0%#" [(set_attr "type" "branch")]) (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "jmp %e0%E0" [(set_attr "type" "branch")]) (define_insn "return" [(return)] "null_epilogue ()" "jmpi lr0%#" [(set_attr "type" "branch")]) (define_insn "indirect_jump" [(set (pc) (match_operand:SI 0 "gpc_reg_operand" "r"))] "" "jmpi %0%#" [(set_attr "type" "branch")]) (define_insn "tablejump" [(set (pc) (match_operand:SI 0 "gpc_reg_operand" "r")) (use (label_ref (match_operand 1 "" "")))] "" "jmpi %0%#" [(set_attr "type" "branch")]) ;; JMPFDEC (define_insn "" [(set (pc) (if_then_else (ge (match_operand:SI 0 "gpc_reg_operand" "r") (const_int 0)) (label_ref (match_operand 1 "" "")) (pc))) (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))] "" "jmpfdec %0,%l1%#" [(set_attr "type" "branch")]) gcc-2.5.8/config/a29k/unix.h100444 22011 13 5720 5453234421 14140 0ustar kenneruser/* Definitions of target machine for GNU compiler, for AMD Am29000 CPU, Unix. Copyright (C) 1991 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@nyu.edu) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* This is mostly the same as a29k.h, except that we define unix instead of EPI and define unix-style machine names. */ #include "a29k/a29k.h" /* Set our default target to be the 29050; that is the more interesting chip for Unix systems. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (1+2+8+64) #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dam29k -Da29k -Dam29000 -Asystem(unix) -Acpu(a29k) -Amachine(a29k)" #undef CPP_SPEC #define CPP_SPEC "%{!m29000:-Dam29050 -D__am29050__}" /* Use a default linker configuration file. */ #undef LINK_SPEC #define LINK_SPEC "-T default.gld%s" /* Define the magic numbers that we recognize as COFF. */ #define MY_ISCOFF(magic) ((magic) == SIPFBOMAGIC || (magic) == SIPRBOMAGIC) /* For some systems, it is best if double-word objects are aligned on a doubleword boundary. We want to maintain compatibility with MetaWare in a29k.h, but do not feel constrained to do so here. */ #undef BIGGEST_ALIGNMENT #define BIGGEST_ALIGNMENT 64 /* Add shared data as a kludge for now. */ #undef ASM_FILE_START #define ASM_FILE_START(FILE) \ { char *p, *after_dir = main_input_filename; \ if (TARGET_29050) \ fprintf (FILE, "\t.cputype 29050\n"); \ for (p = main_input_filename; *p; p++) \ if (*p == '/') \ after_dir = p + 1; \ fprintf (FILE, "\t.file "); \ output_quoted_string (FILE, after_dir); \ fprintf (FILE, "\n"); \ if (flag_shared_data) \ fprintf (FILE, "\t.sect .shdata,data\n"); \ fprintf (FILE, "\t.sect .lit,lit\n"); } /* Output before shared data. */ #define SHARED_SECTION_ASM_OP "\t.use .shdata" /* If we want shared data, we have to turn off commons. */ #define OVERRIDE_OPTIONS if (flag_shared_data) flag_no_common = 1; #if 0 /* This would be needed except that the 29k doesn't have strict alignment requirements. */ #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ (((TYPE) != 0) \ ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \ ? PARM_BOUNDARY \ : TYPE_ALIGN(TYPE)) \ : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \ ? PARM_BOUNDARY \ : GET_MODE_ALIGNMENT(MODE))) #endif gcc-2.5.8/config/a29k/x-unix100444 22011 13 102 5331751540 14125 0ustar kenneruser# Needed for missing functions in Sym1. CLIB=-lsysv -liberty -lld gcc-2.5.8/config/a29k/xm-a29k.h100444 22011 13 2502 5413067241 14340 0ustar kenneruser/* Configuration for GNU C-compiler for AMD Am29000 processor. Copyright (C) 1987, 1988, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* #defines that need visibility everywhere. */ #define FALSE 0 #define TRUE 1 /* This describes the machine the compiler is hosted on. */ #define HOST_BITS_PER_CHAR 8 #define HOST_BITS_PER_SHORT 16 #define HOST_BITS_PER_INT 32 #define HOST_BITS_PER_LONG 32 #define HOST_BITS_PER_LONGLONG 64 #define HOST_WORDS_BIG_ENDIAN /* target machine dependencies. tm.h is a symbolic link to the actual target specific file. */ #include "tm.h" /* Arguments to use with `exit'. */ #define SUCCESS_EXIT_CODE 0 #define FATAL_EXIT_CODE 33 gcc-2.5.8/config/a29k/xm-unix.h100444 22011 13 2573 5413067212 14563 0ustar kenneruser/* Configuration for GNU C-compiler for AMD Am29000 processor. Copyright (C) 1987, 1988, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* #defines that need visibility everywhere. */ #define FALSE 0 #define TRUE 1 /* This describes the machine the compiler is hosted on. */ #define HOST_BITS_PER_CHAR 8 #define HOST_BITS_PER_SHORT 16 #define HOST_BITS_PER_INT 32 #define HOST_BITS_PER_LONG 32 #define HOST_BITS_PER_LONGLONG 64 #define HOST_WORDS_BIG_ENDIAN /* target machine dependencies. tm.h is a symbolic link to the actual target specific file. */ #include "tm.h" /* Arguments to use with `exit'. */ #define SUCCESS_EXIT_CODE 0 #define FATAL_EXIT_CODE 33 /* Ultra is V7, which is closest to USG. */ #define USG gcc-2.5.8/config/alpha/ 40777 22011 13 0 5520736515 13236 5ustar kennerusergcc-2.5.8/config/alpha/alpha-gdb.h100444 22011 13 1756 5456630664 15334 0ustar kenneruser/* Definitions of target machine for GNU compiler, for DEC Alpha, using encapsulated stabs. Copyright (C) 1992, 1993 Free Software Foundation, Inc. Contributed by Peter Schauer (pes@regent.e-technik.tu-muenchen.de). This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "alpha/alpha.h" #undef PREFERRED_DEBUGGING_TYPE #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG gcc-2.5.8/config/alpha/alpha.c100444 22011 13 126330 5520457100 14611 0ustar kenneruser/* Subroutines used for code generation on the DEC Alpha. Copyright (C) 1992, 1993 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@nyu.edu) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include "config.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "output.h" #include "insn-attr.h" #include "flags.h" #include "recog.h" #include "reload.h" #include "expr.h" #include "obstack.h" #include "tree.h" /* Save information from a "cmpxx" operation until the branch or scc is emitted. */ rtx alpha_compare_op0, alpha_compare_op1; int alpha_compare_fp_p; /* Save the name of the current function as used by the assembler. This is used by the epilogue. */ char *alpha_function_name; /* Non-zero if inside of a function, because the Alpha asm can't handle .files inside of functions. */ static int inside_function = FALSE; /* Nonzero if the current function needs gp. */ int alpha_function_needs_gp; extern char *version_string; /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */ int zap_mask (value) HOST_WIDE_INT value; { int i; for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR; i++, value >>= 8) if ((value & 0xff) != 0 && (value & 0xff) != 0xff) return 0; return 1; } /* Returns 1 if OP is either the constant zero or a register. If a register, it must be in the proper mode unless MODE is VOIDmode. */ int reg_or_0_operand (op, mode) register rtx op; enum machine_mode mode; { return op == const0_rtx || register_operand (op, mode); } /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or any register. */ int reg_or_6bit_operand (op, mode) register rtx op; enum machine_mode mode; { return ((GET_CODE (op) == CONST_INT && (unsigned HOST_WIDE_INT) INTVAL (op) < 64) || register_operand (op, mode)); } /* Return 1 if OP is an 8-bit constant or any register. */ int reg_or_8bit_operand (op, mode) register rtx op; enum machine_mode mode; { return ((GET_CODE (op) == CONST_INT && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100) || register_operand (op, mode)); } /* Return 1 if the operand is a valid second operand to an add insn. */ int add_operand (op, mode) register rtx op; enum machine_mode mode; { if (GET_CODE (op) == CONST_INT) return ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) < 0x10000 || ((INTVAL (op) & 0xffff) == 0 && (INTVAL (op) >> 31 == -1 || INTVAL (op) >> 31 == 0))); return register_operand (op, mode); } /* Return 1 if the operand is a valid second operand to a sign-extending add insn. */ int sext_add_operand (op, mode) register rtx op; enum machine_mode mode; { if (GET_CODE (op) == CONST_INT) return ((unsigned HOST_WIDE_INT) INTVAL (op) < 255 || (unsigned HOST_WIDE_INT) (- INTVAL (op)) < 255); return register_operand (op, mode); } /* Return 1 if OP is the constant 4 or 8. */ int const48_operand (op, mode) register rtx op; enum machine_mode mode; { return (GET_CODE (op) == CONST_INT && (INTVAL (op) == 4 || INTVAL (op) == 8)); } /* Return 1 if OP is a valid first operand to an AND insn. */ int and_operand (op, mode) register rtx op; enum machine_mode mode; { if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode) return (zap_mask (CONST_DOUBLE_LOW (op)) && zap_mask (CONST_DOUBLE_HIGH (op))); if (GET_CODE (op) == CONST_INT) return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100 || zap_mask (INTVAL (op))); return register_operand (op, mode); } /* Return 1 if OP is a constant that is the width, in bits, of an integral mode smaller than DImode. */ int mode_width_operand (op, mode) register rtx op; enum machine_mode mode; { return (GET_CODE (op) == CONST_INT && (INTVAL (op) == 8 || INTVAL (op) == 16 || INTVAL (op) == 32)); } /* Return 1 if OP is a constant that is the width of an integral machine mode smaller than an integer. */ int mode_mask_operand (op, mode) register rtx op; enum machine_mode mode; { #if HOST_BITS_PER_WIDE_INT == 32 if (GET_CODE (op) == CONST_DOUBLE) return CONST_DOUBLE_HIGH (op) == 0 && CONST_DOUBLE_LOW (op) == -1; #endif if (GET_CODE (op) == CONST_INT) return (INTVAL (op) == 0xff || INTVAL (op) == 0xffff #if HOST_BITS_PER_WIDE_INT == 64 || INTVAL (op) == 0xffffffff #endif ); } /* Return 1 if OP is a multiple of 8 less than 64. */ int mul8_operand (op, mode) register rtx op; enum machine_mode mode; { return (GET_CODE (op) == CONST_INT && (unsigned HOST_WIDE_INT) INTVAL (op) < 64 && (INTVAL (op) & 7) == 0); } /* Return 1 if OP is the constant zero in floating-point. */ int fp0_operand (op, mode) register rtx op; enum machine_mode mode; { return (GET_MODE (op) == mode && GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode)); } /* Return 1 if OP is the floating-point constant zero or a register. */ int reg_or_fp0_operand (op, mode) register rtx op; enum machine_mode mode; { return fp0_operand (op, mode) || register_operand (op, mode); } /* Return 1 if OP is a register or a constant integer. */ int reg_or_cint_operand (op, mode) register rtx op; enum machine_mode mode; { return GET_CODE (op) == CONST_INT || register_operand (op, mode); } /* Return 1 if OP is a valid operand for the source of a move insn. */ int input_operand (op, mode) register rtx op; enum machine_mode mode; { if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) return 0; if (GET_MODE_CLASS (mode) == MODE_FLOAT && GET_MODE (op) != mode) return 0; switch (GET_CODE (op)) { case LABEL_REF: case SYMBOL_REF: case CONST: return mode == DImode; case REG: return 1; case SUBREG: if (register_operand (op, mode)) return 1; /* ... fall through ... */ case MEM: return mode != HImode && mode != QImode && general_operand (op, mode); case CONST_DOUBLE: return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); case CONST_INT: return mode == QImode || mode == HImode || add_operand (op, mode); } return 0; } /* Return 1 if OP is a SYMBOL_REF for a function known to be in this file. */ int current_file_function_operand (op, mode) rtx op; enum machine_mode mode; { return (GET_CODE (op) == SYMBOL_REF && (SYMBOL_REF_FLAG (op) || op == XEXP (DECL_RTL (current_function_decl), 0))); } /* Return 1 if OP is a valid Alpha comparison operator. Here we know which comparisons are valid in which insn. */ int alpha_comparison_operator (op, mode) register rtx op; enum machine_mode mode; { enum rtx_code code = GET_CODE (op); if (mode != GET_MODE (op) || GET_RTX_CLASS (code) != '<') return 0; return (code == EQ || code == LE || code == LT || (mode == DImode && (code == LEU || code == LTU))); } /* Return 1 if OP is a signed comparison operation. */ int signed_comparison_operator (op, mode) register rtx op; enum machine_mode mode; { switch (GET_CODE (op)) { case EQ: case NE: case LE: case LT: case GE: case GT: return 1; } return 0; } /* Return 1 if this is a divide or modulus operator. */ int divmod_operator (op, mode) register rtx op; enum machine_mode mode; { switch (GET_CODE (op)) { case DIV: case MOD: case UDIV: case UMOD: return 1; } return 0; } /* Return 1 if this memory address is a known aligned register plus a constant. It must be a valid address. This means that we can do this as an aligned reference plus some offset. Take into account what reload will do. We could say that out-of-range stack slots are alignable, but that would complicate get_aligned_mem and it isn't worth the trouble since few functions have large stack space. */ int aligned_memory_operand (op, mode) register rtx op; enum machine_mode mode; { if (GET_CODE (op) == SUBREG) { if (GET_MODE (op) != mode) return 0; op = SUBREG_REG (op); mode = GET_MODE (op); } if (reload_in_progress && GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) op = reg_equiv_mem[REGNO (op)]; if (GET_CODE (op) != MEM || GET_MODE (op) != mode || ! memory_address_p (mode, XEXP (op, 0))) return 0; op = XEXP (op, 0); if (GET_CODE (op) == PLUS) op = XEXP (op, 0); return (GET_CODE (op) == REG && (REGNO (op) == STACK_POINTER_REGNUM || op == frame_pointer_rtx || (REGNO (op) >= FIRST_VIRTUAL_REGISTER && REGNO (op) <= LAST_VIRTUAL_REGISTER))); } /* Similar, but return 1 if OP is a MEM which is not alignable. */ int unaligned_memory_operand (op, mode) register rtx op; enum machine_mode mode; { if (GET_CODE (op) == SUBREG) { if (GET_MODE (op) != mode) return 0; op = SUBREG_REG (op); mode = GET_MODE (op); } if (reload_in_progress && GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) op = reg_equiv_mem[REGNO (op)]; if (GET_CODE (op) != MEM || GET_MODE (op) != mode) return 0; op = XEXP (op, 0); if (! memory_address_p (mode, op)) return 1; if (GET_CODE (op) == PLUS) op = XEXP (op, 0); return (GET_CODE (op) != REG || (REGNO (op) != STACK_POINTER_REGNUM && op != frame_pointer_rtx && (REGNO (op) < FIRST_VIRTUAL_REGISTER || REGNO (op) > LAST_VIRTUAL_REGISTER))); } /* Return 1 if OP is any memory location. During reload a pseudo matches. */ int any_memory_operand (op, mode) register rtx op; enum machine_mode mode; { return (GET_CODE (op) == MEM || (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG) || (reload_in_progress && GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER) || (reload_in_progress && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG && REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER)); } /* REF is an alignable memory location. Place an aligned SImode reference into *PALIGNED_MEM and the number of bits to shift into *PBITNUM. */ void get_aligned_mem (ref, paligned_mem, pbitnum) rtx ref; rtx *paligned_mem, *pbitnum; { rtx base; HOST_WIDE_INT offset = 0; if (GET_CODE (ref) == SUBREG) { offset = SUBREG_WORD (ref) * UNITS_PER_WORD; if (BYTES_BIG_ENDIAN) offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref))) - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref))))); ref = SUBREG_REG (ref); } if (GET_CODE (ref) == REG) ref = reg_equiv_mem[REGNO (ref)]; if (reload_in_progress) base = find_replacement (&XEXP (ref, 0)); else base = XEXP (ref, 0); if (GET_CODE (base) == PLUS) offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0); *paligned_mem = gen_rtx (MEM, SImode, plus_constant (base, offset & ~3)); MEM_IN_STRUCT_P (*paligned_mem) = MEM_IN_STRUCT_P (ref); MEM_VOLATILE_P (*paligned_mem) = MEM_VOLATILE_P (ref); RTX_UNCHANGING_P (*paligned_mem) = RTX_UNCHANGING_P (ref); *pbitnum = GEN_INT ((offset & 3) * 8); } /* Similar, but just get the address. Handle the two reload cases. */ rtx get_unaligned_address (ref) rtx ref; { rtx base; HOST_WIDE_INT offset = 0; if (GET_CODE (ref) == SUBREG) { offset = SUBREG_WORD (ref) * UNITS_PER_WORD; if (BYTES_BIG_ENDIAN) offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref))) - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref))))); ref = SUBREG_REG (ref); } if (GET_CODE (ref) == REG) ref = reg_equiv_mem[REGNO (ref)]; if (reload_in_progress) base = find_replacement (&XEXP (ref, 0)); else base = XEXP (ref, 0); if (GET_CODE (base) == PLUS) offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0); return plus_constant (base, offset); } /* Subfunction of the following function. Update the flags of any MEM found in part of X. */ static void alpha_set_memflags_1 (x, in_struct_p, volatile_p, unchanging_p) rtx x; int in_struct_p, volatile_p, unchanging_p; { int i; switch (GET_CODE (x)) { case SEQUENCE: case PARALLEL: for (i = XVECLEN (x, 0) - 1; i >= 0; i--) alpha_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, volatile_p, unchanging_p); break; case INSN: alpha_set_memflags_1 (PATTERN (x), in_struct_p, volatile_p, unchanging_p); break; case SET: alpha_set_memflags_1 (SET_DEST (x), in_struct_p, volatile_p, unchanging_p); alpha_set_memflags_1 (SET_SRC (x), in_struct_p, volatile_p, unchanging_p); break; case MEM: MEM_IN_STRUCT_P (x) = in_struct_p; MEM_VOLATILE_P (x) = volatile_p; RTX_UNCHANGING_P (x) = unchanging_p; break; } } /* Given INSN, which is either an INSN or a SEQUENCE generated to perform a memory operation, look for any MEMs in either a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and volatile flags from REF into each of the MEMs found. If REF is not a MEM, don't do anything. */ void alpha_set_memflags (insn, ref) rtx insn; rtx ref; { /* Note that it is always safe to get these flags, though they won't be what we think if REF is not a MEM. */ int in_struct_p = MEM_IN_STRUCT_P (ref); int volatile_p = MEM_VOLATILE_P (ref); int unchanging_p = RTX_UNCHANGING_P (ref); if (GET_CODE (ref) != MEM || (! in_struct_p && ! volatile_p && ! unchanging_p)) return; alpha_set_memflags_1 (insn, in_struct_p, volatile_p, unchanging_p); } /* Try to output insns to set TARGET equal to the constant C if it can be done in less than N insns. Returns 1 if it can be done and the insns have been emitted. If it would take more than N insns, zero is returned and no insns and emitted. */ int alpha_emit_set_const (target, c, n) rtx target; HOST_WIDE_INT c; int n; { HOST_WIDE_INT new = c; int i, bits; #if HOST_BITS_PER_WIDE_INT == 64 /* We are only called for SImode and DImode. If this is SImode, ensure that we are sign extended to a full word. This does not make any sense when cross-compiling on a narrow machine. */ if (GET_MODE (target) == SImode) c = (c & 0xffffffff) - 2 * (c & 0x80000000); #endif /* If this is a sign-extended 32-bit constant, we can do this in at most three insns, so do it if we have enough insns left. We always have a sign-extended 32-bit constant when compiling on a narrow machine. */ if (HOST_BITS_PER_WIDE_INT != 64 || c >> 31 == -1 || c >> 31 == 0) { HOST_WIDE_INT low = (c & 0xffff) - 2 * (c & 0x8000); HOST_WIDE_INT tmp1 = c - low; HOST_WIDE_INT high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000); HOST_WIDE_INT extra = 0; /* If HIGH will be interpreted as negative but the constant is positive, we must adjust it to do two ldha insns. */ if ((high & 0x8000) != 0 && c >= 0) { extra = 0x4000; tmp1 -= 0x40000000; high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000); } if (c == low || (low == 0 && extra == 0)) { emit_move_insn (target, GEN_INT (c)); return 1; } else if (n >= 2 + (extra != 0)) { emit_move_insn (target, GEN_INT (low)); if (extra != 0) emit_insn (gen_add2_insn (target, GEN_INT (extra << 16))); emit_insn (gen_add2_insn (target, GEN_INT (high << 16))); return 1; } } /* If we couldn't do it that way, try some other methods (that depend on being able to compute in the target's word size). But if we have no instructions left, don't bother. Also, don't even try if this is SImode (in which case we should have already done something, but do a sanity check here). */ if (n == 1 || HOST_BITS_PER_WIDE_INT < 64 || GET_MODE (target) != DImode) return 0; /* First, see if can load a value into the target that is the same as the constant except that all bytes that are 0 are changed to be 0xff. If we can, then we can do a ZAPNOT to obtain the desired constant. */ for (i = 0; i < 64; i += 8) if ((new & ((HOST_WIDE_INT) 0xff << i)) == 0) new |= (HOST_WIDE_INT) 0xff << i; if (alpha_emit_set_const (target, new, n - 1)) { emit_insn (gen_anddi3 (target, target, GEN_INT (c | ~ new))); return 1; } /* Find, see if we can load a related constant and then shift and possibly negate it to get the constant we want. Try this once each increasing numbers of insns. */ for (i = 1; i < n; i++) { /* First try complementing. */ if (alpha_emit_set_const (target, ~ c, i)) { emit_insn (gen_one_cmpldi2 (target, target)); return 1; } /* First try to form a constant and do a left shift. We can do this if some low-order bits are zero; the exact_log2 call below tells us that information. The bits we are shifting out could be any value, but here we'll just try the 0- and sign-extended forms of the constant. To try to increase the chance of having the same constant in more than one insn, start at the highest number of bits to shift, but try all possibilities in case a ZAPNOT will be useful. */ if ((bits = exact_log2 (c & - c)) > 0) for (; bits > 0; bits--) if (alpha_emit_set_const (target, c >> bits, i) || alpha_emit_set_const (target, ((unsigned HOST_WIDE_INT) c) >> bits, i)) { emit_insn (gen_ashldi3 (target, target, GEN_INT (bits))); return 1; } /* Now try high-order zero bits. Here we try the shifted-in bits as all zero and all ones. */ if ((bits = HOST_BITS_PER_WIDE_INT - floor_log2 (c) - 1) > 0) for (; bits > 0; bits--) if (alpha_emit_set_const (target, c << bits, i) || alpha_emit_set_const (target, ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)), i)) { emit_insn (gen_lshrdi3 (target, target, GEN_INT (bits))); return 1; } /* Now try high-order 1 bits. We get that with a sign-extension. But one bit isn't enough here. */ if ((bits = HOST_BITS_PER_WIDE_INT - floor_log2 (~ c) - 2) > 0) for (; bits > 0; bits--) if (alpha_emit_set_const (target, c << bits, i) || alpha_emit_set_const (target, ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)), i)) { emit_insn (gen_ashrdi3 (target, target, GEN_INT (bits))); return 1; } } return 0; } /* Adjust the cost of a scheduling dependency. Return the new cost of a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ int alpha_adjust_cost (insn, link, dep_insn, cost) rtx insn; rtx link; rtx dep_insn; int cost; { rtx set; /* If the dependence is an anti-dependence, there is no cost. For an output dependence, there is sometimes a cost, but it doesn't seem worth handling those few cases. */ if (REG_NOTE_KIND (link) != 0) return 0; /* If INSN is a store insn and DEP_INSN is setting the data being stored, we can sometimes lower the cost. */ if (recog_memoized (insn) >= 0 && get_attr_type (insn) == TYPE_ST && (set = single_set (dep_insn)) != 0 && GET_CODE (PATTERN (insn)) == SET && rtx_equal_p (SET_DEST (set), SET_SRC (PATTERN (insn)))) switch (get_attr_type (dep_insn)) { case TYPE_LD: /* No savings here. */ return cost; case TYPE_IMULL: case TYPE_IMULQ: /* In these cases, we save one cycle. */ return cost - 2; default: /* In all other cases, we save two cycles. */ return MAX (0, cost - 4); } /* Another case that needs adjustment is an arithmetic or logical operation. It's cost is usually one cycle, but we default it to two in the MD file. The only case that it is actually two is for the address in loads and stores. */ if (recog_memoized (dep_insn) >= 0 && get_attr_type (dep_insn) == TYPE_IADDLOG) switch (get_attr_type (insn)) { case TYPE_LD: case TYPE_ST: return cost; default: return 2; } /* The final case is when a compare feeds into an integer branch. The cost is only one cycle in that case. */ if (recog_memoized (dep_insn) >= 0 && get_attr_type (dep_insn) == TYPE_ICMP && recog_memoized (insn) >= 0 && get_attr_type (insn) == TYPE_IBR) return 2; /* Otherwise, return the default cost. */ return cost; } /* Print an operand. Recognize special options, documented below. */ void print_operand (file, x, code) FILE *file; rtx x; char code; { int i; switch (code) { case 'r': /* If this operand is the constant zero, write it as "$31". */ if (GET_CODE (x) == REG) fprintf (file, "%s", reg_names[REGNO (x)]); else if (x == CONST0_RTX (GET_MODE (x))) fprintf (file, "$31"); else output_operand_lossage ("invalid %%r value"); break; case 'R': /* Similar, but for floating-point. */ if (GET_CODE (x) == REG) fprintf (file, "%s", reg_names[REGNO (x)]); else if (x == CONST0_RTX (GET_MODE (x))) fprintf (file, "$f31"); else output_operand_lossage ("invalid %%R value"); break; case 'N': /* Write the 1's complement of a constant. */ if (GET_CODE (x) != CONST_INT) output_operand_lossage ("invalid %%N value"); fprintf (file, "%ld", ~ INTVAL (x)); break; case 'P': /* Write 1 << C, for a constant C. */ if (GET_CODE (x) != CONST_INT) output_operand_lossage ("invalid %%P value"); fprintf (file, "%ld", (HOST_WIDE_INT) 1 << INTVAL (x)); break; case 'h': /* Write the high-order 16 bits of a constant, sign-extended. */ if (GET_CODE (x) != CONST_INT) output_operand_lossage ("invalid %%h value"); fprintf (file, "%ld", INTVAL (x) >> 16); break; case 'L': /* Write the low-order 16 bits of a constant, sign-extended. */ if (GET_CODE (x) != CONST_INT) output_operand_lossage ("invalid %%L value"); fprintf (file, "%ld", (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000)); break; case 'm': /* Write mask for ZAP insn. */ if (GET_CODE (x) == CONST_DOUBLE) { HOST_WIDE_INT mask = 0; HOST_WIDE_INT value; value = CONST_DOUBLE_LOW (x); for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR; i++, value >>= 8) if (value & 0xff) mask |= (1 << i); value = CONST_DOUBLE_HIGH (x); for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR; i++, value >>= 8) if (value & 0xff) mask |= (1 << (i + sizeof (int))); fprintf (file, "%ld", mask & 0xff); } else if (GET_CODE (x) == CONST_INT) { HOST_WIDE_INT mask = 0, value = INTVAL (x); for (i = 0; i < 8; i++, value >>= 8) if (value & 0xff) mask |= (1 << i); fprintf (file, "%ld", mask); } else output_operand_lossage ("invalid %%m value"); break; case 'M': /* 'b', 'w', or 'l' as the value of the constant. */ if (GET_CODE (x) != CONST_INT || (INTVAL (x) != 8 && INTVAL (x) != 16 && INTVAL (x) != 32)) output_operand_lossage ("invalid %%M value"); fprintf (file, "%s", INTVAL (x) == 8 ? "b" : INTVAL (x) == 16 ? "w" : "l"); break; case 'U': /* Similar, except do it from the mask. */ if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xff) fprintf (file, "b"); else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffff) fprintf (file, "w"); #if HOST_BITS_PER_WIDE_INT == 32 else if (GET_CODE (x) == CONST_DOUBLE && CONST_DOUBLE_HIGH (x) == 0 && CONST_DOUBLE_LOW (x) == -1) fprintf (file, "l"); #else else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffffffff) fprintf (file, "l"); #endif else output_operand_lossage ("invalid %%U value"); break; case 's': /* Write the constant value divided by 8. */ if (GET_CODE (x) != CONST_INT && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64 && (INTVAL (x) & 7) != 8) output_operand_lossage ("invalid %%s value"); fprintf (file, "%ld", INTVAL (x) / 8); break; case 'S': /* Same, except compute (64 - c) / 8 */ if (GET_CODE (x) != CONST_INT && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64 && (INTVAL (x) & 7) != 8) output_operand_lossage ("invalid %%s value"); fprintf (file, "%ld", (64 - INTVAL (x)) / 8); break; case 'C': /* Write out comparison name. */ if (GET_RTX_CLASS (GET_CODE (x)) != '<') output_operand_lossage ("invalid %%C value"); if (GET_CODE (x) == LEU) fprintf (file, "ule"); else if (GET_CODE (x) == LTU) fprintf (file, "ult"); else fprintf (file, "%s", GET_RTX_NAME (GET_CODE (x))); break; case 'D': /* Similar, but write reversed code. We can't get an unsigned code here. */ if (GET_RTX_CLASS (GET_CODE (x)) != '<') output_operand_lossage ("invalid %%D value"); fprintf (file, "%s", GET_RTX_NAME (reverse_condition (GET_CODE (x)))); break; case 'E': /* Write the divide or modulus operator. */ switch (GET_CODE (x)) { case DIV: fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q"); break; case UDIV: fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q"); break; case MOD: fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q"); break; case UMOD: fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q"); break; default: output_operand_lossage ("invalid %%E value"); break; } break; case 'A': /* Write "_u" for unaligned access. */ if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND) fprintf (file, "_u"); break; case 0: if (GET_CODE (x) == REG) fprintf (file, "%s", reg_names[REGNO (x)]); else if (GET_CODE (x) == MEM) output_address (XEXP (x, 0)); else output_addr_const (file, x); break; default: output_operand_lossage ("invalid %%xn code"); } } /* Do what is necessary for `va_start'. The argument is ignored; We look at the current function to determine if stdarg or varargs is used and fill in an initial va_list. A pointer to this constructor is returned. */ struct rtx_def * alpha_builtin_saveregs (arglist) tree arglist; { rtx block, addr, argsize; tree fntype = TREE_TYPE (current_function_decl); int stdarg = (TYPE_ARG_TYPES (fntype) != 0 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node)); /* Compute the current position into the args, taking into account both registers and memory. */ argsize = plus_constant (current_function_arg_offset_rtx, current_function_args_info * UNITS_PER_WORD); /* Allocate the va_list constructor */ block = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD); RTX_UNCHANGING_P (block) = 1; RTX_UNCHANGING_P (XEXP (block, 0)) = 1; /* Store the address of the first integer register in the __va_base member. */ emit_move_insn (change_address (block, DImode, XEXP (block, 0)), force_operand (plus_constant (virtual_incoming_args_rtx, 6 * UNITS_PER_WORD), NULL_RTX)); /* Store the argsize as the __va_offset member. */ emit_move_insn (change_address (block, Pmode, plus_constant (XEXP (block, 0), UNITS_PER_WORD)), force_operand (argsize, NULL_RTX)); /* Return the address of the va_list constructor, but don't put it in a register. Doing so would fail when not optimizing and produce worse code when optimizing. */ return XEXP (block, 0); } /* This page contains routines that are used to determine what the function prologue and epilogue code will do and write them out. */ /* Compute the size of the save area in the stack. */ int alpha_sa_size () { int size = 0; int i; for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) if (! fixed_regs[i] && ! call_used_regs[i] && regs_ever_live[i]) size++; /* If some registers were saved but not reg 26, reg 26 must also be saved, so leave space for it. */ if (size != 0 && ! regs_ever_live[26]) size++; return size * 8; } /* Return 1 if this function can directly return via $26. */ int direct_return () { return (reload_completed && alpha_sa_size () == 0 && get_frame_size () == 0 && current_function_pretend_args_size == 0); } /* Write a version stamp. Don't write anything if we are running as a cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */ #ifndef CROSS_COMPILE #include #endif void alpha_write_verstamp (file) FILE *file; { #ifdef MS_STAMP char *p; fprintf (file, "\t.verstamp %d %d ", MS_STAMP, LS_STAMP); for (p = version_string; *p != ' ' && *p != 0; p++) fprintf (file, "%c", *p == '.' ? ' ' : *p); fprintf (file, "\n"); #endif } /* Write code to add constant C to register number IN_REG (possibly 31) and put the result into OUT_REG. Write the code to FILE. */ static void add_long_const (file, c, in_reg, out_reg) HOST_WIDE_INT c; int in_reg, out_reg; FILE *file; { HOST_WIDE_INT low = (c & 0xffff) - 2 * (c & 0x8000); HOST_WIDE_INT tmp1 = c - low; HOST_WIDE_INT high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000); HOST_WIDE_INT extra = 0; /* We don't have code to write out constants larger than 32 bits. */ #if HOST_BITS_PER_LONG_INT == 64 if ((unsigned HOST_WIDE_INT) c >> 32 != 0) abort (); #endif /* If HIGH will be interpreted as negative, we must adjust it to do two ldha insns. Note that we will never be building a negative constant here. */ if (high & 0x8000) { extra = 0x4000; tmp1 -= 0x40000000; high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000); } if (low != 0) { if (low >= 0 && low < 255) fprintf (file, "\taddq $%d,%d,$%d\n", in_reg, low, out_reg); else fprintf (file, "\tlda $%d,%d($%d)\n", out_reg, low, in_reg); in_reg = out_reg; } if (extra) { fprintf (file, "\tldah $%d,%d($%d)\n", out_reg, extra, in_reg); in_reg = out_reg; } if (high) fprintf (file, "\tldah $%d,%d($%d)\n", out_reg, high, in_reg); } /* Write function prologue. */ void output_prolog (file, size) FILE *file; int size; { HOST_WIDE_INT frame_size = ((size + current_function_outgoing_args_size + current_function_pretend_args_size + alpha_sa_size () + 15) & ~15); HOST_WIDE_INT reg_offset = size + current_function_outgoing_args_size; HOST_WIDE_INT start_reg_offset = reg_offset; HOST_WIDE_INT actual_start_reg_offset = start_reg_offset; rtx insn; int reg_offset_base_reg = 30; unsigned reg_mask = 0; int i; /* Ecoff can handle multiple .file directives, put out file and lineno. We have to do that before the .ent directive as we cannot switch files within procedures with native ecoff because line numbers are linked to procedure descriptors. Outputting the lineno helps debugging of one line functions as they would otherwise get no line number at all. Please note that we would like to put out last_linenum from final.c, but it is not accesible. */ if (write_symbols == SDB_DEBUG) { ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl)); if (debug_info_level != DINFO_LEVEL_TERSE) ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl)); } /* The assembly language programmer's guide states that the second argument to the .ent directive, the lex_level, is ignored by the assembler, so we might as well omit it. */ fprintf (file, "\t.ent "); assemble_name (file, alpha_function_name); fprintf (file, "\n"); ASM_OUTPUT_LABEL (file, alpha_function_name); inside_function = TRUE; /* Set up offsets to alpha virtual arg/local debugging pointer. */ alpha_auto_offset = -frame_size + current_function_pretend_args_size; alpha_arg_offset = -frame_size + 48; /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first. Even if we are a static function, we still need to do this in case our address is taken and passed to something like qsort. */ alpha_function_needs_gp = 0; for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) if ((GET_CODE (insn) == CALL_INSN) || (GET_RTX_CLASS (GET_CODE (insn)) == 'i' && GET_CODE (PATTERN (insn)) != USE && GET_CODE (PATTERN (insn)) != CLOBBER && (get_attr_type (insn) == TYPE_LDSYM || get_attr_type (insn) == TYPE_ISUBR))) { alpha_function_needs_gp = 1; break; } if (alpha_function_needs_gp) fprintf (file, "\tldgp $29,0($27)\n"); /* Put a label after the GP load so we can enter the function at it. */ assemble_name (file, alpha_function_name); fprintf (file, "..ng:\n"); /* Adjust the stack by the frame size. If the frame size is > 4096 bytes, we need to be sure we probe somewhere in the first and last 4096 bytes (we can probably get away without the latter test) and every 8192 bytes in between. If the frame size is > 32768, we do this in a loop. Otherwise, we generate the explicit probe instructions. Note that we are only allowed to adjust sp once in the prologue. */ if (frame_size < 32768) { if (frame_size > 4096) { int probed = 4096; int regnum = 2; fprintf (file, "\tldq $%d,-%d($30)\n", regnum++, probed); while (probed + 8192 < frame_size) fprintf (file, "\tldq $%d,-%d($30)\n", regnum++, probed += 8192); if (probed + 4096 < frame_size) fprintf (file, "\tldq $%d,-%d($30)\n", regnum++, probed += 4096); if (regnum > 9) abort (); } if (frame_size != 0) fprintf (file, "\tlda $30,-%d($30)\n", frame_size); } else { /* Here we generate code to set R4 to SP + 4096 and set R5 to the number of 8192 byte blocks to probe. We then probe each block in the loop and then set SP to the proper location. If the amount remaining is > 4096, we have to do one more probe. */ HOST_WIDE_INT blocks = (frame_size + 4096) / 8192; HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192; add_long_const (file, blocks, 31, 5); fprintf (file, "\tlda $4,4096($30)\n"); assemble_name (file, alpha_function_name); fprintf (file, "..sc:\n"); fprintf (file, "\tldq $6,-8192($4)\n"); fprintf (file, "\tsubq $5,1,$5\n"); fprintf (file, "\tlda $4,-8192($4)\n"); fprintf (file, "\tbne $5"); assemble_name (file, alpha_function_name); fprintf (file, "%s..sc\n"); fprintf (file, "\tlda $30,-%d($4)\n", leftover); if (leftover > 4096) fprintf (file, "\tldq $2,%d($30)\n", leftover - 4096); } /* Describe our frame. */ fprintf (file, "\t.frame $%d,%d,$26,%d\n", frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM, frame_size, current_function_pretend_args_size); /* If reg_offset is "close enough" to 2**15 that one of the offsets would overflow a store instruction, compute the base of the register save area into $28. */ if (reg_offset >= 32768 - alpha_sa_size () && alpha_sa_size () != 0) { add_long_const (file, reg_offset, 30, 28); reg_offset_base_reg = 28; reg_offset = start_reg_offset = 0; } /* Save register 26 if it is used or if any other register needs to be saved. */ if (regs_ever_live[26] || alpha_sa_size () != 0) { reg_mask |= 1 << 26; fprintf (file, "\tstq $26,%d($%d)\n", reg_offset, reg_offset_base_reg); reg_offset += 8; } /* Now save any other used integer registers required to be saved. */ for (i = 0; i < 32; i++) if (! fixed_regs[i] && ! call_used_regs[i] && regs_ever_live[i] && i != 26) { reg_mask |= 1 << i; fprintf (file, "\tstq $%d,%d($%d)\n", i, reg_offset, reg_offset_base_reg); reg_offset += 8; } /* Print the register mask and do floating-point saves. */ if (reg_mask) fprintf (file, "\t.mask 0x%x,%d\n", reg_mask, actual_start_reg_offset - frame_size); start_reg_offset = reg_offset; reg_mask = 0; for (i = 0; i < 32; i++) if (! fixed_regs[i + 32] && ! call_used_regs[i + 32] && regs_ever_live[i + 32]) { reg_mask |= 1 << i; fprintf (file, "\tstt $f%d,%d($%d)\n", i, reg_offset, reg_offset_base_reg); reg_offset += 8; } /* Print the floating-point mask, if we've saved any fp register. */ if (reg_mask) fprintf (file, "\t.fmask 0x%x,%d\n", reg_mask, actual_start_reg_offset); /* If we need a frame pointer, set it from the stack pointer. Note that this must always be the last instruction in the prologue. */ if (frame_pointer_needed) fprintf (file, "\tbis $30,$30,$15\n"); /* End the prologue and say if we used gp. */ fprintf (file, "\t.prologue %d\n", alpha_function_needs_gp); } /* Write function epilogue. */ void output_epilog (file, size) FILE *file; int size; { rtx insn = get_last_insn (); HOST_WIDE_INT frame_size = ((size + current_function_outgoing_args_size + current_function_pretend_args_size + alpha_sa_size () + 15) & ~15); HOST_WIDE_INT reg_offset = size + current_function_outgoing_args_size; HOST_WIDE_INT frame_size_from_reg_save = frame_size - reg_offset; int reg_offset_base_reg = 30; int i; /* If the last insn was a BARRIER, we don't have to write anything except the .end pseudo-op. */ if (GET_CODE (insn) == NOTE) insn = prev_nonnote_insn (insn); if (insn == 0 || GET_CODE (insn) != BARRIER) { int fp_offset; /* If we have a frame pointer, restore SP from it. */ if (frame_pointer_needed) fprintf (file, "\tbis $15,$15,$30\n"); /* If the register save area is out of range, put its address into $28. */ if (reg_offset >= 32768 - alpha_sa_size () && alpha_sa_size () != 0) { add_long_const (file, reg_offset, 30, 28); reg_offset_base_reg = 28; reg_offset = 0; } /* Restore all the registers, starting with the return address register. */ if (regs_ever_live[26] || alpha_sa_size () != 0) { fprintf (file, "\tldq $26,%d($%d)\n", reg_offset, reg_offset_base_reg); reg_offset += 8; } /* Now restore any other used integer registers that that we saved, except for FP if it is being used as FP, since it must be restored last. */ for (i = 0; i < 32; i++) if (! fixed_regs[i] && ! call_used_regs[i] && regs_ever_live[i] && i != 26) { if (i == FRAME_POINTER_REGNUM && frame_pointer_needed) fp_offset = reg_offset; else fprintf (file, "\tldq $%d,%d($%d)\n", i, reg_offset, reg_offset_base_reg); reg_offset += 8; } for (i = 0; i < 32; i++) if (! fixed_regs[i + 32] && ! call_used_regs[i + 32] && regs_ever_live[i + 32]) { fprintf (file, "\tldt $f%d,%d($%d)\n", i, reg_offset, reg_offset_base_reg); reg_offset += 8; } /* If the stack size is large, compute the size of the stack into a register because the old FP restore, stack pointer adjust, and return are required to be consecutive instructions. However, if the new stack pointer can be computed by adding the a constant to the start of the register save area, we can do it that way. */ if (frame_size > 32767 && ! (reg_offset_base_reg != 30 && frame_size_from_reg_save < 32768)) add_long_const (file, frame_size, 31, 1); /* If we needed a frame pointer and we have to restore it, do it now. This must be done in one instruction immediately before the SP update. */ if (frame_pointer_needed && regs_ever_live[FRAME_POINTER_REGNUM]) fprintf (file, "\tldq $15,%d($%d)\n", fp_offset, reg_offset_base_reg); /* Now update the stack pointer, if needed. This must be done in one, stylized, instruction. */ if (frame_size > 32768) { if (reg_offset_base_reg != 30 && frame_size_from_reg_save < 32768) { if (frame_size_from_reg_save < 255) fprintf (file, "\taddq $%d,%d,$30\n", reg_offset_base_reg, frame_size_from_reg_save); else fprintf (file, "\tlda %30,%d($%d)\n", frame_size_from_reg_save, reg_offset_base_reg); } else fprintf (file, "\taddq $1,$30,$30\n"); } else if (frame_size != 0) fprintf (file, "\tlda $30,%d($30)\n", frame_size); /* Finally return to the caller. */ fprintf (file, "\tret $31,($26),1\n"); } /* End the function. */ fprintf (file, "\t.end "); assemble_name (file, alpha_function_name); fprintf (file, "\n"); inside_function = FALSE; /* Show that we know this function if it is called again. */ SYMBOL_REF_FLAG (XEXP (DECL_RTL (current_function_decl), 0)) = 1; } /* Debugging support. */ #include "gstab.h" /* Count the number of sdb related labels are generated (to find block start and end boundaries). */ int sdb_label_count = 0; /* Next label # for each statement. */ static int sym_lineno = 0; /* Count the number of .file directives, so that .loc is up to date. */ static int num_source_filenames = 0; /* Name of the file containing the current function. */ static char *current_function_file = ""; /* Offsets to alpha virtual arg/local debugging pointers. */ long alpha_arg_offset; long alpha_auto_offset; /* Emit a new filename to a stream. */ void alpha_output_filename (stream, name) FILE *stream; char *name; { static int first_time = TRUE; char ltext_label_name[100]; if (first_time) { first_time = FALSE; ++num_source_filenames; current_function_file = name; fprintf (stream, "\t.file\t%d ", num_source_filenames); output_quoted_string (stream, name); fprintf (stream, "\n"); if (!TARGET_GAS && write_symbols == DBX_DEBUG) fprintf (stream, "\t#@stabs\n"); } else if (!TARGET_GAS && write_symbols == DBX_DEBUG) { ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0); fprintf (stream, "%s ", ASM_STABS_OP); output_quoted_string (stream, name); fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]); } else if (name != current_function_file && strcmp (name, current_function_file) != 0) { if (inside_function && ! TARGET_GAS) fprintf (stream, "\t#.file\t%d ", num_source_filenames); else { ++num_source_filenames; current_function_file = name; fprintf (stream, "\t.file\t%d ", num_source_filenames); } output_quoted_string (stream, name); fprintf (stream, "\n"); } } /* Emit a linenumber to a stream. */ void alpha_output_lineno (stream, line) FILE *stream; int line; { if (! TARGET_GAS && write_symbols == DBX_DEBUG) { /* mips-tfile doesn't understand .stabd directives. */ ++sym_lineno; fprintf (stream, "$LM%d:\n\t%s %d,0,%d,$LM%d\n", sym_lineno, ASM_STABN_OP, N_SLINE, line, sym_lineno); } else fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line); } gcc-2.5.8/config/alpha/alpha.h100444 22011 13 210362 5472141755 14631 0ustar kenneruser/* Definitions of target machine for GNU compiler, for DEC Alpha. Copyright (C) 1992, 1993 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@nyu.edu) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "\ -Dunix -D__osf__ -D__alpha -D__alpha__ -D_LONGLONG -DSYSTYPE_BSD \ -D_SYSTYPE_BSD -Asystem(unix) -Asystem(xpg4) -Acpu(alpha) -Amachine(alpha)" /* Write out the correct language type definition for the header files. Unless we have assembler language, write out the symbols for C. */ #define CPP_SPEC "\ %{!.S: -D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}} \ %{.S: -D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ %{.cc: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus} \ %{.cxx: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus} \ %{.C: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus} \ %{.m: -D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C}" /* Set the spec to use for signed char. The default tests the above macro but DEC's compiler can't handle the conditional in a "constant" operand. */ #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}" /* No point in running CPP on our assembler output. */ #define ASM_SPEC "-nocpp" /* Right now Alpha OSF/1 doesn't seem to have debugging libraries. */ #define LIB_SPEC "%{p:-lprof1} -lc" /* Pass "-G 8" to ld because Alpha's CC does. Pass -O3 if we are optimizing, -O1 if we are not. Pass -non_shared or -call_shared as appropriate. */ #define LINK_SPEC \ "-G 8 %{O*:-O3} %{!O*:-O1} %{static:-non_shared} %{!static:-call_shared}" /* Print subsidiary information on the compiler version in use. */ #define TARGET_VERSION /* Define the location for the startup file on OSF/1 for Alpha. */ #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/" /* Run-time compilation parameters selecting different hardware subsets. */ extern int target_flags; /* This means that floating-point support exists in the target implementation of the Alpha architecture. This is usually the default. */ #define TARGET_FP (target_flags & 1) /* This means that floating-point registers are allowed to be used. Note that Alpha implementations without FP operations are required to provide the FP registers. */ #define TARGET_FPREGS (target_flags & 2) /* This means that gas is used to process the assembler file. */ #define MASK_GAS 4 #define TARGET_GAS (target_flags & MASK_GAS) /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */ #define TARGET_SWITCHES \ { {"no-soft-float", 1}, \ {"soft-float", -1}, \ {"fp-regs", 2}, \ {"no-fp-regs", -3}, \ {"alpha-as", -MASK_GAS}, \ {"gas", MASK_GAS}, \ {"", TARGET_DEFAULT} } #define TARGET_DEFAULT 3 /* Define this macro to change register usage conditional on target flags. On the Alpha, we use this to disable the floating-point registers when they don't exist. */ #define CONDITIONAL_REGISTER_USAGE \ if (! TARGET_FPREGS) \ for (i = 32; i < 64; i++) \ fixed_regs[i] = call_used_regs[i] = 1; /* Define this to change the optimizations performed by default. */ #define OPTIMIZATION_OPTIONS(LEVEL) \ { \ if ((LEVEL) > 0) \ { \ flag_force_addr = 1; \ flag_force_mem = 1; \ flag_omit_frame_pointer = 1; \ } \ } /* target machine storage layout */ /* Define to enable software floating point emulation. */ #define REAL_ARITHMETIC /* Define the size of `int'. The default is the same as the word size. */ #define INT_TYPE_SIZE 32 /* Define the size of `long long'. The default is the twice the word size. */ #define LONG_LONG_TYPE_SIZE 64 /* The two floating-point formats we support are S-floating, which is 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double' and `long double' are T. */ #define FLOAT_TYPE_SIZE 32 #define DOUBLE_TYPE_SIZE 64 #define LONG_DOUBLE_TYPE_SIZE 64 #define WCHAR_TYPE "short unsigned int" #define WCHAR_TYPE_SIZE 16 /* Define this macro if it is advisable to hold scalars in registers in a wider mode than that declared by the program. In such cases, the value is constrained to be within the bounds of the declared type, but kept valid in the wider mode. The signedness of the extension may differ from that of the type. For Alpha, we always store objects in a full register. 32-bit objects are always sign-extended, but smaller objects retain their signedness. */ #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ if (GET_MODE_CLASS (MODE) == MODE_INT \ && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ { \ if ((MODE) == SImode) \ (UNSIGNEDP) = 0; \ (MODE) = DImode; \ } /* Define this if function arguments should also be promoted using the above procedure. */ #define PROMOTE_FUNCTION_ARGS /* Likewise, if the function return value is promoted. */ #define PROMOTE_FUNCTION_RETURN /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. There are no such instructions on the Alpha, but the documentation is little endian. */ #define BITS_BIG_ENDIAN 0 /* Define this if most significant byte of a word is the lowest numbered. This is false on the Alpha. */ #define BYTES_BIG_ENDIAN 0 /* Define this if most significant word of a multiword number is lowest numbered. For Alpha we can decide arbitrarily since there are no machine instructions for them. Might as well be consistent with bytes. */ #define WORDS_BIG_ENDIAN 0 /* number of bits in an addressable storage unit */ #define BITS_PER_UNIT 8 /* Width in bits of a "word", which is the contents of a machine register. Note that this is not necessarily the width of data type `int'; if using 16-bit ints on a 68000, this would still be 32. But on a machine with 16-bit registers, this would be 16. */ #define BITS_PER_WORD 64 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 8 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ #define POINTER_SIZE 64 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ #define PARM_BOUNDARY 64 /* Boundary (in *bits*) on which stack pointer should be aligned. */ #define STACK_BOUNDARY 64 /* Allocation boundary (in *bits*) for the code of a function. */ #define FUNCTION_BOUNDARY 64 /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 64 /* Every structure's size must be a multiple of this. */ #define STRUCTURE_SIZE_BOUNDARY 8 /* A bitfield declared as `int' forces `int' alignment for the struct. */ #define PCC_BITFIELD_TYPE_MATTERS 1 /* Align loop starts for optimal branching. ??? Kludge this and the next macro for the moment by not doing anything if we don't optimize and also if we are writing ECOFF symbols to work around a bug in DEC's assembler. */ #define ASM_OUTPUT_LOOP_ALIGN(FILE) \ if (optimize > 0 && write_symbols != SDB_DEBUG) \ ASM_OUTPUT_ALIGN (FILE, 5) /* This is how to align an instruction for optimal branching. On Alpha we'll get better performance by aligning on a quadword boundary. */ #define ASM_OUTPUT_ALIGN_CODE(FILE) \ if (optimize > 0 && write_symbols != SDB_DEBUG) \ ASM_OUTPUT_ALIGN ((FILE), 4) /* No data type wants to be aligned rounder than this. */ #define BIGGEST_ALIGNMENT 64 /* Make strings word-aligned so strcpy from constants will be faster. */ #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ (TREE_CODE (EXP) == STRING_CST \ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) /* Make arrays of chars word-aligned for the same reasons. */ #define DATA_ALIGNMENT(TYPE, ALIGN) \ (TREE_CODE (TYPE) == ARRAY_TYPE \ && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) /* Set this non-zero if move instructions will actually fail to work when given unaligned data. Since we get an error message when we do one, call them invalid. */ #define STRICT_ALIGNMENT 1 /* Set this non-zero if unaligned move instructions are extremely slow. On the Alpha, they trap. */ #define SLOW_UNALIGNED_ACCESS 1 /* Standard register usage. */ /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. We define all 32 integer registers, even though $31 is always zero, and all 32 floating-point registers, even though $f31 is also always zero. We do not bother defining the FP status register and there are no other registers. Since $31 is always zero, we will use register number 31 as the argument pointer. It will never appear in the generated code because we will always be eliminating it in favor of the stack poointer or frame pointer. */ #define FIRST_PSEUDO_REGISTER 64 /* 1 for registers that have pervasive standard uses and are not available for the register allocator. */ #define FIXED_REGISTERS \ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 } /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. */ #define CALL_USED_REGISTERS \ {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } /* List the order in which to allocate registers. Each register must be listed once, even those in FIXED_REGISTERS. We allocate in the following order: $f1 (nonsaved floating-point register) $f10-$f15 (likewise) $f22-$f30 (likewise) $f21-$f16 (likewise, but input args) $f0 (nonsaved, but return value) $f2-$f9 (saved floating-point registers) $1-$8 (nonsaved integer registers) $22-$25 (likewise) $28 (likewise) $0 (likewise, but return value) $21-$16 (likewise, but input args) $27 (procedure value) $9-$14 (saved integer registers) $26 (return PC) $15 (frame pointer) $29 (global pointer) $30, $31, $f31 (stack pointer and always zero/ap) */ #define REG_ALLOC_ORDER \ {33, \ 42, 43, 44, 45, 46, 47, \ 54, 55, 56, 57, 58, 59, 60, 61, 62, \ 53, 52, 51, 50, 49, 48, \ 32, \ 34, 35, 36, 37, 38, 39, 40, 41, \ 1, 2, 3, 4, 5, 6, 7, 8, \ 22, 23, 24, 25, \ 28, \ 0, \ 21, 20, 19, 18, 17, 16, \ 27, \ 9, 10, 11, 12, 13, 14, \ 26, \ 15, \ 29, \ 30, 31, 63 } /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On Alpha, the integer registers can hold any mode. The floating-point registers can hold 32-bit and 64-bit integers as well, but not 16-bit or 8-bit values. If we only allowed the larger integers into FP registers, we'd have to say that QImode and SImode aren't tiable, which is a pain. So say all registers can hold everything and see how that works. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) 1 /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. */ #define MODES_TIEABLE_P(MODE1, MODE2) 1 /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ /* Alpha pc isn't overloaded on a register that the compiler knows about. */ /* #define PC_REGNUM */ /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM 30 /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM 15 /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */ #define FRAME_POINTER_REQUIRED 0 /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM 31 /* Register in which static-chain is passed to a function. For the Alpha, this is based on an example; the calling sequence doesn't seem to specify this. */ #define STATIC_CHAIN_REGNUM 1 /* Register in which address to store a structure value arrives in the function. On the Alpha, the address is passed as a hidden argument. */ #define STRUCT_VALUE 0 /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. One of the classes must always be named ALL_REGS and include all hard regs. If there is more than one class, another class must be named NO_REGS and contain no registers. The name GENERAL_REGS must be the name of a class (or an alias for another name such as ALL_REGS). This is the class of registers that is allowed by "g" or "r" in a register constraint. Also, registers outside this class are allocated only when instructions express preferences for them. The classes must be numbered in nondecreasing order; that is, a larger-numbered class must never be contained completely in a smaller-numbered class. For any two classes, it is very desirable that there be another class that represents their union. */ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" } /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS \ { {0, 0}, {~0, 0}, {0, ~0}, {~0, ~0} } /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ #define REGNO_REG_CLASS(REGNO) ((REGNO) >= 32 ? FLOAT_REGS : GENERAL_REGS) /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS NO_REGS #define BASE_REG_CLASS GENERAL_REGS /* Get reg_class from a letter such as appears in the machine description. */ #define REG_CLASS_FROM_LETTER(C) \ ((C) == 'f' ? FLOAT_REGS : NO_REGS) /* Define this macro to change register usage conditional on target flags. */ /* #define CONDITIONAL_REGISTER_USAGE */ /* The letters I, J, K, L, M, N, O, and P in a register constraint string can be used to stand for particular ranges of immediate operands. This macro defines what the ranges are. C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. For Alpha: `I' is used for the range of constants most insns can contain. `J' is the constant zero. `K' is used for the constant in an LDA insn. `L' is used for the constant in a LDAH insn. `M' is used for the constants that can be AND'ed with using a ZAP insn. `N' is used for complemented 8-bit constants. `O' is used for negated 8-bit constants. `P' is used for the constants 1, 2 and 3. */ #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \ : (C) == 'J' ? (VALUE) == 0 \ : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \ : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \ && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \ : (C) == 'M' ? zap_mask (VALUE) \ : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \ : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \ : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \ : 0) /* Similar, but for floating or large integer constants, and defining letters G and H. Here VALUE is the CONST_DOUBLE rtx itself. For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE that is the operand of a ZAP insn. */ #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \ && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \ : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \ && zap_mask (CONST_DOUBLE_LOW (VALUE)) \ && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \ : 0) /* Optional extra constraints for this machine. For the Alpha, `Q' means that this is a memory operand but not a reference to an unaligned location. */ #define EXTRA_CONSTRAINT(OP, C) \ ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) != AND \ : 0) /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. On the Alpha, all constants except zero go into a floating-point register via memory. */ #define PREFERRED_RELOAD_CLASS(X, CLASS) \ (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \ ? ((CLASS) == FLOAT_REGS ? NO_REGS : GENERAL_REGS) \ : (CLASS)) /* Loading and storing HImode or QImode values to and from memory usually requires a scratch register. The exceptions are loading QImode and HImode from an aligned address to a general register. We also cannot load an unaligned address into an FP register. */ #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \ (((GET_CODE (IN) == MEM \ || (GET_CODE (IN) == REG && REGNO (IN) >= FIRST_PSEUDO_REGISTER) \ || (GET_CODE (IN) == SUBREG \ && (GET_CODE (SUBREG_REG (IN)) == MEM \ || (GET_CODE (SUBREG_REG (IN)) == REG \ && REGNO (SUBREG_REG (IN)) >= FIRST_PSEUDO_REGISTER)))) \ && (((CLASS) == FLOAT_REGS \ && ((MODE) == SImode || (MODE) == HImode || (MODE) == QImode)) \ || (((MODE) == QImode || (MODE) == HImode) \ && unaligned_memory_operand (IN, MODE)))) \ ? GENERAL_REGS \ : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == MEM \ && GET_CODE (XEXP (IN, 0)) == AND) ? GENERAL_REGS \ : NO_REGS) #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \ (((GET_CODE (OUT) == MEM \ || (GET_CODE (OUT) == REG && REGNO (OUT) >= FIRST_PSEUDO_REGISTER) \ || (GET_CODE (OUT) == SUBREG \ && (GET_CODE (SUBREG_REG (OUT)) == MEM \ || (GET_CODE (SUBREG_REG (OUT)) == REG \ && REGNO (SUBREG_REG (OUT)) >= FIRST_PSEUDO_REGISTER)))) \ && (((MODE) == HImode || (MODE) == QImode \ || ((MODE) == SImode && (CLASS) == FLOAT_REGS)))) \ ? GENERAL_REGS \ : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == MEM \ && GET_CODE (XEXP (OUT, 0)) == AND) ? GENERAL_REGS \ : NO_REGS) /* If we are copying between general and FP registers, we need a memory location. */ #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) ((CLASS1) != (CLASS2)) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* Define the cost of moving between registers of various classes. Moving between FLOAT_REGS and anything else except float regs is expensive. In fact, we make it quite expensive because we really don't want to do these moves unless it is clearly worth it. Optimizations may reduce the impact of not being able to allocate a pseudo to a hard register. */ #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) ? 2 : 20) /* A C expressions returning the cost of moving data of MODE from a register to or from memory. On the Alpha, bump this up a bit. */ #define MEMORY_MOVE_COST(MODE) 6 /* Provide the cost of a branch. Exact meaning under development. */ #define BRANCH_COST 5 /* Adjust the cost of dependencies. */ #define ADJUST_COST(INSN,LINK,DEP,COST) \ (COST) = alpha_adjust_cost (INSN, LINK, DEP, COST) /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack makes the stack pointer a smaller address. */ #define STACK_GROWS_DOWNWARD /* Define this if the nominal address of the stack frame is at the high-address end of the local variables; that is, each additional local variable allocated goes at a more negative offset in the frame. */ /* #define FRAME_GROWS_DOWNWARD */ /* Offset within stack frame to start allocating local variables at. If FRAME_GROWS_DOWNWARD, this is the offset to the END of the first local allocated. Otherwise, it is the offset to the BEGINNING of the first local allocated. */ #define STARTING_FRAME_OFFSET current_function_outgoing_args_size /* If we generate an insn to push BYTES bytes, this says how many the stack pointer really advances by. On Alpha, don't define this because there are no push insns. */ /* #define PUSH_ROUNDING(BYTES) */ /* Define this if the maximum size of all the outgoing args is to be accumulated and pushed during the prologue. The amount can be found in the variable current_function_outgoing_args_size. */ #define ACCUMULATE_OUTGOING_ARGS /* Offset of first parameter from the argument pointer register value. */ #define FIRST_PARM_OFFSET(FNDECL) 0 /* Definitions for register eliminations. We have two registers that can be eliminated on the Alpha. First, the frame pointer register can often be eliminated in favor of the stack pointer register. Secondly, the argument pointer register can always be eliminated; it is replaced with either the stack or frame pointer. */ /* This is an array of structures. Each structure initializes one pair of eliminable registers. The "from" register number is given first, followed by "to". Eliminations of the same "from" register are listed in order of preference. */ #define ELIMINABLE_REGS \ {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} /* Given FROM and TO register numbers, say whether this elimination is allowed. Frame pointer elimination is automatically handled. All eliminations are valid since the cases where FP can't be eliminated are already handled. */ #define CAN_ELIMINATE(FROM, TO) 1 /* Define the offset between two registers, one to be eliminated, and the other its replacement, at the start of a routine. */ #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ { if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ (OFFSET) = 0; \ else \ { \ (OFFSET) = ((get_frame_size () + current_function_outgoing_args_size \ + current_function_pretend_args_size \ + alpha_sa_size () + 15) \ & ~ 15); \ if ((FROM) == ARG_POINTER_REGNUM) \ (OFFSET) -= current_function_pretend_args_size; \ } \ } /* Define this if stack space is still allocated for a parameter passed in a register. */ /* #define REG_PARM_STACK_SPACE */ /* Value is the number of bytes of arguments automatically popped when returning from a subroutine call. FUNTYPE is the data type of the function (as a tree), or for a library call it is an identifier node for the subroutine name. SIZE is the number of bytes of arguments passed on the stack. */ #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0 /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. On Alpha the value is found in $0 for integer functions and $f0 for floating-point functions. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ gen_rtx (REG, \ ((TREE_CODE (VALTYPE) == INTEGER_TYPE \ || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \ || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \ || TREE_CODE (VALTYPE) == CHAR_TYPE \ || TREE_CODE (VALTYPE) == POINTER_TYPE \ || TREE_CODE (VALTYPE) == OFFSET_TYPE) \ && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ ? word_mode : TYPE_MODE (VALTYPE), \ TARGET_FPREGS && TREE_CODE (VALTYPE) == REAL_TYPE ? 32 : 0) /* Define how to find the value returned by a library function assuming the value has mode MODE. */ #define LIBCALL_VALUE(MODE) \ gen_rtx (REG, MODE, \ TARGET_FPREGS && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 0) /* The definition of this macro implies that there are cases where a scalar value cannot be returned in registers. For the Alpha, any structure or union type is returned in memory, as are integers whose size is larger than 64 bits. */ #define RETURN_IN_MEMORY(TYPE) \ (TYPE_MODE (TYPE) == BLKmode \ || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64)) /* 1 if N is a possible register number for a function value as seen by the caller. */ #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 32) /* 1 if N is a possible register number for function argument passing. On Alpha, these are $16-$21 and $f16-$f21. */ #define FUNCTION_ARG_REGNO_P(N) \ (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32)) /* Define a data type for recording info about an argument list during the scan of that argument list. This data type should hold all necessary information about the function itself and about the args processed so far, enough to enable macros such as FUNCTION_ARG to determine where the next arg should go. On Alpha, this is a single integer, which is a number of words of arguments scanned so far. Thus 6 or more means all following args should go on the stack. */ #define CUMULATIVE_ARGS int /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) (CUM) = 0 /* Define intermediate macro to compute the size (in registers) of an argument for the Alpha. */ #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \ ((MODE) != BLKmode \ ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \ : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ if (MUST_PASS_IN_STACK (MODE, TYPE)) \ (CUM) = 6; \ else \ (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED) /* Determine where to put an argument to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. MODE is the argument's machine mode. TYPE is the data type of the argument (as a tree). This is null for libcalls where that information may not be available. CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called. NAMED is nonzero if this argument is a named parameter (otherwise it is an extra parameter matching an ellipsis). On Alpha the first 6 words of args are normally in registers and the rest are pushed. */ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ ((CUM) < 6 && ! MUST_PASS_IN_STACK (MODE, TYPE) \ ? gen_rtx(REG, (MODE), \ (CUM) + 16 + (TARGET_FPREGS \ && GET_MODE_CLASS (MODE) == MODE_FLOAT) * 32) : 0) /* Specify the padding direction of arguments. On the Alpha, we must pad upwards in order to be able to pass args in registers. */ #define FUNCTION_ARG_PADDING(MODE, TYPE) upward /* For an arg passed partly in registers and partly in memory, this is the number of registers used. For args passed entirely in registers or entirely in memory, zero. */ #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \ ? 6 - (CUM) : 0) /* Perform any needed actions needed for a function that is receiving a variable number of arguments. CUM is as above. MODE and TYPE are the mode and type of the current parameter. PRETEND_SIZE is a variable that should be set to the amount of stack that must be pushed by the prolog to pretend that our caller pushed it. Normally, this macro will push all remaining incoming registers on the stack and set PRETEND_SIZE to the length of the registers pushed. On the Alpha, we allocate space for all 12 arg registers, but only push those that are remaining. However, if NO registers need to be saved, don't allocate any space. This is not only because we won't need the space, but because AP includes the current_pretend_args_size and we don't want to mess up any ap-relative addresses already made. If we are not to use the floating-point registers, save the integer registers where we would put the floating-point registers. This is not the most efficient way to implement varargs with just one register class, but it isn't worth doing anything more efficient in this rare case. */ #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ { if ((CUM) < 6) \ { \ if (! (NO_RTL)) \ { \ move_block_from_reg \ (16 + CUM, \ gen_rtx (MEM, BLKmode, \ plus_constant (virtual_incoming_args_rtx, \ ((CUM) + 6)* UNITS_PER_WORD)), \ 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \ move_block_from_reg \ (16 + (TARGET_FPREGS ? 32 : 0) + CUM, \ gen_rtx (MEM, BLKmode, \ plus_constant (virtual_incoming_args_rtx, \ (CUM) * UNITS_PER_WORD)), \ 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \ } \ PRETEND_SIZE = 12 * UNITS_PER_WORD; \ } \ } /* Generate necessary RTL for __builtin_saveregs(). ARGLIST is the argument list; see expr.c. */ extern struct rtx_def *alpha_builtin_saveregs (); #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) alpha_builtin_saveregs (ARGLIST) /* Define the information needed to generate branch and scc insns. This is stored from the compare operation. Note that we can't use "rtx" here since it hasn't been defined! */ extern struct rtx_def *alpha_compare_op0, *alpha_compare_op1; extern int alpha_compare_fp_p; /* This macro produces the initial definition of a function name. On the Alpha, we need to save the function name for the prologue and epilogue. */ extern char *alpha_function_name; #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ { \ alpha_function_name = NAME; \ } /* This macro generates the assembly code for function entry. FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. Refer to the array `regs_ever_live' to determine which registers to save; `regs_ever_live[I]' is nonzero if register number I is ever used in the function. This macro is responsible for knowing which registers should not be saved even if used. */ #define FUNCTION_PROLOGUE(FILE, SIZE) output_prolog (FILE, SIZE) /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ #define FUNCTION_PROFILER(FILE, LABELNO) /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, the stack pointer does not matter. The value is tested only in functions that have frame pointers. No definition is equivalent to always zero. */ #define EXIT_IGNORE_STACK 1 /* This macro generates the assembly code for function exit, on machines that need it. If FUNCTION_EPILOGUE is not defined then individual return instructions are generated for each return statement. Args are same as for FUNCTION_PROLOGUE. The function epilogue should not depend on the current stack pointer! It should use the frame pointer only. This is mandatory because of alloca; we also take advantage of it to omit stack adjustments before returning. */ #define FUNCTION_EPILOGUE(FILE, SIZE) output_epilog (FILE, SIZE) /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. The trampoline should set the static chain pointer to value placed into the trampoline and should branch to the specified routine. Note that $27 has been set to the address of the trampoline, so we can use it for addressability of the two data items. Trampolines are always aligned to FUNCTION_BOUNDARY, which is 64 bits. */ #define TRAMPOLINE_TEMPLATE(FILE) \ { \ fprintf (FILE, "\tldq $1,24($27)\n"); \ fprintf (FILE, "\tldq $27,16($27)\n"); \ fprintf (FILE, "\tjmp $31,($27),0\n"); \ fprintf (FILE, "\tnop\n"); \ fprintf (FILE, "\t.quad 0,0\n"); \ } /* Section in which to place the trampoline. On Alpha, instructions may only be placed in a text segment. */ #define TRAMPOLINE_SECTION text_section /* Length in units of the trampoline for entering a nested function. */ #define TRAMPOLINE_SIZE 32 /* Emit RTL insns to initialize the variable parts of a trampoline. FNADDR is an RTX for the address of the function's pure code. CXT is an RTX for the static chain value for the function. We assume here that a function will be called many more times than its address is taken (e.g., it might be passed to qsort), so we take the trouble to initialize the "hint" field in the JMP insn. Note that the hint field is PC (new) + 4 * bits 13:0. */ #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ rtx _temp, _temp1, _addr; \ \ _addr = memory_address (Pmode, plus_constant ((TRAMP), 16)); \ emit_move_insn (gen_rtx (MEM, Pmode, _addr), (FNADDR)); \ _addr = memory_address (Pmode, plus_constant ((TRAMP), 24)); \ emit_move_insn (gen_rtx (MEM, Pmode, _addr), (CXT)); \ \ _temp = force_operand (plus_constant ((TRAMP), 12), NULL_RTX); \ _temp = expand_binop (DImode, sub_optab, (FNADDR), _temp, _temp, 1, \ OPTAB_WIDEN); \ _temp = expand_shift (RSHIFT_EXPR, Pmode, _temp, \ build_int_2 (2, 0), NULL_RTX, 1); \ _temp = expand_and (gen_lowpart (SImode, _temp), \ GEN_INT (0x3fff), 0); \ \ _addr = memory_address (SImode, plus_constant ((TRAMP), 8)); \ _temp1 = force_reg (SImode, gen_rtx (MEM, SImode, _addr)); \ _temp1 = expand_and (_temp1, GEN_INT (0xffffc000), NULL_RTX); \ _temp1 = expand_binop (SImode, ior_optab, _temp1, _temp, _temp1, 1, \ OPTAB_WIDEN); \ \ emit_move_insn (gen_rtx (MEM, SImode, _addr), _temp1); \ \ emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \ "__enable_execute_stack"), \ 0, VOIDmode, 1,_addr, Pmode); \ \ emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, \ gen_rtvec (1, const0_rtx), 0)); \ } /* Attempt to turn on access permissions for the stack. */ #define TRANSFER_FROM_TRAMPOLINE \ \ void \ __enable_execute_stack (addr) \ void *addr; \ { \ long size = getpagesize (); \ long mask = ~(size-1); \ char *page = (char *) (((long) addr) & mask); \ char *end = (char *) ((((long) (addr + TRAMPOLINE_SIZE)) & mask) + size); \ \ /* 7 is PROT_READ | PROT_WRITE | PROT_EXEC */ \ if (mprotect (page, end - page, 7) < 0) \ perror ("mprotect of trampoline code"); \ } /* Addressing modes, and classification of registers for them. */ /* #define HAVE_POST_INCREMENT */ /* #define HAVE_POST_DECREMENT */ /* #define HAVE_PRE_DECREMENT */ /* #define HAVE_PRE_INCREMENT */ /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. */ #define REGNO_OK_FOR_INDEX_P(REGNO) 0 #define REGNO_OK_FOR_BASE_P(REGNO) \ (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)) /* Maximum number of registers that can appear in a valid memory address. */ #define MAX_REGS_PER_ADDRESS 1 /* Recognize any constant value that is a valid address. For the Alpha, there are only constants none since we want to use LDA to load any symbolic addresses into registers. */ #define CONSTANT_ADDRESS_P(X) \ (GET_CODE (X) == CONST_INT \ && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) /* Include all constant integers and constant doubles, but not floating-point, except for floating-point zero. */ #define LEGITIMATE_CONSTANT_P(X) \ (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \ || (X) == CONST0_RTX (GET_MODE (X))) /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. The usual definition accepts all pseudo regs; the other rejects them unless they have been allocated suitable hard regs. The symbol REG_OK_STRICT causes the latter definition to be used. Most source files want to accept pseudo regs in the hope that they will get allocated to the class that the insn wants them to be in. Source files for reload pass need to be strict. After reload, it makes no difference, since pseudo regs have been eliminated by then. */ #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ #define REG_OK_FOR_INDEX_P(X) 0 /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ #define REG_OK_FOR_BASE_P(X) \ (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER) #else /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) #endif /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. For Alpha, we have either a constant address or the sum of a register and a constant address, or just a register. For DImode, any of those forms can be surrounded with an AND that clear the low-order three bits; this is an "unaligned" access. We also allow a SYMBOL_REF that is the name of the current function as valid address. This is for CALL_INSNs. It cannot be used in any other context. First define the basic valid address. */ #define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \ { if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \ goto ADDR; \ if (CONSTANT_ADDRESS_P (X)) \ goto ADDR; \ if (GET_CODE (X) == PLUS \ && REG_P (XEXP (X, 0)) \ && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ goto ADDR; \ } /* Now accept the simple address, or, for DImode only, an AND of a simple address that turns off the low three bits. */ extern char *current_function_name; #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \ if ((MODE) == DImode \ && GET_CODE (X) == AND \ && GET_CODE (XEXP (X, 1)) == CONST_INT \ && INTVAL (XEXP (X, 1)) == -8) \ GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \ if ((MODE) == Pmode && GET_CODE (X) == SYMBOL_REF \ && ! strcmp (XSTR (X, 0), current_function_name)) \ goto ADDR; \ } /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. OLDX is the address as it was before break_out_memory_refs was called. In some cases it is useful to look at this to decide what needs to be done. MODE and WIN are passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. It is always safe for this macro to do nothing. It exists to recognize opportunities to optimize the output. For the Alpha, there are three cases we handle: (1) If the address is (plus reg const_int) and the CONST_INT is not a valid offset, compute the high part of the constant and add it to the register. Then our address is (plus temp low-part-const). (2) If the address is (const (plus FOO const_int)), find the low-order part of the CONST_INT. Then load FOO plus any high-order part of the CONST_INT into a register. Our address is (plus reg low-part-const). This is done to reduce the number of GOT entries. (3) If we have a (plus reg const), emit the load as in (2), then add the two registers, and finally generate (plus reg low-part-const) as our address. */ #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ && GET_CODE (XEXP (X, 1)) == CONST_INT \ && ! CONSTANT_ADDRESS_P (XEXP (X, 1))) \ { \ HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \ HOST_WIDE_INT highpart = val - lowpart; \ rtx high = GEN_INT (highpart); \ rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0), \ high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \ \ (X) = plus_constant (temp, lowpart); \ goto WIN; \ } \ else if (GET_CODE (X) == CONST \ && GET_CODE (XEXP (X, 0)) == PLUS \ && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \ { \ HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \ HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \ HOST_WIDE_INT highpart = val - lowpart; \ rtx high = XEXP (XEXP (X, 0), 0); \ \ if (highpart) \ high = plus_constant (high, highpart); \ \ (X) = plus_constant (force_reg (Pmode, high), lowpart); \ goto WIN; \ } \ else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ && GET_CODE (XEXP (X, 1)) == CONST \ && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS \ && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \ { \ HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \ HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \ HOST_WIDE_INT highpart = val - lowpart; \ rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0); \ \ if (highpart) \ high = plus_constant (high, highpart); \ \ high = expand_binop (Pmode, add_optab, XEXP (X, 0), \ force_reg (Pmode, high), \ high, 1, OPTAB_LIB_WIDEN); \ (X) = plus_constant (high, lowpart); \ goto WIN; \ } \ } /* Go to LABEL if ADDR (a legitimate address expression) has an effect that depends on the machine mode it is used for. On the Alpha this is true only for the unaligned modes. We can simplify this test since we know that the address must be valid. */ #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ { if (GET_CODE (ADDR) == AND) goto LABEL; } /* Compute the cost of an address. For the Alpha, all valid addresses are the same cost. */ #define ADDRESS_COST(X) 0 /* Define this if some processing needs to be done immediately before emitting code for an insn. */ /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */ /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE SImode /* Define this if the tablejump instruction expects the table to contain offsets from the address of the table. Do not define this if the table should contain absolute addresses. */ /* #define CASE_VECTOR_PC_RELATIVE */ /* Specify the tree operation to be used to convert reals to integers. */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR /* This is the kind of divide that is easiest to do in the general case. */ #define EASY_DIV_EXPR TRUNC_DIV_EXPR /* Define this as 1 if `char' should by default be signed; else as 0. */ #define DEFAULT_SIGNED_CHAR 1 /* This flag, if defined, says the same insns that convert to a signed fixnum also convert validly to an unsigned one. We actually lie a bit here as overflow conditions are different. But they aren't being checked anyway. */ #define FIXUNS_TRUNC_LIKE_FIX_TRUNC /* Max number of bytes we can move to or from memory in one reasonably fast instruction. */ #define MOVE_MAX 8 /* Largest number of bytes of an object that can be placed in a register. On the Alpha we have plenty of registers, so use TImode. */ #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) /* Nonzero if access to memory by bytes is no faster than for words. Also non-zero if doing byte operations (specifically shifts) in registers is undesirable. On the Alpha, we want to not use the byte operation and instead use masking operations to access fields; these will save instructions. */ #define SLOW_BYTE_ACCESS 1 /* Define if operations between registers always perform the operation on the full register even if a narrower mode is specified. */ #define WORD_REGISTER_OPERATIONS /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly done, NIL if none. */ #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND /* Define if loading short immediate values into registers sign extends. */ #define SHORT_IMMEDIATES_SIGN_EXTEND /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 /* We assume that the store-condition-codes instructions store 0 for false and some other value for true. This is the value stored for true. */ #define STORE_FLAG_VALUE 1 /* Define the value returned by a floating-point comparison instruction. */ #define FLOAT_STORE_FLAG_VALUE 0.5 /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ #define Pmode DImode /* Mode of a function address in a call instruction (for indexing purposes). */ #define FUNCTION_MODE Pmode /* Define this if addresses of constant functions shouldn't be put through pseudo regs where they can be cse'd. Desirable on machines where ordinary constants are expensive but a CALL with constant address is cheap. We define this on the Alpha so that gen_call and gen_call_value get to see the SYMBOL_REF (for the hint field of the jsr). It will then copy it into a register, thus actually letting the address be cse'ed. */ #define NO_FUNCTION_CSE /* Define this to be nonzero if shift instructions ignore all but the low-order few bits. */ #define SHIFT_COUNT_TRUNCATED 1 /* Use atexit for static constructors/destructors, instead of defining our own exit function. */ #define HAVE_ATEXIT /* Compute the cost of computing a constant rtl expression RTX whose rtx-code is CODE. The body of this macro is a portion of a switch statement. If the code is computed here, return it with a return statement. Otherwise, break from the switch. We only care about the cost if it is valid in an insn, so all constants are cheap. */ #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ case CONST_DOUBLE: \ return 0; \ case CONST: \ case SYMBOL_REF: \ case LABEL_REF: \ return 6; \ /* Provide the costs of a rtl expression. This is in the body of a switch on CODE. */ #define RTX_COSTS(X,CODE,OUTER_CODE) \ case PLUS: \ case MINUS: \ if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ return COSTS_N_INSNS (6); \ else if (GET_CODE (XEXP (X, 0)) == MULT \ && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \ return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \ + rtx_cost (XEXP (X, 1), OUTER_CODE)); \ break; \ case MULT: \ if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ return COSTS_N_INSNS (6); \ else if (GET_CODE (XEXP (X, 1)) != CONST_INT \ || exact_log2 (INTVAL (XEXP (X, 1))) < 0) \ return COSTS_N_INSNS (21); \ else if (const48_operand (XEXP (X, 1), VOIDmode)) \ break; \ return COSTS_N_INSNS (2); \ case ASHIFT: \ if (GET_CODE (XEXP (X, 1)) == CONST_INT \ && INTVAL (XEXP (X, 1)) <= 3) \ break; \ /* ... fall through ... */ \ case ASHIFTRT: case LSHIFTRT: case IF_THEN_ELSE: \ return COSTS_N_INSNS (2); \ case DIV: \ case UDIV: \ case MOD: \ case UMOD: \ if (GET_MODE (X) == SFmode) \ return COSTS_N_INSNS (34); \ else if (GET_MODE (X) == DFmode) \ return COSTS_N_INSNS (63); \ else \ return COSTS_N_INSNS (70); \ case MEM: \ return COSTS_N_INSNS (3); /* Control the assembler format that we output. */ /* Output at beginning of assembler file. */ #define ASM_FILE_START(FILE) \ { \ alpha_write_verstamp (FILE); \ fprintf (FILE, "\t.set noreorder\n"); \ fprintf (FILE, "\t.set noat\n"); \ ASM_OUTPUT_SOURCE_FILENAME (FILE, main_input_filename); \ } /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ #define ASM_APP_ON "" /* Output to assembler file text saying following lines no longer contain unusual constructs. */ #define ASM_APP_OFF "" #define TEXT_SECTION_ASM_OP ".text" /* Output before read-only data. */ #define READONLY_DATA_SECTION_ASM_OP ".rdata" /* Output before writable data. */ #define DATA_SECTION_ASM_OP ".data" /* Define an extra section for read-only data, a routine to enter it, and indicate that it is for read-only data. */ #define EXTRA_SECTIONS readonly_data #define EXTRA_SECTION_FUNCTIONS \ void \ literal_section () \ { \ if (in_section != readonly_data) \ { \ fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \ in_section = readonly_data; \ } \ } \ #define READONLY_DATA_SECTION literal_section /* If we are referencing a function that is static or is known to be in this file, make the SYMBOL_REF special. We can use this to see indicate that we can branch to this function without setting PV or restoring GP. */ #define ENCODE_SECTION_INFO(DECL) \ if (TREE_CODE (DECL) == FUNCTION_DECL \ && (TREE_ASM_WRITTEN (DECL) || ! TREE_PUBLIC (DECL))) \ SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ #define REGISTER_NAMES \ {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \ "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \ "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \ "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\ "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"} /* How to renumber registers for dbx and gdb. */ #define DBX_REGISTER_NUMBER(REGNO) (REGNO) /* This is how to output the definition of a user-level label named NAME, such as the label on a static function or variable NAME. */ #define ASM_OUTPUT_LABEL(FILE,NAME) \ do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) /* This is how to output a command to make the user-level label named NAME defined for reference from other files. */ #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) /* This is how to output a reference to a user-level label named NAME. `assemble_name' uses this. */ #define ASM_OUTPUT_LABELREF(FILE,NAME) \ fprintf (FILE, "%s", NAME) /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ if ((PREFIX)[0] == 'L') \ fprintf (FILE, "$%s%d:\n", & (PREFIX)[1], NUM + 32); \ else \ fprintf (FILE, "%s%d:\n", PREFIX, NUM); /* This is how to output a label for a jump table. Arguments are the same as for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is passed. */ #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \ { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); } /* This is how to store into the string LABEL the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ if ((PREFIX)[0] == 'L') \ sprintf (LABEL, "*$%s%d", & (PREFIX)[1], NUM + 32); \ else \ sprintf (LABEL, "*%s%d", PREFIX, NUM) /* This is how to output an assembler line defining a `double' constant. */ #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ { \ if (REAL_VALUE_ISINF (VALUE) \ || REAL_VALUE_ISNAN (VALUE) \ || REAL_VALUE_MINUS_ZERO (VALUE)) \ { \ long t[2]; \ REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ fprintf (FILE, "\t.quad 0x%lx%08lx\n", \ t[1] & 0xffffffff, t[0] & 0xffffffff); \ } \ else \ { \ char str[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str); \ fprintf (FILE, "\t.t_floating %s\n", str); \ } \ } /* This is how to output an assembler line defining a `float' constant. */ #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ { \ if (REAL_VALUE_ISINF (VALUE) \ || REAL_VALUE_ISNAN (VALUE) \ || REAL_VALUE_MINUS_ZERO (VALUE)) \ { \ long t; \ REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \ } \ else \ { \ char str[30]; \ REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \ fprintf (FILE, "\t.s_floating %s\n", str); \ } \ } /* This is how to output an assembler line defining an `int' constant. */ #define ASM_OUTPUT_INT(FILE,VALUE) \ fprintf (FILE, "\t.long %d\n", \ (GET_CODE (VALUE) == CONST_INT \ ? INTVAL (VALUE) & 0xffffffff : (abort (), 0))) /* This is how to output an assembler line defining a `long' constant. */ #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ ( fprintf (FILE, "\t.quad "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* Likewise for `char' and `short' constants. */ #define ASM_OUTPUT_SHORT(FILE,VALUE) \ fprintf (FILE, "\t.word %d\n", \ (GET_CODE (VALUE) == CONST_INT \ ? INTVAL (VALUE) & 0xffff : (abort (), 0))) #define ASM_OUTPUT_CHAR(FILE,VALUE) \ fprintf (FILE, "\t.byte %d\n", \ (GET_CODE (VALUE) == CONST_INT \ ? INTVAL (VALUE) & 0xff : (abort (), 0))) /* We use the default ASCII-output routine, except that we don't write more than 50 characters since the assembler doesn't support very long lines. */ #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \ do { \ FILE *_hide_asm_out_file = (MYFILE); \ unsigned char *_hide_p = (unsigned char *) (MYSTRING); \ int _hide_thissize = (MYLENGTH); \ int _size_so_far = 0; \ { \ FILE *asm_out_file = _hide_asm_out_file; \ unsigned char *p = _hide_p; \ int thissize = _hide_thissize; \ int i; \ fprintf (asm_out_file, "\t.ascii \""); \ \ for (i = 0; i < thissize; i++) \ { \ register int c = p[i]; \ \ if (_size_so_far ++ > 50 && i < thissize - 4) \ _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \ \ if (c == '\"' || c == '\\') \ putc ('\\', asm_out_file); \ if (c >= ' ' && c < 0177) \ putc (c, asm_out_file); \ else \ { \ fprintf (asm_out_file, "\\%o", c); \ /* After an octal-escape, if a digit follows, \ terminate one string constant and start another. \ The Vax assembler fails to stop reading the escape \ after three digits, so this is the only way we \ can get it to parse the data properly. */ \ if (i < thissize - 1 \ && p[i + 1] >= '0' && p[i + 1] <= '9') \ fprintf (asm_out_file, "\"\n\t.ascii \""); \ } \ } \ fprintf (asm_out_file, "\"\n"); \ } \ } \ while (0) /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \ (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \ (REGNO) & 31); /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \ (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \ (REGNO) & 31); /* This is how to output an assembler line for a numeric constant byte. */ #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf (FILE, "\t.byte 0x%x\n", (VALUE) & 0xff) /* This is how to output an element of a case-vector that is absolute. */ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "\t.gprel32 $%d\n", (VALUE) + 32) /* This is how to output an element of a case-vector that is relative. (Alpha does not use such vectors, but we must define this macro anyway.) */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) abort () /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG) != 0) \ fprintf (FILE, "\t.align %d\n", LOG); /* This is how to advance the location counter by SIZE bytes. */ #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t.space %d\n", (SIZE)) /* This says how to output an assembler line to define a global common symbol. */ #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fputs ("\t.comm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%d\n", (SIZE))) /* This says how to output an assembler line to define a local common symbol. */ #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \ ( fputs ("\t.lcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%d\n", (SIZE))) /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) /* Define the parentheses used to group arithmetic operations in assembler code. */ #define ASM_OPEN_PAREN "(" #define ASM_CLOSE_PAREN ")" /* Define results of standard character escape sequences. */ #define TARGET_BELL 007 #define TARGET_BS 010 #define TARGET_TAB 011 #define TARGET_NEWLINE 012 #define TARGET_VT 013 #define TARGET_FF 014 #define TARGET_CR 015 /* Print operand X (an rtx) in assembler syntax to file FILE. CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. For `%' followed by punctuation, CODE is the punctuation and X is null. */ #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) /* Determine which codes are valid without a following integer. These must not be alphabetic. */ #define PRINT_OPERAND_PUNCT_VALID_P(CODE) 0 /* Print a memory address as an operand to reference that memory location. */ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ { rtx addr = (ADDR); \ int basereg = 31; \ HOST_WIDE_INT offset = 0; \ \ if (GET_CODE (addr) == AND) \ addr = XEXP (addr, 0); \ \ if (GET_CODE (addr) == REG) \ basereg = REGNO (addr); \ else if (GET_CODE (addr) == CONST_INT) \ offset = INTVAL (addr); \ else if (GET_CODE (addr) == PLUS \ && GET_CODE (XEXP (addr, 0)) == REG \ && GET_CODE (XEXP (addr, 1)) == CONST_INT) \ basereg = REGNO (XEXP (addr, 0)), offset = INTVAL (XEXP (addr, 1)); \ else \ abort (); \ \ fprintf (FILE, "%d($%d)", offset, basereg); \ } /* Define the codes that are matched by predicates in alpha.c. */ #define PREDICATE_CODES \ {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ {"add_operand", {SUBREG, REG, CONST_INT}}, \ {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \ {"const48_operand", {CONST_INT}}, \ {"and_operand", {SUBREG, REG, CONST_INT}}, \ {"mode_mask_operand", {CONST_INT}}, \ {"mul8_operand", {CONST_INT}}, \ {"mode_width_operand", {CONST_INT}}, \ {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \ {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \ {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \ {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \ {"fp0_operand", {CONST_DOUBLE}}, \ {"current_file_function_operand", {SYMBOL_REF}}, \ {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ SYMBOL_REF, CONST, LABEL_REF}}, \ {"aligned_memory_operand", {MEM}}, \ {"unaligned_memory_operand", {MEM}}, \ {"any_memory_operand", {MEM}}, /* Definitions for debugging. */ #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */ #define DBX_DEBUGGING_INFO /* generate embedded stabs */ #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */ #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */ #define PREFERRED_DEBUGGING_TYPE ((len > 1 && !strncmp (str, "ggdb", len)) ? DBX_DEBUG : SDB_DEBUG) #endif /* Correct the offset of automatic variables and arguments. Note that the Alpha debug format wants all automatic variables and arguments to be in terms of two different offsets from the virtual frame pointer, which is the stack pointer before any adjustment in the function. The offset for the argument pointer is fixed for the native compiler, it is either zero (for the no arguments case) or large enough to hold all argument registers. The offset for the auto pointer is the fourth argument to the .frame directive (local_offset). To stay compatible with the native tools we use the same offsets from the virtual frame pointer and adjust the debugger arg/auto offsets accordingly. These debugger offsets are set up in output_prolog. */ long alpha_arg_offset; long alpha_auto_offset; #define DEBUGGER_AUTO_OFFSET(X) \ ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset) #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset) #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \ alpha_output_lineno (STREAM, LINE) extern void alpha_output_lineno (); #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ alpha_output_filename (STREAM, NAME) extern void alpha_output_filename (); /* mips-tfile.c limits us to strings of one page. */ #define DBX_CONTIN_LENGTH 4000 /* By default, turn on GDB extensions. */ #define DEFAULT_GDB_EXTENSIONS 1 /* If we are smuggling stabs through the ALPHA ECOFF object format, put a comment in front of the .stab operation so that the ALPHA assembler does not choke. The mips-tfile program will correctly put the stab into the object file. */ #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs") #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn") #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd") /* Forward references to tags are allowed. */ #define SDB_ALLOW_FORWARD_REFERENCES /* Unknown tags are also allowed. */ #define SDB_ALLOW_UNKNOWN_REFERENCES #define PUT_SDB_DEF(a) \ do { \ fprintf (asm_out_file, "\t%s.def\t", \ (TARGET_GAS) ? "" : "#"); \ ASM_OUTPUT_LABELREF (asm_out_file, a); \ fputc (';', asm_out_file); \ } while (0) #define PUT_SDB_PLAIN_DEF(a) \ do { \ fprintf (asm_out_file, "\t%s.def\t.%s;", \ (TARGET_GAS) ? "" : "#", (a)); \ } while (0) #define PUT_SDB_TYPE(a) \ do { \ fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \ } while (0) /* For block start and end, we create labels, so that later we can figure out where the correct offset is. The normal .ent/.end serve well enough for functions, so those are just commented out. */ extern int sdb_label_count; /* block start/end next label # */ #define PUT_SDB_BLOCK_START(LINE) \ do { \ fprintf (asm_out_file, \ "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \ sdb_label_count, \ (TARGET_GAS) ? "" : "#", \ sdb_label_count, \ (LINE)); \ sdb_label_count++; \ } while (0) #define PUT_SDB_BLOCK_END(LINE) \ do { \ fprintf (asm_out_file, \ "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \ sdb_label_count, \ (TARGET_GAS) ? "" : "#", \ sdb_label_count, \ (LINE)); \ sdb_label_count++; \ } while (0) #define PUT_SDB_FUNCTION_START(LINE) #define PUT_SDB_FUNCTION_END(LINE) #define PUT_SDB_EPILOGUE_END(NAME) /* Specify to run a post-processor, mips-tfile after the assembler has run to stuff the ecoff debug information into the object file. This is needed because the Alpha assembler provides no way of specifying such information in the assembly file. */ #if (TARGET_DEFAULT & MASK_GAS) != 0 #define ASM_FINAL_SPEC "\ %{malpha-as: %{!mno-mips-tfile: \ \n mips-tfile %{v*: -v} \ %{K: -I %b.o~} \ %{!K: %{save-temps: -I %b.o~}} \ %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \ %{.s:%i} %{!.s:%g.s}}}" #else #define ASM_FINAL_SPEC "\ %{!mgas: %{!mno-mips-tfile: \ \n mips-tfile %{v*: -v} \ %{K: -I %b.o~} \ %{!K: %{save-temps: -I %b.o~}} \ %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \ %{.s:%i} %{!.s:%g.s}}}" #endif /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for mips-tdump.c to print them out. These must match the corresponding definitions in gdb/mipsread.c. Unfortunately, gcc and gdb do not currently share any directories. */ #define CODE_MASK 0x8F300 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK) #define MIPS_MARK_STAB(code) ((code)+CODE_MASK) #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK) /* Override some mips-tfile definitions. */ #define SHASH_SIZE 511 #define THASH_SIZE 55 gcc-2.5.8/config/alpha/alpha.md100444 22011 13 300252 5506572466 15005 0ustar kenneruser;;- Machine description for DEC Alpha for GNU C compiler ;; Copyright (C) 1992 Free Software Foundation, Inc. ;; Contributed by Richard Kenner (kenner@nyu.edu) ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ;; Define an insn type attribute. This is used in function unit delay ;; computations, among other purposes. For the most part, we use the names ;; defined in the EV4 documentation, but add a few that we have to know about ;; separately. (define_attr "type" "ld,st,ibr,fbr,jsr,iaddlog,shiftcm,icmp,imull,imulq,fpop,fdivs,fdivt,ldsym,isubr" (const_string "shiftcm")) ;; We include four function units: ABOX, which computes the address, ;; BBOX, used for branches, EBOX, used for integer operations, and FBOX, ;; used for FP operations. ;; ;; We assume that we have been successful in getting double issues and ;; hence multiply all costs by two insns per cycle. The minimum time in ;; a function unit is 2 cycle, which will tend to produce the double ;; issues. ;; Memory delivers its result in three cycles. (define_function_unit "abox" 1 0 (eq_attr "type" "ld,ldsym,st") 6 2) ;; Branches have no delay cost, but do tie up the unit for two cycles. (define_function_unit "bbox" 1 1 (eq_attr "type" "ibr,fbr,jsr") 4 4) ;; Arithmetic insns are normally have their results available after two ;; cycles. There are a number of exceptions. They are encoded in ;; ADJUST_COST. Some of the other insns have similar exceptions. (define_function_unit "ebox" 1 0 (eq_attr "type" "iaddlog,shiftcm,icmp") 4 2) ;; These really don't take up the integer pipeline, but they do occupy ;; IBOX1; we approximate here. (define_function_unit "ebox" 1 0 (eq_attr "type" "imull") 42 2) (define_function_unit "ebox" 1 0 (eq_attr "type" "imulq") 46 2) (define_function_unit "imult" 1 0 (eq_attr "type" "imull") 42 38) (define_function_unit "imult" 1 0 (eq_attr "type" "imulq") 46 42) (define_function_unit "fbox" 1 0 (eq_attr "type" "fpop") 12 2) (define_function_unit "fbox" 1 0 (eq_attr "type" "fdivs") 68 0) (define_function_unit "fbox" 1 0 (eq_attr "type" "fdivt") 126 0) (define_function_unit "divider" 1 0 (eq_attr "type" "fdivs") 68 60) (define_function_unit "divider" 1 0 (eq_attr "type" "fdivt") 126 118) ;; First define the arithmetic insns. Note that the 32-bit forms also ;; sign-extend. ;; Note that we can do sign extensions in both FP and integer registers. ;; However, the result must be in the same type of register as the input. ;; The register preferencing code can't handle this case very well, so, for ;; now, don't let the FP case show up here for preferencing. Also, ;; sign-extends in FP registers take two instructions. (define_insn "extendsidi2" [(set (match_operand:DI 0 "register_operand" "=r,r,*f") (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,*f")))] "" "@ addl %1,$31,%0 ldl %0,%1 cvtql %1,%0\;cvtlq %0,%0" [(set_attr "type" "iaddlog,ld,fpop")]) (define_insn "addsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ") (match_operand:SI 2 "add_operand" "rI,O,K,L")))] "" "@ addl %r1,%2,%0 subl %r1,%n2,%0 lda %0,%2(%r1) ldah %0,%h2(%r1)" [(set_attr "type" "iaddlog")]) (define_split [(set (match_operand:SI 0 "register_operand" "") (plus:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "const_int_operand" "")))] "! add_operand (operands[2], SImode)" [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] " { HOST_WIDE_INT val = INTVAL (operands[2]); HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); HOST_WIDE_INT rest = val - low; operands[3] = GEN_INT (rest); operands[4] = GEN_INT (low); }") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r,r") (sign_extend:DI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") (match_operand:SI 2 "sext_add_operand" "rI,O"))))] "" "@ addl %r1,%2,%0 subl %r1,%n2,%0" [(set_attr "type" "iaddlog")]) (define_split [(set (match_operand:DI 0 "register_operand" "") (sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "const_int_operand" "")))) (clobber (match_operand:SI 3 "register_operand" ""))] "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) % 4 == 0" [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3) (match_dup 5)) (match_dup 1))))] " { HOST_WIDE_INT val = INTVAL (operands[2]) / 4; int mult = 4; if (val % 2 == 0) val /= 2, mult = 8; operands[4] = GEN_INT (val); operands[5] = GEN_INT (mult); }") (define_insn "adddi3" [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ") (match_operand:DI 2 "add_operand" "rI,O,K,L")))] "" "@ addq %r1,%2,%0 subq %r1,%n2,%0 lda %0,%2(%r1) ldah %0,%h2(%r1)" [(set_attr "type" "iaddlog")]) ;; Don't do this if we are adjusting SP since we don't want to do ;; it in two steps. (define_split [(set (match_operand:DI 0 "register_operand" "") (plus:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "const_int_operand" "")))] "! add_operand (operands[2], DImode) && REGNO (operands[0]) != STACK_POINTER_REGNUM" [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] " { HOST_WIDE_INT val = INTVAL (operands[2]); HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); HOST_WIDE_INT rest = val - low; operands[3] = GEN_INT (rest); operands[4] = GEN_INT (low); }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r") (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ") (match_operand:SI 2 "const48_operand" "I,I")) (match_operand:SI 3 "sext_add_operand" "rI,O")))] "" "@ s%2addl %r1,%3,%0 s%2subl %r1,%n3,%0" [(set_attr "type" "iaddlog")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r,r") (sign_extend:DI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ") (match_operand:SI 2 "const48_operand" "I,I")) (match_operand:SI 3 "sext_add_operand" "rI,O"))))] "" "@ s%2addl %r1,%3,%0 s%2subl %r1,%n3,%0" [(set_attr "type" "iaddlog")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r,r") (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ") (match_operand:DI 2 "const48_operand" "I,I")) (match_operand:DI 3 "reg_or_8bit_operand" "rI,O")))] "" "@ s%2addq %r1,%3,%0 s%2subq %1,%n3,%0" [(set_attr "type" "iaddlog")]) ;; These variants of the above insns can occur if the third operand ;; is the frame pointer. This is a kludge, but there doesn't ;; seem to be a way around it. Only recognize them while reloading. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=&r") (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "const48_operand" "I")) (match_operand:SI 3 "register_operand" "r")) (match_operand:SI 4 "const_int_operand" "rI")))] "reload_in_progress" "s%2addl %r1,%3,%0\;addl %0,%4,%0" [(set_attr "type" "iaddlog")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=&r") (sign_extend:DI (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "const48_operand" "I")) (match_operand:SI 3 "register_operand" "r")) (match_operand:SI 4 "const_int_operand" "rI"))))] "reload_in_progress" "s%2addl %r1,%3,%0\;addl %0,%4,%0" [(set_attr "type" "iaddlog")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=&r") (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (match_operand:DI 2 "const48_operand" "I")) (match_operand:DI 3 "register_operand" "r")) (match_operand:DI 4 "const_int_operand" "rI")))] "reload_in_progress" "s%2addq %r1,%3,%0\;addq %0,%4,%0" [(set_attr "type" "iaddlog")]) (define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))] "" "subl $31,%1,%0" [(set_attr "type" "iaddlog")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))] "" "subl $31,%1,%0" [(set_attr "type" "iaddlog")]) (define_insn "negdi2" [(set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))] "" "subq $31,%1,%0" [(set_attr "type" "iaddlog")]) (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "reg_or_8bit_operand" "rI")))] "" "subl %r1,%2,%0" [(set_attr "type" "iaddlog")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] "" "subl %r1,%2,%0" [(set_attr "type" "iaddlog")]) (define_insn "subdi3" [(set (match_operand:DI 0 "register_operand" "=r") (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (match_operand:DI 2 "reg_or_8bit_operand" "rI")))] "" "subq %r1,%2,%0" [(set_attr "type" "iaddlog")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "const48_operand" "I")) (match_operand:SI 3 "reg_or_8bit_operand" "rI")))] "" "s%2subl %r1,%3,%0" [(set_attr "type" "iaddlog")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "const48_operand" "I")) (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] "" "s%2subl %r1,%3,%0" [(set_attr "type" "iaddlog")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (minus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (match_operand:DI 2 "const48_operand" "I")) (match_operand:DI 3 "reg_or_8bit_operand" "rI")))] "" "s%2subq %r1,%3,%0" [(set_attr "type" "iaddlog")]) (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") (match_operand:SI 2 "reg_or_8bit_operand" "rI")))] "" "mull %r1,%2,%0" [(set_attr "type" "imull")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] "" "mull %r1,%2,%0" [(set_attr "type" "imull")]) (define_insn "muldi3" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ") (match_operand:DI 2 "reg_or_8bit_operand" "rI")))] "" "mulq %r1,%2,%0" [(set_attr "type" "imulq")]) ;; The divide and remainder operations always take their inputs from ;; r24 and r25, put their output in r27, and clobber r23 and r28. (define_expand "divsi3" [(parallel [(set (reg:SI 27) (div:SI (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" ""))) (clobber (reg:DI 23)) (clobber (reg:DI 28))]) (set (match_operand:SI 0 "general_operand" "") (reg:SI 27))] "" " { rtx in0 = gen_rtx (REG, SImode, 24); rtx in1 = gen_rtx (REG, SImode, 25); emit_move_insn (in0, operands[1]); emit_move_insn (in1, operands[2]); operands[1] = in0, operands[2] = in1; }") (define_expand "udivsi3" [(parallel [(set (reg:SI 27) (udiv:SI (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" ""))) (clobber (reg:DI 23)) (clobber (reg:DI 28))]) (set (match_operand:SI 0 "general_operand" "") (reg:SI 27))] "" " { rtx in0 = gen_rtx (REG, SImode, 24); rtx in1 = gen_rtx (REG, SImode, 25); emit_move_insn (in0, operands[1]); emit_move_insn (in1, operands[2]); operands[1] = in0, operands[2] = in1; }") (define_expand "modsi3" [(parallel [(set (reg:SI 27) (mod:SI (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" ""))) (clobber (reg:DI 23)) (clobber (reg:DI 28))]) (set (match_operand:SI 0 "general_operand" "") (reg:SI 27))] "" " { rtx in0 = gen_rtx (REG, SImode, 24); rtx in1 = gen_rtx (REG, SImode, 25); emit_move_insn (in0, operands[1]); emit_move_insn (in1, operands[2]); operands[1] = in0, operands[2] = in1; }") (define_expand "umodsi3" [(parallel [(set (reg:SI 27) (umod:SI (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" ""))) (clobber (reg:DI 23)) (clobber (reg:DI 28))]) (set (match_operand:SI 0 "general_operand" "") (reg:SI 27))] "" " { rtx in0 = gen_rtx (REG, SImode, 24); rtx in1 = gen_rtx (REG, SImode, 25); emit_move_insn (in0, operands[1]); emit_move_insn (in1, operands[2]); operands[1] = in0, operands[2] = in1; }") (define_expand "divdi3" [(parallel [(set (reg:DI 27) (div:DI (match_operand:DI 1 "general_operand" "") (match_operand:DI 2 "general_operand" ""))) (clobber (reg:DI 23)) (clobber (reg:DI 28))]) (set (match_operand:DI 0 "general_operand" "") (reg:DI 27))] "" " { rtx in0 = gen_rtx (REG, DImode, 24); rtx in1 = gen_rtx (REG, DImode, 25); emit_move_insn (in0, operands[1]); emit_move_insn (in1, operands[2]); operands[1] = in0, operands[2] = in1; }") (define_expand "udivdi3" [(parallel [(set (reg:DI 27) (udiv:DI (match_operand:DI 1 "general_operand" "") (match_operand:DI 2 "general_operand" ""))) (clobber (reg:DI 23)) (clobber (reg:DI 28))]) (set (match_operand:DI 0 "general_operand" "") (reg:DI 27))] "" " { rtx in0 = gen_rtx (REG, DImode, 24); rtx in1 = gen_rtx (REG, DImode, 25); emit_move_insn (in0, operands[1]); emit_move_insn (in1, operands[2]); operands[1] = in0, operands[2] = in1; }") (define_expand "moddi3" [(parallel [(set (reg:DI 27) (mod:DI (match_operand:DI 1 "general_operand" "") (match_operand:DI 2 "general_operand" ""))) (clobber (reg:DI 23)) (clobber (reg:DI 28))]) (set (match_operand:DI 0 "general_operand" "") (reg:DI 27))] "" " { rtx in0 = gen_rtx (REG, DImode, 24); rtx in1 = gen_rtx (REG, DImode, 25); emit_move_insn (in0, operands[1]); emit_move_insn (in1, operands[2]); operands[1] = in0, operands[2] = in1; }") (define_expand "umoddi3" [(parallel [(set (reg:DI 27) (umod:DI (match_operand:DI 1 "general_operand" "") (match_operand:DI 2 "general_operand" ""))) (clobber (reg:DI 23)) (clobber (reg:DI 28))]) (set (match_operand:DI 0 "general_operand" "") (reg:DI 27))] "" " { rtx in0 = gen_rtx (REG, DImode, 24); rtx in1 = gen_rtx (REG, DImode, 25); emit_move_insn (in0, operands[1]); emit_move_insn (in1, operands[2]); operands[1] = in0, operands[2] = in1; }") (define_insn "" [(set (reg:SI 27) (match_operator:SI 1 "divmod_operator" [(reg:SI 24) (reg:SI 25)])) (clobber (reg:DI 23)) (clobber (reg:DI 28))] "" "%E1 $24,$25,$27" [(set_attr "type" "isubr")]) (define_insn "" [(set (reg:DI 27) (match_operator:DI 1 "divmod_operator" [(reg:DI 24) (reg:DI 25)])) (clobber (reg:DI 23)) (clobber (reg:DI 28))] "" "%E1 $24,$25,$27" [(set_attr "type" "isubr")]) ;; Next are the basic logical operations. These only exist in DImode. (define_insn "anddi3" [(set (match_operand:DI 0 "register_operand" "=r,r,r") (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ") (match_operand:DI 2 "and_operand" "rI,N,MH")))] "" "@ and %r1,%2,%0 bic %r1,%N2,%0 zapnot %r1,%m2,%0" [(set_attr "type" "iaddlog,iaddlog,shiftcm")]) ;; There are times when we can split and AND into two AND insns. This occurs ;; when we can first clear any bytes and then clear anything else. For ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07". ;; Only to this when running on 64-bit host since the computations are ;; too messy otherwise. (define_split [(set (match_operand:DI 0 "register_operand" "") (and:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "const_int_operand" "")))] "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)" [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3))) (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))] " { unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]); unsigned HOST_WIDE_INT mask2 = mask1; int i; /* For each byte that isn't all zeros, make it all ones. */ for (i = 0; i < 64; i += 8) if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0) mask1 |= (HOST_WIDE_INT) 0xff << i; /* Now turn on any bits we've just turned off. */ mask2 |= ~ mask1; operands[3] = GEN_INT (mask1); operands[4] = GEN_INT (mask2); }") (define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "=r") (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))] "" "zapnot %1,1,%0" [(set_attr "type" "iaddlog")]) (define_insn "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))] "" "zapnot %1,1,%0" [(set_attr "type" "iaddlog")]) (define_insn "zero_extendqidi2" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))] "" "zapnot %1,1,%0" [(set_attr "type" "iaddlog")]) (define_insn "zero_extendhisi2" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))] "" "zapnot %1,3,%0" [(set_attr "type" "iaddlog")]) (define_insn "zero_extendhidi2" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))] "" "zapnot %1,3,%0" [(set_attr "type" "iaddlog")]) (define_insn "zero_extendsidi2" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] "" "zapnot %1,15,%0" [(set_attr "type" "iaddlog")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")) (match_operand:DI 2 "reg_or_0_operand" "rJ")))] "" "bic %r2,%1,%0" [(set_attr "type" "iaddlog")]) (define_insn "iordi3" [(set (match_operand:DI 0 "register_operand" "=r") (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ") (match_operand:DI 2 "reg_or_8bit_operand" "rI")))] "" "bis %r1,%2,%0" [(set_attr "type" "iaddlog")]) (define_insn "one_cmpldi2" [(set (match_operand:DI 0 "register_operand" "=r") (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))] "" "ornot $31,%1,%0" [(set_attr "type" "iaddlog")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")) (match_operand:DI 2 "reg_or_0_operand" "rJ")))] "" "ornot %r2,%1,%0" [(set_attr "type" "iaddlog")]) (define_insn "xordi3" [(set (match_operand:DI 0 "register_operand" "=r") (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ") (match_operand:DI 2 "reg_or_8bit_operand" "rI")))] "" "xor %r1,%2,%0" [(set_attr "type" "iaddlog")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ") (match_operand:DI 2 "reg_or_8bit_operand" "rI"))))] "" "eqv %r1,%2,%0" [(set_attr "type" "iaddlog")]) ;; Next come the shifts and the various extract and insert operations. (define_insn "ashldi3" [(set (match_operand:DI 0 "register_operand" "=r,r") (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ") (match_operand:DI 2 "reg_or_6bit_operand" "P,rI")))] "" "* { switch (which_alternative) { case 0: if (operands[2] == const1_rtx) return \"addq %r1,%r1,%0\"; else return \"s%P2addq %r1,0,%0\"; case 1: return \"sll %r1,%2,%0\"; } }" [(set_attr "type" "iaddlog,shiftcm")]) ;; This is the same as (sign_extend (shift X [123])). (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ashiftrt:DI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (match_operand:DI 2 "const_int_operand" "i")) (const_int 32)))] "INTVAL (operands[2]) >= 33 && INTVAL (operands[2]) <= 35" "* { switch (INTVAL (operands[2])) { case 33: return \"addl %r1,%r1,%0\"; case 34: return \"s4addl %r1,0,%0\"; case 35: return \"s8addl %r1,0,%0\"; default: abort (); } }" [(set_attr "type" "iaddlog")]) (define_insn "lshrdi3" [(set (match_operand:DI 0 "register_operand" "=r") (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (match_operand:DI 2 "reg_or_6bit_operand" "rI")))] "" "srl %r1,%2,%0") (define_insn "ashrdi3" [(set (match_operand:DI 0 "register_operand" "=r") (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (match_operand:DI 2 "reg_or_6bit_operand" "rI")))] "" "sra %r1,%2,%0") (define_expand "extendqihi2" [(set (match_dup 2) (ashift:DI (match_operand:QI 1 "register_operand" "") (const_int 56))) (set (match_operand:HI 0 "register_operand" "") (ashiftrt:DI (match_dup 2) (const_int 56)))] "" " { operands[0] = gen_lowpart (DImode, operands[0]); operands[1] = gen_lowpart (DImode, operands[1]); operands[2] = gen_reg_rtx (DImode); }") (define_expand "extendqisi2" [(set (match_dup 2) (ashift:DI (match_operand:QI 1 "register_operand" "") (const_int 56))) (set (match_operand:SI 0 "register_operand" "") (ashiftrt:DI (match_dup 2) (const_int 56)))] "" " { operands[0] = gen_lowpart (DImode, operands[0]); operands[1] = gen_lowpart (DImode, operands[1]); operands[2] = gen_reg_rtx (DImode); }") (define_expand "extendqidi2" [(set (match_dup 2) (ashift:DI (match_operand:QI 1 "register_operand" "") (const_int 56))) (set (match_operand:DI 0 "register_operand" "") (ashiftrt:DI (match_dup 2) (const_int 56)))] "" " { operands[1] = gen_lowpart (DImode, operands[1]); operands[2] = gen_reg_rtx (DImode); }") (define_expand "extendhisi2" [(set (match_dup 2) (ashift:DI (match_operand:HI 1 "register_operand" "") (const_int 48))) (set (match_operand:SI 0 "register_operand" "") (ashiftrt:DI (match_dup 2) (const_int 48)))] "" " { operands[0] = gen_lowpart (DImode, operands[0]); operands[1] = gen_lowpart (DImode, operands[1]); operands[2] = gen_reg_rtx (DImode); }") (define_expand "extendhidi2" [(set (match_dup 2) (ashift:DI (match_operand:HI 1 "register_operand" "") (const_int 48))) (set (match_operand:DI 0 "register_operand" "") (ashiftrt:DI (match_dup 2) (const_int 48)))] "" " { operands[1] = gen_lowpart (DImode, operands[1]); operands[2] = gen_reg_rtx (DImode); }") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (match_operand:DI 2 "mode_width_operand" "n") (match_operand:DI 3 "mul8_operand" "I")))] "" "ext%M2l %r1,%s3,%0") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (match_operand:DI 2 "mode_width_operand" "n") (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI") (const_int 3))))] "" "ext%M2l %r1,%3,%0") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (const_int 8) (ashift:DI (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") (const_int -1)) (const_int 3))) (const_int 56)))] "" "extqh %r1,%2,%0") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (const_int 16) (ashift:DI (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") (const_int -2)) (const_int 3))) (const_int 48)))] "" "extwh %r1,%2,%0") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (const_int 32) (ashift:DI (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") (const_int -4)) (const_int 3))) (const_int 32)))] "" "extlh %r1,%2,%0") ;; This converts an extXl into an extXh with an appropriate adjustment ;; to the address calculation. (define_split [(set (match_operand:DI 0 "register_operand" "") (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "mode_width_operand" "") (ashift:DI (match_operand:DI 3 "" "") (const_int 3))) (match_operand:DI 4 "const_int_operand" ""))) (clobber (match_operand:DI 5 "register_operand" ""))] "INTVAL (operands[4]) == 64 - INTVAL (operands[2])" [(set (match_dup 5) (match_dup 6)) (set (match_dup 0) (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2) (ashift:DI (plus:DI (match_dup 5) (match_dup 7)) (const_int 3))) (match_dup 4)))] " { operands[6] = plus_constant (operands[3], INTVAL (operands[2]) / BITS_PER_UNIT); operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT); }") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r")) (match_operand:DI 2 "mul8_operand" "I")))] "" "insbl %1,%s2,%0") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r")) (match_operand:DI 2 "mul8_operand" "I")))] "" "inswl %1,%s2,%0") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (match_operand:DI 2 "mul8_operand" "I")))] "" "insll %1,%s2,%0") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r")) (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") (const_int 3))))] "" "insbl %1,%2,%0") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r")) (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") (const_int 3))))] "" "inswl %1,%2,%0") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") (const_int 3))))] "" "insll %1,%2,%0") ;; We do not include the insXh insns because they are complex to express ;; and it does not appear that we would ever want to generate them. (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (and:DI (ashift:DI (match_operand:DI 2 "mode_mask_operand" "n") (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI") (const_int 3))) (match_operand:DI 1 "reg_or_0_operand" "rJ")))] "" "msk%U2l %r1,%3,%0") ;; We do not include the mskXh insns because it does not appear we would ever ;; generate one. ;; Floating-point operations. All the double-precision insns can extend ;; from single, so indicate that. The exception are the ones that simply ;; play with the sign bits; it's not clear what to do there. (define_insn "abssf2" [(set (match_operand:SF 0 "register_operand" "=f") (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "cpys $f31,%R1,%0" [(set_attr "type" "fpop")]) (define_insn "absdf2" [(set (match_operand:DF 0 "register_operand" "=f") (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "cpys $f31,%R1,%0" [(set_attr "type" "fpop")]) (define_insn "negsf2" [(set (match_operand:SF 0 "register_operand" "=f") (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "cpysn %1,%R1,%0" [(set_attr "type" "fpop")]) (define_insn "negdf2" [(set (match_operand:DF 0 "register_operand" "=f") (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "cpysn %1,%R1,%0" [(set_attr "type" "fpop")]) (define_insn "addsf3" [(set (match_operand:SF 0 "register_operand" "=f") (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG") (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "adds %R1,%R2,%0" [(set_attr "type" "fpop")]) (define_insn "adddf3" [(set (match_operand:DF 0 "register_operand" "=f") (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG") (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "addt %R1,%R2,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (plus:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG")) (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "addt %R1,%R2,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (plus:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")) (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] "TARGET_FP" "addt %R1,%R2,%0" [(set_attr "type" "fpop")]) (define_insn "fix_truncdfdi2" [(set (match_operand:DI 0 "register_operand" "=f") (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "cvttqc %R1,%0" [(set_attr "type" "fpop")]) (define_insn "fix_truncsfdi2" [(set (match_operand:DI 0 "register_operand" "=f") (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))] "TARGET_FP" "cvttqc %R1,%0" [(set_attr "type" "fpop")]) (define_insn "floatdisf2" [(set (match_operand:SF 0 "register_operand" "=f") (float:SF (match_operand:DI 1 "register_operand" "f")))] "TARGET_FP" "cvtqs %1,%0" [(set_attr "type" "fpop")]) (define_insn "floatdidf2" [(set (match_operand:DF 0 "register_operand" "=f") (float:DF (match_operand:DI 1 "register_operand" "f")))] "TARGET_FP" "cvtqt %1,%0" [(set_attr "type" "fpop")]) (define_insn "extendsfdf2" [(set (match_operand:DF 0 "register_operand" "=f,f") (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))] "TARGET_FP" "@ addt $f31,%1,%0 lds %0,%1" [(set_attr "type" "fpop,ld")]) (define_insn "truncdfsf2" [(set (match_operand:SF 0 "register_operand" "=f") (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "cvtts %R1,%0" [(set_attr "type" "fpop")]) (define_insn "divsf3" [(set (match_operand:SF 0 "register_operand" "=f") (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG") (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "divs %R1,%R2,%0" [(set_attr "type" "fdivs")]) (define_insn "divdf3" [(set (match_operand:DF 0 "register_operand" "=f") (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG") (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "divt %R1,%R2,%0" [(set_attr "type" "fdivt")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG")) (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "divt %R1,%R2,%0" [(set_attr "type" "fdivt")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG") (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] "TARGET_FP" "divt %R1,%R2,%0" [(set_attr "type" "fdivt")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG")) (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] "TARGET_FP" "divt %R1,%R2,%0" [(set_attr "type" "fdivt")]) (define_insn "mulsf3" [(set (match_operand:SF 0 "register_operand" "=f") (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG") (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "muls %R1,%R2,%0" [(set_attr "type" "fpop")]) (define_insn "muldf3" [(set (match_operand:DF 0 "register_operand" "=f") (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG") (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "mult %R1,%R2,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (mult:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG")) (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "mult %R1,%R2,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (mult:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")) (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] "TARGET_FP" "mult %R1,%R2,%0" [(set_attr "type" "fpop")]) (define_insn "subsf3" [(set (match_operand:SF 0 "register_operand" "=f") (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG") (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "subs %R1,%R2,%0" [(set_attr "type" "fpop")]) (define_insn "subdf3" [(set (match_operand:DF 0 "register_operand" "=f") (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG") (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "subt %R1,%R2,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (minus:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG")) (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] "TARGET_FP" "subt %R1,%R2,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG") (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] "TARGET_FP" "subt %R1,%R2,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (minus:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG")) (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] "TARGET_FP" "subt %R1,%R2,%0" [(set_attr "type" "fpop")]) ;; Next are all the integer comparisons, and conditional moves and branches ;; and some of the related define_expand's and define_split's. (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (match_operator:DI 1 "alpha_comparison_operator" [(match_operand:DI 2 "reg_or_0_operand" "rJ") (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))] "" "cmp%C1 %r2,%3,%0" [(set_attr "type" "icmp")]) ;; There are three important special-case that don't fit the above pattern ;; but which we want to handle here. (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ne:DI (match_operand:DI 1 "register_operand" "r") (const_int 0)))] "" "cmpult $31,%1,%0" [(set_attr "type" "icmp")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (gt:DI (match_operand:DI 1 "register_operand" "r") (const_int 0)))] "" "cmplt $31,%1,%0" [(set_attr "type" "icmp")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ge:DI (match_operand:DI 1 "register_operand" "r") (const_int 0)))] "" "cmple $31,%1,%0" [(set_attr "type" "icmp")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r,r") (if_then_else:DI (match_operator 2 "signed_comparison_operator" [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ") (const_int 0)]) (match_operand:DI 1 "reg_or_8bit_operand" "rI,0") (match_operand:DI 4 "reg_or_8bit_operand" "0,rI")))] "" "@ cmov%C2 %r3,%1,%0 cmov%D2 %r3,%4,%0") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r,r") (if_then_else:DI (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") (const_int 1) (const_int 0)) (const_int 0)) (match_operand:DI 1 "reg_or_8bit_operand" "rI,0") (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))] "" "@ cmovlbc %r2,%1,%0 cmovlbs %r2,%3,%0") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r,r") (if_then_else:DI (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") (const_int 1) (const_int 0)) (const_int 0)) (match_operand:DI 1 "reg_or_8bit_operand" "rI,0") (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))] "" "@ cmovlbs %r2,%1,%0 cmovlbc %r2,%3,%0") ;; This form is added since combine thinks that an IF_THEN_ELSE with both ;; arms constant is a single insn, so it won't try to form it if combine ;; knows they are really two insns. This occurs in divides by powers ;; of two. (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (if_then_else:DI (match_operator 2 "signed_comparison_operator" [(match_operand:DI 3 "reg_or_0_operand" "rJ") (const_int 0)]) (plus:DI (match_dup 0) (match_operand:DI 1 "reg_or_8bit_operand" "rI")) (match_dup 0))) (clobber (match_scratch:DI 4 "=&r"))] "" "addq %0,%1,%4\;cmov%C2 %r3,%4,%0") (define_split [(set (match_operand:DI 0 "register_operand" "") (if_then_else:DI (match_operator 2 "signed_comparison_operator" [(match_operand:DI 3 "reg_or_0_operand" "") (const_int 0)]) (plus:DI (match_dup 0) (match_operand:DI 1 "reg_or_8bit_operand" "")) (match_dup 0))) (clobber (match_operand:DI 4 "register_operand" ""))] "" [(set (match_dup 4) (plus:DI (match_dup 0) (match_dup 1))) (set (match_dup 0) (if_then_else:DI (match_op_dup 2 [(match_dup 3) (const_int 0)]) (match_dup 4) (match_dup 0)))] "") (define_split [(parallel [(set (match_operand:DI 0 "register_operand" "") (if_then_else:DI (match_operator 1 "comparison_operator" [(zero_extract:DI (match_operand:DI 2 "register_operand" "") (const_int 1) (match_operand:DI 3 "const_int_operand" "")) (const_int 0)]) (match_operand:DI 4 "reg_or_8bit_operand" "") (match_operand:DI 5 "reg_or_8bit_operand" ""))) (clobber (match_operand:DI 6 "register_operand" ""))])] "INTVAL (operands[3]) != 0" [(set (match_dup 6) (lshiftrt:DI (match_dup 2) (match_dup 3))) (set (match_dup 0) (if_then_else:DI (match_op_dup 1 [(zero_extract:DI (match_dup 6) (const_int 1) (const_int 0)) (const_int 0)]) (match_dup 4) (match_dup 5)))] "") ;; For ABS, we have two choices, depending on whether the input and output ;; registers are the same or not. (define_expand "absdi2" [(set (match_operand:DI 0 "register_operand" "") (abs:DI (match_operand:DI 1 "register_operand" "")))] "" " { if (rtx_equal_p (operands[0], operands[1])) emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode))); else emit_insn (gen_absdi2_diff (operands[0], operands[1])); DONE; }") (define_expand "absdi2_same" [(set (match_operand:DI 1 "register_operand" "") (neg:DI (match_operand:DI 0 "register_operand" ""))) (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0)) (match_dup 0) (match_dup 1)))] "" "") (define_expand "absdi2_diff" [(set (match_operand:DI 0 "register_operand" "") (neg:DI (match_operand:DI 1 "register_operand" ""))) (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0)) (match_dup 0) (match_dup 1)))] "" "") (define_split [(set (match_operand:DI 0 "register_operand" "") (abs:DI (match_dup 0))) (clobber (match_operand:DI 2 "register_operand" ""))] "" [(set (match_dup 1) (neg:DI (match_dup 0))) (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0)) (match_dup 0) (match_dup 1)))] "") (define_split [(set (match_operand:DI 0 "register_operand" "") (abs:DI (match_operand:DI 1 "register_operand" "")))] "! rtx_equal_p (operands[0], operands[1])" [(set (match_dup 0) (neg:DI (match_dup 1))) (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0)) (match_dup 0) (match_dup 1)))] "") (define_split [(set (match_operand:DI 0 "register_operand" "") (neg:DI (abs:DI (match_dup 0)))) (clobber (match_operand:DI 2 "register_operand" ""))] "" [(set (match_dup 1) (neg:DI (match_dup 0))) (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0)) (match_dup 0) (match_dup 1)))] "") (define_split [(set (match_operand:DI 0 "register_operand" "") (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))] "! rtx_equal_p (operands[0], operands[1])" [(set (match_dup 0) (neg:DI (match_dup 1))) (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0)) (match_dup 0) (match_dup 1)))] "") (define_expand "smaxdi3" [(set (match_dup 3) (le:DI (match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 2 "reg_or_8bit_operand" ""))) (set (match_operand:DI 0 "register_operand" "") (if_then_else:DI (eq (match_dup 3) (const_int 0)) (match_dup 1) (match_dup 2)))] "" " { operands[3] = gen_reg_rtx (DImode); }") (define_split [(set (match_operand:DI 0 "register_operand" "") (smax:DI (match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 2 "reg_or_8bit_operand" ""))) (clobber (match_operand:DI 3 "register_operand" ""))] "operands[2] != const0_rtx" [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2))) (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) (match_dup 1) (match_dup 2)))] "") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (smax:DI (match_operand:DI 1 "register_operand" "0") (const_int 0)))] "" "cmovlt %0,0,%0") (define_expand "smindi3" [(set (match_dup 3) (lt:DI (match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 2 "reg_or_8bit_operand" ""))) (set (match_operand:DI 0 "register_operand" "") (if_then_else:DI (ne (match_dup 3) (const_int 0)) (match_dup 1) (match_dup 2)))] "" " { operands[3] = gen_reg_rtx (DImode); }") (define_split [(set (match_operand:DI 0 "register_operand" "") (smin:DI (match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 2 "reg_or_8bit_operand" ""))) (clobber (match_operand:DI 3 "register_operand" ""))] "operands[2] != const0_rtx" [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2))) (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) (match_dup 1) (match_dup 2)))] "") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (smin:DI (match_operand:DI 1 "register_operand" "0") (const_int 0)))] "" "cmovgt %0,0,%0") (define_expand "umaxdi3" [(set (match_dup 3) (leu:DI (match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 2 "reg_or_8bit_operand" ""))) (set (match_operand:DI 0 "register_operand" "") (if_then_else:DI (eq (match_dup 3) (const_int 0)) (match_dup 1) (match_dup 2)))] "" " { operands[3] = gen_reg_rtx (DImode); }") (define_split [(set (match_operand:DI 0 "register_operand" "") (umax:DI (match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 2 "reg_or_8bit_operand" ""))) (clobber (match_operand:DI 3 "register_operand" ""))] "operands[2] != const0_rtx" [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2))) (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) (match_dup 1) (match_dup 2)))] "") (define_expand "umindi3" [(set (match_dup 3) (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 2 "reg_or_8bit_operand" ""))) (set (match_operand:DI 0 "register_operand" "") (if_then_else:DI (ne (match_dup 3) (const_int 0)) (match_dup 1) (match_dup 2)))] "" " { operands[3] = gen_reg_rtx (DImode); }") (define_split [(set (match_operand:DI 0 "register_operand" "") (umin:DI (match_operand:DI 1 "reg_or_0_operand" "") (match_operand:DI 2 "reg_or_8bit_operand" ""))) (clobber (match_operand:DI 3 "register_operand" ""))] "operands[2] != const0_rtx" [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2))) (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) (match_dup 1) (match_dup 2)))] "") (define_insn "" [(set (pc) (if_then_else (match_operator 1 "signed_comparison_operator" [(match_operand:DI 2 "reg_or_0_operand" "rJ") (const_int 0)]) (label_ref (match_operand 0 "" "")) (pc)))] "" "b%C1 %r2,%0" [(set_attr "type" "ibr")]) (define_insn "" [(set (pc) (if_then_else (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (const_int 1) (const_int 0)) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "blbs %r1,%0" [(set_attr "type" "ibr")]) (define_insn "" [(set (pc) (if_then_else (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") (const_int 1) (const_int 0)) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "blbc %r1,%0" [(set_attr "type" "ibr")]) (define_split [(parallel [(set (pc) (if_then_else (match_operator 1 "comparison_operator" [(zero_extract:DI (match_operand:DI 2 "register_operand" "") (const_int 1) (match_operand:DI 3 "const_int_operand" "")) (const_int 0)]) (label_ref (match_operand 0 "" "")) (pc))) (clobber (match_operand:DI 4 "register_operand" ""))])] "INTVAL (operands[3]) != 0" [(set (match_dup 4) (lshiftrt:DI (match_dup 2) (match_dup 3))) (set (pc) (if_then_else (match_op_dup 1 [(zero_extract:DI (match_dup 4) (const_int 1) (const_int 0)) (const_int 0)]) (label_ref (match_dup 0)) (pc)))] "") ;; The following are the corresponding floating-point insns. Recall ;; we need to have variants that expand the arguments from SF mode ;; to DFmode. (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (match_operator:DF 1 "alpha_comparison_operator" [(match_operand:DF 2 "reg_or_fp0_operand" "fG") (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))] "TARGET_FP" "cmpt%C1 %R2,%R3,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (match_operator:DF 1 "alpha_comparison_operator" [(float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG")) (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))] "TARGET_FP" "cmpt%C1 %R2,%R3,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (match_operator:DF 1 "alpha_comparison_operator" [(match_operand:DF 2 "reg_or_fp0_operand" "fG") (float_extend:DF (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))] "TARGET_FP" "cmpt%C1 %R2,%R3,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (match_operator:DF 1 "alpha_comparison_operator" [(float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG")) (float_extend:DF (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))] "TARGET_FP" "cmpt%C1 %R2,%R3,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f,f") (if_then_else:DF (match_operator 3 "signed_comparison_operator" [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG") (match_operand:DF 2 "fp0_operand" "G,G")]) (match_operand:DF 1 "reg_or_fp0_operand" "fG,0") (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))] "TARGET_FP" "@ fcmov%C3 %R4,%R1,%0 fcmov%D3 %R4,%R5,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=f,f") (if_then_else:SF (match_operator 3 "signed_comparison_operator" [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG") (match_operand:DF 2 "fp0_operand" "G,G")]) (match_operand:SF 1 "reg_or_fp0_operand" "fG,0") (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))] "TARGET_FP" "@ fcmov%C3 %R4,%R1,%0 fcmov%D3 %R4,%R5,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f,f") (if_then_else:DF (match_operator 3 "signed_comparison_operator" [(match_operand:DF 1 "reg_or_fp0_operand" "fG,fG") (match_operand:DF 2 "fp0_operand" "G,G")]) (float_extend:DF (match_operand:SF 4 "reg_or_fp0_operand" "fG,0")) (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))] "TARGET_FP" "@ fcmov%C3 %R4,%R1,%0 fcmov%D3 %R4,%R5,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f,f") (if_then_else:DF (match_operator 3 "signed_comparison_operator" [(float_extend:DF (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG")) (match_operand:DF 2 "fp0_operand" "G,G")]) (match_operand:DF 1 "reg_or_fp0_operand" "fG,0") (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))] "TARGET_FP" "@ fcmov%C3 %R4,%R1,%0 fcmov%D3 %R4,%R5,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=f,f") (if_then_else:SF (match_operator 3 "signed_comparison_operator" [(float_extend:DF (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG")) (match_operand:DF 2 "fp0_operand" "G,G")]) (match_operand:SF 1 "reg_or_fp0_operand" "fG,0") (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))] "TARGET_FP" "@ fcmov%C3 %R4,%R1,%0 fcmov%D3 %R4,%R5,%0" [(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f,f") (if_then_else:DF (match_operator 3 "signed_comparison_operator" [(float_extend:DF (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG")) (match_operand:DF 2 "fp0_operand" "G,G")]) (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")) (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))] "TARGET_FP" "@ fcmov%C3 %R4,%R1,%0 fcmov%D3 %R4,%R5,%0" [(set_attr "type" "fpop")]) (define_expand "maxdf3" [(set (match_dup 3) (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "") (match_operand:DF 2 "reg_or_fp0_operand" ""))) (set (match_operand:DF 0 "register_operand" "") (if_then_else:DF (eq (match_dup 3) (const_int 0)) (match_dup 1) (match_dup 2)))] "TARGET_FP" " { operands[3] = gen_reg_rtx (DFmode); }") (define_expand "mindf3" [(set (match_dup 3) (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "") (match_operand:DF 2 "reg_or_fp0_operand" ""))) (set (match_operand:DF 0 "register_operand" "") (if_then_else:DF (ne (match_dup 3) (const_int 0)) (match_dup 1) (match_dup 2)))] "TARGET_FP" " { operands[3] = gen_reg_rtx (DFmode); }") (define_expand "maxsf3" [(set (match_dup 3) (le:DF (match_operand:SF 1 "reg_or_fp0_operand" "") (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "")))) (set (match_operand:SF 0 "register_operand" "") (if_then_else:SF (eq (match_dup 3) (const_int 0)) (match_dup 1) (match_dup 2)))] "TARGET_FP" " { operands[3] = gen_reg_rtx (SFmode); }") (define_expand "minsf3" [(set (match_dup 3) (lt:DF (match_operand:SF 1 "reg_or_fp0_operand" "") (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "")))) (set (match_operand:SF 0 "register_operand" "") (if_then_else:SF (ne (match_dup 3) (const_int 0)) (match_dup 1) (match_dup 2)))] "TARGET_FP" " { operands[3] = gen_reg_rtx (SFmode); }") (define_insn "" [(set (pc) (if_then_else (match_operator 1 "signed_comparison_operator" [(match_operand:DF 2 "reg_or_fp0_operand" "fG") (match_operand:DF 3 "fp0_operand" "G")]) (label_ref (match_operand 0 "" "")) (pc)))] "TARGET_FP" "fb%C1 %R2,%0" [(set_attr "type" "fbr")]) (define_insn "" [(set (pc) (if_then_else (match_operator 1 "signed_comparison_operator" [(float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG")) (match_operand:DF 3 "fp0_operand" "G")]) (label_ref (match_operand 0 "" "")) (pc)))] "TARGET_FP" "fb%C1 %R2,%0" [(set_attr "type" "fbr")]) ;; These are the main define_expand's used to make conditional branches ;; and compares. (define_expand "cmpdf" [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "") (match_operand:DF 1 "reg_or_fp0_operand" "")))] "" " { alpha_compare_op0 = operands[0]; alpha_compare_op1 = operands[1]; alpha_compare_fp_p = 1; DONE; }") (define_expand "cmpdi" [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "") (match_operand:DI 1 "reg_or_8bit_operand" "")))] "" " { alpha_compare_op0 = operands[0]; alpha_compare_op1 = operands[1]; alpha_compare_fp_p = 0; DONE; }") (define_expand "beq" [(set (match_dup 1) (match_dup 2)) (set (pc) (if_then_else (match_dup 3) (label_ref (match_operand 0 "" "")) (pc)))] "" " { enum machine_mode mode; enum rtx_code compare_code, branch_code; if (alpha_compare_fp_p) mode = DFmode, compare_code = EQ, branch_code = NE; else { mode = DImode, compare_code = MINUS, branch_code = EQ; if (GET_CODE (alpha_compare_op1) == CONST_INT) { compare_code = PLUS; alpha_compare_op1 = GEN_INT (- INTVAL (alpha_compare_op1)); } } operands[1] = gen_reg_rtx (mode); operands[2] = gen_rtx (compare_code, mode, alpha_compare_op0, alpha_compare_op1); operands[3] = gen_rtx (branch_code, VOIDmode, operands[1], CONST0_RTX (mode)); }") (define_expand "bne" [(set (match_dup 1) (match_dup 2)) (set (pc) (if_then_else (match_dup 3) (label_ref (match_operand 0 "" "")) (pc)))] "" " { enum machine_mode mode; enum rtx_code compare_code, branch_code; if (alpha_compare_fp_p) mode = DFmode, compare_code = EQ, branch_code = EQ; else { mode = DImode, compare_code = MINUS, branch_code = NE; if (GET_CODE (alpha_compare_op1) == CONST_INT) { compare_code = PLUS; alpha_compare_op1 = GEN_INT (- INTVAL (alpha_compare_op1)); } } operands[1] = gen_reg_rtx (mode); operands[2] = gen_rtx (compare_code, mode, alpha_compare_op0, alpha_compare_op1); operands[3] = gen_rtx (branch_code, VOIDmode, operands[1], CONST0_RTX (mode)); }") (define_expand "blt" [(set (match_dup 1) (match_dup 2)) (set (pc) (if_then_else (match_dup 3) (label_ref (match_operand 0 "" "")) (pc)))] "" " { enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode; operands[1] = gen_reg_rtx (mode); operands[2] = gen_rtx (LT, mode, alpha_compare_op0, alpha_compare_op1); operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode)); }") (define_expand "ble" [(set (match_dup 1) (match_dup 2)) (set (pc) (if_then_else (match_dup 3) (label_ref (match_operand 0 "" "")) (pc)))] "" " { enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode; operands[1] = gen_reg_rtx (mode); operands[2] = gen_rtx (LE, mode, alpha_compare_op0, alpha_compare_op1); operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode)); }") (define_expand "bgt" [(set (match_dup 1) (match_dup 2)) (set (pc) (if_then_else (match_dup 3) (label_ref (match_operand 0 "" "")) (pc)))] "" " { if (alpha_compare_fp_p) { operands[1] = gen_reg_rtx (DFmode); operands[2] = gen_rtx (LT, DFmode, alpha_compare_op1, alpha_compare_op0); operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode)); } else { operands[1] = gen_reg_rtx (DImode); operands[2] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1); operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx); } }") (define_expand "bge" [(set (match_dup 1) (match_dup 2)) (set (pc) (if_then_else (match_dup 3) (label_ref (match_operand 0 "" "")) (pc)))] "" " { if (alpha_compare_fp_p) { operands[1] = gen_reg_rtx (DFmode); operands[2] = gen_rtx (LE, DFmode, alpha_compare_op1, alpha_compare_op0); operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode)); } else { operands[1] = gen_reg_rtx (DImode); operands[2] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1); operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx); } }") (define_expand "bltu" [(set (match_dup 1) (match_dup 2)) (set (pc) (if_then_else (match_dup 3) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_reg_rtx (DImode); operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1); operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx); }") (define_expand "bleu" [(set (match_dup 1) (match_dup 2)) (set (pc) (if_then_else (match_dup 3) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_reg_rtx (DImode); operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1); operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx); }") (define_expand "bgtu" [(set (match_dup 1) (match_dup 2)) (set (pc) (if_then_else (match_dup 3) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_reg_rtx (DImode); operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1); operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx); }") (define_expand "bgeu" [(set (match_dup 1) (match_dup 2)) (set (pc) (if_then_else (match_dup 3) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_reg_rtx (DImode); operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1); operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx); }") (define_expand "seq" [(set (match_operand:DI 0 "register_operand" "") (match_dup 1))] "" " { if (alpha_compare_fp_p) FAIL; operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1); }") (define_expand "sne" [(set (match_operand:DI 0 "register_operand" "") (match_dup 1)) (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))] "" " { if (alpha_compare_fp_p) FAIL; operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1); }") (define_expand "slt" [(set (match_operand:DI 0 "register_operand" "") (match_dup 1))] "" " { if (alpha_compare_fp_p) FAIL; operands[1] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1); }") (define_expand "sle" [(set (match_operand:DI 0 "register_operand" "") (match_dup 1))] "" " { if (alpha_compare_fp_p) FAIL; operands[1] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1); }") (define_expand "sgt" [(set (match_operand:DI 0 "register_operand" "") (match_dup 1))] "" " { if (alpha_compare_fp_p) FAIL; operands[1] = gen_rtx (LT, DImode, force_reg (DImode, alpha_compare_op1), alpha_compare_op0); }") (define_expand "sge" [(set (match_operand:DI 0 "register_operand" "") (match_dup 1))] "" " { if (alpha_compare_fp_p) FAIL; operands[1] = gen_rtx (LE, DImode, force_reg (DImode, alpha_compare_op1), alpha_compare_op0); }") (define_expand "sltu" [(set (match_operand:DI 0 "register_operand" "") (match_dup 1))] "" " { if (alpha_compare_fp_p) FAIL; operands[1] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1); }") (define_expand "sleu" [(set (match_operand:DI 0 "register_operand" "") (match_dup 1))] "" " { if (alpha_compare_fp_p) FAIL; operands[1] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1); }") (define_expand "sgtu" [(set (match_operand:DI 0 "register_operand" "") (match_dup 1))] "" " { if (alpha_compare_fp_p) FAIL; operands[1] = gen_rtx (LTU, DImode, force_reg (DImode, alpha_compare_op1), alpha_compare_op0); }") (define_expand "sgeu" [(set (match_operand:DI 0 "register_operand" "") (match_dup 1))] "" " { if (alpha_compare_fp_p) FAIL; operands[1] = gen_rtx (LEU, DImode, force_reg (DImode, alpha_compare_op1), alpha_compare_op0); }") ;; These define_split definitions are used in cases when comparisons have ;; not be stated in the correct way and we need to reverse the second ;; comparison. For example, x >= 7 has to be done as x < 6 with the ;; comparison that tests the result being reversed. We have one define_split ;; for each use of a comparison. They do not match valid insns and need ;; not generate valid insns. ;; ;; We can also handle equality comparisons (and inequality comparisons in ;; cases where the resulting add cannot overflow) by doing an add followed by ;; a comparison with zero. This is faster since the addition takes one ;; less cycle than a compare when feeding into a conditional move. ;; For this case, we also have an SImode pattern since we can merge the add ;; and sign extend and the order doesn't matter. ;; ;; We do not do this for floating-point, since it isn't clear how the "wrong" ;; operation could have been generated. (define_split [(set (match_operand:DI 0 "register_operand" "") (if_then_else:DI (match_operator 1 "comparison_operator" [(match_operand:DI 2 "reg_or_0_operand" "") (match_operand:DI 3 "reg_or_cint_operand" "")]) (match_operand:DI 4 "reg_or_cint_operand" "") (match_operand:DI 5 "reg_or_cint_operand" ""))) (clobber (match_operand:DI 6 "register_operand" ""))] "operands[3] != const0_rtx" [(set (match_dup 6) (match_dup 7)) (set (match_dup 0) (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] " { enum rtx_code code = GET_CODE (operands[1]); int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); /* If we are comparing for equality with a constant and that constant appears in the arm when the register equals the constant, use the register since that is more likely to match (and to produce better code if both would). */ if (code == EQ && GET_CODE (operands[3]) == CONST_INT && rtx_equal_p (operands[4], operands[3])) operands[4] = operands[2]; else if (code == NE && GET_CODE (operands[3]) == CONST_INT && rtx_equal_p (operands[5], operands[3])) operands[5] = operands[2]; if (code == NE || code == EQ || (extended_count (operands[2], DImode, unsignedp) >= 1 && extended_count (operands[3], DImode, unsignedp) >= 1)) { if (GET_CODE (operands[3]) == CONST_INT) operands[7] = gen_rtx (PLUS, DImode, operands[2], GEN_INT (- INTVAL (operands[3]))); else operands[7] = gen_rtx (MINUS, DImode, operands[2], operands[3]); operands[8] = gen_rtx (code, VOIDmode, operands[6], const0_rtx); } else if (code == EQ || code == LE || code == LT || code == LEU || code == LTU) { operands[7] = gen_rtx (code, DImode, operands[2], operands[3]); operands[8] = gen_rtx (NE, VOIDmode, operands[6], const0_rtx); } else { operands[7] = gen_rtx (reverse_condition (code), DImode, operands[2], operands[3]); operands[8] = gen_rtx (EQ, VOIDmode, operands[6], const0_rtx); } }") (define_split [(set (match_operand:DI 0 "register_operand" "") (if_then_else:DI (match_operator 1 "comparison_operator" [(match_operand:SI 2 "reg_or_0_operand" "") (match_operand:SI 3 "reg_or_cint_operand" "")]) (match_operand:DI 4 "reg_or_8bit_operand" "") (match_operand:DI 5 "reg_or_8bit_operand" ""))) (clobber (match_operand:DI 6 "register_operand" ""))] "operands[3] != const0_rtx && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)" [(set (match_dup 6) (match_dup 7)) (set (match_dup 0) (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] " { enum rtx_code code = GET_CODE (operands[1]); int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); rtx tem; if ((code != NE && code != EQ && ! (extended_count (operands[2], DImode, unsignedp) >= 1 && extended_count (operands[3], DImode, unsignedp) >= 1))) FAIL; if (GET_CODE (operands[3]) == CONST_INT) tem = gen_rtx (PLUS, SImode, operands[2], GEN_INT (- INTVAL (operands[3]))); else tem = gen_rtx (MINUS, SImode, operands[2], operands[3]); operands[7] = gen_rtx (SIGN_EXTEND, DImode, tem); operands[8] = gen_rtx (GET_CODE (operands[1]), VOIDmode, operands[6], const0_rtx); }") (define_split [(set (pc) (if_then_else (match_operator 1 "comparison_operator" [(match_operand:DI 2 "reg_or_0_operand" "") (match_operand:DI 3 "reg_or_cint_operand" "")]) (label_ref (match_operand 0 "" "")) (pc))) (clobber (match_operand:DI 4 "register_operand" ""))] "operands[3] != const0_rtx" [(set (match_dup 4) (match_dup 5)) (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))] " { enum rtx_code code = GET_CODE (operands[1]); int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); if (code == NE || code == EQ || (extended_count (operands[2], DImode, unsignedp) >= 1 && extended_count (operands[3], DImode, unsignedp) >= 1)) { if (GET_CODE (operands[3]) == CONST_INT) operands[5] = gen_rtx (PLUS, DImode, operands[2], GEN_INT (- INTVAL (operands[3]))); else operands[5] = gen_rtx (MINUS, DImode, operands[2], operands[3]); operands[6] = gen_rtx (code, VOIDmode, operands[4], const0_rtx); } else if (code == EQ || code == LE || code == LT || code == LEU || code == LTU) { operands[5] = gen_rtx (code, DImode, operands[2], operands[3]); operands[6] = gen_rtx (NE, VOIDmode, operands[4], const0_rtx); } else { operands[5] = gen_rtx (reverse_condition (code), DImode, operands[2], operands[3]); operands[6] = gen_rtx (EQ, VOIDmode, operands[4], const0_rtx); } }") (define_split [(set (pc) (if_then_else (match_operator 1 "comparison_operator" [(match_operand:SI 2 "reg_or_0_operand" "") (match_operand:SI 3 "const_int_operand" "")]) (label_ref (match_operand 0 "" "")) (pc))) (clobber (match_operand:DI 4 "register_operand" ""))] "operands[3] != const0_rtx && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)" [(set (match_dup 4) (match_dup 5)) (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))] " { rtx tem; if (GET_CODE (operands[3]) == CONST_INT) tem = gen_rtx (PLUS, SImode, operands[2], GEN_INT (- INTVAL (operands[3]))); else tem = gen_rtx (MINUS, SImode, operands[2], operands[3]); operands[5] = gen_rtx (SIGN_EXTEND, DImode, tem); operands[6] = gen_rtx (GET_CODE (operands[1]), VOIDmode, operands[4], const0_rtx); }") ;; Here are the CALL and unconditional branch insns. (define_expand "call" [(parallel [(call (mem:DI (match_dup 2)) (match_operand 1 "" "")) (use (match_operand:DI 0 "" "")) (clobber (reg:DI 26))])] "" " { if (GET_CODE (operands[0]) != MEM) abort (); operands[0] = XEXP (operands[0], 0); operands[2] = gen_rtx (REG, DImode, 27); emit_move_insn (operands[2], operands[0]); if (GET_CODE (operands[0]) != SYMBOL_REF) operands[0] = const0_rtx; }") (define_expand "call_value" [(parallel [(set (match_operand 0 "" "") (call (mem:DI (match_dup 3)) (match_operand 2 "" ""))) (use (match_operand:DI 1 "" "")) (clobber (reg:DI 26))])] "" " { if (GET_CODE (operands[1]) != MEM) abort (); operands[1] = XEXP (operands[1], 0); operands[3] = gen_rtx (REG, DImode, 27); emit_move_insn (operands[3], operands[1]); if (GET_CODE (operands[1]) != SYMBOL_REF) operands[1] = const0_rtx; }") (define_insn "" [(call (mem:DI (reg:DI 27)) (match_operand 0 "" "")) (use (match_operand:DI 1 "" "")) (clobber (reg:DI 26))] "" "jsr $26,($27),%1\;ldgp $29,0($26)" [(set_attr "type" "jsr")]) (define_insn "" [(set (match_operand 0 "register_operand" "=rf") (call (mem:DI (reg:DI 27)) (match_operand 1 "" ""))) (use (match_operand:DI 2 "" "")) (clobber (reg:DI 26))] "" "jsr $26,($27),%2\;ldgp $29,0($26)" [(set_attr "type" "jsr")]) (define_insn "" [(call (mem:DI (match_operand 1 "current_file_function_operand" "i")) (match_operand 0 "" "")) (use (match_dup 1)) (clobber (reg:DI 26))] "" "bsr $26,%1..ng" [(set_attr "type" "ibr")]) (define_insn "" [(set (match_operand 0 "register_operand" "=rf") (call (mem:DI (match_operand 1 "current_file_function_operand" "i")) (match_operand 2 "" ""))) (use (match_dup 1)) (clobber (reg:DI 26))] "" "bsr $26,%1..ng" [(set_attr "type" "ibr")]) ;; Call subroutine returning any type. (define_expand "untyped_call" [(parallel [(call (match_operand 0 "" "") (const_int 0)) (match_operand 1 "" "") (match_operand 2 "" "")])] "" " { int i; emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); for (i = 0; i < XVECLEN (operands[2], 0); i++) { rtx set = XVECEXP (operands[2], 0, i); emit_move_insn (SET_DEST (set), SET_SRC (set)); } /* The optimizer does not know that the call sets the function value registers we stored in the result block. We avoid problems by claiming that all hard registers are used and clobbered at this point. */ emit_insn (gen_blockage ()); DONE; }") ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and ;; all of memory. This blocks insns from being moved across this point. (define_insn "blockage" [(unspec_volatile [(const_int 0)] 1)] "" "") (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "br $31,%l0" [(set_attr "type" "ibr")]) (define_insn "return" [(return)] "direct_return ()" "ret $31,($26),1" [(set_attr "type" "ibr")]) (define_insn "indirect_jump" [(set (pc) (match_operand:DI 0 "register_operand" "r"))] "" "jmp $31,(%0),0" [(set_attr "type" "ibr")]) (define_insn "nop" [(const_int 0)] "" "bis $31,$31,$31" [(set_attr "type" "iaddlog")]) (define_expand "tablejump" [(set (match_dup 3) (sign_extend:DI (match_operand:SI 0 "register_operand" ""))) (parallel [(set (pc) (plus:DI (match_dup 3) (reg:DI 29))) (use (label_ref (match_operand 1 "" ""))) (clobber (match_scratch:DI 2 "=r"))])] "" " { operands[3] = gen_reg_rtx (DImode); }") (define_insn "" [(set (pc) (plus:DI (match_operand:DI 0 "register_operand" "r") (reg:DI 29))) (use (label_ref (match_operand 1 "" ""))) (clobber (match_scratch:DI 2 "=r"))] "" "* { rtx best_label = 0; rtx jump_table_insn = next_active_insn (operands[1]); if (GET_CODE (jump_table_insn) == JUMP_INSN && GET_CODE (PATTERN (jump_table_insn)) == ADDR_VEC) { rtx jump_table = PATTERN (jump_table_insn); int n_labels = XVECLEN (jump_table, 0); int best_count = -1; int i, j; for (i = 0; i < n_labels; i++) { int count = 1; for (j = i + 1; j < n_labels; j++) if (XEXP (XVECEXP (jump_table, 0, i), 0) == XEXP (XVECEXP (jump_table, 0, j), 0)) count++; if (count > best_count) best_count = count, best_label = XVECEXP (jump_table, 0, i); } } if (best_label) { operands[3] = best_label; return \"addq %0,$29,%2\;jmp $31,(%2),%3\"; } else return \"addq %0,$29,%2\;jmp $31,(%2),0\"; }" [(set_attr "type" "ibr")]) ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't ;; want to have to include pal.h in our .s file. (define_insn "" [(unspec_volatile [(const_int 0)] 0)] "" "call_pal 0x86") ;; Finally, we have the basic data motion insns. The byte and word insns ;; are done via define_expand. Start with the floating-point insns, since ;; they are simpler. (define_insn "" [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m") (match_operand:SF 1 "input_operand" "rG,m,rG,f,G,m,fG"))] "register_operand (operands[0], SFmode) || reg_or_fp0_operand (operands[1], SFmode)" "@ bis %r1,%r1,%0 ldl %0,%1 stl %r1,%0 cpys %1,%1,%0 cpys $f31,$f31,%0 lds %0,%1 sts %R1,%0" [(set_attr "type" "iaddlog,ld,st,fpop,fpop,ld,st")]) (define_insn "" [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m") (match_operand:DF 1 "input_operand" "rG,m,rG,f,G,m,fG"))] "register_operand (operands[0], DFmode) || reg_or_fp0_operand (operands[1], DFmode)" "@ bis %r1,%r1,%0 ldq %0,%1 stq %r1,%0 cpys %1,%1,%0 cpys $f31,$f31,%0 ldt %0,%1 stt %R1,%0" [(set_attr "type" "iaddlog,ld,st,fpop,fpop,ld,st")]) (define_expand "movsf" [(set (match_operand:SF 0 "nonimmediate_operand" "") (match_operand:SF 1 "general_operand" ""))] "" " { if (GET_CODE (operands[0]) == MEM && ! reg_or_fp0_operand (operands[1], SFmode)) operands[1] = force_reg (SFmode, operands[1]); }") (define_expand "movdf" [(set (match_operand:DF 0 "nonimmediate_operand" "") (match_operand:DF 1 "general_operand" ""))] "" " { if (GET_CODE (operands[0]) == MEM && ! reg_or_fp0_operand (operands[1], DFmode)) operands[1] = force_reg (DFmode, operands[1]); }") ;; There is a problem with 32-bit values in FP registers. We keep such ;; values in the register as a quadword. This is done on loads by using ;; the cvtlq instruction. On stores, we can't do anything directly from ;; floating-point registers. Disallow such an operation and let reload ;; use an integer register instead. Don't encourage 32-bit values to ;; be placed in FP registers at all. (define_insn "" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,*f") (match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,*f,J,m"))] "register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)" "@ bis %1,%1,%0 bis $31,$31,%0 bis $31,%1,%0 lda %0,%1 ldah %0,%h1 ldl %0,%1 stl %r1,%0 cpys %1,%1,%0 cpys $f31,$f31,%0 lds %0,%1\;cvtlq %0,%0" [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ld,st,fpop,fpop,ld")]) (define_insn "" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,f,f") (match_operand:HI 1 "input_operand" "r,J,I,n,f,J"))] "register_operand (operands[0], HImode) || register_operand (operands[1], HImode)" "@ bis %1,%1,%0 bis $31,$31,%0 bis $31,%1,%0 lda %0,%L1 cpys %1,%1,%0 cpys $f31,$f31,%0" [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,fpop,fpop")]) (define_insn "" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,f,f") (match_operand:QI 1 "input_operand" "r,J,I,n,f,J"))] "register_operand (operands[0], QImode) || register_operand (operands[1], QImode)" "@ bis %1,%1,%0 bis $31,$31,%0 bis $31,%1,%0 lda %0,%L1 cpys %1,%1,%0 cpys $f31,$f31,%0" [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,fpop,fpop")]) ;; We do two major things here: handle mem->mem and construct long ;; constants. (define_expand "movsi" [(set (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))] "" " { if (GET_CODE (operands[0]) == MEM && ! reg_or_0_operand (operands[1], SImode)) operands[1] = force_reg (SImode, operands[1]); if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode)) ; else if (GET_CODE (operands[1]) == CONST_INT) { if (alpha_emit_set_const (operands[0], INTVAL (operands[1]), 3)) DONE; else abort (); } }") ;; Split a load of a large constant into the appropriate two-insn ;; sequence. (define_split [(set (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "const_int_operand" ""))] "! add_operand (operands[1], SImode)" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))] " { if (alpha_emit_set_const (operands[0], INTVAL (operands[1]), 2)) DONE; else FAIL; }") (define_insn "" [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,r,r,m,f,f,f,Q") (match_operand:DI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,Q,fG"))] "register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode)" "@ bis %1,%1,%0 bis $31,$31,%0 bis $31,%1,%0 lda %0,%1 ldah %0,%h1 lda %0,%1 ldq%A1 %0,%1 stq%A0 %r1,%0 cpys %1,%1,%0 cpys $f31,$f31,%0 ldt %0,%1 stt %R1,%0" [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ldsym,ld,st,fpop,fpop,ld,st")]) ;; We do three major things here: handle mem->mem, put 64-bit constants in ;; memory, and construct long 32-bit constants. (define_expand "movdi" [(set (match_operand:DI 0 "general_operand" "") (match_operand:DI 1 "general_operand" ""))] "" " { if (GET_CODE (operands[0]) == MEM && ! reg_or_0_operand (operands[1], DImode)) operands[1] = force_reg (DImode, operands[1]); if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode)) ; else if (GET_CODE (operands[1]) == CONST_INT && alpha_emit_set_const (operands[0], INTVAL (operands[1]), 3)) DONE; else if (CONSTANT_P (operands[1])) { operands[1] = force_const_mem (DImode, operands[1]); if (reload_in_progress) { emit_move_insn (operands[0], XEXP (operands[1], 0)); XEXP (operands[1], 0) = operands[0]; } else operands[1] = validize_mem (operands[1]); } else abort (); }") ;; Split a load of a large constant into the appropriate two-insn ;; sequence. (define_split [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "const_int_operand" ""))] "! add_operand (operands[1], DImode)" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] " { if (alpha_emit_set_const (operands[0], INTVAL (operands[1]), 2)) DONE; else FAIL; }") ;; These are the partial-word cases. ;; ;; First we have the code to load an aligned word. Operand 0 is the register ;; in which to place the result. It's mode is QImode or HImode. Operand 1 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the ;; number of bits within the word that the value is. Operand 3 is an SImode ;; scratch register. If operand 0 is a hard register, operand 3 may be the ;; same register. It is allowed to conflict with operand 1 as well. (define_expand "aligned_loadqi" [(set (match_operand:SI 3 "register_operand" "") (match_operand:SI 1 "memory_operand" "")) (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0) (zero_extract:DI (subreg:DI (match_dup 3) 0) (const_int 8) (match_operand:DI 2 "const_int_operand" "")))] "" "") (define_expand "aligned_loadhi" [(set (match_operand:SI 3 "register_operand" "") (match_operand:SI 1 "memory_operand" "")) (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0) (zero_extract:DI (subreg:DI (match_dup 3) 0) (const_int 16) (match_operand:DI 2 "const_int_operand" "")))] "" "") ;; Similar for unaligned loads. For QImode, we use the sequence from the ;; Alpha Architecture manual. However, for HImode, we do not. HImode pointers ;; are normally aligned to the byte boundary, so an HImode object cannot ;; cross a longword boundary. We could use a sequence similar to that for ;; QImode, but that would fail if the pointer, was, in fact, not aligned. ;; Instead, we clear bit 1 in the address and do an ldl. If the low-order ;; bit was not aligned, this will trap and the trap handler will do what is ;; needed. ;; ;; Here operand 1 is the address. Operands 2 and 3 are temporaries, where ;; operand 3 can overlap the input and output registers. (define_expand "unaligned_loadqi" [(set (match_operand:DI 2 "register_operand" "") (mem:DI (and:DI (match_operand:DI 1 "address_operand" "") (const_int -8)))) (set (match_operand:DI 3 "register_operand" "") (match_dup 1)) (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0) (zero_extract:DI (match_dup 2) (const_int 8) (ashift:DI (match_dup 3) (const_int 3))))] "" "") ;; For this, the address must already be in a register. We also need two ;; DImode temporaries, neither of which may overlap the input (and hence the ;; output, since they might be the same register), but both of which may ;; be the same. (define_expand "unaligned_loadhi" [(set (match_operand:DI 2 "register_operand" "") (and:DI (match_operand:DI 1 "register_operand" "") (const_int -7))) (set (match_operand:DI 3 "register_operand" "") (mem:DI (match_dup 2))) (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0) (zero_extract:DI (match_dup 3) (const_int 16) (ashift:DI (match_dup 1) (const_int 3))))] "" "") ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the ;; aligned SImode MEM. Operand 1 is the register containing the ;; byte or word to store. Operand 2 is the number of bits within the word that ;; the value should be placed. Operands 3 and 4 are SImode temporaries. (define_expand "aligned_store" [(set (match_operand:SI 3 "register_operand" "") (match_operand:SI 0 "memory_operand" "")) (set (subreg:DI (match_dup 3) 0) (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5))) (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0) (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" "")) (match_operand:DI 2 "const_int_operand" ""))) (set (subreg:DI (match_dup 4) 0) (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0))) (set (match_dup 0) (match_dup 4))] "" " { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1])) << INTVAL (operands[2]))); }") ;; For the unaligned byte case, we use code similar to that in the ;; Architecture book, but reordered to lower the number of registers ;; required. Operand 0 is the address. Operand 1 is the data to store. ;; Operands 2, 3, and 4 are DImode temporaries, where the last two may ;; be the same temporary, if desired. If the address is in a register, ;; operand 2 can be that register. (define_expand "unaligned_storeqi" [(set (match_operand:DI 3 "register_operand" "") (mem:DI (and:DI (match_operand:DI 0 "address_operand" "") (const_int -8)))) (set (match_operand:DI 2 "register_operand" "") (match_dup 0)) (set (match_dup 3) (and:DI (ashift:DI (const_int 255) (ashift:DI (match_dup 2) (const_int 3))) (match_dup 3))) (set (match_operand:DI 4 "register_operand" "") (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "")) (ashift:DI (match_dup 2) (const_int 3)))) (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3))) (set (mem:DI (and:DI (match_dup 0) (const_int -8))) (match_dup 4))] "" "") ;; This is the code for storing into an unaligned short. It uses the same ;; trick as loading from an unaligned short. It needs lots of temporaries. ;; However, during reload, we only have two registers available. So we ;; repeat code so that only two temporaries are available. During RTL ;; generation, we can use different pseudos for each temporary and CSE ;; will remove the redundancies. During reload, we have to settle with ;; what we get. Luckily, unaligned accesses of this kind produced during ;; reload are quite rare. ;; ;; Operand 0 is the address of the memory location. Operand 1 contains the ;; data to store. The rest of the operands are all temporaries, with ;; various overlap possibilities during reload. See reload_outhi for ;; details of this use. (define_expand "unaligned_storehi" [(set (match_operand:DI 2 "register_operand" "") (match_operand:DI 0 "address_operand" "")) (set (match_operand:DI 3 "register_operand" "") (and:DI (match_dup 2) (const_int -7))) (set (match_operand:DI 4 "register_operand" "") (mem:DI (match_dup 3))) (set (match_operand:DI 5 "register_operand" "") (and:DI (ashift:DI (const_int 65535) (ashift:DI (match_dup 2) (const_int 3))) (match_dup 4))) (set (match_operand:DI 6 "register_operand" "") (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "")) (ashift:DI (match_dup 2) (const_int 3)))) (set (match_operand:DI 7 "register_operand" "") (ior:DI (match_dup 5) (match_dup 6))) (set (match_operand:DI 8 "register_operand" "") (match_dup 0)) (set (match_operand:DI 9 "register_operand" "") (and:DI (match_dup 8) (const_int -7))) (set (mem:DI (match_dup 9)) (match_dup 7))] "" "") ;; Here are the define_expand's for QI and HI moves that use the above ;; patterns. We have the normal sets, plus the ones that need scratch ;; registers for reload. (define_expand "movqi" [(set (match_operand:QI 0 "general_operand" "") (match_operand:QI 1 "general_operand" ""))] "" " { extern rtx get_unaligned_address (); /* If the output is not a register, the input must be. */ if (GET_CODE (operands[0]) == MEM) operands[1] = force_reg (QImode, operands[1]); /* Handle four memory cases, unaligned and aligned for either the input or the output. The only case where we can be called during reload is for aligned loads; all other cases require temporaries. */ if (GET_CODE (operands[1]) == MEM || (GET_CODE (operands[1]) == SUBREG && GET_CODE (SUBREG_REG (operands[1])) == MEM) || (reload_in_progress && GET_CODE (operands[1]) == REG && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) || (reload_in_progress && GET_CODE (operands[1]) == SUBREG && GET_CODE (SUBREG_REG (operands[1])) == REG && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER)) { if (aligned_memory_operand (operands[1], QImode)) { rtx aligned_mem, bitnum; rtx scratch = (reload_in_progress ? gen_rtx (REG, SImode, REGNO (operands[0])) : gen_reg_rtx (SImode)); get_aligned_mem (operands[1], &aligned_mem, &bitnum); emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum, scratch)); } else { /* Don't pass these as parameters since that makes the generated code depend on parameter evaluation order which will cause bootstrap failures. */ rtx temp1 = gen_reg_rtx (DImode); rtx temp2 = gen_reg_rtx (DImode); rtx seq = gen_unaligned_loadqi (operands[0], get_unaligned_address (operands[1]), temp1, temp2); alpha_set_memflags (seq, operands[1]); emit_insn (seq); } DONE; } else if (GET_CODE (operands[0]) == MEM || (GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == MEM) || (reload_in_progress && GET_CODE (operands[0]) == REG && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER) || (reload_in_progress && GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == REG && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)) { if (aligned_memory_operand (operands[0], QImode)) { rtx aligned_mem, bitnum; rtx temp1 = gen_reg_rtx (SImode); rtx temp2 = gen_reg_rtx (SImode); get_aligned_mem (operands[0], &aligned_mem, &bitnum); emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, temp1, temp2)); } else { rtx temp1 = gen_reg_rtx (DImode); rtx temp2 = gen_reg_rtx (DImode); rtx temp3 = gen_reg_rtx (DImode); rtx seq = gen_unaligned_storeqi (get_unaligned_address (operands[0]), operands[1], temp1, temp2, temp3); alpha_set_memflags (seq, operands[0]); emit_insn (seq); } DONE; } }") (define_expand "movhi" [(set (match_operand:HI 0 "general_operand" "") (match_operand:HI 1 "general_operand" ""))] "" " { extern rtx get_unaligned_address (); /* If the output is not a register, the input must be. */ if (GET_CODE (operands[0]) == MEM) operands[1] = force_reg (HImode, operands[1]); /* Handle four memory cases, unaligned and aligned for either the input or the output. The only case where we can be called during reload is for aligned loads; all other cases require temporaries. */ if (GET_CODE (operands[1]) == MEM || (GET_CODE (operands[1]) == SUBREG && GET_CODE (SUBREG_REG (operands[1])) == MEM) || (reload_in_progress && GET_CODE (operands[1]) == REG && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) || (reload_in_progress && GET_CODE (operands[1]) == SUBREG && GET_CODE (SUBREG_REG (operands[1])) == REG && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER)) { if (aligned_memory_operand (operands[1], HImode)) { rtx aligned_mem, bitnum; rtx scratch = (reload_in_progress ? gen_rtx (REG, SImode, REGNO (operands[0])) : gen_reg_rtx (SImode)); get_aligned_mem (operands[1], &aligned_mem, &bitnum); emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum, scratch)); } else { rtx addr = force_reg (DImode, force_operand (get_unaligned_address (operands[1]), NULL_RTX)); rtx scratch1 = gen_reg_rtx (DImode); rtx scratch2 = gen_reg_rtx (DImode); rtx seq = gen_unaligned_loadhi (operands[0], addr, scratch1, scratch2); alpha_set_memflags (seq, operands[1]); emit_insn (seq); } DONE; } else if (GET_CODE (operands[0]) == MEM || (GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == MEM) || (reload_in_progress && GET_CODE (operands[0]) == REG && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER) || (reload_in_progress && GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == REG && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)) { if (aligned_memory_operand (operands[0], HImode)) { rtx aligned_mem, bitnum; rtx temp1 = gen_reg_rtx (SImode); rtx temp2 = gen_reg_rtx (SImode); get_aligned_mem (operands[0], &aligned_mem, &bitnum); emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, temp1, temp2)); } else { rtx temp1 = gen_reg_rtx (DImode); rtx temp2 = gen_reg_rtx (DImode); rtx temp3 = gen_reg_rtx (DImode); rtx temp4 = gen_reg_rtx (DImode); rtx temp5 = gen_reg_rtx (DImode); rtx temp6 = gen_reg_rtx (DImode); rtx temp7 = gen_reg_rtx (DImode); rtx temp8 = gen_reg_rtx (DImode); rtx seq = gen_unaligned_storehi (get_unaligned_address (operands[0]), operands[1], temp1, temp2,temp3, temp4, temp5, temp6,temp7, temp8); alpha_set_memflags (seq, operands[0]); emit_insn (seq); } DONE; } }") ;; Here are the versions for reload. Note that in the unaligned cases ;; we know that the operand must not be a pseudo-register because stack ;; slots are always aligned references. (define_expand "reload_inqi" [(parallel [(match_operand:QI 0 "register_operand" "=r") (match_operand:QI 1 "unaligned_memory_operand" "m") (match_operand:DI 2 "register_operand" "=&r")])] "" " { extern rtx get_unaligned_address (); rtx addr = get_unaligned_address (operands[1]); rtx seq = gen_unaligned_loadqi (operands[0], addr, operands[2], gen_rtx (REG, DImode, REGNO (operands[0]))); alpha_set_memflags (seq, operands[1]); emit_insn (seq); DONE; }") (define_expand "reload_inhi" [(parallel [(match_operand:HI 0 "register_operand" "=r") (match_operand:HI 1 "unaligned_memory_operand" "m") (match_operand:TI 2 "register_operand" "=&r")])] "" " { extern rtx get_unaligned_address (); rtx addr = get_unaligned_address (operands[1]); rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2])); rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1); rtx seq; if (GET_CODE (addr) != REG) { emit_insn (gen_rtx (SET, VOIDmode, scratch2, addr)); addr = scratch2; } seq = gen_unaligned_loadhi (operands[0], addr, scratch1, scratch1); alpha_set_memflags (seq, operands[1]); emit_insn (seq); DONE; }") (define_expand "reload_outqi" [(parallel [(match_operand:QI 0 "any_memory_operand" "=m") (match_operand:QI 1 "register_operand" "r") (match_operand:TI 2 "register_operand" "=&r")])] "" " { extern rtx get_unaligned_address (); if (aligned_memory_operand (operands[0], QImode)) { rtx aligned_mem, bitnum; get_aligned_mem (operands[0], &aligned_mem, &bitnum); emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, gen_rtx (REG, SImode, REGNO (operands[2])), gen_rtx (REG, SImode, REGNO (operands[2]) + 1))); } else { rtx addr = get_unaligned_address (operands[0]); rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2])); rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1); rtx seq; if (GET_CODE (addr) == REG) scratch1 = addr; seq = gen_unaligned_storeqi (addr, operands[1], scratch1, scratch2, scratch2); alpha_set_memflags (seq, operands[0]); emit_insn (seq); } DONE; }") (define_expand "reload_outhi" [(parallel [(match_operand:HI 0 "any_memory_operand" "=m") (match_operand:HI 1 "register_operand" "r") (match_operand:TI 2 "register_operand" "=&r")])] "" " { extern rtx get_unaligned_address (); if (aligned_memory_operand (operands[0], HImode)) { rtx aligned_mem, bitnum; get_aligned_mem (operands[0], &aligned_mem, &bitnum); emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, gen_rtx (REG, SImode, REGNO (operands[2])), gen_rtx (REG, SImode, REGNO (operands[2]) + 1))); } else { rtx addr = get_unaligned_address (operands[0]); rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2])); rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1); rtx scratch_a = GET_CODE (addr) == REG ? addr : scratch1; rtx seq; seq = gen_unaligned_storehi (addr, operands[1], scratch_a, scratch2, scratch2, scratch2, scratch1, scratch2, scratch_a, scratch1); alpha_set_memflags (seq, operands[0]); emit_insn (seq); } DONE; }") ;; Subroutine of stack space allocation. Perform a stack probe. (define_expand "probe_stack" [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))] "" " { operands[0] = gen_rtx (MEM, DImode, plus_constant (stack_pointer_rtx, INTVAL (operands[0]))); MEM_VOLATILE_P (operands[0]) = 1; operands[1] = gen_reg_rtx (DImode); }") ;; This is how we allocate stack space. If we are allocating a ;; constant amount of space and we know it is less than 4096 ;; bytes, we need do nothing. ;; ;; If it is more than 4096 bytes, we need to probe the stack ;; periodically. (define_expand "allocate_stack" [(set (reg:DI 30) (plus:DI (reg:DI 30) (match_operand:DI 0 "reg_or_cint_operand" "")))] "" " { if (GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) < 32768) { if (INTVAL (operands[0]) >= 4096) { /* We do this the same way as in the prologue and generate explicit probes. Then we update the stack by the constant. */ int probed = 4096; emit_insn (gen_probe_stack (GEN_INT (- probed))); while (probed + 8192 < INTVAL (operands[0])) emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192)))); if (probed + 4096 < INTVAL (operands[0])) emit_insn (gen_probe_stack (GEN_INT (- (probed += 4096)))); } operands[0] = GEN_INT (- INTVAL (operands[0])); } else { rtx out_label = 0; rtx loop_label = gen_label_rtx (); rtx count = gen_reg_rtx (DImode); rtx access = gen_reg_rtx (Pmode); rtx memref = gen_rtx (MEM, DImode, access); MEM_VOLATILE_P (memref) = 1; /* If the amount to be allocated is not a constant, we only need to do something special if it is >= 4096. */ if (GET_CODE (operands[0]) != CONST_INT) { operands[0] = force_reg (DImode, operands[0]); out_label = gen_label_rtx (); emit_insn (gen_cmpdi (operands[0], force_reg (DImode, GEN_INT (4096)))); emit_jump_insn (gen_ble (out_label)); /* Compute COUNT = (N + 4096) / 8192. N is known positive. */ emit_insn (gen_adddi3 (count, operands[0], GEN_INT (4096))); emit_insn (gen_lshrdi3 (count, count, GEN_INT (13))); } else emit_move_insn (count, GEN_INT ((INTVAL (operands[0]) + 4096) >> 13)); /* ACCESS = SP + 4096. */ emit_insn (gen_adddi3 (access, stack_pointer_rtx, GEN_INT (4096))); emit_label (loop_label); /* Each iteration subtracts 8192 from ACCESS and references it. */ emit_insn (gen_adddi3 (count, count, constm1_rtx)); emit_insn (gen_adddi3 (access, access, GEN_INT (-8192))); emit_move_insn (gen_reg_rtx (DImode), memref); emit_insn (gen_cmpdi (count, const0_rtx)); emit_jump_insn (gen_bgt (loop_label)); if (out_label) emit_label (out_label); /* We need to subtract operands[0] from SP. We know it isn't a constant less than 32768, so we know we have to load it into a register. */ emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, force_reg (Pmode, operands[0]))); /* Now, unless we have a constant and we know that we are within 4096 from the end, we need to access sp + 4096. */ if (! (GET_CODE (operands[0]) == CONST_INT && (INTVAL (operands[0]) % 8192) < 4096)) emit_insn (gen_probe_stack (GEN_INT (4096))); DONE; } }") gcc-2.5.8/config/alpha/osf12.h100444 22011 13 2050 5470271477 14432 0ustar kenneruser/* Definitions of target machine for GNU compiler, for DEC Alpha. Copyright (C) 1992, 1993 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@nyu.edu) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "alpha/alpha.h" /* In OSF 1.2, there is a linker bug that prevents use of -O3 to the linker. */ #undef LINK_SPEC #define LINK_SPEC \ "-G 8 -O1 %{static:-non_shared} %{!static:-call_shared}" gcc-2.5.8/config/alpha/xm-alpha.h100444 22011 13 3631 5455104403 15200 0ustar kenneruser/* Configuration for GNU C-compiler for DEC Alpha. Copyright (C) 1990, 1992, 1993 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@nyu.edu). This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* #defines that need visibility everywhere. */ #define FALSE 0 #define TRUE 1 /* This describes the machine the compiler is hosted on. */ #define HOST_BITS_PER_CHAR 8 #define HOST_BITS_PER_SHORT 16 #define HOST_BITS_PER_INT 32 #define HOST_BITS_PER_LONG 64 #define HOST_BITS_PER_LONGLONG 64 /* #define HOST_WORDS_BIG_ENDIAN */ /* target machine dependencies. tm.h is a symbolic link to the actual target specific file. */ #include "tm.h" /* Arguments to use with `exit'. */ #define SUCCESS_EXIT_CODE 0 #define FAILURE_EXIT_CODE 2 #define FATAL_EXIT_CODE 3 /* If not compiled with GNU C, use the C alloca. */ #ifndef __GNUC__ #define USE_C_ALLOCA #endif /* The host compiler has problems with enum bitfields since it makes them signed so we can't fit all our codes in. */ #ifndef __GNUC__ #define ONLY_INT_FIELDS #endif /* Declare some functions needed for this machine. We don't want to include these in the sources since other machines might define them differently. */ extern void *malloc (), *realloc (), *sbrk (), *calloc (), *alloca (); #include "string.h" gcc-2.5.8/config/aoutos.h100444 22011 13 6043 5317154750 13725 0ustar kenneruser/* aoutos.h -- operating system specific defines to be used when targeting GCC for some system that uses a.out file format. Copyright (C) 1992 Free Software Foundation, Inc. Written by Ron Guilmette (rfg@ncd.com). This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* To use this file, make up a file with a name like: ?????aout.h where ????? is replaced by the name of the basic hardware that you are targeting for. Then, in the file ?????aout.h, put something like: #include "?????.h" #include "aoutos.h" followed by any really system-specific defines (or overrides of defines) which you find that you need. Now, modify the configure or configure.in script to properly use the new ?????aout.h file when configuring for the system. */ /* Define a symbol indicating that we are using aoutos.h. */ #define USING_AOUTOS_H /* A C statement (sans semicolon) to output an element in the table of global constructors. If using GNU LD, tell it that this is part of the static destructor set. This code works for any machine provided you use GNU as/ld. If not using GNU LD, rely on a "collect" program to look for names defined in the particular form we choose as global constructor function names. */ #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ do { \ if (flag_gnu_linker) \ { \ /* Output an N_SETT (0x16, 22.) for the name. */ \ fprintf (FILE, "%s \"___CTOR_LIST__\",22,0,0,", ASM_STABS_OP); \ assemble_name (FILE, NAME); \ fputc ('\n', FILE); \ } \ } while (0) /* A C statement (sans semicolon) to output an element in the table of global destructors. */ #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ do { \ if (flag_gnu_linker) \ { \ /* Output an N_SETT (0x16, 22.) for the name. */ \ fprintf (FILE, "%s \"___DTOR_LIST__\",22,0,0,", ASM_STABS_OP); \ assemble_name (FILE, NAME); \ fputc ('\n', FILE); \ } \ } while (0) /* Likewise for entries we want to record for garbage collection. Garbage collection is still under development. */ #define ASM_OUTPUT_GC_ENTRY(FILE,NAME) \ do { \ if (flag_gnu_linker) \ { \ /* Output an N_SETT (0x16, 22.) for the name. */ \ fprintf (FILE, "%s \"___PTR_LIST__\",22,0,0,", ASM_STABS_OP); \ assemble_name (FILE, NAME); \ fputc ('\n', FILE); \ } \ } while (0) gcc-2.5.8/config/arm/ 40777 22011 13 0 5502603156 12722 5ustar kennerusergcc-2.5.8/config/arm/arm.c100444 22011 13 205424 5500623255 14003 0ustar kenneruser/* Output routines for GCC for ARM/RISCiX. Copyright (C) 1991, 1993 Free Software Foundation, Inc. Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include "assert.h" #include "config.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "output.h" #include "insn-attr.h" #include "flags.h" #include "reload.h" /* The maximum number of insns skipped which will be conditionalised if possible. */ #define MAX_INSNS_SKIPPED 5 /* Some function declarations. */ extern FILE *asm_out_file; extern char *output_multi_immediate (); extern char *arm_output_asm_insn (); extern void arm_increase_location (); /* Define the information needed to generate branch insns. This is stored from the compare operation. */ rtx arm_compare_op0, arm_compare_op1; int arm_compare_fp; /* What type of cpu are we compiling for? */ enum processor_type arm_cpu; /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we must report the mode of the memory reference from PRINT_OPERAND to PRINT_OPERAND_ADDRESS. */ int output_memory_reference_mode; /* Nonzero if the prologue must setup `fp'. */ int current_function_anonymous_args; /* Location counter of .text segment. */ int arm_text_location = 0; /* Set to one if we think that lr is only saved because of subroutine calls, but all of these can be `put after' return insns */ int lr_save_eliminated; /* A hash table is used to store text segment labels and their associated offset from the start of the text segment. */ struct label_offset { char *name; int offset; struct label_offset *cdr; }; #define LABEL_HASH_SIZE 257 static struct label_offset *offset_table[LABEL_HASH_SIZE]; /* Set to 1 when a return insn is output, this means that the epilogue is not needed. */ static int return_used_this_function; /* For an explanation of these variables, see final_prescan_insn below. */ int arm_ccfsm_state; int arm_current_cc; rtx arm_target_insn; int arm_target_label; /* Return 1 if it is possible to return using a single instruction */ int use_return_insn () { int regno; if (!reload_completed ||current_function_pretend_args_size || current_function_anonymous_args || (get_frame_size () && !(TARGET_APCS || frame_pointer_needed))) return 0; /* Can't be done if any of the FPU regs are pushed, since this also requires an insn */ for (regno = 20; regno < 24; regno++) if (regs_ever_live[regno]) return 0; return 1; } /* Return the number of mov instructions needed to get the constant VALUE into a register. */ int arm_const_nmoves (value) register int value; { register int i; if (value == 0) return (1); for (i = 0; value; i++, value &= ~0xff) while ((value & 3) == 0) value = (value >> 2) | ((value & 3) << 30); return (i); } /* arm_const_nmoves */ /* Return TRUE if int I is a valid immediate ARM constant. */ int const_ok_for_arm (i) HOST_WIDE_INT i; { unsigned HOST_WIDE_INT mask = ~0xFF; do { if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0) return(TRUE); mask = (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff) >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffff); } while (mask != ~0xFF); return (FALSE); } /* const_ok_for_arm */ /* This code has been fixed for cross compilation. */ static int fpa_consts_inited = 0; char *strings_fpa[8] = { "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0" }; static REAL_VALUE_TYPE values_fpa[8]; static void init_fpa_table () { int i; REAL_VALUE_TYPE r; for (i = 0; i < 8; i++) { r = REAL_VALUE_ATOF (strings_fpa[i], DFmode); values_fpa[i] = r; } fpa_consts_inited = 1; } /* Return TRUE if rtx X is a valid immediate FPU constant. */ int const_double_rtx_ok_for_fpu (x) rtx x; { REAL_VALUE_TYPE r; int i; if (!fpa_consts_inited) init_fpa_table (); REAL_VALUE_FROM_CONST_DOUBLE (r, x); if (REAL_VALUE_MINUS_ZERO (r)) return 0; for (i = 0; i < 8; i++) if (REAL_VALUES_EQUAL (r, values_fpa[i])) return 1; return 0; } /* const_double_rtx_ok_for_fpu */ /* Return TRUE if rtx X is a valid immediate FPU constant. */ int neg_const_double_rtx_ok_for_fpu (x) rtx x; { REAL_VALUE_TYPE r; int i; if (!fpa_consts_inited) init_fpa_table (); REAL_VALUE_FROM_CONST_DOUBLE (r, x); r = REAL_VALUE_NEGATE (r); if (REAL_VALUE_MINUS_ZERO (r)) return 0; for (i = 0; i < 8; i++) if (REAL_VALUES_EQUAL (r, values_fpa[i])) return 1; return 0; } /* neg_const_double_rtx_ok_for_fpu */ /* Predicates for `match_operand' and `match_operator'. */ /* s_register_operand is the same as register_operand, but it doesn't accept (SUBREG (MEM)...). */ int s_register_operand (op, mode) register rtx op; enum machine_mode mode; { if (GET_MODE (op) != mode && mode != VOIDmode) return 0; if (GET_CODE (op) == SUBREG) { op = SUBREG_REG (op); } /* We don't consider registers whose class is NO_REGS to be a register operand. */ return (GET_CODE (op) == REG && (REGNO (op) >= FIRST_PSEUDO_REGISTER || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); } /* Return 1 if OP is an item in memory, given that we are in reload. */ int reload_memory_operand (op, mode) rtx op; enum machine_mode mode; { int regno = true_regnum (op); return (! CONSTANT_P (op) && (regno == -1 || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER))); } /* Return TRUE for valid operands for the rhs of an ARM instruction. */ int arm_rhs_operand (op, mode) rtx op; enum machine_mode mode; { return (s_register_operand (op, mode) || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))); } /* arm_rhs_operand */ /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load. */ int arm_rhsm_operand (op, mode) rtx op; enum machine_mode mode; { return (s_register_operand (op, mode) || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))) || memory_operand (op, mode)); } /* arm_rhs_operand */ /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a constant that is valid when negated. */ int arm_add_operand (op, mode) rtx op; enum machine_mode mode; { return (s_register_operand (op, mode) || (GET_CODE (op) == CONST_INT && (const_ok_for_arm (INTVAL (op)) || const_ok_for_arm (-INTVAL (op))))); } /* arm_rhs_operand */ int arm_not_operand (op, mode) rtx op; enum machine_mode mode; { return (s_register_operand (op, mode) || (GET_CODE (op) == CONST_INT && (const_ok_for_arm (INTVAL (op)) || const_ok_for_arm (~INTVAL (op))))); } /* arm_rhs_operand */ /* Return TRUE for valid operands for the rhs of an FPU instruction. */ int fpu_rhs_operand (op, mode) rtx op; enum machine_mode mode; { if (s_register_operand (op, mode)) return(TRUE); else if (GET_CODE (op) == CONST_DOUBLE) return (const_double_rtx_ok_for_fpu (op)); else return (FALSE); } /* fpu_rhs_operand */ int fpu_add_operand (op, mode) rtx op; enum machine_mode mode; { if (s_register_operand (op, mode)) return(TRUE); else if (GET_CODE (op) == CONST_DOUBLE) return const_double_rtx_ok_for_fpu (op) || neg_const_double_rtx_ok_for_fpu (op); return (FALSE); } /* Return nonzero if OP is a constant power of two. */ int power_of_two_operand (op, mode) rtx op; enum machine_mode mode; { if (GET_CODE (op) == CONST_INT) { int value = INTVAL(op); return (value != 0 && (value & (value-1)) == 0); } return (FALSE); } /* power_of_two_operand */ /* Return TRUE for a valid operand of a DImode operation. Either: REG, CONST_DOUBLE or MEM(DImode_address). Note that this disallows MEM(REG+REG), but allows MEM(PRE/POST_INC/DEC(REG)). */ int di_operand (op, mode) rtx op; enum machine_mode mode; { if (s_register_operand (op, mode)) return (TRUE); switch (GET_CODE (op)) { case CONST_DOUBLE: case CONST_INT: return (TRUE); case MEM: return (memory_address_p (DImode, XEXP (op, 0))); default: return (FALSE); } } /* di_operand */ /* Return TRUE for valid index operands. */ int index_operand (op, mode) rtx op; enum machine_mode mode; { return (s_register_operand(op, mode) || (immediate_operand (op, mode) && INTVAL (op) < 4096 && INTVAL (op) > -4096)); } /* index_operand */ /* Return TRUE for valid shifts by a constant. This also accepts any power of two on the (somewhat overly relaxed) assumption that the shift operator in this case was a mult. */ int const_shift_operand (op, mode) rtx op; enum machine_mode mode; { return (power_of_two_operand (op, mode) || (immediate_operand (op, mode) && (INTVAL (op) < 32 && INTVAL (op) > 0))); } /* const_shift_operand */ /* Return TRUE for arithmetic operators which can be combined with a multiply (shift). */ int shiftable_operator (x, mode) rtx x; enum machine_mode mode; { if (GET_MODE (x) != mode) return FALSE; else { enum rtx_code code = GET_CODE (x); return (code == PLUS || code == MINUS || code == IOR || code == XOR || code == AND); } } /* shiftable_operator */ /* Return TRUE for shift operators. */ int shift_operator (x, mode) rtx x; enum machine_mode mode; { if (GET_MODE (x) != mode) return FALSE; else { enum rtx_code code = GET_CODE (x); if (code == MULT) return power_of_two_operand (XEXP (x, 1)); return (code == ASHIFT || code == LSHIFT || code == ASHIFTRT || code == LSHIFTRT); } } /* shift_operator */ int equality_operator (x, mode) rtx x; enum machine_mode mode; { return (GET_CODE (x) == EQ || GET_CODE (x) == NE); } /* Return TRUE for SMIN SMAX UMIN UMAX operators. */ int minmax_operator (x, mode) rtx x; enum machine_mode mode; { enum rtx_code code = GET_CODE (x); if (GET_MODE (x) != mode) return FALSE; return code == SMIN || code == SMAX || code == UMIN || code == UMAX; } /* minmax_operator */ /* return TRUE if x is EQ or NE */ /* Return TRUE if this is the condition code register, if we aren't given a mode, accept any class CCmode register */ int cc_register (x, mode) rtx x; enum machine_mode mode; { if (mode == VOIDmode) { mode = GET_MODE (x); if (GET_MODE_CLASS (mode) != MODE_CC) return FALSE; } if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24) return TRUE; return FALSE; } enum rtx_code minmax_code (x) rtx x; { enum rtx_code code = GET_CODE (x); if (code == SMAX) return GE; if (code == SMIN) return LE; if (code == UMIN) return LEU; if (code == UMAX) return GEU; abort (); } /* Return 1 if memory locations are adjacent */ adjacent_mem_locations (a, b) rtx a, b; { int val0 = 0, val1 = 0; int reg0, reg1; if ((GET_CODE (XEXP (a, 0)) == REG || (GET_CODE (XEXP (a, 0)) == PLUS && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) && (GET_CODE (XEXP (b, 0)) == REG || (GET_CODE (XEXP (b, 0)) == PLUS && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) { if (GET_CODE (XEXP (a, 0)) == PLUS) { reg0 = REGNO (XEXP (XEXP (a, 0), 0)); val0 = INTVAL (XEXP (XEXP (a, 0), 1)); } else reg0 = REGNO (XEXP (a, 0)); if (GET_CODE (XEXP (b, 0)) == PLUS) { reg1 = REGNO (XEXP (XEXP (b, 0), 0)); val1 = INTVAL (XEXP (XEXP (b, 0), 1)); } else reg1 = REGNO (XEXP (b, 0)); return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4); } return 0; } /* Return 1 if OP is a load multiple operation. It is known to be parallel and the first section will be tested. */ load_multiple_operation (op, mode) rtx op; enum machine_mode mode; { int count = XVECLEN (op, 0); int dest_regno; rtx src_addr; int i = 1, base = 0; rtx elt; if (count <= 1 || GET_CODE (XVECEXP (op, 0, 0)) != SET) return 0; /* Check to see if this might be a write-back */ if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) { i++; base = 1; /* Now check it more carefully */ if (GET_CODE (SET_DEST (elt)) != REG || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0)) != REGNO (SET_DEST (elt))) return 0; count--; } /* Perform a quick check so we don't blow up below. */ if (count <= i || GET_CODE (XVECEXP (op, 0, i - 1)) != SET || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM) return 0; dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1))); src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0); for (; i < count; i++) { rtx elt = XVECEXP (op, 0, i); if (GET_CODE (elt) != SET || GET_CODE (SET_DEST (elt)) != REG || GET_MODE (SET_DEST (elt)) != SImode || REGNO (SET_DEST (elt)) != dest_regno + i - base || GET_CODE (SET_SRC (elt)) != MEM || GET_MODE (SET_SRC (elt)) != SImode || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4) return 0; } return 1; } /* Return 1 if OP is a store multiple operation. It is known to be parallel and the first section will be tested. */ store_multiple_operation (op, mode) rtx op; enum machine_mode mode; { int count = XVECLEN (op, 0); int src_regno; rtx dest_addr; int i = 1, base = 0; rtx elt; if (count <= 1 || GET_CODE (XVECEXP (op, 0, 0)) != SET) return 0; /* Check to see if this might be a write-back */ if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) { i++; base = 1; /* Now check it more carefully */ if (GET_CODE (SET_DEST (elt)) != REG || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0)) != REGNO (SET_DEST (elt))) return 0; count--; } /* Perform a quick check so we don't blow up below. */ if (count <= i || GET_CODE (XVECEXP (op, 0, i - 1)) != SET || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG) return 0; src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1))); dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0); for (; i < count; i++) { elt = XVECEXP (op, 0, i); if (GET_CODE (elt) != SET || GET_CODE (SET_SRC (elt)) != REG || GET_MODE (SET_SRC (elt)) != SImode || REGNO (SET_SRC (elt)) != src_regno + i - base || GET_CODE (SET_DEST (elt)) != MEM || GET_MODE (SET_DEST (elt)) != SImode || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4) return 0; } return 1; } /* Routines for use in generating RTL */ rtx arm_gen_load_multiple (base_regno, count, from, up, write_back) int base_regno; int count; rtx from; int up; int write_back; { int i = 0, j; rtx result; int sign = up ? 1 : -1; result = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + (write_back ? 2 : 0))); if (write_back) { XVECEXP (result, 0, 0) = gen_rtx (SET, GET_MODE (from), from, plus_constant (from, count * 4 * sign)); i = 1; count++; } for (j = 0; i < count; i++, j++) { XVECEXP (result, 0, i) = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, base_regno + j), gen_rtx (MEM, SImode, plus_constant (from, j * 4 * sign))); } if (write_back) XVECEXP (result, 0, i) = gen_rtx (CLOBBER, SImode, from); return result; } rtx arm_gen_store_multiple (base_regno, count, to, up, write_back) int base_regno; int count; rtx to; int up; int write_back; { int i = 0, j; rtx result; int sign = up ? 1 : -1; result = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + (write_back ? 2 : 0))); if (write_back) { XVECEXP (result, 0, 0) = gen_rtx (SET, GET_MODE (to), to, plus_constant (to, count * 4 * sign)); i = 1; count++; } for (j = 0; i < count; i++, j++) { XVECEXP (result, 0, i) = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, plus_constant (to, j * 4 * sign)), gen_rtx (REG, SImode, base_regno + j)); } if (write_back) XVECEXP (result, 0, i) = gen_rtx (CLOBBER, SImode, to); return result; } /* X and Y are two things to compare using CODE. Emit the compare insn and return the rtx for register 0 in the proper mode. FP means this is a floating point compare: I don't think that it is needed on the arm. */ rtx gen_compare_reg (code, x, y, fp) enum rtx_code code; rtx x, y; { enum machine_mode mode = SELECT_CC_MODE (code, x, y); rtx cc_reg = gen_rtx (REG, mode, 24); emit_insn (gen_rtx (SET, VOIDmode, cc_reg, gen_rtx (COMPARE, mode, x, y))); return cc_reg; } arm_reload_out_hi (operands) rtx operands[]; { rtx base = find_replacement (&XEXP (operands[0], 0)); emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (MEM, QImode, base), gen_rtx (SUBREG, QImode, operands[1], 0))); emit_insn (gen_rtx (SET, VOIDmode, operands[2], gen_rtx (LSHIFTRT, SImode, gen_rtx (SUBREG, SImode, operands[1], 0), GEN_INT (8)))); emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (MEM, QImode, plus_constant (base, 1)), gen_rtx (SUBREG, QImode, operands[2], 0))); } /* Check to see if a branch is forwards or backwards. Return TRUE if it is backwards. */ int arm_backwards_branch (from, to) int from, to; { return (insn_addresses[to] <= insn_addresses[from]); } /* Check to see if a branch is within the distance that can be done using an arithmetic expression. */ int short_branch (from, to) int from, to; { int delta = insn_addresses[from] + 2 - insn_addresses[to]; return abs (delta) < 245; /* A small margin for safety */ } /* Check to see that the insn isn't the target of the conditionalizing code */ int arm_insn_not_targeted (insn) rtx insn; { return insn != arm_target_insn; } /* Routines to output assembly language. */ /* fp_immediate_constant if the rtx is the correct value then return the string of the number. In this way we can ensure that valid double constants are generated even when cross compiling. */ char * fp_immediate_constant (x) rtx (x); { REAL_VALUE_TYPE r; int i; if (!fpa_consts_inited) init_fpa_table (); REAL_VALUE_FROM_CONST_DOUBLE (r, x); for (i = 0; i < 8; i++) if (REAL_VALUES_EQUAL (r, values_fpa[i])) return strings_fpa[i]; abort (); } /* Output the operands of a LDM/STM instruction to STREAM. MASK is the ARM register set mask of which only bits 0-15 are important. INSTR is the possibly suffixed base register. HAT unequals zero if a hat must follow the register list. */ void print_multi_reg (stream, instr, mask, hat) FILE *stream; char *instr; int mask, hat; { int i; int not_first = FALSE; fprintf (stream, "\t%s, {", instr); for (i = 0; i < 16; i++) if (mask & (1 << i)) { if (not_first) fprintf (stream, ", "); fprintf (stream, "%s", reg_names[i]); not_first = TRUE; } fprintf (stream, "}%s\n", hat ? "^" : ""); } /* print_multi_reg */ /* Output a 'call' insn. */ char * output_call (operands) rtx operands[]; { /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ if (REGNO (operands[0]) == 14) { operands[0] = gen_rtx (REG, SImode, 12); arm_output_asm_insn ("mov\t%0, lr", operands); } arm_output_asm_insn ("mov\tlr, pc", operands); arm_output_asm_insn ("mov\tpc, %0", operands); return (""); } /* output_call */ static int eliminate_lr2ip (x) rtx *x; { int something_changed = 0; rtx x0 = *x; int code = GET_CODE (x0); register int i, j; register char *fmt; switch (code) { case REG: if (REGNO (x0) == 14) { *x = gen_rtx (REG, SImode, 12); return 1; } return 0; default: /* Scan through the sub-elements and change any references there */ fmt = GET_RTX_FORMAT (code); for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) if (fmt[i] == 'e') something_changed |= eliminate_lr2ip (&XEXP (x0, i)); else if (fmt[i] == 'E') for (j = 0; j < XVECLEN (x0, i); j++) something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j)); return something_changed; } } /* Output a 'call' insn that is a reference in memory. */ char * output_call_mem (operands) rtx operands[]; { operands[0] = copy_rtx (operands[0]); /* Be ultra careful */ /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */ if (eliminate_lr2ip (&operands[0])) arm_output_asm_insn ("mov\tip, lr", operands); arm_output_asm_insn ("mov\tlr, pc", operands); arm_output_asm_insn ("ldr\tpc, %0", operands); return (""); } /* output_call */ /* Output a move from arm registers to an fpu registers. OPERANDS[0] is an fpu register. OPERANDS[1] is the first registers of an arm register pair. */ char * output_mov_long_double_fpu_from_arm (operands) rtx operands[]; { int arm_reg0 = REGNO (operands[1]); rtx ops[3]; if (arm_reg0 == 12) abort(); ops[0] = gen_rtx (REG, SImode, arm_reg0); ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0); ops[2] = gen_rtx (REG, SImode, 2 + arm_reg0); arm_output_asm_insn ("stmfd\tsp!, {%0, %1, %2}", ops); arm_output_asm_insn ("ldfe\t%0, [sp], #12", operands); return (""); } /* output_mov_long_double_fpu_from_arm */ /* Output a move from an fpu register to arm registers. OPERANDS[0] is the first registers of an arm register pair. OPERANDS[1] is an fpu register. */ char * output_mov_long_double_arm_from_fpu (operands) rtx operands[]; { int arm_reg0 = REGNO (operands[0]); rtx ops[3]; if (arm_reg0 == 12) abort(); ops[0] = gen_rtx (REG, SImode, arm_reg0); ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0); ops[2] = gen_rtx (REG, SImode, 2 + arm_reg0); arm_output_asm_insn ("stfe\t%1, [sp, #-12]!", operands); arm_output_asm_insn ("ldmfd\tsp!, {%0, %1, %2}", ops); return(""); } /* output_mov_long_double_arm_from_fpu */ /* Output a move from arm registers to arm registers of a long double OPERANDS[0] is the destination. OPERANDS[1] is the source. */ char * output_mov_long_double_arm_from_arm (operands) rtx operands[]; { /* We have to be careful here because the two might overlap */ int dest_start = REGNO (operands[0]); int src_start = REGNO (operands[1]); rtx ops[2]; int i; if (dest_start < src_start) { for (i = 0; i < 3; i++) { ops[0] = gen_rtx (REG, SImode, dest_start + i); ops[1] = gen_rtx (REG, SImode, src_start + i); arm_output_asm_insn ("mov\t%0, %1", ops); } } else { for (i = 2; i >= 0; i--) { ops[0] = gen_rtx (REG, SImode, dest_start + i); ops[1] = gen_rtx (REG, SImode, src_start + i); arm_output_asm_insn ("mov\t%0, %1", ops); } } return ""; } /* Output a move from arm registers to an fpu registers. OPERANDS[0] is an fpu register. OPERANDS[1] is the first registers of an arm register pair. */ char * output_mov_double_fpu_from_arm (operands) rtx operands[]; { int arm_reg0 = REGNO (operands[1]); rtx ops[2]; if (arm_reg0 == 12) abort(); ops[0] = gen_rtx (REG, SImode, arm_reg0); ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0); arm_output_asm_insn ("stmfd\tsp!, {%0, %1}", ops); arm_output_asm_insn ("ldfd\t%0, [sp], #8", operands); return (""); } /* output_mov_double_fpu_from_arm */ /* Output a move from an fpu register to arm registers. OPERANDS[0] is the first registers of an arm register pair. OPERANDS[1] is an fpu register. */ char * output_mov_double_arm_from_fpu (operands) rtx operands[]; { int arm_reg0 = REGNO (operands[0]); rtx ops[2]; if (arm_reg0 == 12) abort(); ops[0] = gen_rtx (REG, SImode, arm_reg0); ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0); arm_output_asm_insn ("stfd\t%1, [sp, #-8]!", operands); arm_output_asm_insn ("ldmfd\tsp!, {%0, %1}", ops); return(""); } /* output_mov_double_arm_from_fpu */ /* Output a move between double words. It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM or MEM<-REG and all MEMs must be offsettable addresses. */ char * output_move_double (operands) rtx operands[]; { enum rtx_code code0 = GET_CODE (operands[0]); enum rtx_code code1 = GET_CODE (operands[1]); rtx otherops[2]; if (code0 == REG) { int reg0 = REGNO (operands[0]); otherops[0] = gen_rtx (REG, SImode, 1 + reg0); if (code1 == REG) { int reg1 = REGNO (operands[1]); if (reg1 == 12) abort(); otherops[1] = gen_rtx (REG, SImode, 1 + reg1); /* Ensure the second source is not overwritten */ if (reg0 == 1 + reg1) { arm_output_asm_insn("mov\t%0, %1", otherops); arm_output_asm_insn("mov\t%0, %1", operands); } else { arm_output_asm_insn("mov\t%0, %1", operands); arm_output_asm_insn("mov\t%0, %1", otherops); } } else if (code1 == CONST_DOUBLE) { otherops[1] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_HIGH (operands[1])); operands[1] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (operands[1])); output_mov_immediate (operands, FALSE, ""); output_mov_immediate (otherops, FALSE, ""); } else if (code1 == CONST_INT) { otherops[1] = const0_rtx; /* sign extend the intval into the high-order word */ /* Note: output_mov_immediate may clobber operands[1], so we put this out first */ if (INTVAL (operands[1]) < 0) arm_output_asm_insn ("mvn\t%0, %1", otherops); else arm_output_asm_insn ("mov\t%0, %1", otherops); output_mov_immediate (operands, FALSE, ""); } else if (code1 == MEM) { switch (GET_CODE (XEXP (operands[1], 0))) { case REG: /* Handle the simple case where address is [r, #0] more efficient. */ operands[1] = XEXP (operands[1], 0); arm_output_asm_insn ("ldmia\t%1, %M0", operands); break; case PRE_INC: operands[1] = XEXP (XEXP (operands[1], 0), 0); arm_output_asm_insn ("add\t%1, %1, #8", operands); arm_output_asm_insn ("ldmia\t%1, %M0", operands); break; case PRE_DEC: operands[1] = XEXP (XEXP (operands[1], 0), 0); arm_output_asm_insn ("sub\t%1, %1, #8", operands); arm_output_asm_insn ("ldmia\t%1, %M0", operands); break; case POST_INC: operands[1] = XEXP (XEXP (operands[1], 0), 0); arm_output_asm_insn ("ldmia\t%1!, %M0", operands); break; case POST_DEC: operands[1] = XEXP (XEXP (operands[1], 0), 0); arm_output_asm_insn ("ldmia\t%1, %M0", operands); arm_output_asm_insn ("sub\t%1, %1, #8", operands); break; default: otherops[1] = adj_offsettable_operand (operands[1], 4); /* Take care of overlapping base/data reg. */ if (reg_mentioned_p (operands[0], operands[1])) { arm_output_asm_insn ("ldr\t%0, %1", otherops); arm_output_asm_insn ("ldr\t%0, %1", operands); } else { arm_output_asm_insn ("ldr\t%0, %1", operands); arm_output_asm_insn ("ldr\t%0, %1", otherops); } } } else abort(); /* Constraints should prevent this */ } else if (code0 == MEM && code1 == REG) { if (REGNO (operands[1]) == 12) abort(); switch (GET_CODE (XEXP (operands[0], 0))) { case REG: operands[0] = XEXP (operands[0], 0); arm_output_asm_insn ("stmia\t%0, %M1", operands); break; case PRE_INC: operands[0] = XEXP (XEXP (operands[0], 0), 0); arm_output_asm_insn ("add\t%0, %0, #8", operands); arm_output_asm_insn ("stmia\t%0, %M1", operands); break; case PRE_DEC: operands[0] = XEXP (XEXP (operands[0], 0), 0); arm_output_asm_insn ("sub\t%0, %0, #8", operands); arm_output_asm_insn ("stmia\t%0, %M1", operands); break; case POST_INC: operands[0] = XEXP (XEXP (operands[0], 0), 0); arm_output_asm_insn ("stmia\t%0!, %M1", operands); break; case POST_DEC: operands[0] = XEXP (XEXP (operands[0], 0), 0); arm_output_asm_insn ("stmia\t%0, %M1", operands); arm_output_asm_insn ("sub\t%0, %0, #8", operands); break; default: otherops[0] = adj_offsettable_operand (operands[0], 4); otherops[1] = gen_rtx (REG, SImode, 1 + REGNO (operands[1])); arm_output_asm_insn ("str\t%1, %0", operands); arm_output_asm_insn ("str\t%1, %0", otherops); } } else abort(); /* Constraints should prevent this */ return(""); } /* output_move_double */ /* Output an arbitrary MOV reg, #n. OPERANDS[0] is a register. OPERANDS[1] is a const_int. */ char * output_mov_immediate (operands) rtx operands[2]; { int n = INTVAL (operands[1]); int n_ones = 0; int i; /* Try to use one MOV */ if (const_ok_for_arm (n)) return (arm_output_asm_insn ("mov\t%0, %1", operands)); /* Try to use one MVN */ if (const_ok_for_arm(~n)) { operands[1] = gen_rtx (CONST_INT, VOIDmode, ~n); return (arm_output_asm_insn ("mvn\t%0, %1", operands)); } /* If all else fails, make it out of ORRs or BICs as appropriate. */ for (i=0; i < 32; i++) if (n & 1 << i) n_ones++; if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */ output_multi_immediate(operands, "mvn\t%0, %1", "bic\t%0, %0, %1", 1, ~n); else output_multi_immediate(operands, "mov\t%0, %1", "orr\t%0, %0, %1", 1, n); return(""); } /* output_mov_immediate */ /* Output an ADD r, s, #n where n may be too big for one instruction. If adding zero to one register, output nothing. */ char * output_add_immediate (operands) rtx operands[3]; { int n = INTVAL (operands[2]); if (n != 0 || REGNO (operands[0]) != REGNO (operands[1])) { if (n < 0) output_multi_immediate (operands, "sub\t%0, %1, %2", "sub\t%0, %0, %2", 2, -n); else output_multi_immediate (operands, "add\t%0, %1, %2", "add\t%0, %0, %2", 2, n); } return(""); } /* output_add_immediate */ /* Output a multiple immediate operation. OPERANDS is the vector of operands referred to in the output patterns. INSTR1 is the output pattern to use for the first constant. INSTR2 is the output pattern to use for subsequent constants. IMMED_OP is the index of the constant slot in OPERANDS. N is the constant value. */ char * output_multi_immediate (operands, instr1, instr2, immed_op, n) rtx operands[]; char *instr1, *instr2; int immed_op, n; { if (n == 0) { operands[immed_op] = const0_rtx; arm_output_asm_insn (instr1, operands); /* Quick and easy output */ } else { int i; char *instr = instr1; /* Note that n is never zero here (which would give no output) */ for (i = 0; i < 32; i += 2) { if (n & (3 << i)) { operands[immed_op] = gen_rtx (CONST_INT, VOIDmode, n & (255 << i)); arm_output_asm_insn (instr, operands); instr = instr2; i += 6; } } } return (""); } /* output_multi_immediate */ /* Return the appropriate ARM instruction for the operation code. The returned result should not be overwritten. OP is the rtx of the operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator was shifted. */ char * arithmetic_instr (op, shift_first_arg) rtx op; { switch (GET_CODE(op)) { case PLUS: return ("add"); case MINUS: if (shift_first_arg) return ("rsb"); else return ("sub"); case IOR: return ("orr"); case XOR: return ("eor"); case AND: return ("and"); default: abort(); } return (""); /* stupid cc */ } /* arithmetic_instr */ /* Ensure valid constant shifts and return the appropriate shift mnemonic for the operation code. The returned result should not be overwritten. OP is the rtx code of the shift. SHIFT_PTR points to the shift size operand. */ char * shift_instr (op, shift_ptr) enum rtx_code op; rtx *shift_ptr; { int min_shift = 0; int max_shift = 31; char *mnem; switch (op) { case ASHIFT: mnem = "asl"; break; case LSHIFT: mnem = "lsl"; break; case ASHIFTRT: mnem = "asr"; max_shift = 32; break; case LSHIFTRT: mnem = "lsr"; max_shift = 32; break; case MULT: *shift_ptr = gen_rtx (CONST_INT, VOIDmode, int_log2 (INTVAL (*shift_ptr))); return ("asl"); default: abort(); } if (GET_CODE (*shift_ptr) == CONST_INT) { int shift = INTVAL (*shift_ptr); if (shift < min_shift) *shift_ptr = gen_rtx (CONST_INT, VOIDmode, 0); else if (shift > max_shift) *shift_ptr = gen_rtx (CONST_INT, VOIDmode, max_shift); } return (mnem); } /* shift_instr */ /* Obtain the shift from the POWER of two. */ int int_log2 (power) unsigned int power; { int shift = 0; while (((1 << shift) & power) == 0) { if (shift > 31) abort(); shift++; } return (shift); } /* int_log2 */ /* Output an arithmetic instruction which may set the condition code. OPERANDS[0] is the destination register. OPERANDS[1] is the arithmetic operator expression. OPERANDS[2] is the left hand argument. OPERANDS[3] is the right hand argument. CONST_FIRST_ARG is TRUE if the first argument of the operator was constant. SET_COND is TRUE when the condition code should be set. */ char * output_arithmetic (operands, const_first_arg, set_cond) rtx operands[4]; int const_first_arg; int set_cond; { char mnemonic[80]; char *instr = arithmetic_instr (operands[1], const_first_arg); sprintf (mnemonic, "%s%s\t%%0, %%2, %%3", instr, set_cond ? "s" : ""); return (arm_output_asm_insn (mnemonic, operands)); } /* output_arithmetic */ /* Output an arithmetic instruction with a shift. OPERANDS[0] is the destination register. OPERANDS[1] is the arithmetic operator expression. OPERANDS[2] is the unshifted register. OPERANDS[3] is the shift operator expression. OPERANDS[4] is the shifted register. OPERANDS[5] is the shift constant or register. SHIFT_FIRST_ARG is TRUE if the first argument of the operator was shifted. SET_COND is TRUE when the condition code should be set. */ char * output_arithmetic_with_shift (operands, shift_first_arg, set_cond) rtx operands[6]; int shift_first_arg; int set_cond; { char mnemonic[80]; char *instr = arithmetic_instr (operands[1], shift_first_arg); char *condbit = set_cond ? "s" : ""; char *shift = shift_instr (GET_CODE (operands[3]), &operands[5]); sprintf (mnemonic, "%s%s\t%%0, %%2, %%4, %s %%5", instr, condbit, shift); return (arm_output_asm_insn (mnemonic, operands)); } /* output_arithmetic_with_shift */ /* Output an arithmetic instruction with a power of two multiplication. OPERANDS[0] is the destination register. OPERANDS[1] is the arithmetic operator expression. OPERANDS[2] is the unmultiplied register. OPERANDS[3] is the multiplied register. OPERANDS[4] is the constant multiple (power of two). SHIFT_FIRST_ARG is TRUE if the first arg of the operator was multiplied. */ char * output_arithmetic_with_immediate_multiply (operands, shift_first_arg) rtx operands[5]; int shift_first_arg; { char mnemonic[80]; char *instr = arithmetic_instr (operands[1], shift_first_arg); int shift = int_log2 (INTVAL (operands[4])); sprintf (mnemonic, "%s\t%%0, %%2, %%3, asl#%d", instr, shift); return (arm_output_asm_insn (mnemonic, operands)); } /* output_arithmetic_with_immediate_multiply */ /* Output a move with a shift. OP is the shift rtx code. OPERANDS[0] = destination register. OPERANDS[1] = source register. OPERANDS[2] = shift constant or register. */ char * output_shifted_move (op, operands) enum rtx_code op; rtx operands[2]; { char mnemonic[80]; if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0) sprintf (mnemonic, "mov\t%%0, %%1"); else sprintf (mnemonic, "mov\t%%0, %%1, %s %%2", shift_instr (op, &operands[2])); return (arm_output_asm_insn (mnemonic, operands)); } /* output_shifted_move */ char * output_shift_compare (operands, neg) rtx *operands; int neg; { char buf[80]; if (neg) sprintf (buf, "cmn\t%%1, %%3, %s %%4", shift_instr (GET_CODE (operands[2]), &operands[4])); else sprintf (buf, "cmp\t%%1, %%3, %s %%4", shift_instr (GET_CODE (operands[2]), &operands[4])); return arm_output_asm_insn (buf, operands); } /* output_shift_compare */ /* Output a .ascii pseudo-op, keeping track of lengths. This is because /bin/as is horribly restrictive. */ void output_ascii_pseudo_op (stream, p, len) FILE *stream; unsigned char *p; int len; { int i; int len_so_far = 1000; int chars_so_far = 0; for (i = 0; i < len; i++) { register int c = p[i]; if (len_so_far > 50) { if (chars_so_far) fputs ("\"\n", stream); fputs ("\t.ascii\t\"", stream); len_so_far = 0; arm_increase_location (chars_so_far); chars_so_far = 0; } if (c == '\"' || c == '\\') { putc('\\', stream); len_so_far++; } if (c >= ' ' && c < 0177) { putc (c, stream); len_so_far++; } else { fprintf (stream, "\\%03o", c); len_so_far +=4; } chars_so_far++; } fputs ("\"\n", stream); arm_increase_location (chars_so_far); } /* output_ascii_pseudo_op */ /* Try to determine whether a pattern really clobbers the link register. This information is useful when peepholing, so that lr need not be pushed if we combine a call followed by a return. NOTE: This code does not check for side-effect expressions in a SET_SRC: such a check should not be needed because these only update an existing value within a register; the register must still be set elsewhere within the function. */ static int pattern_really_clobbers_lr (x) rtx x; { int i; switch (GET_CODE (x)) { case SET: switch (GET_CODE (SET_DEST (x))) { case REG: return REGNO (SET_DEST (x)) == 14; case SUBREG: if (GET_CODE (XEXP (SET_DEST (x), 0)) == REG) return REGNO (XEXP (SET_DEST (x), 0)) == 14; if (GET_CODE (XEXP (SET_DEST (x), 0)) == MEM) return 0; abort (); default: return 0; } case PARALLEL: for (i = 0; i < XVECLEN (x, 0); i++) if (pattern_really_clobbers_lr (XVECEXP (x, 0, i))) return 1; return 0; case CLOBBER: switch (GET_CODE (XEXP (x, 0))) { case REG: return REGNO (XEXP (x, 0)) == 14; case SUBREG: if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG) return REGNO (XEXP (XEXP (x, 0), 0)) == 14; abort (); default: return 0; } case UNSPEC: return 1; default: return 0; } } static int function_really_clobbers_lr (first) rtx first; { rtx insn, next; for (insn = first; insn; insn = next_nonnote_insn (insn)) { switch (GET_CODE (insn)) { case BARRIER: case NOTE: case CODE_LABEL: case JUMP_INSN: /* Jump insns only change the PC (and conds) */ case INLINE_HEADER: break; case INSN: if (pattern_really_clobbers_lr (PATTERN (insn))) return 1; break; case CALL_INSN: /* Don't yet know how to handle those calls that are not to a SYMBOL_REF */ if (GET_CODE (PATTERN (insn)) != PARALLEL) abort (); switch (GET_CODE (XVECEXP (PATTERN (insn), 0, 0))) { case CALL: if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn), 0, 0), 0), 0)) != SYMBOL_REF) return 1; break; case SET: if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 0), 0)) != SYMBOL_REF) return 1; break; default: /* Don't recognize it, be safe */ return 1; } /* A call can be made (by peepholing) not to clobber lr iff it is followed by a return. There may, however, be a use insn iff we are returning the result of the call. If we run off the end of the insn chain, then that means the call was at the end of the function. Unfortunately we don't have a return insn for the peephole to recognize, so we must reject this. (Can this be fixed by adding our own insn?) */ if ((next = next_nonnote_insn (insn)) == NULL) return 1; if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == USE && (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) && (REGNO (SET_DEST (XVECEXP (PATTERN (insn), 0, 0))) == REGNO (XEXP (PATTERN (next), 0)))) if ((next = next_nonnote_insn (next)) == NULL) return 1; if (GET_CODE (next) == JUMP_INSN && GET_CODE (PATTERN (next)) == RETURN) break; return 1; default: abort (); } } /* We have reached the end of the chain so lr was _not_ clobbered */ return 0; } char * output_return_instruction (operand, really_return) rtx operand; int really_return; { char instr[100]; int reg, live_regs = 0; if (current_function_calls_alloca && !really_return) abort(); for (reg = 4; reg < 10; reg++) if (regs_ever_live[reg]) live_regs++; if (live_regs || (regs_ever_live[14] && !lr_save_eliminated)) live_regs++; if (frame_pointer_needed) live_regs += 4; if (live_regs) { if (lr_save_eliminated || !regs_ever_live[14]) live_regs++; if (frame_pointer_needed) strcpy (instr, "ldm%d0ea\tfp, {"); else strcpy (instr, "ldm%d0fd\tsp!, {"); for (reg = 4; reg < 10; reg++) if (regs_ever_live[reg]) { strcat (instr, reg_names[reg]); if (--live_regs) strcat (instr, ", "); } if (frame_pointer_needed) { strcat (instr, reg_names[11]); strcat (instr, ", "); strcat (instr, reg_names[13]); strcat (instr, ", "); strcat (instr, really_return ? reg_names[15] : reg_names[14]); } else strcat (instr, really_return ? reg_names[15] : reg_names[14]); strcat (instr, (TARGET_6 || !really_return) ? "}" : "}^"); arm_output_asm_insn (instr, &operand); } else if (really_return) { strcpy (instr, TARGET_6 ? "mov%d0\tpc, lr" : "mov%d0s\tpc, lr"); arm_output_asm_insn (instr, &operand); } return_used_this_function = 1; return ""; } /* The amount of stack adjustment that happens here, in output_return and in output_epilogue must be exactly the same as was calculated during reload, or things will point to the wrong place. The only time we can safely ignore this constraint is when a function has no arguments on the stack, no stack frame requirement and no live registers execpt for `lr'. If we can guarantee that by making all function calls into tail calls and that lr is not clobbered in any other way, then there is no need to push lr onto the stack. */ void output_prologue (f, frame_size) FILE *f; int frame_size; { int reg, live_regs_mask = 0, code_size = 0; rtx operands[3]; /* Nonzero if we must stuff some register arguments onto the stack as if they were passed there. */ int store_arg_regs = 0; if (arm_ccfsm_state || arm_target_insn) abort (); /* Sanity check */ return_used_this_function = 0; lr_save_eliminated = 0; fprintf (f, "\t@ args = %d, pretend = %d, frame = %d\n", current_function_args_size, current_function_pretend_args_size, frame_size); fprintf (f, "\t@ frame_needed = %d, current_function_anonymous_args = %d\n", frame_pointer_needed, current_function_anonymous_args); if (current_function_anonymous_args && current_function_pretend_args_size) store_arg_regs = 1; for (reg = 4; reg < 10; reg++) if (regs_ever_live[reg]) live_regs_mask |= (1 << reg); if (frame_pointer_needed) { live_regs_mask |= 0xD800; fputs ("\tmov\tip, sp\n", f); code_size += 4; } else if (regs_ever_live[14]) { if (! current_function_args_size && !function_really_clobbers_lr (get_insns ())) { fprintf (f,"\t@ I don't think this function clobbers lr\n"); lr_save_eliminated = 1; } else live_regs_mask |= 0x4000; } /* If CURRENT_FUNCTION_PRETEND_ARGS_SIZE, adjust the stack pointer to make room. If also STORE_ARG_REGS store the argument registers involved in the created slot (this is for stdarg and varargs). */ if (current_function_pretend_args_size) { if (store_arg_regs) { int arg_size, mask = 0; assert (current_function_pretend_args_size <= 16); for (reg = 3, arg_size = current_function_pretend_args_size; arg_size > 0; reg--, arg_size -= 4) mask |= (1 << reg); print_multi_reg (f, "stmfd\tsp!", mask, FALSE); code_size += 4; } else { operands[0] = operands[1] = stack_pointer_rtx; operands[2] = gen_rtx (CONST_INT, VOIDmode, -current_function_pretend_args_size); output_add_immediate (operands); } } if (live_regs_mask) { /* if a di mode load/store multiple is used, and the base register is r3, then r4 can become an ever live register without lr doing so, in this case we need to push lr as well, or we will fail to get a proper return. */ live_regs_mask |= 0x4000; lr_save_eliminated = 0; print_multi_reg (f, "stmfd\tsp!", live_regs_mask, FALSE); code_size += 4; } for (reg = 23; reg > 19; reg--) if (regs_ever_live[reg]) { fprintf (f, "\tstfe\t%s, [sp, #-12]!\n", reg_names[reg]); code_size += 4; } if (frame_pointer_needed) { /* Make `fp' point to saved value of `pc'. */ operands[0] = gen_rtx (REG, SImode, HARD_FRAME_POINTER_REGNUM); operands[1] = gen_rtx (REG, SImode, 12); operands[2] = gen_rtx (CONST_INT, VOIDmode, - (4 + current_function_pretend_args_size)); output_add_immediate (operands); } if (frame_size) { operands[0] = operands[1] = stack_pointer_rtx; operands[2] = gen_rtx (CONST_INT, VOIDmode, -frame_size); output_add_immediate (operands); } arm_increase_location (code_size); } /* output_prologue */ void output_epilogue (f, frame_size) FILE *f; int frame_size; { int reg, live_regs_mask = 0, code_size = 0; /* If we need this then it will always be at lesat this much */ int floats_offset = 24; rtx operands[3]; if (use_return_insn() && return_used_this_function) { if (frame_size && !(frame_pointer_needed || TARGET_APCS)) { abort (); } return; } for (reg = 4; reg <= 10; reg++) if (regs_ever_live[reg]) { live_regs_mask |= (1 << reg); floats_offset += 4; } if (frame_pointer_needed) { for (reg = 23; reg >= 20; reg--) if (regs_ever_live[reg]) { fprintf (f, "\tldfe\t%s, [fp, #-%d]\n", reg_names[reg], floats_offset); floats_offset += 12; code_size += 4; } live_regs_mask |= 0xA800; print_multi_reg (f, "ldmea\tfp", live_regs_mask, TARGET_6 ? FALSE : TRUE); code_size += 4; } else { /* Restore stack pointer if necessary. */ if (frame_size) { operands[0] = operands[1] = stack_pointer_rtx; operands[2] = gen_rtx (CONST_INT, VOIDmode, frame_size); output_add_immediate (operands); } for (reg = 20; reg < 24; reg++) if (regs_ever_live[reg]) { fprintf (f, "\tldfe\t%s, [sp], #12\n", reg_names[reg]); code_size += 4; } if (current_function_pretend_args_size == 0 && regs_ever_live[14]) { print_multi_reg (f, "ldmfd\tsp!", live_regs_mask | 0x8000, TARGET_6 ? FALSE : TRUE); code_size += 4; } else { if (live_regs_mask || regs_ever_live[14]) { live_regs_mask |= 0x4000; print_multi_reg (f, "ldmfd\tsp!", live_regs_mask, FALSE); code_size += 4; } if (current_function_pretend_args_size) { operands[0] = operands[1] = stack_pointer_rtx; operands[2] = gen_rtx (CONST_INT, VOIDmode, current_function_pretend_args_size); output_add_immediate (operands); } fputs (TARGET_6 ? "\tmov\tpc, lr\n" : "\tmovs\tpc, lr\n", f); code_size += 4; } } arm_increase_location (code_size); current_function_anonymous_args = 0; } /* output_epilogue */ /* Increase the `arm_text_location' by AMOUNT if we're in the text segment. */ void arm_increase_location (amount) int amount; { if (in_text_section ()) arm_text_location += amount; } /* arm_increase_location */ /* Like output_asm_insn (), but also increases the arm_text_location (if in the .text segment, of course, even though this will always be true). Returns the empty string. */ char * arm_output_asm_insn (template, operands) char *template; rtx *operands; { extern FILE *asm_out_file; output_asm_insn (template, operands); if (in_text_section ()) arm_text_location += 4; fflush (asm_out_file); return (""); } /* arm_output_asm_insn */ /* Output a label definition. If this label is within the .text segment, it is stored in OFFSET_TABLE, to be used when building `llc' instructions. Maybe GCC remembers names not starting with a `*' for a long time, but this is a minority anyway, so we just make a copy. Do not store the leading `*' if the name starts with one. */ void arm_asm_output_label (stream, name) FILE *stream; char *name; { char *real_name, *s; struct label_offset *cur; int hash = 0; assemble_name (stream, name); fputs (":\n", stream); if (! in_text_section ()) return; if (name[0] == '*') { real_name = xmalloc (1 + strlen (&name[1])); strcpy (real_name, &name[1]); } else { real_name = xmalloc (2 + strlen (name)); strcpy (real_name, "_"); strcat (real_name, name); } for (s = real_name; *s; s++) hash += *s; hash = hash % LABEL_HASH_SIZE; cur = (struct label_offset *) xmalloc (sizeof (struct label_offset)); cur->name = real_name; cur->offset = arm_text_location; cur->cdr = offset_table[hash]; offset_table[hash] = cur; } /* arm_asm_output_label */ /* Output the instructions needed to perform what Martin's /bin/as called llc: load an SImode thing from the function's constant pool. XXX This could be enhanced in that we do not really need a pointer in the constant pool pointing to the real thing. If we can address this pointer, we can also address what it is pointing at, in fact, anything in the text segment which has been defined already within this .s file. */ char * arm_output_llc (operands) rtx *operands; { char *s, *name = XSTR (XEXP (operands[1], 0), 0); struct label_offset *he; int hash = 0, conditional = (arm_ccfsm_state == 3 || arm_ccfsm_state == 4); if (*name != '*') abort (); for (s = &name[1]; *s; s++) hash += *s; hash = hash % LABEL_HASH_SIZE; he = offset_table[hash]; while (he && strcmp (he->name, &name[1])) he = he->cdr; if (!he) abort (); if (arm_text_location + 8 - he->offset < 4095) { fprintf (asm_out_file, "\tldr%s\t%s, [pc, #%s - . - 8]\n", conditional ? arm_condition_codes[arm_current_cc] : "", reg_names[REGNO (operands[0])], &name[1]); arm_increase_location (4); return (""); } else { int offset = - (arm_text_location + 8 - he->offset); char *reg_name = reg_names[REGNO (operands[0])]; /* ??? This is a hack, assuming the constant pool never is more than (1 + 255) * 4096 == 1Meg away from the PC. */ if (offset > 1000000) abort (); fprintf (asm_out_file, "\tsub%s\t%s, pc, #(8 + . - %s) & ~4095\n", conditional ? arm_condition_codes[arm_current_cc] : "", reg_name, &name[1]); fprintf (asm_out_file, "\tldr%s\t%s, [%s, #- ((4 + . - %s) & 4095)]\n", conditional ? arm_condition_codes[arm_current_cc] : "", reg_name, reg_name, &name[1]); arm_increase_location (8); } return (""); } /* arm_output_llc */ /* output_load_symbol () load a symbol that is known to be in the text segment into a register */ char * output_load_symbol (operands) rtx *operands; { char *s, *name = XSTR (operands[1], 0); struct label_offset *he; int hash = 0; int offset; if (*name != '*') abort (); for (s = &name[1]; *s; s++) hash += *s; hash = hash % LABEL_HASH_SIZE; he = offset_table[hash]; while (he && strcmp (he->name, &name[1])) he = he->cdr; if (!he) abort (); offset = (arm_text_location + 8 - he->offset); if (offset < 0) abort (); /* If the symbol is word aligned then we might be able to reduce the number of loads */ if ((offset & 3) == 0) { arm_output_asm_insn ("sub\t%0, pc, #(8 + . -%a1) & 1023", operands); if (offset > 0x3ff) { arm_output_asm_insn ("sub\t%0, %0, #(4 + . -%a1) & 261120", operands); if (offset > 0x3ffff) { arm_output_asm_insn ("sub\t%0, %0, #(. -%a1) & 66846720", operands); if (offset > 0x3ffffff) arm_output_asm_insn ("sub\t%0, %0, #(. - 4 -%a1) & -67108864", operands); } } } else { arm_output_asm_insn ("sub\t%0, pc, #(8 + . -%a1) & 255", operands); if (offset > 0x0ff) { arm_output_asm_insn ("sub\t%0, %0, #(4 + . -%a1) & 65280", operands); if (offset > 0x0ffff) { arm_output_asm_insn ("sub\t%0, %0, #(. -%a1) & 16711680", operands); if (offset > 0x0ffffff) arm_output_asm_insn ("sub\t%0, %0, #(. - 4 -%a1) & -16777216", operands); } } } return ""; } /* Output code resembling an .lcomm directive. /bin/as doesn't have this directive hence this hack, which works by reserving some `.space' in the bss segment directly. XXX This is a severe hack, which is guaranteed NOT to work since it doesn't define STATIC COMMON space but merely STATIC BSS space. */ void output_lcomm_directive (stream, name, size, rounded) FILE *stream; char *name; int size, rounded; { fputs ("\n\t.bss\t@ .lcomm\n", stream); assemble_name (stream, name); fprintf (stream, ":\t.space\t%d\n", rounded); if (in_text_section ()) fputs ("\n\t.text\n", stream); else fputs ("\n\t.data\n", stream); } /* output_lcomm_directive */ /* A finite state machine takes care of noticing whether or not instructions can be conditionally executed, and thus decrease execution time and code size by deleting branch instructions. The fsm is controlled by final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */ /* The state of the fsm controlling condition codes are: 0: normal, do nothing special 1: make ASM_OUTPUT_OPCODE not output this instruction 2: make ASM_OUTPUT_OPCODE not output this instruction 3: make instructions conditional 4: make instructions conditional State transitions (state->state by whom under condition): 0 -> 1 final_prescan_insn if the `target' is a label 0 -> 2 final_prescan_insn if the `target' is an unconditional branch 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached (the target label has CODE_LABEL_NUMBER equal to arm_target_label). 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached (the target insn is arm_target_insn). If the jump clobbers the conditions then we use states 2 and 4. A similar thing can be done with conditional return insns. XXX In case the `target' is an unconditional branch, this conditionalising of the instructions always reduces code size, but not always execution time. But then, I want to reduce the code size to somewhere near what /bin/cc produces. */ /* The condition codes of the ARM, and the inverse function. */ char *arm_condition_codes[] = { "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" }; #define ARM_INVERSE_CONDITION_CODE(X) ((X) ^ 1) /* Returns the index of the ARM condition code string in `arm_condition_codes'. COMPARISON should be an rtx like `(eq (...) (...))'. */ int get_arm_condition_code (comparison) rtx comparison; { switch (GET_CODE (comparison)) { case NE: return (1); case EQ: return (0); case GE: return (10); case GT: return (12); case LE: return (13); case LT: return (11); case GEU: return (2); case GTU: return (8); case LEU: return (9); case LTU: return (3); default: abort (); } /*NOTREACHED*/ return (42); } /* get_arm_condition_code */ void final_prescan_insn (insn, opvec, noperands) rtx insn; rtx *opvec; int noperands; { /* BODY will hold the body of INSN. */ register rtx body = PATTERN (insn); /* This will be 1 if trying to repeat the trick, and things need to be reversed if it appears to fail. */ int reverse = 0; /* JUMP_CLOBBERS will be one implies that the conditions if a branch is taken are clobbered, even if the rtl suggests otherwise. It also means that we have to grub around within the jump expression to find out what the conditions are when the jump isn't taken. */ int jump_clobbers = 0; /* If we start with a return insn, we only succeed if we find another one. */ int seeking_return = 0; /* START_INSN will hold the insn from where we start looking. This is the first insn after the following code_label if REVERSE is true. */ rtx start_insn = insn; /* If in state 4, check if the target branch is reached, in order to change back to state 0. */ if (arm_ccfsm_state == 4) { if (insn == arm_target_insn) { arm_target_insn = NULL; arm_ccfsm_state = 0; } return; } /* If in state 3, it is possible to repeat the trick, if this insn is an unconditional branch to a label, and immediately following this branch is the previous target label which is only used once, and the label this branch jumps to is not too far off. */ if (arm_ccfsm_state == 3) { if (simplejump_p (insn)) { start_insn = next_nonnote_insn (start_insn); if (GET_CODE (start_insn) == BARRIER) { /* XXX Isn't this always a barrier? */ start_insn = next_nonnote_insn (start_insn); } if (GET_CODE (start_insn) == CODE_LABEL && CODE_LABEL_NUMBER (start_insn) == arm_target_label && LABEL_NUSES (start_insn) == 1) reverse = TRUE; else return; } else if (GET_CODE (body) == RETURN) { start_insn = next_nonnote_insn (start_insn); if (GET_CODE (start_insn) == BARRIER) start_insn = next_nonnote_insn (start_insn); if (GET_CODE (start_insn) == CODE_LABEL && CODE_LABEL_NUMBER (start_insn) == arm_target_label && LABEL_NUSES (start_insn) == 1) { reverse = TRUE; seeking_return = 1; } else return; } else return; } if (arm_ccfsm_state != 0 && !reverse) abort (); if (GET_CODE (insn) != JUMP_INSN) return; /* This jump might be paralled with a clobber of the condition codes the jump should always come first */ if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) body = XVECEXP (body, 0, 0); #if 0 /* If this is a conditional return then we don't want to know */ if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)) return; #endif if (reverse || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)) { int insns_skipped = 0, fail = FALSE, succeed = FALSE; /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */ int then_not_else = TRUE; rtx this_insn = start_insn, label = 0; if (get_attr_conds (insn) == CONDS_JUMP_CLOB) jump_clobbers = 1; /* Register the insn jumped to. */ if (reverse) { if (!seeking_return) label = XEXP (SET_SRC (body), 0); } else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF) label = XEXP (XEXP (SET_SRC (body), 1), 0); else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF) { label = XEXP (XEXP (SET_SRC (body), 2), 0); then_not_else = FALSE; } else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) seeking_return = 1; else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) { seeking_return = 1; then_not_else = FALSE; } else abort (); /* See how many insns this branch skips, and what kind of insns. If all insns are okay, and the label or unconditional branch to the same label is not too far away, succeed. */ for (insns_skipped = 0; !fail && !succeed && insns_skipped < MAX_INSNS_SKIPPED; insns_skipped++) { rtx scanbody; this_insn = next_nonnote_insn (this_insn); if (!this_insn) break; scanbody = PATTERN (this_insn); switch (GET_CODE (this_insn)) { case CODE_LABEL: /* Succeed if it is the target label, otherwise fail since control falls in from somewhere else. */ if (this_insn == label) { if (jump_clobbers) { arm_ccfsm_state = 2; this_insn = next_nonnote_insn (this_insn); } else arm_ccfsm_state = 1; succeed = TRUE; } else fail = TRUE; break; case BARRIER: /* Succeed if the following insn is the target label. Otherwise fail. If return insns are used then the last insn in a function will be a barrier. */ this_insn = next_nonnote_insn (this_insn); if (this_insn && this_insn == label) { if (jump_clobbers) { arm_ccfsm_state = 2; this_insn = next_nonnote_insn (this_insn); } else arm_ccfsm_state = 1; succeed = TRUE; } else fail = TRUE; break; case CALL_INSN: /* The arm 6xx uses full 32 bit addresses so the cc is not preserved over calls */ if (TARGET_6) fail = TRUE; break; case JUMP_INSN: /* If this is an unconditional branch to the same label, succeed. If it is to another label, do nothing. If it is conditional, fail. */ /* XXX Probably, the test for the SET and the PC are unnecessary. */ if (GET_CODE (scanbody) == SET && GET_CODE (SET_DEST (scanbody)) == PC) { if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF && XEXP (SET_SRC (scanbody), 0) == label && !reverse) { arm_ccfsm_state = 2; succeed = TRUE; } else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) fail = TRUE; } else if (GET_CODE (scanbody) == RETURN && seeking_return) { arm_ccfsm_state = 2; succeed = TRUE; } else if (GET_CODE (scanbody) == PARALLEL) { switch (get_attr_conds (this_insn)) { case CONDS_NOCOND: break; default: fail = TRUE; break; } } break; case INSN: /* Instructions using or affecting the condition codes make it fail. */ if ((GET_CODE (scanbody) == SET || GET_CODE (scanbody) == PARALLEL) && get_attr_conds (this_insn) != CONDS_NOCOND) fail = TRUE; break; default: break; } } if (succeed) { if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse)) arm_target_label = CODE_LABEL_NUMBER (label); else if (seeking_return || arm_ccfsm_state == 2) { while (this_insn && GET_CODE (PATTERN (this_insn)) == USE) { this_insn = next_nonnote_insn (this_insn); if (this_insn && (GET_CODE (this_insn) == BARRIER || GET_CODE (this_insn) == CODE_LABEL)) abort (); } if (!this_insn) { /* Oh, dear! we ran off the end.. give up */ recog (PATTERN (insn), insn, NULL_PTR); arm_ccfsm_state = 0; arm_target_insn = NULL; return; } arm_target_insn = this_insn; } else abort (); if (jump_clobbers) { if (reverse) abort (); arm_current_cc = get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body), 0), 0), 1)); if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND) arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE) arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); } else { /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from what it was. */ if (!reverse) arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), 0)); } if (reverse || then_not_else) arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); } /* restore recog_operand (getting the attributes of other insns can destroy this array, but final.c assumes that it remains intact accross this call; since the insn has been recognized already we call recog direct). */ recog (PATTERN (insn), insn, NULL_PTR); } } /* final_prescan_insn */ /* EOF */ gcc-2.5.8/config/arm/arm.h100444 22011 13 211614 5500623634 14007 0ustar kenneruser/* Definitions of target machine for GNU compiler, for Acorn RISC Machine. Copyright (C) 1991, 1993 Free Software Foundation, Inc. Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Sometimes the directive `riscos' is checked. This does not imply that this tm file can be used unchanged to build a GCC for RISC OS. (Since in fact, it can't.) */ extern void output_prologue (); extern void output_epilogue (); extern char *arm_output_asm_insn (); extern char *arm_output_llc (); extern char *arithmetic_instr (); extern char *output_add_immediate (); extern char *output_call (); extern char *output_call_mem (); extern char *output_move_double (); extern char *output_mov_double_fpu_from_arm (); extern char *output_mov_double_arm_from_fpu (); extern char *output_mov_long_double_fpu_from_arm (); extern char *output_mov_long_double_arm_from_fpu (); extern char *output_mov_long_double_arm_from_arm (); extern char *output_mov_immediate (); extern char *output_multi_immediate (); extern char *output_shifted_move (); extern char *output_shift_compare (); extern char *output_arithmetic_with_immediate_multiply (); extern char *output_arithmetic_with_shift (); extern char *output_return_instruction (); extern char *output_load_symbol (); extern char *fp_immediate_constant (); extern char *shift_instr (); extern struct rtx_def *gen_compare_reg (); extern struct rtx_def *arm_gen_store_multiple (); extern struct rtx_def *arm_gen_load_multiple (); extern char *arm_condition_codes[]; /* This is needed by the tail-calling peepholes */ extern int frame_pointer_needed; #ifndef CPP_PREDEFINES #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)" #endif #ifndef CPP_SPEC #define CPP_SPEC "%{m6:-D__arm6__}" #endif /* Run-time Target Specification. */ #ifndef TARGET_VERSION #define TARGET_VERSION \ fputs (" (ARM/generic)", stderr); #endif /* Run-time compilation parameters selecting different hardware subsets. On the ARM, misuse it in a different way. */ extern int target_flags; /* Nonzero if the function prologue (and epilogue) should obey the ARM Procedure Call Standard. */ #define TARGET_APCS (target_flags & 1) /* Nonzero if the function prologue should output the function name to enable the post mortem debugger to print a backtrace (very useful on RISCOS, unused on RISCiX). Specifying this flag also enables -mapcs. XXX Must still be implemented in the prologue. */ #define TARGET_POKE_FUNCTION_NAME (target_flags & 2) /* Nonzero if floating point instructions are emulated by the FPE, in which case instruction scheduling becomes very uninteresting. */ #define TARGET_FPE (target_flags & 4) /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration of condition flags when returning from a branch & link (ie. a function) */ #define TARGET_6 (target_flags & 8) /* ARM_EXTRA_TARGET_SWITCHES is used in riscix.h to define some options which are passed to the preprocessor and the assembler post-processor. They aren't needed in the main pass of the compiler, but if we don't define them in target switches cc1 complains about them. For the sake of argument lets allocate bit 31 of target flags for such options. */ #ifndef ARM_EXTRA_TARGET_SWITCHES #define ARM_EXTRA_TARGET_SWITCHES #endif #define TARGET_SWITCHES \ { \ {"apcs", 1}, \ {"poke-function-name", 2}, \ {"fpe", 4}, \ {"6", 8}, \ {"2", -8}, \ {"3", -8}, \ ARM_EXTRA_TARGET_SWITCHES \ {"", TARGET_DEFAULT } \ } /* Which processor we are running on. Currently this is only used to get the condition code clobbering attribute right when we are running on an arm 6 */ enum processor_type { PROCESSOR_ARM2, PROCESSOR_ARM3, PROCESSOR_ARM6 }; /* Recast the cpu class to be the cpu attribute. */ /* Recast the cpu class to be the cpu attribute. */ #define arm_cpu_attr ((enum attr_cpu)arm_cpu) extern enum processor_type arm_cpu; #define TARGET_DEFAULT 0 #define TARGET_MEM_FUNCTIONS 1 /* OVERRIDE_OPTIONS takes care of the following: - if -mpoke-function-name, then -mapcs. - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name. - if floating point is done by emulation, forget about instruction scheduling. Note that this only saves compilation time; it doesn't matter for the final code. */ #ifndef TARGET_WHEN_DEBUGGING #define TARGET_WHEN_DEBUGGING 1 #endif #define OVERRIDE_OPTIONS \ { \ if (write_symbols != NO_DEBUG && flag_omit_frame_pointer) \ warning ("-g without a frame pointer may not give sensible debugging");\ if (TARGET_POKE_FUNCTION_NAME) \ target_flags |= 1; \ if (TARGET_FPE) \ flag_schedule_insns = flag_schedule_insns_after_reload = 0; \ arm_cpu = TARGET_6 ? PROCESSOR_ARM6: PROCESSOR_ARM2; \ } /* Omitting the frame pointer is a very good idea on the ARM, especially if not TARGET_APCS, in which case all that pushing on function entry isn't mandatory anymore. Unfortunately this is not permitted since we mustn't change the flags when -g is enabled and without a frame pointer debugging using dbx is impossible. Forcing loads to be explicit allows cse to work better */ #define OPTIMIZATION_OPTIONS(OPTIMIZE) \ { \ if (OPTIMIZE) \ flag_force_mem = 1; \ } /* Target machine storage Layout. */ /* Define this macro if it is advisable to hold scalars in registers in a wider mode than that declared by the program. In such cases, the value is constrained to be within the bounds of the declared type, but kept valid in the wider mode. The signedness of the extension may differ from that of the type. */ /* It is far faster to zero extend chars than to sign extend them */ #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ if (GET_MODE_CLASS (MODE) == MODE_INT \ && GET_MODE_SIZE (MODE) < 4) \ { \ if (MODE == QImode) \ UNSIGNEDP = 1; \ (MODE) = SImode; \ } /* Define for XFmode extended real floating point support. This will automatically cause REAL_ARITHMETIC to be defined. */ /* For the ARM: I think I have added all the code to make this work. Unfortunately, early releases of the floating point emulation code on RISCiX used a different format for extended precision numbers. On my RISCiX box there is a bug somewhere which causes the machine to lock up when running enquire with long doubles. There is the additional aspect that Norcroft C treats long doubles as doubles and we ought to remain compatible. Perhaps someone with an FPA coprocessor and not running RISCiX would like to try this someday. */ /* #define LONG_DOUBLE_TYPE_SIZE 96 */ /* Disable XFmode patterns in md file */ #define ENABLE_XF_PATTERNS 0 /* Define if you don't want extended real, but do want to use the software floating point emulator for REAL_ARITHMETIC and decimal <-> binary conversion. */ /* See comment above */ #define REAL_ARITHMETIC /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. */ #define BITS_BIG_ENDIAN 0 /* Define this if most significant byte of a word is the lowest numbered. */ #define BYTES_BIG_ENDIAN 0 /* Define this if most significant word of a multiword number is the lowest numbered. */ #define WORDS_BIG_ENDIAN 0 /* Define this if most significant word of doubles is the lowest numbered */ #define FLOAT_WORDS_BIG_ENDIAN 1 /* Number of bits in an addressable storage unit */ #define BITS_PER_UNIT 8 #define BITS_PER_WORD 32 #define UNITS_PER_WORD 4 #define POINTER_SIZE 32 #define PARM_BOUNDARY 32 #define STACK_BOUNDARY 32 #define FUNCTION_BOUNDARY 32 #define EMPTY_FIELD_BOUNDARY 32 #define BIGGEST_ALIGNMENT 32 /* Make strings word-aligned so strcpy from constants will be faster. */ #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ (TREE_CODE (EXP) == STRING_CST \ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) /* Every structures size must be a multiple of 32 bits. */ #define STRUCTURE_SIZE_BOUNDARY 32 /* Non-zero if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 1 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT /* Define number of bits in most basic integer type. (If undefined, default is BITS_PER_WORD). */ /* #define INT_TYPE_SIZE */ /* Standard register usage. */ /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): (S - saved over call). r0 * argument word/integer result r1-r3 argument word r4-r8 S register variable r9 S (rfp) register variable (real frame pointer) r10 F S (sl) stack limit (not currently used) r11 F S (fp) argument pointer r12 (ip) temp workspace r13 F S (sp) lower end of current stack frame r14 (lr) link address/workspace r15 F (pc) program counter f0 floating point result f1-f3 floating point scratch f4-f7 S floating point variable cc This is NOT a real register, but is used internally to represent things that use or set the condition codes. sfp This isn't either. It is used during rtl generation since the offset between the frame pointer and the auto's isn't known until after register allocation. afp Nor this, we only need this because of non-local goto. Without it fp appears to be used and the elimination code won't get rid of sfp. It tracks fp exactly at all times. *: See CONDITIONAL_REGISTER_USAGE */ /* The stack backtrace structure is as follows: fp points to here: | save code pointer | [fp] | return link value | [fp, #-4] | return sp value | [fp, #-8] | return fp value | [fp, #-12] [| saved r10 value |] [| saved r9 value |] [| saved r8 value |] [| saved r7 value |] [| saved r6 value |] [| saved r5 value |] [| saved r4 value |] [| saved r3 value |] [| saved r2 value |] [| saved r1 value |] [| saved r0 value |] [| saved f7 value |] three words [| saved f6 value |] three words [| saved f5 value |] three words [| saved f4 value |] three words r0-r3 are not normally saved in a C function. */ /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */ #define FIRST_PSEUDO_REGISTER 27 /* 1 for registers that have pervasive standard uses and are not available for the register allocator. */ #define FIXED_REGISTERS \ { \ 0,0,0,0,0,0,0,0, \ 0,0,1,1,0,1,0,1, \ 0,0,0,0,0,0,0,0, \ 1,1,1 \ } /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. The CC is not preserved over function calls on the ARM 6, so it is easier to assume this for all. SFP is preserved, since FP is. */ #define CALL_USED_REGISTERS \ { \ 1,1,1,1,0,0,0,0, \ 0,0,1,1,1,1,1,1, \ 1,1,1,1,0,0,0,0, \ 1,1,1 \ } /* If doing stupid life analysis, avoid a bug causing a return value r0 to be trampled. This effectively reduces the number of available registers by 1. XXX It is a hack, I know. XXX Is this still needed? */ #define CONDITIONAL_REGISTER_USAGE \ { \ if (obey_regdecls) \ fixed_regs[0] = 1; \ } /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP mode. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \ && (REGNO) != ARG_POINTER_REGNUM) ? 1 \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. This is TRUE for ARM regs since they can hold anything, and TRUE for FPU regs holding FP. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \ ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \ || REGNO == ARG_POINTER_REGNUM \ || GET_MODE_CLASS (MODE) == MODE_FLOAT)) /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. */ #define MODES_TIEABLE_P(MODE1, MODE2) \ (((MODE1) == SFmode || (MODE1) == DFmode) \ == ((MODE2) == SFmode || (MODE2) == DFmode)) /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ /* Define this if the program counter is overloaded on a register. */ #define PC_REGNUM 15 /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM 13 /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM 25 /* Define this to be where the real frame pointer is if it is not possible to work out the offset between the frame pointer and the automatic variables until after register allocation has taken place. FRAME_POINTER_REGNUM should point to a special register that we will make sure is eliminated. */ #define HARD_FRAME_POINTER_REGNUM 11 /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. If we have to have a frame pointer we might as well make use of it. APCS says that the frame pointer does not need to be pushed in leaf functions. */ #define FRAME_POINTER_REQUIRED (TARGET_APCS && !leaf_function_p ()) /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM 26 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain as an invisible last argument (possible since varargs don't exist in Pascal), so the following is not true. */ #define STATIC_CHAIN_REGNUM 8 /* Register in which address to store a structure value is passed to a function. */ #define STRUCT_VALUE_REGNUM 0 /* Internal, so that we don't need to refer to a raw number */ #define CC_REGNUM 24 /* The order in which register should be allocated. It is good to use ip since no saving is required (though calls clobber it) and it never contains function parameters. It is quite good to use lr since other calls may clobber it anyway. Allocate r0 through r3 in reverse order since r3 is least likely to contain a function parameter; in addition results are returned in r0. */ #define REG_ALLOC_ORDER \ { \ 3, 2, 1, 0, 12, 14, 4, 5, \ 6, 7, 8, 10, 9, 11, 13, 15, \ 16, 17, 18, 19, 20, 21, 22, 23, \ 24, 25 \ } /* Register and constant classes. */ /* Register classes: all ARM regs or all FPU regs---simple! */ enum reg_class { NO_REGS, FPU_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ { \ "NO_REGS", \ "FPU_REGS", \ "GENERAL_REGS", \ "ALL_REGS", \ } /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS \ { \ 0x0000000, /* NO_REGS */ \ 0x0FF0000, /* FPU_REGS */ \ 0x200FFFF, /* GENERAL_REGS */ \ 0x2FFFFFF /* ALL_REGS */ \ } /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ #define REGNO_REG_CLASS(REGNO) \ (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \ || REGNO == ARG_POINTER_REGNUM) \ ? GENERAL_REGS : (REGNO) == CC_REGNUM \ ? NO_REGS : FPU_REGS) /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS GENERAL_REGS #define BASE_REG_CLASS GENERAL_REGS /* Get reg_class from a letter such as appears in the machine description. We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */ #define REG_CLASS_FROM_LETTER(C) \ ((C)=='f' ? FPU_REGS : NO_REGS) /* The letters I, J, K, L and M in a register constraint string can be used to stand for particular ranges of immediate operands. This macro defines what the ranges are. C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. I: immediate arithmetic operand (i.e. 8 bits shifted as required). J: valid indexing constants. K: as I but also (not (value)) ok. L: as I but also (neg (value)) ok.*/ #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? const_ok_for_arm (VALUE) : \ (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \ (C) == 'K' ? (const_ok_for_arm (VALUE) || const_ok_for_arm (~(VALUE))) : \ (C) == 'L' ? (const_ok_for_arm (VALUE) || const_ok_for_arm (-(VALUE))) : 0) /* For the ARM, `Q' means that this is a memory operand that is just an offset from a register. `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL address. This means that the symbol is in the text segment and can be accessed without using a load. */ #define EXTRA_CONSTRAINT(OP, C) \ ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ : (C) == 'S' ? CONSTANT_ADDRESS_P (OP) : 0) /* Constant letter 'G' for the FPU immediate constants. 'H' means the same constant negated. */ #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \ ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \ : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0) /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. */ #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) /* Return the register class of a scratch register needed to copy IN into or out of a register in CLASS in MODE. If it can be done directly, NO_REGS is returned. */ #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ (((MODE) == DFmode && (CLASS) == GENERAL_REGS \ && true_regnum (X) == -1) ? GENERAL_REGS \ : ((MODE) == HImode && true_regnum (X) == -1) ? GENERAL_REGS : NO_REGS) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */ #define CLASS_MAX_NREGS(CLASS, MODE) \ ((CLASS) == FPU_REGS ? 1 \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */ #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \ || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \ ? 20 : 2) /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack makes the stack pointer a smaller address. */ #define STACK_GROWS_DOWNWARD 1 /* Define this if the nominal address of the stack frame is at the high-address end of the local variables; that is, each additional local variable allocated goes at a more negative offset in the frame. */ #define FRAME_GROWS_DOWNWARD 1 /* Offset within stack frame to start allocating local variables at. If FRAME_GROWS_DOWNWARD, this is the offset to the END of the first local allocated. Otherwise, it is the offset to the BEGINNING of the first local allocated. */ #define STARTING_FRAME_OFFSET 0 /* If we generate an insn to push BYTES bytes, this says how many the stack pointer really advances by. */ #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) /* Offset of first parameter from the argument pointer register value. */ #define FIRST_PARM_OFFSET(FNDECL) 4 /* Value is the number of byte of arguments automatically popped when returning from a subroutine call. FUNTYPE is the data type of the function (as a tree), or for a library call it is an identifier node for the subroutine name. SIZE is the number of bytes of arguments passed on the stack. On the ARM, the caller does not pop any of its arguments that were passed on the stack. */ #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0 /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \ ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \ : gen_rtx (REG, TYPE_MODE (VALTYPE), 0)) /* Define how to find the value returned by a library function assuming the value has mode MODE. */ #define LIBCALL_VALUE(MODE) \ (GET_MODE_CLASS (MODE) == MODE_FLOAT \ ? gen_rtx (REG, MODE, 16) \ : gen_rtx (REG, MODE, 0)) /* 1 if N is a possible register number for a function value. On the ARM, only r0 and f0 can return results. */ #define FUNCTION_VALUE_REGNO_P(REGNO) \ ((REGNO) == 0 || (REGNO) == 16) /* Define where to put the arguments to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. MODE is the argument's machine mode. TYPE is the data type of the argument (as a tree). This is null for libcalls where that information may not be available. CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called. NAMED is nonzero if this argument is a named parameter (otherwise it is an extra parameter matching an ellipsis). On the ARM, normally the first 16 bytes are passed in registers r0-r3; all other arguments are passed on the stack. If (NAMED == 0) (which happens only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is passed in the stack (function_prologue will indeed make it pass in the stack if necessary). */ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ ((NAMED) \ ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \ : 0) /* For an arg passed partly in registers and partly in memory, this is the number of registers used. For args passed entirely in registers or entirely in memory, zero. */ #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \ ? GET_MODE_SIZE (MODE) \ : int_size_in_bytes (TYPE)) \ ? 4 - (CUM) / 4 : 0) /* A C type for declaring a variable that is used as the first argument of `FUNCTION_ARG' and other related values. For some target machines, the type `int' suffices and can hold the number of bytes of argument so far. On the ARM, this is the number of bytes of arguments scanned so far. */ #define CUMULATIVE_ARGS int /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. On the ARM, the offset starts at 0. */ #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \ ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0)) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ (CUM) += ((MODE) != BLKmode \ ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ : (int_size_in_bytes (TYPE) + 3) & ~3) \ /* 1 if N is a possible register number for function argument passing. On the ARM, r0-r3 are used to pass args. */ #define FUNCTION_ARG_REGNO_P(REGNO) \ ((REGNO) >= 0 && (REGNO) <= 3) /* Perform any actions needed for a function that is receiving a variable number of arguments. CUM is as above. MODE and TYPE are the mode and type of the current parameter. PRETEND_SIZE is a variable that should be set to the amount of stack that must be pushed by the prolog to pretend that our caller pushed it. Normally, this macro will push all remaining incoming registers on the stack and set PRETEND_SIZE to the length of the registers pushed. On the ARM, PRETEND_SIZE is set in order to have the prologue push the last named arg and all anonymous args onto the stack. XXX I know the prologue shouldn't be pushing registers, but it is faster that way. */ #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ { \ extern int current_function_anonymous_args; \ current_function_anonymous_args = 1; \ if ((CUM) < 16) \ (PRETEND_SIZE) = 16 - (CUM); \ } /* Generate assembly output for the start of a function. */ #define FUNCTION_PROLOGUE(STREAM, SIZE) \ output_prologue ((STREAM), (SIZE)) /* Call the function profiler with a given profile label. The Acorn compiler puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr'' seems like a good idea to stick with cc convention. ``prof'' doesn't seem to mind about this! */ #define FUNCTION_PROFILER(STREAM,LABELNO) \ { \ fprintf(STREAM, "\tmov\tip, lr\n"); \ fprintf(STREAM, "\tbl\tmcount\n"); \ fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \ arm_increase_location (12); \ } /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, the stack pointer does not matter. The value is tested only in functions that have frame pointers. No definition is equivalent to always zero. On the ARM, the function epilogue recovers the stack pointer from the frame. */ #define EXIT_IGNORE_STACK 1 /* Generate the assembly code for function exit. */ #define FUNCTION_EPILOGUE(STREAM, SIZE) \ output_epilogue ((STREAM), (SIZE)) /* Determine if the epilogue should be output as RTL. You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ #define USE_RETURN_INSN use_return_insn () /* Definitions for register eliminations. This is an array of structures. Each structure initializes one pair of eliminable registers. The "from" register number is given first, followed by "to". Eliminations of the same "from" register are listed in order of preference. We have two registers that can be eliminated on the ARM. First, the arg pointer register can often be eliminated in favor of the stack pointer register. Secondly, the pseudo frame pointer register can always be eliminated; it is replaced with either the stack or the real frame pointer. */ #define ELIMINABLE_REGS \ {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} /* Given FROM and TO register numbers, say whether this elimination is allowed. Frame pointer elimination is automatically handled. All eliminations are permissible. Note that ARG_POINTER_REGNUM and HARD_FRAME_POINTER_REGNUM are infact the same thing. If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */ #define CAN_ELIMINATE(FROM, TO) \ (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1) /* Define the offset between two registers, one to be eliminated, and the other its replacement, at the start of a routine. */ #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ { \ if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\ (OFFSET) = 0; \ else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\ (OFFSET) = (get_frame_size () + 3 & ~3); \ else \ { \ int regno; \ int offset = 12; \ \ for (regno = 4; regno <= 10; regno++) \ if (regs_ever_live[regno]) \ offset += 4; \ for (regno = 20; regno <=23; regno++) \ if (regs_ever_live[regno]) \ offset += 12; \ if ((FROM) == FRAME_POINTER_REGNUM) \ (OFFSET) = -offset; \ else \ { \ if (! regs_ever_live[HARD_FRAME_POINTER_REGNUM]) \ offset -= 16; \ if (regs_ever_live[14]) \ offset += 4; \ (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \ } \ } \ } #if 0 /* Store in the variable DEPTH the initial difference between the frame pointer reg contents and the stack pointer reg contents, as of the start of the function body. This depends on the layout of the fixed parts of the stack frame and on how registers are saved. */ #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ { \ int regno; \ int offset = 12; \ \ for (regno = 0; regno < FRAME_POINTER_REGNUM; regno++) \ if (regs_ever_live[regno]) \ offset += 4; \ for (regno = 20; regno < 24; regno++) \ if (regs_ever_live[regno]) \ offset += 12; \ (DEPTH) = offset + (get_frame_size () + 3 & ~3); \ } #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ (DEPTH) = (get_frame_size () + 3) & ~3; #endif /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. On the ARM, (if r8 is the static chain regnum, and remembering that referencing pc adds an offset of 8) the trampoline looks like: ldr r8, [pc, #0] ldr pc, [pc] .word static chain value .word function's address */ #define TRAMPOLINE_TEMPLATE(FILE) \ { \ fprintf ((FILE), "\tldr\tr8, [pc, #0]\n"); \ fprintf ((FILE), "\tldr\tpc, [pc, #0]\n"); \ fprintf ((FILE), "\t.word\t0\n"); \ fprintf ((FILE), "\t.word\t0\n"); \ } /* Length in units of the trampoline for entering a nested function. */ #define TRAMPOLINE_SIZE 16 /* Alignment required for a trampoline in units. */ #define TRAMPOLINE_ALIGN 4 /* Emit RTL insns to initialize the variable parts of a trampoline. FNADDR is an RTX for the address of the function's pure code. CXT is an RTX for the static chain value for the function. */ #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \ (CXT)); \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \ (FNADDR)); \ } /* Call the function profiler with a given profile label. The Acorn compiler puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr'' seems like a good idea to stick with cc convention. ``prof'' doesn't seem to mind about this! */ #define FUNCTION_PROFILER(STREAM,LABELNO) \ { \ fprintf(STREAM, "\tmov\tip, lr\n"); \ fprintf(STREAM, "\tbl\tmcount\n"); \ fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \ arm_increase_location (12); \ } /* Addressing modes, and classification of registers for them. */ #define HAVE_POST_INCREMENT 1 #define HAVE_PRE_INCREMENT 1 #define HAVE_POST_DECREMENT 1 #define HAVE_PRE_DECREMENT 1 /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. On the ARM, don't allow the pc to be used. */ #define REGNO_OK_FOR_BASE_P(REGNO) \ ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \ || (REGNO) == ARG_POINTER_REGNUM \ || (unsigned) reg_renumber[(REGNO)] < 15 \ || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \ || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM) #define REGNO_OK_FOR_INDEX_P(REGNO) \ REGNO_OK_FOR_BASE_P(REGNO) /* Maximum number of registers that can appear in a valid memory address. Shifts in addresses can't be by a register. */ #define MAX_REGS_PER_ADDRESS 2 /* Recognize any constant value that is a valid address. */ /* XXX We can address any constant, eventually... */ #if 0 #define CONSTANT_ADDRESS_P(X) \ ( GET_CODE(X) == LABEL_REF \ || GET_CODE(X) == SYMBOL_REF \ || GET_CODE(X) == CONST_INT \ || GET_CODE(X) == CONST ) #endif #define CONSTANT_ADDRESS_P(X) \ (GET_CODE (X) == SYMBOL_REF \ && (CONSTANT_POOL_ADDRESS_P (X) || SYMBOL_REF_FLAG (X))) /* Nonzero if the constant value X is a legitimate general operand. It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. On the ARM, allow any integer (invalid ones are removed later by insn patterns), nice doubles and symbol_refs which refer to the function's constant pool XXX. */ #define LEGITIMATE_CONSTANT_P(X) \ (GET_CODE (X) == CONST_INT \ || (GET_CODE (X) == CONST_DOUBLE \ && (const_double_rtx_ok_for_fpu (X) \ || neg_const_double_rtx_ok_for_fpu (X))) \ || CONSTANT_ADDRESS_P (X)) /* Symbols in the text segment can be accessed without indirecting via the constant pool; it may take an extra binary operation, but this is still faster than indirecting via memory. */ #define ENCODE_SECTION_INFO(decl) \ { \ if (TREE_CONSTANT (decl) \ && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \ { \ rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \ ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \ SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \ } \ } /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. The usual definition accepts all pseudo regs; the other rejects them unless they have been allocated suitable hard regs. The symbol REG_OK_STRICT causes the latter definition to be used. */ #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ #define REG_OK_FOR_BASE_P(X) \ (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM) /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ #define REG_OK_FOR_INDEX_P(X) \ REG_OK_FOR_BASE_P(X) #define REG_OK_FOR_PRE_POST_P(X) \ (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM) #else /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) #define REG_OK_FOR_PRE_POST_P(X) \ (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \ || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \ || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \ || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM) #endif /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ #define BASE_REGISTER_RTX_P(X) \ (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) #define INDEX_REGISTER_RTX_P(X) \ (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can only be small constants. */ #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \ do \ { \ int range; \ int code = GET_CODE (INDEX); \ \ if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \ { \ if (code == CONST_INT && INTVAL (INDEX) < 1024 \ && INTVAL (INDEX) > -1024 \ && (INTVAL (INDEX) & 3) == 0) \ goto LABEL; \ } \ else \ { \ if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \ goto LABEL; \ if (GET_MODE_SIZE (MODE) <= 4 && code == MULT) \ { \ rtx xiop0 = XEXP (INDEX, 0); \ rtx xiop1 = XEXP (INDEX, 1); \ if (INDEX_REGISTER_RTX_P (xiop0) \ && power_of_two_operand (xiop1, SImode)) \ goto LABEL; \ if (INDEX_REGISTER_RTX_P (xiop1) \ && power_of_two_operand (xiop0, SImode)) \ goto LABEL; \ } \ if (GET_MODE_SIZE (MODE) <= 4 \ && (code == LSHIFTRT || code == ASHIFTRT || code == LSHIFT \ || code == ASHIFT || code == ROTATERT)) \ { \ rtx op = XEXP (INDEX, 1); \ if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \ && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \ && INTVAL (op) <= 31) \ goto LABEL; \ } \ range = (MODE) == HImode ? 4095 : 4096; \ if (code == CONST_INT && INTVAL (INDEX) < range \ && INTVAL (INDEX) > -range) \ goto LABEL; \ } \ } while (0) /* Jump to LABEL if X is a valid address RTX. This must also take REG_OK_STRICT into account when deciding about valid registers, but it uses the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool. Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol refs must be forced though a static cell to ensure addressability. */ #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ { \ if (BASE_REGISTER_RTX_P (X)) \ goto LABEL; \ else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ && GET_CODE (XEXP (X, 0)) == REG \ && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ goto LABEL; \ else if ((MODE) == TImode) \ ; \ else if (GET_CODE (X) == PLUS) \ { \ rtx xop0 = XEXP(X,0); \ rtx xop1 = XEXP(X,1); \ \ if (BASE_REGISTER_RTX_P (xop0)) \ GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ else if (BASE_REGISTER_RTX_P (xop1)) \ GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ } \ else if (GET_CODE (X) == MINUS) \ { \ rtx xop0 = XEXP (X,0); \ rtx xop1 = XEXP (X,1); \ \ if (BASE_REGISTER_RTX_P (xop0)) \ GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \ } \ else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ && GET_CODE (X) == SYMBOL_REF \ && CONSTANT_POOL_ADDRESS_P (X)) \ goto LABEL; \ else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \ && GET_CODE (XEXP (X, 0)) == REG \ && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ goto LABEL; \ } /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. OLDX is the address as it was before break_out_memory_refs was called. In some cases it is useful to look at this to decide what needs to be done. MODE and WIN are passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. It is always safe for this macro to do nothing. It exists to recognize opportunities to optimize the output. On the ARM, try to convert [REG, #BIGCONST] into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST], where VALIDCONST == 0 in case of TImode. */ #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ { \ if (GET_CODE (X) == PLUS) \ { \ rtx xop0 = XEXP (X, 0); \ rtx xop1 = XEXP (X, 1); \ \ if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \ { \ int n = INTVAL (xop1); \ int low_n = ((MODE) == TImode ? 0 \ : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \ rtx base_reg = gen_reg_rtx (SImode); \ rtx val = force_operand (gen_rtx (PLUS, SImode, xop0, \ gen_rtx (CONST_INT, \ VOIDmode, n - low_n)), \ 0); \ emit_move_insn (base_reg, val); \ (X) = (low_n == 0 ? base_reg \ : gen_rtx (PLUS, SImode, base_reg, \ gen_rtx (CONST_INT, VOIDmode, low_n))); \ } \ else if (BASE_REGISTER_RTX_P (xop1) && GET_CODE (xop0) == CONST_INT) \ { \ int n = INTVAL (xop0); \ int low_n = ((MODE) == TImode ? 0 \ : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \ rtx base_reg = gen_reg_rtx (SImode); \ rtx val = force_operand (gen_rtx (PLUS, SImode, xop1, \ gen_rtx (CONST_INT, \ VOIDmode, n - low_n)), \ 0); \ emit_move_insn (base_reg, val); \ (X) = (low_n == 0 ? base_reg \ : gen_rtx (PLUS, SImode, base_reg, \ gen_rtx (CONST_INT, VOIDmode, low_n))); \ } \ } \ if (memory_address_p (MODE, X)) \ goto win; \ } /* Go to LABEL if ADDR (a legitimate address expression) has an effect that depends on the machine mode it is used for. */ #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ { \ if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \ || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \ goto LABEL; \ } /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE SImode /* Define this if the tablejump instruction expects the table to contain offsets from the address of the table. Do not define this if the table should contain absolute addresses. */ /* #define CASE_VECTOR_PC_RELATIVE */ /* Specify the tree operation to be used to convert reals to integers. */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR /* This is the kind of divide that is easiest to do in the general case. */ #define EASY_DIV_EXPR TRUNC_DIV_EXPR /* signed 'char' is most compatible, but RISC OS wants it unsigned. unsigned is probably best, but may break some code. */ #ifndef DEFAULT_SIGNED_CHAR #define DEFAULT_SIGNED_CHAR 1 #endif /* Don't cse the address of the function being compiled. */ #define NO_RECURSIVE_FUNCTION_CSE 1 /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ #define MOVE_MAX 4 /* Define if operations between registers always perform the operation on the full register even if a narrower mode is specified. */ #define WORD_REGISTER_OPERATIONS /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly done, NIL if none. */ #define LOAD_EXTEND_OP(MODE) \ ((MODE) == QImode ? ZERO_EXTEND : NIL) /* Define this if zero-extension is slow (more than one real instruction). On the ARM, it is more than one instruction only if not fetching from memory. */ /* #define SLOW_ZERO_EXTEND */ /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS 0 /* Immediate shift counts are truncated by the output routines (or was it the assembler?). Shift counts in a register are truncated by ARM. Note that the native compiler puts too large (> 32) immediate shift counts into a register and shifts by the register, letting the ARM decide what to do instead of doing that itself. */ /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). On the arm, Y in a register is used modulo 256 for the shift. Only for rotates is modulo 32 used. */ /* #define SHIFT_COUNT_TRUNCATED 1 */ /* XX This is not true, is it? */ /* All integers have the same format so truncation is easy. */ #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 /* Calling from registers is a massive pain. */ #define NO_FUNCTION_CSE 1 /* Chars and shorts should be passed as ints. */ #define PROMOTE_PROTOTYPES 1 /* The machine modes of pointers and functions */ #define Pmode SImode #define FUNCTION_MODE Pmode /* The structure type of the machine dependent info field of insns No uses for this yet. */ /* #define INSN_MACHINE_INFO struct machine_info */ /* The relative costs of various types of constants. Note that cse.c defines REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ case CONST_INT: \ if (const_ok_for_arm (INTVAL (RTX))) \ return (OUTER_CODE) == SET ? 2 : -1; \ else if (OUTER_CODE == AND \ && const_ok_for_arm (~INTVAL (RTX))) \ return -1; \ else if ((OUTER_CODE == COMPARE \ || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \ && const_ok_for_arm (-INTVAL (RTX))) \ return -1; \ else \ return 5; \ case CONST: \ case LABEL_REF: \ case SYMBOL_REF: \ return 6; \ case CONST_DOUBLE: \ if (const_double_rtx_ok_for_fpu (RTX)) \ return (OUTER_CODE) == SET ? 2 : -1; \ else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \ && neg_const_double_rtx_ok_for_fpu (RTX)) \ return -1; \ return(7); #define RTX_COSTS(X,CODE,OUTER_CODE) \ case MEM: \ { \ int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1;\ return (COSTS_N_INSNS (10*num_words)); \ } \ case MULT: \ if (GET_CODE (XEXP (X, 1)) == CONST_INT \ && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \ return rtx_cost (XEXP (X, 0), GET_CODE (X))+1; \ return COSTS_N_INSNS (9); \ case LSHIFT: \ case ASHIFT: \ case LSHIFTRT: \ case ASHIFTRT: \ if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ return rtx_cost (XEXP (X, 0), GET_CODE (X))+1; \ break; \ case MINUS: \ { \ enum rtx_code code = GET_CODE (XEXP (X, 1)); \ if (code == MULT) \ { \ if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT \ && exact_log2 (INTVAL (XEXP (XEXP (X, 0), 1))) >= 0) \ return COSTS_N_INSNS (1); \ break; \ } \ else if (code == ASHIFT || code == LSHIFT || code == ASHIFTRT \ || code == LSHIFTRT) \ return COSTS_N_INSNS (1); \ } /* fall through */ \ case PLUS: \ case IOR: \ case XOR: \ case AND: \ { \ enum rtx_code code = GET_CODE (XEXP (X, 0)); \ if (code == MULT) \ { \ if (GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ && exact_log2 (INTVAL (XEXP (XEXP (X, 0), 1))) >= 0) \ return COSTS_N_INSNS (1); \ if (GET_CODE (X) == PLUS) \ return COSTS_N_INSNS (12); \ break; \ } \ else if (code == ASHIFT || code == LSHIFT || code == ASHIFTRT \ || code == LSHIFTRT) \ return COSTS_N_INSNS (1); \ break; \ } \ case NOT: \ return rtx_cost (XEXP (X, 0), GET_CODE (XEXP (X, 0))); \ case IF_THEN_ELSE: \ { \ if (GET_CODE (XEXP(X,1)) == PC || GET_CODE (XEXP(X,2)) == PC) \ return COSTS_N_INSNS (4); \ return COSTS_N_INSNS (1); \ } \ case SIGN_EXTEND: \ return COSTS_N_INSNS (2); \ case ZERO_EXTEND: \ if (GET_MODE (XEXP (X, 0)) == QImode) \ { \ if (GET_CODE (XEXP (X, 0)) == MEM) \ return COSTS_N_INSNS (10); \ return COSTS_N_INSNS (1); \ } \ break; \ case COMPARE: \ if (GET_CODE (XEXP (X, 1)) == REG) \ return 4; \ case SMIN: \ case SMAX: \ case UMIN: \ case UMAX: \ return COSTS_N_INSNS (3); \ case ABS: \ if (GET_MODE (X) == SImode) \ return COSTS_N_INSNS (2); \ return COSTS_N_INSNS (1); /* Moves to and from memory are quite expensive */ #define MEMORY_MOVE_COST(MODE) 10 /* All address computations that can be done are free */ #define ADDRESS_COST(x) 2 /* Try to generate sequences that don't involve branches, we can then use conditional instructions */ #define BRANCH_COST 4 /* Condition code information. */ /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, return the mode to be used for the comparison. CCFPEmode should be used with floating inequalites, CCFPmode should be used with floating equalities. CC_NOOVmode should be used with SImode integer equalites CCmode should be used otherwise. */ #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE" #define SELECT_CC_MODE(OP,X,Y) \ (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ : ((GET_MODE (X) == SImode) \ && ((OP) == EQ || (OP) == NE) \ && (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ || GET_CODE (X) == AND || GET_CODE (X) == IOR \ || GET_CODE (X) == XOR || GET_CODE (X) == MULT \ || GET_CODE (X) == NOT || GET_CODE (X) == NEG \ || GET_CODE (X) == LSHIFT || GET_CODE (X) == LSHIFTRT \ || GET_CODE (X) == ASHIFT || GET_CODE (X) == ASHIFTRT \ || GET_CODE (X) == ROTATERT || GET_CODE (X) == ZERO_EXTRACT) \ ? CC_NOOVmode \ : GET_MODE (X) == QImode ? CC_NOOVmode : CCmode)) #define STORE_FLAG_VALUE 1 /* Define the information needed to generate branch insns. This is stored from the compare operation. Note that we can't use "rtx" here since it hasn't been defined! */ extern struct rtx_def *arm_compare_op0, *arm_compare_op1; extern int arm_compare_fp; /* Define the codes that are matched by predicates in arm.c */ #define PREDICATE_CODES \ {"s_register_operand", {SUBREG, REG}}, \ {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ {"shift_operator", {ASHIFT, LSHIFT, ASHIFTRT, LSHIFTRT, MULT}}, \ {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ {"load_multiple_operation", {PARALLEL}}, \ {"store_multiple_operation", {PARALLEL}}, \ {"equality_operator", {EQ, NE}}, \ {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \ {"const_shift_operand", {CONST_INT}}, \ {"index_operand", {SUBREG, REG, CONST_INT}}, \ {"cc_register", {REG}}, /* Assembler output control */ #ifndef ARM_OS_NAME #define ARM_OS_NAME "(generic)" #endif /* The text to go at the start of the assembler file */ #define ASM_FILE_START(STREAM) \ { \ extern char *version_string; \ \ fprintf (STREAM,"@ Generated by gcc %s for ARM/%s\n", version_string, \ ARM_OS_NAME); \ fprintf (STREAM,"rfp\t.req\tr9\n"); \ fprintf (STREAM,"fp\t.req\tr11\n"); \ fprintf (STREAM,"ip\t.req\tr12\n"); \ fprintf (STREAM,"sp\t.req\tr13\n"); \ fprintf (STREAM,"lr\t.req\tr14\n"); \ fprintf (STREAM,"pc\t.req\tr15\n"); \ } #define ASM_APP_ON "" #define ASM_APP_OFF "" /* Switch to the text or data segment. */ #define TEXT_SECTION_ASM_OP ".text" #define DATA_SECTION_ASM_OP ".data" /* The assembler's names for the registers. RFP need not always be used as the Real framepointer; it can also be used as a normal general register. Note that the name `fp' is horribly misleading since `fp' is in fact only the argument-and-return-context pointer. */ #define REGISTER_NAMES \ { \ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ "r8","rfp", "sl", "fp", "ip", "sp", "lr", "pc", \ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ "cc", "sfp", "afp" \ } /* Arm Assembler barfs on dollars */ #define DOLLARS_IN_IDENTIFIERS 0 #define NO_DOLLAR_IN_LABEL /* DBX register number for a given compiler register number */ #define DBX_REGISTER_NUMBER(REGNO) (REGNO) /* Generate DBX debugging information. riscix.h will undefine this because the native assembler does not support stabs. */ #define DBX_DEBUGGING_INFO 1 /* Acorn dbx moans about continuation chars, so don't use any. */ #define DBX_CONTIN_LENGTH 0 /* Output a source filename for the debugger. RISCiX dbx insists that the ``desc'' field is set to compiler version number >= 315 (sic). */ #define DBX_OUTPUT_MAIN_SOURCE_FILENAME(STREAM,NAME) \ do { \ fprintf (STREAM, ".stabs \"%s\",%d,0,315,%s\n", (NAME), N_SO, \ <ext_label_name[1]); \ text_section (); \ ASM_OUTPUT_INTERNAL_LABEL (STREAM, "Ltext", 0); \ } while (0) /* Output a label definition. */ #define ASM_OUTPUT_LABEL(STREAM,NAME) \ arm_asm_output_label ((STREAM), (NAME)) /* Output a function label definition. */ #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ ASM_OUTPUT_LABEL(STREAM, NAME) /* Output a globalising directive for a label. */ #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \ (fprintf (STREAM, "\t.global\t"), \ assemble_name (STREAM, NAME), \ fputc ('\n',STREAM)) \ /* Output a reference to a label. */ #define ASM_OUTPUT_LABELREF(STREAM,NAME) \ fprintf (STREAM, "_%s", NAME) /* Make an internal label into a string. */ #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ sprintf (STRING, "*%s%d", PREFIX, NUM) /* Output an internal label definition. */ #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \ do \ { \ char *s = (char *) alloca (11 + strlen (PREFIX)); \ extern int arm_target_label, arm_ccfsm_state; \ extern rtx arm_target_insn; \ \ if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \ && !strcmp (PREFIX, "L")) \ { \ arm_ccfsm_state = 0; \ arm_target_insn = NULL; \ } \ strcpy (s, "*"); \ sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM)); \ arm_asm_output_label (STREAM, s); \ } while (0) /* Nothing special is done about jump tables */ /* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */ /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ /* Construct a private name. */ #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \ ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \ sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER))) /* Output a push or a pop instruction (only used when profiling). */ #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ (arm_increase_location (4) \ , fprintf(STREAM,"\tstmfd\tsp!,{%s}\n", reg_names[REGNO])) #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ (arm_increase_location (4) \ , fprintf(STREAM,"\tldmfd\tsp!,{%s}\n", reg_names[REGNO])) /* Output a relative address. Not needed since jump tables are absolute but we must define it anyway. */ #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \ fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM) /* Output an element of a dispatch table. */ #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ (arm_increase_location (4) \ , fprintf (STREAM, "\t.word\tL%d\n", VALUE)) /* Output various types of constants. For real numbers we output hex, with a comment containing the "human" value, this allows us to pass NaN's which the riscix assembler doesn't understand (it also makes cross-assembling less likely to fail). */ #define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \ do { char dstr[30]; \ long l[3]; \ arm_increase_location (12); \ REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ if (sizeof (int) == sizeof (long)) \ fprintf (STREAM, "\t.long 0x%x,0x%x,0x%x\t@ long double %s\n", \ l[2], l[1], l[0], dstr); \ else \ fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\t@ long double %s\n",\ l[0], l[1], l[2], dstr); \ } while (0) #define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \ do { char dstr[30]; \ long l[2]; \ arm_increase_location (8); \ REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ REAL_VALUE_TO_DECIMAL (VALUE, "%.14g", dstr); \ if (sizeof (int) == sizeof (long)) \ fprintf (STREAM, "\t.long 0x%x, 0x%x\t@ double %s\n", l[0], l[1],\ dstr); \ else \ fprintf (STREAM, "\t.long 0x%lx, 0x%lx\t@ double %s\n", l[0], \ l[1], dstr); \ } while (0) #define ASM_OUTPUT_FLOAT(STREAM, VALUE) \ do { char dstr[30]; \ long l; \ arm_increase_location (4); \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ REAL_VALUE_TO_DECIMAL (VALUE, "%.7g", dstr); \ if (sizeof (int) == sizeof (long)) \ fprintf (STREAM, "\t.word 0x%x\t@ float %s\n", l, dstr); \ else \ fprintf (STREAM, "\t.word 0x%lx\t@ float %s\n", l, dstr); \ } while (0); #define ASM_OUTPUT_INT(STREAM, EXP) \ (fprintf (STREAM, "\t.word\t"), \ output_addr_const (STREAM, (EXP)), \ arm_increase_location (4), \ fputc ('\n', STREAM)) #define ASM_OUTPUT_SHORT(STREAM, EXP) \ (fprintf (STREAM, "\t.short\t"), \ output_addr_const (STREAM, (EXP)), \ arm_increase_location (2), \ fputc ('\n', STREAM)) #define ASM_OUTPUT_CHAR(STREAM, EXP) \ (fprintf (STREAM, "\t.byte\t"), \ output_addr_const (STREAM, (EXP)), \ arm_increase_location (1), \ fputc ('\n', STREAM)) #define ASM_OUTPUT_BYTE(STREAM, VALUE) \ (fprintf (STREAM, "\t.byte\t%d\n", VALUE), \ arm_increase_location (1)) #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \ output_ascii_pseudo_op ((STREAM), (unsigned char *)(PTR), (LEN)) /* Output a gap. In fact we fill it with nulls. */ #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \ (arm_increase_location (NBYTES), \ fprintf (STREAM, "\t.space\t%d\n", NBYTES)) /* Align output to a power of two. Horrible /bin/as. */ #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ do \ { \ register int amount = 1 << (POWER); \ extern int arm_text_location; \ \ if (amount == 2) \ fprintf (STREAM, "\t.even\n"); \ else \ fprintf (STREAM, "\t.align\t%d\n", amount - 4); \ \ if (in_text_section ()) \ arm_text_location = ((arm_text_location + amount - 1) \ & ~(amount - 1)); \ } while (0) /* Output a common block */ #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \ (fprintf (STREAM, "\t.comm\t"), \ assemble_name ((STREAM), (NAME)), \ fprintf(STREAM, ", %d\t@%d\n", ROUNDED, SIZE)) /* Output a local common block. /bin/as can't do this, so hack a `.space' into the bss segment. Note that this is *bad* practice. */ #define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \ output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED) /* Output a source filename for the debugger. RISCiX dbx insists that the ``desc'' field is set to compiler version number >= 315 (sic). */ #if 0 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM,NAME) \ fprintf (STREAM, "\t.stabs\t\"%s\", %d, 0, 315, Ltext\n", (NAME), N_SOL) #endif /* Output a source line for the debugger. */ /* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */ /* Output a #ident directive. */ #define ASM_OUTPUT_IDENT(STREAM,STRING) \ fprintf (STREAM,"- - - ident %s\n",STRING) /* The assembler's parentheses characters. */ #define ASM_OPEN_PAREN "(" #define ASM_CLOSE_PAREN ")" /* Target characters. */ #define TARGET_BELL 007 #define TARGET_BS 010 #define TARGET_TAB 011 #define TARGET_NEWLINE 012 #define TARGET_VT 013 #define TARGET_FF 014 #define TARGET_CR 015 /* FINAL_PRESCAN_INSN is used to take a look at the insns, in order to delete small-distance conditional branches and have ASM_OUTPUT_OPCODE make the instructions conditional. Suffixes like s (affect flags) and b (bytewise load/store) need to stay suffixes, so the possible condition code comes before these suffixes. %d or %D may appear in the opcode if it can take a condition; a null rtx will cause no condition to be added, this is what we expect to happen if arm_ccfsm_state is non-zero. */ #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ { \ extern int arm_ccfsm_state, arm_current_cc; \ extern char *arm_condition_codes[]; \ int i; \ \ fflush (STREAM); /* XXX for debugging only. */ \ if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) \ { \ for (i = 0; *(PTR) != ' ' && *(PTR) != '\t' && *(PTR) != '%' && i < 3;\ i++, (PTR)++) \ putc (*(PTR), STREAM); \ fprintf (STREAM, "%s", arm_condition_codes[arm_current_cc]); \ for (; *(PTR) != ' ' && *(PTR) != '\t' && *(PTR) != '%'; (PTR)++) \ putc (*(PTR), STREAM); \ } \ } /* Only perform branch elimination (by making instructions conditional) if we're optimising. Otherwise it's of no use anyway. */ #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ if (optimize) \ final_prescan_insn (INSN, OPVEC, NOPERANDS) /* Output an operand of an instruction. If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */ #define PRINT_OPERAND(STREAM, X, CODE) \ { \ if ((CODE) == 'd') \ { \ if (X) \ fputs (arm_condition_codes[get_arm_condition_code (X)], \ (STREAM)); \ } \ else if ((CODE) == 'D') \ { \ if (X) \ fputs (arm_condition_codes[get_arm_condition_code (X) ^ 1], \ (STREAM)); \ } \ else if ((CODE) == 'R') \ fputs (reg_names[REGNO (X) + 1], (STREAM)); \ else if (GET_CODE (X) == REG) \ { \ if ((CODE) != 'M') \ fputs (reg_names[REGNO (X)], (STREAM)); \ else \ fprintf ((STREAM), "{%s-%s}", \ reg_names[REGNO (X)], \ reg_names[REGNO (X) - 1 \ + ((GET_MODE_SIZE (GET_MODE (X)) \ + GET_MODE_SIZE (SImode) - 1) \ / GET_MODE_SIZE (SImode))]); \ } \ else if (GET_CODE (X) == MEM) \ { \ extern int output_memory_reference_mode; \ output_memory_reference_mode = GET_MODE (X); \ output_address (XEXP (X, 0)); \ } \ else if (GET_CODE(X) == CONST_DOUBLE) \ fprintf(STREAM,"#%s", fp_immediate_constant(X)); \ else if (GET_CODE (X) == NEG) \ { \ fputc ('-', (STREAM)); \ output_operand ((X), 0); \ } \ else \ { \ fputc('#', STREAM); \ output_addr_const(STREAM, X); \ } \ } /* Output the address of an operand. */ #define PRINT_OPERAND_ADDRESS(STREAM,X) \ { \ int is_minus = GET_CODE (X) == MINUS; \ \ if (GET_CODE (X) == REG) \ fprintf (STREAM, "[%s, #0]", reg_names[REGNO (X)]); \ else if (GET_CODE (X) == PLUS || is_minus) \ { \ rtx base = XEXP (X, 0); \ rtx index = XEXP (X, 1); \ char *base_reg_name; \ int offset = 0; \ int shift; \ if (GET_CODE (base) != REG) \ { \ /* Ensure that BASE is a register (one of them must be). */ \ rtx temp = base; \ base = index; \ index = temp; \ } \ base_reg_name = reg_names[REGNO (base)]; \ switch (GET_CODE (index)) \ { \ case CONST_INT: \ offset = INTVAL (index); \ if (is_minus) \ offset = -offset; \ fprintf (STREAM, "[%s, #%d]", base_reg_name, offset); \ break; \ \ case REG: \ fprintf (STREAM, "[%s, %s%s]", base_reg_name, \ is_minus ? "-" : "", reg_names[REGNO (index)] ); \ break; \ \ case MULT: \ if (GET_CODE (XEXP (index,0)) == CONST_INT) \ { \ shift = int_log2 (INTVAL (XEXP (index, 0))); \ index = XEXP (index, 1); \ } \ else if (GET_CODE(XEXP(index,1)) == CONST_INT) \ { \ shift = int_log2 (INTVAL (XEXP (index, 1))); \ index = XEXP (index, 0); \ } \ else \ abort(); \ fprintf (STREAM, "[%s, %s%s, asl #%d]", base_reg_name, \ is_minus ? "-" : "", reg_names[REGNO (index)], \ shift); \ break; \ case ASHIFTRT: \ case LSHIFTRT: \ case ASHIFT: \ case LSHIFT: \ case ROTATERT: \ { \ char *shift_type = shift_instr (GET_CODE (index), \ &XEXP (index, 1)); \ shift = INTVAL (XEXP (index, 1)); \ index = XEXP (index, 0); \ fprintf (STREAM, "[%s, %s%s, %s #%d]", base_reg_name, \ is_minus ? "-" : "", reg_names[REGNO (index)], \ shift_type, shift); \ break; \ } \ \ default: \ abort(); \ } \ } \ else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ { \ extern int output_memory_reference_mode; \ \ if (GET_CODE (XEXP (X, 0)) != REG) \ abort (); \ \ if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ fprintf (STREAM, "[%s, #%s%d]!", reg_names[REGNO (XEXP (X, 0))],\ GET_CODE (X) == PRE_DEC ? "-" : "", \ GET_MODE_SIZE (output_memory_reference_mode)); \ else \ fprintf (STREAM, "[%s], #%s%d", reg_names[REGNO (XEXP (X, 0))], \ GET_CODE (X) == POST_DEC ? "-" : "", \ GET_MODE_SIZE (output_memory_reference_mode)); \ } \ else output_addr_const(STREAM, X); \ } /* EOF arm.h */ gcc-2.5.8/config/arm/arm.md100444 22011 13 577272 5470724722 14205 0ustar kenneruser;;- Machine description Acorn RISC Machine for GNU compiler ;; Copyright (C) 1991, 1993 Free Software Foundation, Inc. ;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) ;; and Martin Simmons (@harleqn.co.uk). ;; More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk) ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ;; Every template must be output by arm_output_asm_insn, since this keeps ;; track of the offset of labels within the text segment. This is needed to ;; to be able to (correctly) output instructions for loading a value from a ;; function's constant pool, since different instructions are needed when the ;; constant pool is more than 4095 bytes away from the PC. ;; There are patterns in this file to support XFmode arithmetic. ;; Unfortunately RISCiX doesn't work well with these so they are disabled. ;; (See arm.h) ;; UNSPEC Usage: ;; 0 `sin' operation: operand 0 is the result, operand 1 the parameter, ;; the mode is MODE_FLOAT ;; 1 `cos' operation: operand 0 is the result, operand 1 the parameter, ;; the mode is MODE_FLOAT ;; Attributes ; condition codes: this one is used by final_prescan_insn to speed up ; conditionalizing instructions. It saves having to scan the rtl to see if ; it uses or alters the condition codes. ; USE means that the condition codes are used by the insn in the process of ; outputting code, this means (at present) that we can't use the insn in ; inlined branches ; SET means that the purpose of the insn is to set the condition codes in a ; well defined manner. ; CLOB means that the condition codes are altered in an undefined manner, if ; they are altered at all ; JUMP_CLOB is used when the conditions are not defined if a branch is taken, ; but are if the branch wasn't taken; the effect is to limit the branch ; elimination scanning. ; NOCOND means that the condition codes are niether altered nor affect the ; output of this insn (define_attr "conds" "use,set,clob,jump_clob,nocond" (const_string "nocond")) ; CPU attribute is used to determine whether condition codes are clobbered ; by a call insn: on the arm6 they are if in 32-bit addressing mode; on the ; arm2 and arm3 the condition codes are restored by the return. (define_attr "cpu" "arm2,arm3,arm6" (const (symbol_ref "arm_cpu_attr"))) ; LENGTH, all instructions are 4 bytes (define_attr "length" "" (const_int 1)) ; An assembler sequence may clobber the condition codes without us knowing (define_asm_attributes [(set_attr "conds" "clob") (set_attr "length" "1")]) ; TYPE attribute is used to detect floating point instructions which, if ; running on a co-processor can run in parallel with other, basic instructions ; If write-buffer scheduling is enabled then it can also be used in the ; scheduling of writes. ; Classification of each insn ; normal any data instruction that doesn't hit memory or fp regs ; block blockage insn, this blocks all functional units ; float a floating point arithmetic operation (subject to expansion) ; float_em a floating point arithmetic operation that is normally emulated ; f_load a floating point load from memory ; f_store a floating point store to memory ; f_mem_r a transfer of a floating point register to a real reg via mem ; r_mem_f the reverse of f_mem_r ; f_2_r fast transfer float to arm (no memory needed) ; r_2_f fast transfer arm to float ; call a subroutine call ; load any load from memory ; store1 store 1 word to memory from arm registers ; store2 store 2 words ; store3 store 3 words ; store4 store 4 words ; (define_attr "type" "normal,block,float,float_em,f_load,f_store,f_mem_r,r_mem_f,f_2_r,r_2_f,call,load,store1,store2,store3,store4" (const_string "normal")) (define_attr "write_conflict" "no,yes" (if_then_else (eq_attr "type" "block,float_em,f_load,f_store,f_mem_r,r_mem_f,call,load") (const_string "yes") (const_string "no"))) ; The write buffer on some of the arm6 processors is hard to model exactly. ; There is room in the buffer for up to two addresses and up to eight words ; of memory, but the two needn't be split evenly. When writing the two ; addresses are fully pipelined. However, a read from memory that is not ; currently in the cache will block until the writes have completed. ; It is normally the case that FCLK and MCLK will be in the ratio 2:1, so ; writes will take 2 FCLK cycles per word, if FCLK and MCLK are asynchronous ; (they aren't allowed to be at present) then there is a startup cost of 1MCLK ; cycle to add as well. ;; (define_function_unit {name} {num-units} {n-users} {test} ;; {ready-delay} {issue-delay} [{conflict-list}]) ;; This is not well tuned, but I don't have all the details. (define_function_unit "fpa" 1 1 (eq_attr "type" "float") 5 0) (define_function_unit "write_buf" 1 2 (eq_attr "type" "store1") 3 3 [(eq_attr "write_conflict" "yes")]) (define_function_unit "write_buf" 1 2 (eq_attr "type" "store2") 5 5 [(eq_attr "write_conflict" "yes")]) (define_function_unit "write_buf" 1 2 (eq_attr "type" "store3") 7 7 [(eq_attr "write_conflict" "yes")]) (define_function_unit "write_buf" 1 2 (eq_attr "type" "store4") 9 9 [(eq_attr "write_conflict" "yes")]) (define_function_unit "write_buf" 1 2 (eq_attr "type" "r_mem_f") 3 3 [(eq_attr "write_conflict" "yes")]) ;; Note: For DImode insns, there is normally no reason why operands should ;; not be in the same register, what we don't want is for something being ;; written to partially overlap something that is an input. ;; Addition insns. (define_insn "adddi3" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (plus:DI (match_operand:DI 1 "s_register_operand" "%0,0") (match_operand:DI 2 "s_register_operand" "r,0"))) (clobber (reg:CC 24))] "" "* arm_output_asm_insn (\"adds\\t%0, %1, %2\", operands); return (arm_output_asm_insn (\"adc\\t%R0, %R1, %R2\", operands)); " [(set_attr "conds" "clob") (set_attr "length" "2")]) (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (plus:DI (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r,r")) (match_operand:DI 2 "s_register_operand" "r,0"))) (clobber (reg:CC 24))] "" "* arm_output_asm_insn (\"adds\\t%0, %2, %1\", operands); return (arm_output_asm_insn (\"adc\\t%R0, %R2, %1, asr #31\", operands)); " [(set_attr "conds" "clob") (set_attr "length" "2")]) (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (plus:DI (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r,r")) (match_operand:DI 2 "s_register_operand" "r,0"))) (clobber (reg:CC 24))] "" "* arm_output_asm_insn (\"adds\\t%0, %2, %1\", operands); return (arm_output_asm_insn (\"adc\\t%R0, %R2, #0\", operands)); " [(set_attr "conds" "clob") (set_attr "length" "2")]) (define_insn "addsi3" [(set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_add_operand" "rL")))] "" "* if (GET_CODE (operands[2]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[2]))) { operands[2] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[2])); return arm_output_asm_insn (\"sub\\t%0, %1, %2\", operands); } return arm_output_asm_insn (\"add\\t%0, %1, %2\", operands); ") (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (plus:SI (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_add_operand" "rL")) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (match_dup 1) (match_dup 2)))] "" "* if (GET_CODE (operands[2]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[2]))) { operands[2] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[2])); return arm_output_asm_insn (\"subs\\t%0, %1, %2\", operands); } return (arm_output_asm_insn (\"adds\\t%0, %1, %2\", operands)); " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC 24) (compare:CC (match_operand:SI 1 "s_register_operand" "r") (neg:SI (match_operand:SI 2 "arm_add_operand" "rL")))) (set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (match_dup 1) (match_dup 2)))] "" "* if (GET_CODE (operands[2]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[2]))) { operands[2] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[2])); return arm_output_asm_insn (\"subs\\t%0, %1, %2\", operands); } return (arm_output_asm_insn (\"adds\\t%0, %1, %2\", operands)); " [(set_attr "conds" "set")]) (define_insn "incscc" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (plus:SI (match_operator:SI 2 "comparison_operator" [(reg 24) (const_int 0)]) (match_operand:SI 1 "s_register_operand" "0,?r")))] "" "* if (which_alternative == 1) arm_output_asm_insn (\"mov%D2\\t%0, %1\", operands); return arm_output_asm_insn (\"add%d2\\t%0, %1, #1\", operands); " [(set_attr "conds" "use") (set_attr "length" "*,2")]) ; If a constant is too big to fit in a single instruction then the constant ; will be pre-loaded into a register taking at least two insns, we might be ; able to merge it with an add, but it depends on the exact value. (define_split [(set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "immediate_operand" "n")))] "!(const_ok_for_arm (INTVAL (operands[2])) || const_ok_for_arm (-INTVAL (operands[2])))" [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2))) (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))] " { unsigned int val = (unsigned) INTVAL (operands[2]); int i; unsigned int temp; /* this code is similar to the approach followed in movsi, but it must generate exactly two insns */ for (i = 30; i >= 0; i -= 2) { if (val & (3 << i)) { i -= 6; if (i < 0) i = 0; if (const_ok_for_arm (temp = (val & ~(255 << i)))) { val &= 255 << i; break; } /* we might be able to do this as (larger number - small number) */ temp = ((val >> i) & 255) + 1; if (temp > 255 && i < 24) { i += 2; temp = ((val >> i) & 255) + 1; } if (const_ok_for_arm ((temp << i) - val)) { i = temp << i; temp = (unsigned) - (int) (i - val); val = i; break; } FAIL; } } /* if we got here, we have found a way of doing it in two instructions. the two constants are in val and temp */ operands[2] = GEN_INT ((int)val); operands[3] = GEN_INT ((int)temp); } ") (define_insn "addsf3" [(set (match_operand:SF 0 "s_register_operand" "=f,f") (plus:SF (match_operand:SF 1 "s_register_operand" "f,f") (match_operand:SF 2 "fpu_add_operand" "fG,H")))] "" "* { REAL_VALUE_TYPE r; switch (which_alternative) { case 0: return arm_output_asm_insn (\"adfs\\t%0, %1, %2\", operands); case 1: REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]); r = REAL_VALUE_NEGATE (r); operands[2] = CONST_DOUBLE_FROM_REAL_VALUE (r, GET_MODE (operands[2])); return arm_output_asm_insn (\"sufs\\t%0, %1, %2\", operands); } } " [(set_attr "type" "float")]) (define_insn "adddf3" [(set (match_operand:DF 0 "s_register_operand" "=f,f") (plus:DF (match_operand:DF 1 "s_register_operand" "f,f") (match_operand:DF 2 "fpu_add_operand" "fG,H")))] "" "* { REAL_VALUE_TYPE r; switch (which_alternative) { case 0: return (arm_output_asm_insn (\"adfd\\t%0, %1, %2\", operands)); case 1: REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]); r = REAL_VALUE_NEGATE (r); operands[2] = CONST_DOUBLE_FROM_REAL_VALUE (r, GET_MODE (operands[2])); return arm_output_asm_insn (\"sufd\\t%0, %1, %2\", operands); } } " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f,f") (plus:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f,f")) (match_operand:DF 2 "fpu_add_operand" "fG,H")))] "" "* { REAL_VALUE_TYPE r; switch (which_alternative) { case 0: return (arm_output_asm_insn (\"adfd\\t%0, %1, %2\", operands)); case 1: REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]); r = REAL_VALUE_NEGATE (r); operands[2] = CONST_DOUBLE_FROM_REAL_VALUE (r, GET_MODE (operands[2])); return arm_output_asm_insn (\"sufd\\t%0, %1, %2\", operands); } } " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (plus:DF (match_operand:DF 1 "s_register_operand" "f") (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] "" "* return (arm_output_asm_insn (\"adfd\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (plus:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] "" "* return (arm_output_asm_insn (\"adfd\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) (define_insn "addxf3" [(set (match_operand:XF 0 "s_register_operand" "=f,f") (plus:XF (match_operand:XF 1 "s_register_operand" "f,f") (match_operand:XF 2 "fpu_add_operand" "fG,H")))] "ENABLE_XF_PATTERNS" "* { REAL_VALUE_TYPE r; switch (which_alternative) { case 0: return (arm_output_asm_insn (\"adfe\\t%0, %1, %2\", operands)); case 1: REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]); r = REAL_VALUE_NEGATE (r); operands[2] = CONST_DOUBLE_FROM_REAL_VALUE (r, GET_MODE (operands[2])); return arm_output_asm_insn (\"sufe\\t%0, %1, %2\", operands); } } " [(set_attr "type" "float")]) (define_insn "subdi3" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r,&r") (minus:DI (match_operand:DI 1 "s_register_operand" "0,r,0") (match_operand:DI 2 "s_register_operand" "r,0,0"))) (clobber (reg:CC 24))] "" "* arm_output_asm_insn (\"subs\\t%0, %1, %2\", operands); return (arm_output_asm_insn (\"sbc\\t%R0, %R1, %R2\", operands)); " [(set_attr "conds" "clob") (set_attr "length" "2")]) (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (minus:DI (match_operand:DI 1 "s_register_operand" "?r,0") (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))) (clobber (reg:CC 24))] "" "* arm_output_asm_insn (\"subs\\t%0, %1, %2\", operands); return (arm_output_asm_insn (\"sbc\\t%R0, %R1, #0\", operands)); " [(set_attr "conds" "clob") (set_attr "length" "2")]) (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (minus:DI (match_operand:DI 1 "s_register_operand" "r,0") (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))) (clobber (reg:CC 24))] "" "* arm_output_asm_insn (\"subs\\t%0, %1, %2\", operands); return (arm_output_asm_insn (\"sbc\\t%R0, %R1, %2, asr #31\", operands)); " [(set_attr "conds" "clob") (set_attr "length" "2")]) (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (minus:DI (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "?r,0"))) (clobber (reg:CC 24))] "" "* arm_output_asm_insn (\"rsbs\\t%0, %1, %2\", operands); return (arm_output_asm_insn (\"rsc\\t%R0, %R1, #0\", operands)); " [(set_attr "conds" "clob") (set_attr "length" "2")]) (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (minus:DI (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "?r,0"))) (clobber (reg:CC 24))] "" "* arm_output_asm_insn (\"rsbs\\t%0, %1, %2\", operands); return (arm_output_asm_insn (\"rsc\\t%R0, %R1, %2, asr #31\", operands)); " [(set_attr "conds" "clob") (set_attr "length" "2")]) (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=r") (minus:DI (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")) (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r")))) (clobber (reg:CC 24))] "" "* arm_output_asm_insn (\"subs\\t%0, %1, %2\", operands); return (arm_output_asm_insn (\"rsc\\t%R0, %1, %1 @ extend carry\", operands)); " [(set_attr "conds" "clob") (set_attr "length" "2")]) (define_insn "subsi3" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,I") (match_operand:SI 2 "arm_rhs_operand" "rI,r")))] "" "* switch (which_alternative) { case 0: return (arm_output_asm_insn (\"sub\\t%0, %1, %2\", operands)); case 1: return (arm_output_asm_insn (\"rsb\\t%0, %2, %1\", operands)); } ") (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,I") (match_operand:SI 2 "arm_rhs_operand" "rI,r")) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r,r") (minus:SI (match_dup 1) (match_dup 2)))] "" "* switch (which_alternative) { case 0: return arm_output_asm_insn (\"subs\\t%0, %1, %2\", operands); case 1: return arm_output_asm_insn (\"rsbs\\t%0, %2, %1\", operands); } " [(set_attr "conds" "set")]) (define_insn "decscc" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") (match_operator:SI 2 "comparison_operator" [(reg 24) (const_int 0)])))] "" "* if (which_alternative == 1) arm_output_asm_insn (\"mov%D2\\t%0, %1\", operands); return arm_output_asm_insn (\"sub%d2\\t%0, %1, #1\", operands); " [(set_attr "conds" "use") (set_attr "length" "*,2")]) (define_insn "subsf3" [(set (match_operand:SF 0 "s_register_operand" "=f,f") (minus:SF (match_operand:SF 1 "fpu_rhs_operand" "f,G") (match_operand:SF 2 "fpu_rhs_operand" "fG,f")))] "" "* switch (which_alternative) { case 0: return (arm_output_asm_insn (\"sufs\\t%0, %1, %2\", operands)); case 1: return (arm_output_asm_insn (\"rsfs\\t%0, %2, %1\", operands)); } " [(set_attr "type" "float")]) (define_insn "subdf3" [(set (match_operand:DF 0 "s_register_operand" "=f,f") (minus:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G") (match_operand:DF 2 "fpu_rhs_operand" "fG,f")))] "" "* switch (which_alternative) { case 0: return (arm_output_asm_insn (\"sufd\\t%0, %1, %2\", operands)); case 1: return (arm_output_asm_insn (\"rsfd\\t%0, %2, %1\", operands)); } " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (minus:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) (match_operand:DF 2 "fpu_rhs_operand" "fG")))] "" "* return arm_output_asm_insn (\"sufd\\t%0, %1, %2\", operands); " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f,f") (minus:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G") (float_extend:DF (match_operand:SF 2 "s_register_operand" "f,f"))))] "" "* switch (which_alternative) { case 0: return (arm_output_asm_insn (\"sufd\\t%0, %1, %2\", operands)); case 1: return (arm_output_asm_insn (\"rsfd\\t%0, %2, %1\", operands)); } " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (minus:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] "" "* return arm_output_asm_insn (\"sufd\\t%0, %1, %2\", operands); " [(set_attr "type" "float")]) (define_insn "subxf3" [(set (match_operand:XF 0 "s_register_operand" "=f,f") (minus:XF (match_operand:XF 1 "fpu_rhs_operand" "f,G") (match_operand:XF 2 "fpu_rhs_operand" "fG,f")))] "ENABLE_XF_PATTERNS" "* switch (which_alternative) { case 0: return (arm_output_asm_insn (\"sufe\\t%0, %1, %2\", operands)); case 1: return (arm_output_asm_insn (\"rsfe\\t%0, %2, %1\", operands)); } " [(set_attr "type" "float")]) ;; Multiplication insns ;; Use `&' and then `0' to prevent the operands 0 and 1 being the same (define_insn "mulsi3" [(set (match_operand:SI 0 "s_register_operand" "=&r,&r") (mult:SI (match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 1 "s_register_operand" "%?r,0")))] "" "* return (arm_output_asm_insn (\"mul\\t%0, %2, %1\", operands)); ") (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (mult:SI (match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 1 "s_register_operand" "%?r,0")) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=&r,&r") (mult:SI (match_dup 2) (match_dup 1)))] "" "* return (arm_output_asm_insn (\"muls\\t%0, %2, %1\", operands)); " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (mult:SI (match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 1 "s_register_operand" "%?r,0")) (const_int 0))) (clobber (match_scratch:SI 0 "=&r,&r"))] "" "* return (arm_output_asm_insn (\"muls\\t%0, %2, %1\", operands)); " [(set_attr "conds" "set")]) ;; Unnamed templates to match MLA instruction. (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r") (plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r") (match_operand:SI 1 "s_register_operand" "%r,0,r,0")) (match_operand:SI 3 "s_register_operand" "?r,r,0,0")))] "" "* return (arm_output_asm_insn (\"mla\\t%0, %2, %1, %3\", operands)); ") (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r") (match_operand:SI 1 "s_register_operand" "%r,0,r,0")) (match_operand:SI 3 "s_register_operand" "?r,r,0,0")) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r") (plus:SI (mult:SI (match_dup 2) (match_dup 1)) (match_dup 3)))] "" "* return (arm_output_asm_insn (\"mlas\\t%0, %2, %1, %3\", operands)); " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r") (match_operand:SI 1 "s_register_operand" "%r,0,r,0")) (match_operand:SI 3 "s_register_operand" "?r,r,0,0")) (const_int 0))) (clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))] "" "* return (arm_output_asm_insn (\"mlas\\t%0, %2, %1, %3\", operands)); " [(set_attr "conds" "set")]) (define_insn "mulsf3" [(set (match_operand:SF 0 "s_register_operand" "=f") (mult:SF (match_operand:SF 1 "s_register_operand" "f") (match_operand:SF 2 "fpu_rhs_operand" "fG")))] "" "* return (arm_output_asm_insn (\"fmls\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) (define_insn "muldf3" [(set (match_operand:DF 0 "s_register_operand" "=f") (mult:DF (match_operand:DF 1 "s_register_operand" "f") (match_operand:DF 2 "fpu_rhs_operand" "fG")))] "" "* return (arm_output_asm_insn (\"mufd\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (mult:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) (match_operand:DF 2 "fpu_rhs_operand" "fG")))] "" "* return (arm_output_asm_insn (\"mufd\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (mult:DF (match_operand:DF 1 "s_register_operand" "f") (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] "" "* return (arm_output_asm_insn (\"mufd\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (mult:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] "" "* return (arm_output_asm_insn (\"mufd\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) (define_insn "mulxf3" [(set (match_operand:XF 0 "s_register_operand" "=f") (mult:XF (match_operand:XF 1 "s_register_operand" "f") (match_operand:XF 2 "fpu_rhs_operand" "fG")))] "ENABLE_XF_PATTERNS" "* return (arm_output_asm_insn (\"mufe\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) ;; Division insns (define_insn "divsf3" [(set (match_operand:SF 0 "s_register_operand" "=f,f") (div:SF (match_operand:SF 1 "fpu_rhs_operand" "f,G") (match_operand:SF 2 "fpu_rhs_operand" "fG,f")))] "" "* switch (which_alternative) { case 0: return (arm_output_asm_insn (\"fdvs\\t%0, %1, %2\", operands)); case 1: return (arm_output_asm_insn (\"frds\\t%0, %2, %1\", operands)); } " [(set_attr "type" "float")]) (define_insn "divdf3" [(set (match_operand:DF 0 "s_register_operand" "=f,f") (div:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G") (match_operand:DF 2 "fpu_rhs_operand" "fG,f")))] "" "* switch (which_alternative) { case 0: return (arm_output_asm_insn (\"dvfd\\t%0, %1, %2\", operands)); case 1: return (arm_output_asm_insn (\"rdfd\\t%0, %2, %1\", operands)); } " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (div:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) (match_operand:DF 2 "fpu_rhs_operand" "fG")))] "" "* return (arm_output_asm_insn (\"dvfd\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (div:DF (match_operand:DF 1 "fpu_rhs_operand" "fG") (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] "" "* return (arm_output_asm_insn (\"rdfd\\t%0, %2, %1\", operands)); " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (div:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] "" "* return (arm_output_asm_insn (\"dvfd\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) (define_insn "divxf3" [(set (match_operand:XF 0 "s_register_operand" "=f,f") (div:XF (match_operand:XF 1 "fpu_rhs_operand" "f,G") (match_operand:XF 2 "fpu_rhs_operand" "fG,f")))] "ENABLE_XF_PATTERNS" "* switch (which_alternative) { case 0: return (arm_output_asm_insn (\"dvfe\\t%0, %1, %2\", operands)); case 1: return (arm_output_asm_insn (\"rdfe\\t%0, %2, %1\", operands)); } " [(set_attr "type" "float")]) ;; Modulo insns (define_insn "modsf3" [(set (match_operand:SF 0 "s_register_operand" "=f") (mod:SF (match_operand:SF 1 "s_register_operand" "f") (match_operand:SF 2 "fpu_rhs_operand" "fG")))] "" "* return (arm_output_asm_insn (\"rmfs\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) (define_insn "moddf3" [(set (match_operand:DF 0 "s_register_operand" "=f") (mod:DF (match_operand:DF 1 "s_register_operand" "f") (match_operand:DF 2 "fpu_rhs_operand" "fG")))] "" "* return (arm_output_asm_insn (\"rmfd\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (mod:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) (match_operand:DF 2 "fpu_rhs_operand" "fG")))] "" "* return (arm_output_asm_insn (\"rmfd\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (mod:DF (match_operand:DF 1 "s_register_operand" "f") (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] "" "* return (arm_output_asm_insn (\"rmfd\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (mod:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] "" "* return (arm_output_asm_insn (\"rmfd\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) (define_insn "modxf3" [(set (match_operand:XF 0 "s_register_operand" "=f") (mod:XF (match_operand:XF 1 "s_register_operand" "f") (match_operand:XF 2 "fpu_rhs_operand" "fG")))] "ENABLE_XF_PATTERNS" "* return (arm_output_asm_insn (\"rmfe\\t%0, %1, %2\", operands)); " [(set_attr "type" "float")]) ;; Boolean and,ior,xor insns (define_insn "anddi3" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (and:DI (match_operand:DI 1 "s_register_operand" "%0,0") (match_operand:DI 2 "s_register_operand" "r,0")))] "" "* arm_output_asm_insn (\"and\\t%0, %1, %2\", operands); return (arm_output_asm_insn (\"and\\t%R0, %R1, %R2\", operands)); " [(set_attr "length" "2")]) (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (and:DI (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "?r,0")))] "" "* arm_output_asm_insn (\"and\\t%0, %1, %2\", operands); return arm_output_asm_insn (\"mov\\t%R0, #0\", operands); " [(set_attr "length" "2")]) (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (and:DI (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "?r,0")))] "" "* arm_output_asm_insn (\"and\\t%0, %1, %2\", operands); return arm_output_asm_insn (\"and\\t%R0, %R1, %2, asr #31\", operands); " [(set_attr "length" "2")]) (define_insn "andsi3" [(set (match_operand:SI 0 "s_register_operand" "=r") (and:SI (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_not_operand" "rK")))] "" "* if (GET_CODE (operands[2]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[2]))) { operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2])); return arm_output_asm_insn (\"bic\\t%0, %1, %2\", operands); } return arm_output_asm_insn (\"and\\t%0, %1, %2\", operands); ") (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (and:SI (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_not_operand" "rK")) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (and:SI (match_dup 1) (match_dup 2)))] "" "* if (GET_CODE (operands[2]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[2]))) { operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2])); return arm_output_asm_insn (\"bics\\t%0, %1, %2\", operands); } return arm_output_asm_insn (\"ands\\t%0, %1, %2\", operands); " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (and:SI (match_operand:SI 0 "s_register_operand" "r") (match_operand:SI 1 "arm_rhs_operand" "rI")) (const_int 0)))] "" "* return arm_output_asm_insn (\"tst\\t%0, %1\", operands); " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (and:SI (match_operand:SI 0 "s_register_operand" "r") (match_operand:SI 1 "immediate_operand" "K")) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "const_ok_for_arm (~INTVAL (operands[1]))" "* operands[1] = GEN_INT (~INTVAL (operands[1])); return arm_output_asm_insn (\"bics\\t%3, %0, %1\", operands); " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (zero_extract:SI (match_operand:SI 0 "s_register_operand" "r") (match_operand:SI 1 "immediate_operand" "n") (match_operand:SI 2 "immediate_operand" "n")) (const_int 0)))] "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32 && INTVAL (operands[1]) > 0 && INTVAL (operands[1]) + (INTVAL (operands[2]) & 1) <= 8 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32" "* { unsigned int mask = 0; int cnt = INTVAL (operands[1]); while (cnt--) mask = (mask << 1) | 1; operands[1] = gen_rtx (CONST_INT, VOIDmode, mask << INTVAL (operands[2])); return arm_output_asm_insn (\"tst\\t%0, %1\", operands); } " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (zero_extract:SI (match_operand:QI 0 "memory_operand" "m") (match_operand 1 "immediate_operand" "n") (match_operand 2 "immediate_operand" "n")) (const_int 0))) (clobber (match_scratch:QI 3 "=r"))] "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 8 && INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8" "* { unsigned int mask = 0; int cnt = INTVAL (operands[1]); while (cnt--) mask = (mask << 1) | 1; operands[1] = gen_rtx (CONST_INT, VOIDmode, mask << INTVAL (operands[2])); arm_output_asm_insn (\"ldrb\\t%3, %0\", operands); return arm_output_asm_insn (\"tst\\t%3, %1\", operands); } " [(set_attr "conds" "set") (set_attr "length" "2")]) ;; constants for op 2 will never be given to these patterns. (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (and:DI (not:DI (match_operand:DI 2 "s_register_operand" "r,0")) (match_operand:DI 1 "s_register_operand" "0,r")))] "" "* arm_output_asm_insn (\"bic\\t%0, %1, %2\", operands); return arm_output_asm_insn (\"bic\\t%R0, %R1, %R2\", operands); " [(set_attr "length" "2")]) (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (and:DI (not:DI (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r"))) (match_operand:DI 1 "s_register_operand" "?r,0")))] "" "* arm_output_asm_insn (\"bic\\t%0, %1, %2\", operands); if (REGNO (operands[1]) != REGNO (operands[0])) return arm_output_asm_insn (\"mov\\t%R0, %R1\", operands); return \"\"; " [(set_attr "length" "2,1")]) (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (and:DI (not:DI (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r"))) (match_operand:DI 1 "s_register_operand" "?r,0")))] "" "* arm_output_asm_insn (\"bic\\t%0, %1, %2\", operands); return arm_output_asm_insn (\"bic\\t%R0, %R1, %2, asr #31\", operands); " [(set_attr "length" "2")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) (match_operand:SI 1 "s_register_operand" "r")))] "" "* return (arm_output_asm_insn (\"bic\\t%0, %1, %2\", operands)); ") (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (and:SI (not:SI (match_dup 2)) (match_dup 1)))] "" "* return (arm_output_asm_insn (\"bics\\t%0, %1, %2\", operands)); " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] "" "* return (arm_output_asm_insn (\"bics\\t%0, %1, %2\", operands)); " [(set_attr "conds" "set")]) (define_insn "iordi3" [(set (match_operand:DI 0 "s_register_operand" "=&r") (ior:DI (match_operand:DI 1 "s_register_operand" "%0") (match_operand:DI 2 "s_register_operand" "r")))] "" "* arm_output_asm_insn (\"orr\\t%0, %1, %2\", operands); return (arm_output_asm_insn (\"orr\\t%R0, %R1, %R2\", operands)); " [(set_attr "length" "2")]) (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (ior:DI (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "?r,0")))] "" "* arm_output_asm_insn (\"orr\\t%0, %1, %2\", operands); if (REGNO (operands[0]) != REGNO (operands[1])) return (arm_output_asm_insn (\"mov\\t%R0, %R1\", operands)); return \"\"; " [(set_attr "length" "2,1")]) (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (ior:DI (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "?r,0")))] "" "* arm_output_asm_insn (\"orr\\t%0, %1, %2\", operands); return (arm_output_asm_insn (\"orr\\t%R0, %R1, %2, asr #31\", operands)); " [(set_attr "length" "2")]) (define_insn "iorsi3" [(set (match_operand:SI 0 "s_register_operand" "=r") (ior:SI (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rI")))] "" "* return (arm_output_asm_insn (\"orr\\t%0, %1, %2\", operands)); ") (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r") (match_operand:SI 2 "arm_rhs_operand" "rI")) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (ior:SI (match_dup 1) (match_dup 2)))] "" "* return arm_output_asm_insn (\"orrs\\t%0, %1, %2\", operands); " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r") (match_operand:SI 2 "arm_rhs_operand" "rI")) (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] "" "* return arm_output_asm_insn (\"orrs\\t%0, %1, %2\", operands); " [(set_attr "conds" "set")]) (define_insn "xordi3" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (xor:DI (match_operand:DI 1 "s_register_operand" "%0,0") (match_operand:DI 2 "s_register_operand" "r,0")))] "" "* arm_output_asm_insn (\"eor\\t%0, %1, %2\", operands); return arm_output_asm_insn (\"eor\\t%R0, %R1, %R2\", operands); " [(set_attr "length" "2")]) (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (xor:DI (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "?r,0")))] "" "* arm_output_asm_insn (\"eor\\t%0, %1, %2\", operands); if (REGNO (operands[0]) != REGNO (operands[1])) return arm_output_asm_insn (\"mov\\t%R0, %R1\", operands); return \"\"; " [(set_attr "length" "2,1")]) (define_insn "" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (xor:DI (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "?r,0")))] "" "* arm_output_asm_insn (\"eor\\t%0, %1, %2\", operands); return arm_output_asm_insn (\"eor\\t%R0, %R1, %2, asr #31\", operands); " [(set_attr "length" "2")]) (define_insn "xorsi3" [(set (match_operand:SI 0 "s_register_operand" "=r") (xor:SI (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rI")))] "" "* return (arm_output_asm_insn (\"eor\\t%0, %1, %2\", operands)); ") (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rI")) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (xor:SI (match_dup 1) (match_dup 2)))] "" "* return arm_output_asm_insn (\"eors\\t%0, %1, %2\", operands); " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r") (match_operand:SI 1 "arm_rhs_operand" "rI")) (const_int 0)))] "" "* return arm_output_asm_insn (\"teq\\t%0, %1\", operands); " [(set_attr "conds" "set")]) ;; by splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C), ;; (NOT D) we can sometimes merge the final NOT into one of the following ;; insns (define_split [(set (match_operand:SI 0 "s_register_operand" "=r") (ior:SI (and:SI (not:SI (match_operand:SI 1 "s_register_operand" "r")) (not:SI (match_operand:SI 2 "arm_rhs_operand" "rI"))) (match_operand:SI 3 "arm_rhs_operand" "rI"))) (clobber (match_operand:SI 4 "s_register_operand" "=r"))] "" [(set (match_dup 4) (and:SI (ior:SI (match_dup 1) (match_dup 2)) (not:SI (match_dup 3)))) (set (match_dup 0) (not:SI (match_dup 4)))] "" ) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r") (and:SI (ior:SI (match_operand:SI 1 "s_register_operand" "r,r,0") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")) (not:SI (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI"))))] "" "* arm_output_asm_insn (\"orr\\t%0, %1, %2\", operands); return arm_output_asm_insn (\"bic\\t%0, %0, %3\", operands); " [(set_attr "length" "2")]) ;; Minimum and maximum insns (define_insn "smaxsi3" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (smax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) (clobber (reg:CC 24))] "" "* arm_output_asm_insn (\"cmp\\t%1, %2\", operands); if (which_alternative != 0) arm_output_asm_insn (\"movge\\t%0, %1\", operands); if (which_alternative != 1) return arm_output_asm_insn (\"movlt\\t%0, %2\", operands); return \"\"; " [(set_attr "conds" "clob") (set_attr "length" "2,2,3")]) (define_insn "sminsi3" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) (clobber (reg:CC 24))] "" "* arm_output_asm_insn (\"cmp\\t%1, %2\", operands); if (which_alternative != 0) arm_output_asm_insn (\"movle\\t%0, %1\", operands); if (which_alternative != 1) return arm_output_asm_insn (\"movgt\\t%0, %2\", operands); return \"\"; " [(set_attr "conds" "clob") (set_attr "length" "2,2,3")]) (define_insn "umaxsi3" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) (clobber (reg:CC 24))] "" "* arm_output_asm_insn (\"cmp\\t%1, %2\", operands); if (which_alternative != 0) arm_output_asm_insn (\"movcs\\t%0, %1\", operands); if (which_alternative != 1) return arm_output_asm_insn (\"movcc\\t%0, %2\", operands); return \"\"; " [(set_attr "conds" "clob") (set_attr "length" "2,2,3")]) (define_insn "uminsi3" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) (clobber (reg:CC 24))] "" "* arm_output_asm_insn (\"cmp\\t%1, %2\", operands); if (which_alternative != 0) arm_output_asm_insn (\"movcc\\t%0, %1\", operands); if (which_alternative != 1) return arm_output_asm_insn (\"movcs\\t%0, %2\", operands); return \"\"; " [(set_attr "conds" "clob") (set_attr "length" "2,2,3")]) (define_insn "" [(set (match_operand:SI 0 "memory_operand" "=m") (match_operator:SI 3 "minmax_operator" [(match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "s_register_operand" "r")])) (clobber (reg:CC 24))] "" "* operands[3] = gen_rtx (minmax_code (operands[3]), SImode, operands[1], operands[2]); arm_output_asm_insn (\"cmp\\t%1, %2\", operands); arm_output_asm_insn (\"str%d3\\t%1, %0\", operands); return arm_output_asm_insn (\"str%D3\\t%2, %0\", operands); " [(set_attr "conds" "clob") (set_attr "length" "3") (set_attr "type" "store1")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (match_operator:SI 4 "shiftable_operator" [(match_operator:SI 5 "minmax_operator" [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) (match_operand:SI 1 "s_register_operand" "0,?r")])) (clobber (reg:CC 24))] "" "* { char buf[100]; enum rtx_code code = GET_CODE (operands[4]); char *inst = arithmetic_instr (operands[4], TRUE); operands[5] = gen_rtx (minmax_code (operands[5]), SImode, operands[2], operands[3]); arm_output_asm_insn (\"cmp\\t%2, %3\", operands); sprintf (buf, \"%s%%d5\\t%%0, %%1, %%2\", inst); arm_output_asm_insn (buf, operands); if (which_alternative != 0 || operands[3] != const0_rtx || (code != PLUS && code != MINUS && code != IOR && code != XOR)) { sprintf (buf, \"%s%%D5\\t%%0, %%1, %%3\", inst); return arm_output_asm_insn (buf, operands); } return \"\"; } " [(set_attr "conds" "clob") (set_attr "length" "3")]) ;; Shift and rotation insns (define_insn "ashlsi3" [(set (match_operand:SI 0 "s_register_operand" "=r") (ashift:SI (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rn")))] "" "* return (output_shifted_move (ASHIFT, operands)); ") (define_insn "ashrsi3" [(set (match_operand:SI 0 "s_register_operand" "=r") (ashiftrt:SI (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rn")))] "" "* return (output_shifted_move (ASHIFTRT, operands)); ") ;; lshlsi3 is not defined because shift counts cannot be negative ;; An unnamed pattern is needed for expansion of zero_extend. (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (lshift:SI (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rn")))] "" "* return (output_shifted_move (LSHIFT, operands)); ") (define_insn "lshrsi3" [(set (match_operand:SI 0 "s_register_operand" "=r") (lshiftrt:SI (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rn")))] "" "* return (output_shifted_move (LSHIFTRT, operands)); ") ;; rotlsi3 is not defined yet to see what happens (define_insn "rotrsi3" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (rotatert:SI (match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "arm_rhs_operand" "r,n")))] "" "* switch (which_alternative) { case 0: return (arm_output_asm_insn (\"mov\\t%0, %1, ror %2\", operands)); case 1: if (INTVAL(operands[2]) > 31) operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 32); return (arm_output_asm_insn (\"mov\\t%0, %1, ror %2\", operands)); } ") (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (match_operator:SI 1 "shift_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_rhs_operand" "rn")]) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (match_op_dup 1 [(match_dup 2) (match_dup 3)]))] "" "* { char buf[100]; sprintf (buf, \"movs\\t%%0, %%2, %s %%3\", shift_instr (GET_CODE (operands[1]), &operands[3])); return arm_output_asm_insn (buf, operands); } " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (match_operator:SI 1 "shift_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_rhs_operand" "rn")]) (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] "" "* { char buf[100]; sprintf (buf, \"movs\\t%%0, %%2, %s %%3\", shift_instr (GET_CODE (operands[1]), &operands[3])); return arm_output_asm_insn (buf, operands); } " [(set_attr "conds" "set")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (not:SI (match_operator:SI 1 "shift_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_rhs_operand" "rn")])))] "" "* { char buf[100]; sprintf (buf, \"mvn\\t%%0, %%2, %s %%3\", shift_instr (GET_CODE (operands[1]), &operands[3])); return arm_output_asm_insn (buf, operands); } ") (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (not:SI (match_operator:SI 1 "shift_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_rhs_operand" "rn")])) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (not:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])))] "" "* { char buf[100]; sprintf (buf, \"mvns\\t%%0, %%2, %s %%3\", shift_instr (GET_CODE (operands[1]), &operands[3])); return arm_output_asm_insn (buf, operands); } " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (not:SI (match_operator:SI 1 "shift_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_rhs_operand" "rn")])) (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] "" "* { char buf[100]; sprintf (buf, \"mvns\\t%%0, %%2, %s %%3\", shift_instr (GET_CODE (operands[1]), &operands[3])); return arm_output_asm_insn (buf, operands); } " [(set_attr "conds" "set")]) ;; Unary arithmetic insns (define_insn "negdi2" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (neg:DI (match_operand:DI 1 "s_register_operand" "?r,0")))] "" "* arm_output_asm_insn (\"rsbs\\t%0, %1, #0\", operands); return (arm_output_asm_insn (\"rsc\\t%R0, %R1, #0\", operands)); " [(set_attr "conds" "clob") (set_attr "length" "2")]) (define_insn "negsi2" [(set (match_operand:SI 0 "s_register_operand" "=r") (neg:SI (match_operand:SI 1 "s_register_operand" "r")))] "" "* return (arm_output_asm_insn (\"rsb\\t%0, %1, #0\", operands)); ") (define_insn "negsf2" [(set (match_operand:SF 0 "s_register_operand" "=f") (neg:SF (match_operand:SF 1 "s_register_operand" "f")))] "" "* return (arm_output_asm_insn (\"mnfs\\t%0, %1\", operands)); " [(set_attr "type" "float")]) (define_insn "negdf2" [(set (match_operand:DF 0 "s_register_operand" "=f") (neg:DF (match_operand:DF 1 "s_register_operand" "f")))] "" "* return (arm_output_asm_insn (\"mnfd\\t%0, %1\", operands)); " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (neg:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))))] "" "* return (arm_output_asm_insn (\"mnfd\\t%0, %1\", operands)); " [(set_attr "type" "float")]) (define_insn "negxf2" [(set (match_operand:XF 0 "s_register_operand" "=f") (neg:XF (match_operand:XF 1 "s_register_operand" "f")))] "ENABLE_XF_PATTERNS" "* return (arm_output_asm_insn (\"mnfe\\t%0, %1\", operands)); " [(set_attr "type" "float")]) ;; abssi2 doesn't really clobber the condition codes if a different register ;; is being set. To keep things simple, assume during rtl manipulations that ;; it does, but tell the final scan operator the truth. Similarly for ;; (neg (abs...)) (define_insn "abssi2" [(set (match_operand:SI 0 "s_register_operand" "=r,&r") (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))) (clobber (reg 24))] "" "* switch (which_alternative) { case 0: arm_output_asm_insn (\"cmp\\t%0, #0\", operands); return arm_output_asm_insn (\"rsblt\\t%0, %0, #0\", operands); case 1: arm_output_asm_insn (\"eor\\t%0, %1, %1, asr #31\", operands); return arm_output_asm_insn (\"sub\\t%0, %0, %1, asr #31\", operands); } " [(set_attr "conds" "clob,*") (set_attr "length" "2")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,&r") (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))) (clobber (reg 24))] "" "* switch (which_alternative) { case 0: arm_output_asm_insn (\"cmp\\t%0, #0\", operands); return arm_output_asm_insn (\"rsbgt\\t%0, %0, #0\", operands); case 1: arm_output_asm_insn (\"eor\\t%0, %1, %1, asr #31\", operands); return arm_output_asm_insn (\"rsb\\t%0, %0, %1, asr #31\", operands); } " [(set_attr "conds" "clob,*") (set_attr "length" "2")]) (define_insn "abssf2" [(set (match_operand:SF 0 "s_register_operand" "=f") (abs:SF (match_operand:SF 1 "s_register_operand" "f")))] "" "* return (arm_output_asm_insn (\"abss\\t%0, %1\", operands)); " [(set_attr "type" "float")]) (define_insn "absdf2" [(set (match_operand:DF 0 "s_register_operand" "=f") (abs:DF (match_operand:DF 1 "s_register_operand" "f")))] "" "* return (arm_output_asm_insn (\"absd\\t%0, %1\", operands)); " [(set_attr "type" "float")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (abs:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))))] "" "* return (arm_output_asm_insn (\"absd\\t%0, %1\", operands)); " [(set_attr "type" "float")]) (define_insn "absxf2" [(set (match_operand:XF 0 "s_register_operand" "=f") (abs:XF (match_operand:XF 1 "s_register_operand" "f")))] "ENABLE_XF_PATTERNS" "* return (arm_output_asm_insn (\"abse\\t%0, %1\", operands)); " [(set_attr "type" "float")]) (define_insn "sqrtsf2" [(set (match_operand:SF 0 "s_register_operand" "=f") (sqrt:SF (match_operand:SF 1 "s_register_operand" "f")))] "" "* return (arm_output_asm_insn (\"sqts\\t%0, %1\", operands)); " [(set_attr "type" "float_em")]) (define_insn "sqrtdf2" [(set (match_operand:DF 0 "s_register_operand" "=f") (sqrt:DF (match_operand:DF 1 "s_register_operand" "f")))] "" "* return (arm_output_asm_insn (\"sqtd\\t%0, %1\", operands)); " [(set_attr "type" "float_em")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (sqrt:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))))] "" "* return (arm_output_asm_insn (\"sqtd\\t%0, %1\", operands)); " [(set_attr "type" "float_em")]) (define_insn "sqrtxf2" [(set (match_operand:XF 0 "s_register_operand" "=f") (sqrt:XF (match_operand:XF 1 "s_register_operand" "f")))] "ENABLE_XF_PATTERNS" "* return (arm_output_asm_insn (\"sqte\\t%0, %1\", operands)); " [(set_attr "type" "float_em")]) (define_insn "sinsf2" [(set (match_operand:SF 0 "s_register_operand" "=f") (unspec:SF [(match_operand:SF 1 "s_register_operand" "f")] 0))] "" "* return arm_output_asm_insn (\"sins\\t%0, %1\", operands); " [(set_attr "type" "float_em")]) (define_insn "sindf2" [(set (match_operand:DF 0 "s_register_operand" "=f") (unspec:DF [(match_operand:DF 1 "s_register_operand" "f")] 0))] "" "* return arm_output_asm_insn (\"sind\\t%0, %1\", operands); " [(set_attr "type" "float_em")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (unspec:DF [(float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))] 0))] "" "* return arm_output_asm_insn (\"sind\\t%0, %1\", operands); " [(set_attr "type" "float_em")]) (define_insn "sinxf2" [(set (match_operand:XF 0 "s_register_operand" "=f") (unspec:XF [(match_operand:XF 1 "s_register_operand" "f")] 0))] "ENABLE_XF_PATTERNS" "* return arm_output_asm_insn (\"sine\\t%0, %1\", operands); " [(set_attr "type" "float_em")]) (define_insn "cossf2" [(set (match_operand:SF 0 "s_register_operand" "=f") (unspec:SF [(match_operand:SF 1 "s_register_operand" "f")] 1))] "" "* return arm_output_asm_insn (\"coss\\t%0, %1\", operands); " [(set_attr "type" "float_em")]) (define_insn "cosdf2" [(set (match_operand:DF 0 "s_register_operand" "=f") (unspec:DF [(match_operand:DF 1 "s_register_operand" "f")] 1))] "" "* return arm_output_asm_insn (\"cosd\\t%0, %1\", operands); " [(set_attr "type" "float_em")]) (define_insn "" [(set (match_operand:DF 0 "s_register_operand" "=f") (unspec:DF [(float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))] 1))] "" "* return arm_output_asm_insn (\"cosd\\t%0, %1\", operands); " [(set_attr "type" "float_em")]) (define_insn "cosxf2" [(set (match_operand:XF 0 "s_register_operand" "=f") (unspec:XF [(match_operand:XF 1 "s_register_operand" "f")] 1))] "ENABLE_XF_PATTERNS" "* return arm_output_asm_insn (\"cose\\t%0, %1\", operands); " [(set_attr "type" "float_em")]) (define_insn "one_cmpldi2" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (not:DI (match_operand:DI 1 "s_register_operand" "?r,0")))] "" "* arm_output_asm_insn (\"mvn\\t%0, %1\", operands); return arm_output_asm_insn (\"mvn\\t%R0, %R1\", operands); " [(set_attr "length" "2")]) (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "s_register_operand" "=r") (not:SI (match_operand:SI 1 "s_register_operand" "r")))] "" "* return (arm_output_asm_insn (\"mvn\\t%0, %1\", operands)); ") (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (not:SI (match_dup 1)))] "" "* return (arm_output_asm_insn (\"mvns\\t%0, %1\", operands)); " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] "" "* return (arm_output_asm_insn (\"mvns\\t%0, %1\", operands)); " [(set_attr "conds" "set")]) ;; Fixed <--> Floating conversion insns (define_insn "floatsisf2" [(set (match_operand:SF 0 "s_register_operand" "=f") (float:SF (match_operand:SI 1 "s_register_operand" "r")))] "" "* return (arm_output_asm_insn (\"flts\\t%0, %1\", operands)); " [(set_attr "type" "r_2_f")]) (define_insn "floatsidf2" [(set (match_operand:DF 0 "s_register_operand" "=f") (float:DF (match_operand:SI 1 "s_register_operand" "r")))] "" "* return (arm_output_asm_insn (\"fltd\\t%0, %1\", operands)); " [(set_attr "type" "r_2_f")]) (define_insn "floatsixf2" [(set (match_operand:XF 0 "s_register_operand" "=f") (float:XF (match_operand:SI 1 "s_register_operand" "r")))] "ENABLE_XF_PATTERNS" "* return (arm_output_asm_insn (\"flte\\t%0, %1\", operands)); " [(set_attr "type" "r_2_f")]) (define_insn "fix_truncsfsi2" [(set (match_operand:SI 0 "s_register_operand" "=r") (fix:SI (match_operand:SF 1 "s_register_operand" "f")))] "" "* return arm_output_asm_insn (\"fixz\\t%0, %1\", operands); " [(set_attr "type" "f_2_r")]) (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "s_register_operand" "=r") (fix:SI (match_operand:DF 1 "s_register_operand" "f")))] "" "* return arm_output_asm_insn (\"fixz\\t%0, %1\", operands); " [(set_attr "type" "f_2_r")]) (define_insn "fix_truncxfsi2" [(set (match_operand:SI 0 "s_register_operand" "=r") (fix:SI (match_operand:XF 1 "s_register_operand" "f")))] "ENABLE_XF_PATTERNS" "* return arm_output_asm_insn (\"fixz\\t%0, %1\", operands); " [(set_attr "type" "f_2_r")]) ;; Truncation insns (define_insn "truncdfsf2" [(set (match_operand:SF 0 "s_register_operand" "=f") (float_truncate:SF (match_operand:DF 1 "s_register_operand" "f")))] "" "* return (arm_output_asm_insn (\"mvfs\\t%0, %1\", operands)); " [(set_attr "type" "float")]) (define_insn "truncxfsf2" [(set (match_operand:SF 0 "s_register_operand" "=f") (float_truncate:SF (match_operand:XF 1 "s_register_operand" "f")))] "ENABLE_XF_PATTERNS" "* return (arm_output_asm_insn (\"mvfs\\t%0, %1\", operands)); " [(set_attr "type" "float")]) (define_insn "truncxfdf2" [(set (match_operand:DF 0 "s_register_operand" "=f") (float_truncate:DF (match_operand:XF 1 "s_register_operand" "f")))] "ENABLE_XF_PATTERNS" "* return (arm_output_asm_insn (\"mvfd\\t%0, %1\", operands)); " [(set_attr "type" "float")]) ;; Zero and sign extension instructions. (define_insn "zero_extendsidi2" [(set (match_operand:DI 0 "s_register_operand" "=r") (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))] "" "* if (REGNO (operands[1]) != REGNO (operands[0])) arm_output_asm_insn (\"mov\\t%0, %1\", operands); return arm_output_asm_insn (\"mov\\t%R0, #0\", operands); " [(set_attr "length" "2")]) (define_insn "zero_extendqidi2" [(set (match_operand:DI 0 "s_register_operand" "=r,r") (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] "" "* switch (which_alternative) { case 0: arm_output_asm_insn (\"and\\t%0, %1, #255\", operands); break; case 1: arm_output_asm_insn (\"ldrb\\t%0, %1\",operands); break; } return arm_output_asm_insn (\"mov\\t%R0, #0\", operands); " [(set_attr "length" "2") (set_attr "type" "*,load")]) (define_insn "extendsidi2" [(set (match_operand:DI 0 "s_register_operand" "=r") (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))] "" "* if (REGNO (operands[1]) != REGNO (operands[0])) arm_output_asm_insn (\"mov\\t%0, %1\", operands); return arm_output_asm_insn (\"mov\\t%R0, %0, asr #31\", operands); " [(set_attr "length" "2")]) (define_expand "zero_extendhisi2" [(set (match_dup 2) (ashift:SI (match_operand:HI 1 "s_register_operand" "") (const_int 16))) (set (match_operand:SI 0 "s_register_operand" "") (lshiftrt:SI (match_dup 2) (const_int 16)))] "" " { operands[1] = gen_lowpart (SImode, operands[1]); operands[2] = gen_reg_rtx (SImode); }") (define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "s_register_operand" "=r") (zero_extend:HI (match_operand:QI 1 "s_register_operand" "r")))] "" "* return (arm_output_asm_insn (\"and\\t%0, %1, #255\\t@ zero_extendqihi2\", operands)); ") (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (match_operand:QI 1 "s_register_operand" "r") (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (zero_extend:HI (match_dup 1)))] "" "* return arm_output_asm_insn (\"ands\\t%0, %1, #255\", operands); " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (match_operand:QI 0 "s_register_operand" "r") (const_int 0)))] "" "* return arm_output_asm_insn (\"tst\\t%0, #255\", operands); " [(set_attr "conds" "set")]) (define_insn "zero_extendqisi2" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] "" "* switch (which_alternative) { case 0: return (arm_output_asm_insn (\"and\\t%0, %1, #255\\t@ zero_extendqisi2\", operands)); case 1: return (arm_output_asm_insn (\"ldrb\\t%0, %1\\t@ zero_extendqisi2\", operands)); } " [(set_attr "type" "*,load")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (match_operand:QI 1 "s_register_operand" "r") (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (zero_extend:SI (match_dup 1)))] "" "* return arm_output_asm_insn (\"ands\\t%0, %1, #255\", operands); " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (match_operand:QI 1 "s_register_operand" "r") (const_int 0))) (set (match_operand:QI 0 "s_register_operand" "=r") (match_dup 1))] "" "* return arm_output_asm_insn (\"ands\\t%0, %1, #255\", operands); " [(set_attr "conds" "set")]) (define_expand "extendhisi2" [(set (match_dup 2) (ashift:SI (match_operand:HI 1 "s_register_operand" "") (const_int 16))) (set (match_operand:SI 0 "s_register_operand" "") (ashiftrt:SI (match_dup 2) (const_int 16)))] "" " { operands[1] = gen_lowpart (SImode, operands[1]); operands[2] = gen_reg_rtx (SImode); }") (define_expand "extendqihi2" [(set (match_dup 2) (ashift:SI (match_operand:QI 1 "s_register_operand" "") (const_int 24))) (set (match_operand:HI 0 "s_register_operand" "") (ashiftrt:SI (match_dup 2) (const_int 24)))] "" " { operands[0] = gen_lowpart (SImode, operands[0]); operands[1] = gen_lowpart (SImode, operands[1]); operands[2] = gen_reg_rtx (SImode); }") (define_expand "extendqisi2" [(set (match_dup 2) (ashift:SI (match_operand:QI 1 "s_register_operand" "") (const_int 24))) (set (match_operand:SI 0 "s_register_operand" "") (ashiftrt:SI (match_dup 2) (const_int 24)))] "" " { operands[1] = gen_lowpart (SImode, operands[1]); operands[2] = gen_reg_rtx (SImode); }") (define_insn "extendsfdf2" [(set (match_operand:DF 0 "s_register_operand" "=f") (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")))] "" "* return (arm_output_asm_insn (\"mvfd\\t%0, %1\", operands)); " [(set_attr "type" "float")]) (define_insn "extendsfxf2" [(set (match_operand:XF 0 "s_register_operand" "=f") (float_extend:XF (match_operand:SF 1 "s_register_operand" "f")))] "ENABLE_XF_PATTERNS" "* return (arm_output_asm_insn (\"mvfe\\t%0, %1\", operands)); ") (define_insn "extenddfxf2" [(set (match_operand:XF 0 "s_register_operand" "=f") (float_extend:XF (match_operand:DF 1 "s_register_operand" "f")))] "ENABLE_XF_PATTERNS" "* return (arm_output_asm_insn (\"mvfe\\t%0, %1\", operands)); " [(set_attr "type" "float")]) ;; Move insns (including loads and stores) ;; XXX Just some ideas about movti. ;; I don't think these are a good idea on the arm, there just aren't enough ;; registers ;;(define_expand "loadti" ;; [(set (match_operand:TI 0 "s_register_operand" "") ;; (mem:TI (match_operand:SI 1 "address_operand" "")))] ;; "" "") ;;(define_expand "storeti" ;; [(set (mem:TI (match_operand:TI 0 "address_operand" "")) ;; (match_operand:TI 1 "s_register_operand" ""))] ;; "" "") ;;(define_expand "movti" ;; [(set (match_operand:TI 0 "general_operand" "") ;; (match_operand:TI 1 "general_operand" ""))] ;; "" ;; " ;;{ ;; rtx insn; ;; ;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) ;; operands[1] = copy_to_reg (operands[1]); ;; if (GET_CODE (operands[0]) == MEM) ;; insn = gen_storeti (XEXP (operands[0], 0), operands[1]); ;; else if (GET_CODE (operands[1]) == MEM) ;; insn = gen_loadti (operands[0], XEXP (operands[1], 0)); ;; else ;; FAIL; ;; ;; emit_insn (insn); ;; DONE; ;;}") ;; Recognise garbage generated above. ;;(define_insn "" ;; [(set (match_operand:TI 0 "general_operand" "=r,r,r,<,>,m") ;; (match_operand:TI 1 "general_operand" "<,>,m,r,r,r"))] ;; "" ;; "* ;; { ;; register mem = (which_alternative < 3); ;; register char *template; ;; ;; operands[mem] = XEXP (operands[mem], 0); ;; switch (which_alternative) ;; { ;; case 0: template = \"ldmdb\\t%1!, %M0\"; break; ;; case 1: template = \"ldmia\\t%1!, %M0\"; break; ;; case 2: template = \"ldmia\\t%1, %M0\"; break; ;; case 3: template = \"stmdb\\t%0!, %M1\"; break; ;; case 4: template = \"stmia\\t%0!, %M1\"; break; ;; case 5: template = \"stmia\\t%0, %M1\"; break; ;; } ;; return (arm_output_asm_insn (template, operands)); ;; }") (define_insn "movdi" [(set (match_operand:DI 0 "di_operand" "=r,r,r,o<>,r") (match_operand:DI 1 "di_operand" "rK,n,o<>,r,F"))] "" "* return (output_move_double (operands)); " [(set_attr "length" "2,8,2,2,8") (set_attr "type" "*,*,load,store2,*")]) (define_expand "movsi" [(set (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))] "" " /* Everything except mem = const or mem = mem can be done easily */ if (GET_CODE (operands[0]) == MEM) operands[1] = force_reg (SImode, operands[1]); if (GET_CODE (operands[1]) == CONST_INT && !(const_ok_for_arm (INTVAL (operands[1])) || const_ok_for_arm (~INTVAL (operands[1])))) { int n = INTVAL (operands[1]); rtx tmpreg, tmpreg2; int i, n_ones = 0, first = 1, last = 0; if (GET_CODE (operands[0]) != REG && GET_CODE (operands[0]) != SUBREG) abort (); for (i = 0; i < 32; i++) if (n & 1 << i) n_ones++; /* These loops go the opposite way around to those in arm.c so that the last constant may be more likely to be eliminted into the next instruction */ if (n_ones > 16) { n = (~n) & 0xffffffff; for (i = 30; i >= 0; i -= 2) { if (n & (3 << i)) { i -= 6; if (i < 0) i = 0; if ((n & (255 << i)) == n) last = 1; if (first) { rtx equal; rtx insn = emit_insn (gen_movsi (tmpreg = (reload_in_progress || reload_completed) ? operands[0] : gen_reg_rtx (SImode), equal = gen_rtx (CONST_INT, VOIDmode, ~(n & (255 << i))))); first = 0; } else { rtx constant; rtx insn = emit_insn (gen_subsi3 (tmpreg2 = (reload_in_progress || reload_completed || last) ? operands[0] : gen_reg_rtx (SImode), tmpreg, constant = gen_rtx (CONST_INT, VOIDmode, n & (255 << i)))); tmpreg = tmpreg2; } n &= ~(255 << i); } } } else { for (i = 30; i >= 0; i -= 2) { if (n & (3 << i)) { i -= 6; if (i < 0) i = 0; if ((n & (255 << i)) == n) last = 1; if (first) { rtx equal; rtx insn = emit_insn (gen_movsi (tmpreg = (reload_in_progress || reload_completed) ? operands[0] : gen_reg_rtx (SImode), equal = gen_rtx (CONST_INT, VOIDmode, n & (255 << i)))); first = 0; } else { rtx constant; rtx insn = emit_insn (gen_addsi3 (tmpreg2 = (reload_in_progress || reload_completed || last) ? operands[0] : gen_reg_rtx (SImode), tmpreg, constant = gen_rtx (CONST_INT, VOIDmode, n & (255 << i)))); tmpreg = tmpreg2; } n &= ~(255 << i); } } } DONE; } ") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=r,r,r,m,r") (match_operand:SI 1 "general_operand" "m,K,r,r,S"))] "(register_operand (operands[0], SImode) && (GET_CODE (operands[1]) != CONST_INT || const_ok_for_arm (INTVAL (operands[1])) || const_ok_for_arm (~INTVAL (operands[1]))) && (GET_CODE (operands[1]) != SYMBOL_REF || CONSTANT_ADDRESS_P (operands[1]))) || register_operand (operands[1], SImode)" "* switch (which_alternative) { case 2: return (arm_output_asm_insn (\"mov\\t%0, %1\", operands)); case 1: if (!const_ok_for_arm (INTVAL (operands[1]))) { operands[1] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[1])); return arm_output_asm_insn (\"mvn\\t%0, %1\", operands); } return arm_output_asm_insn (\"mov\\t%0, %1\", operands); case 0: if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))) return (arm_output_llc (operands)); else return (arm_output_asm_insn (\"ldr\\t%0, %1\", operands)); case 3: return (arm_output_asm_insn (\"str\\t%1, %0\", operands)); case 4: return output_load_symbol (operands); } " [(set_attr "length" "2,*,*,*,4") (set_attr "type" "load,*,*,store1,*")]) ;; If copying one reg to another we can set the condition codes according to ;; its value. Such a move is common after a return from subroutine and the ;; result is being tested against zero. (define_insn "" [(set (reg:CC 24) (compare (match_operand:SI 1 "s_register_operand" "r") (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (match_dup 1))] "" "* if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG && REGNO (operands[0]) == REGNO (operands[1])) return arm_output_asm_insn (\"cmp\\t%0, #0\", operands); return arm_output_asm_insn (\"subs\\t%0, %1, #0\", operands); " [(set_attr "conds" "set")]) ;; Subroutine to store a half word from a register into memory. ;; Operand 0 is the source register (HImode) ;; Operand 1 is the destination address in a register (SImode) ;; In both this routine and the next, we must be careful not to spill ;; a memory address of reg+large_const into a seperate PLUS insn, since this ;; can generate unrecognizable rtl. (define_expand "storehi" [;; store the low byte (set (mem:QI (match_operand:SI 1 "" "")) (match_dup 3)) ;; extract the high byte (set (match_dup 2) (ashiftrt:SI (match_operand 0 "" "") (const_int 8))) ;; store the high byte (set (mem:QI (match_dup 4)) (subreg:QI (match_dup 2) 0))] ;explicit subreg safe "" " { enum rtx_code code = GET_CODE (operands[1]); if ((code == PLUS || code == MINUS) && (GET_CODE (XEXP (operands[1], 1)) == REG || GET_CODE (XEXP (operands[1], 0)) != REG)) operands[1] = force_reg (SImode, operands[1]); operands[4] = plus_constant (operands[1], 1); operands[3] = gen_lowpart (QImode, operands[0]); operands[0] = gen_lowpart (SImode, operands[0]); operands[2] = gen_reg_rtx (SImode); } ") ;; Subroutine to store a half word integer constant into memory. ;; Operand 0 is the constant ;; Operand 1 is the destination address in a register (SImode) (define_expand "storeinthi" [;; store the low byte (set (mem:QI (match_operand:SI 1 "" "")) (match_operand 0 "" "")) ;; store the high byte (set (mem:QI (match_dup 3)) (match_dup 2))] "" " { int value = INTVAL (operands[0]); enum rtx_code code = GET_CODE (operands[1]); if ((code == PLUS || code == MINUS) && (GET_CODE (XEXP (operands[1], 1)) == REG || GET_CODE (XEXP (operands[1], 0)) != REG)) operands[1] = force_reg (SImode, operands[1]); operands[0] = force_reg (QImode, gen_rtx (CONST_INT, VOIDmode, value & 255)); operands[2] = force_reg (QImode, gen_rtx (CONST_INT, VOIDmode,(value>>8) & 255)); operands[3] = plus_constant (operands[1], 1); } ") (define_expand "movhi" [(set (match_operand:HI 0 "general_operand" "") (match_operand:HI 1 "general_operand" ""))] "" " { rtx insn; if (reload_in_progress || reload_completed) insn = gen_rtx (SET, VOIDmode, operands[0], operands[1]); else { if (GET_CODE (operands[0]) == MEM) { if (GET_CODE (operands[1]) == CONST_INT) { insn = gen_storeinthi (operands[1], XEXP (operands[0],0)); } else { if (GET_CODE (operands[1]) == MEM) operands[1] = force_reg (HImode, operands[1]); insn = gen_storehi (operands[1], XEXP (operands[0], 0)); } } else if (GET_CODE (operands[1]) == CONST_INT && !(const_ok_for_arm (INTVAL (operands[1])) || const_ok_for_arm (~INTVAL (operands[1])))) { rtx reg, reg2; /* no need to be clever, this will always take two insns. The top sixteen bits should be all zeros or all ones. */ if (INTVAL (operands[1]) < 0) { emit_insn (gen_movsi (reg = gen_reg_rtx (SImode), GEN_INT (INTVAL (operands[1]) | ~(0x0ff00)))); emit_insn (gen_addsi3 (reg2 = gen_reg_rtx (SImode), reg, GEN_INT (-((~INTVAL (operands[1])) & 0xff)))); } else { emit_insn (gen_movsi (reg = gen_reg_rtx (SImode), GEN_INT (INTVAL (operands[1]) & 0xff00))); emit_insn (gen_addsi3 (reg2 = gen_reg_rtx (SImode), reg, GEN_INT (INTVAL (operands[1]) & 0x00ff))); } insn = gen_rtx (SET, HImode, operands[0], gen_rtx (SUBREG, HImode, reg2, 0)); } else insn = gen_rtx (SET, VOIDmode, operands[0], operands[1]); } emit_insn (insn); DONE; }") ;; Pattern to recognise insn generated default case above (define_insn "" [(set (match_operand:HI 0 "general_operand" "=r,r,r,m") (match_operand:HI 1 "general_operand" "r,K,m,r"))] "(register_operand (operands[0], HImode) && (GET_CODE (operands[1]) != CONST_INT || const_ok_for_arm (INTVAL (operands[1])) || const_ok_for_arm (~INTVAL (operands[1])))) || register_operand (operands[1], HImode)" "* switch (which_alternative) { case 1: if (!const_ok_for_arm (INTVAL (operands[1]))) { operands[1] = GEN_INT (~INTVAL (operands[1])); return arm_output_asm_insn (\"mvn\\t%0, %1\", operands); } /* fall through */ case 0: return arm_output_asm_insn (\"mov\\t%0, %1\\t@movhi\", operands); case 2: return arm_output_asm_insn (\"ldr\\t%0, %1\\t@movhi\", operands); case 3: return arm_output_asm_insn (\"str\\t%1, %0\\t@movhi\", operands); } " [(set_attr "type" "*,*,load,store1")]) (define_expand "reload_outhi" [(parallel [(match_operand:HI 0 "reload_memory_operand" "=o") (match_operand:HI 1 "s_register_operand" "r") (match_operand:SI 2 "s_register_operand" "=&r")])] "" " arm_reload_out_hi (operands); DONE; ") (define_expand "movqi" [(set (match_operand:QI 0 "general_operand" "") (match_operand:QI 1 "general_operand" ""))] "" " /* Everything except mem = const or mem = mem can be done easily */ if (!(reload_in_progress || reload_completed)) { rtx reg; if (GET_CODE (operands[1]) == CONST_INT) { emit_insn (gen_movsi (reg = gen_reg_rtx (SImode), operands[1])); operands[1] = gen_rtx (SUBREG, QImode, reg, 0); } } if (GET_CODE (operands[0]) == MEM) operands[1] = force_reg (QImode, operands[1]); ") (define_insn "" [(set (match_operand:QI 0 "general_operand" "=r,r,r,m") (match_operand:QI 1 "general_operand" "r,K,m,r"))] "register_operand (operands[0], QImode) || register_operand (operands[1], QImode)" "* switch (which_alternative) { case 1: if (INTVAL (operands[1]) < 0) { operands[1] = GEN_INT (~INTVAL (operands[1])); return arm_output_asm_insn (\"mvn\\t%0, %1\", operands); } case 0: return (arm_output_asm_insn (\"mov\\t%0, %1\", operands)); case 2: return (arm_output_asm_insn (\"ldrb\\t%0, %1\", operands)); case 3: return (arm_output_asm_insn (\"strb\\t%1, %0\", operands)); } " [(set_attr "type" "*,*,load,store1")]) (define_insn "movsf" [(set (match_operand:SF 0 "general_operand" "=f,f,f,m,f,r,r,r,m") (match_operand:SF 1 "general_operand" "fG,H,m,f,r,f,r,m,r"))] "" "* { REAL_VALUE_TYPE r; switch (which_alternative) { case 0: return arm_output_asm_insn (\"mvfs\\t%0, %1\", operands); case 1: REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); r = REAL_VALUE_NEGATE (r); operands[1] = CONST_DOUBLE_FROM_REAL_VALUE (r, GET_MODE (operands[1])); return arm_output_asm_insn (\"mnfs\\t%0, %1\", operands); case 2: return arm_output_asm_insn (\"ldfs\\t%0, %1\", operands); case 3: return arm_output_asm_insn (\"stfs\\t%1, %0\", operands); case 4: arm_output_asm_insn(\"stmfd\\tsp!, {%1}\", operands); return arm_output_asm_insn (\"ldfs\\t%0, [sp],#4\", operands); case 5: arm_output_asm_insn(\"stfs\\t%1, [sp,#-4]!\", operands); return arm_output_asm_insn (\"ldmfd\\tsp!, {%0}\", operands); case 6: return arm_output_asm_insn (\"mov\\t%0, %1\", operands); case 7: return arm_output_asm_insn (\"ldr\\t%0, %1\\t@ float\", operands); case 8: return arm_output_asm_insn (\"str\\t%1, %0\\t@ float\", operands); } } " [(set_attr "length" "1,1,1,1,2,2,1,1,1") (set_attr "type" "float,float,f_load,f_store,r_mem_f,f_mem_r,*,load,store1")]) (define_expand "movdf" [(parallel [(set (match_operand:DF 0 "general_operand" "") (match_operand:DF 1 "general_operand" "")) (clobber (match_scratch:SI 2 ""))])] "" " if (GET_CODE (operands[0]) == MEM) operands[1] = force_reg (DFmode, operands[1]); ") ;; Reloading a df mode value stored in integer regs to memory can require a ;; scratch reg. (define_expand "reload_outdf" [(parallel [(set (match_operand:DF 0 "reload_memory_operand" "=o") (match_operand:DF 1 "s_register_operand" "r")) (clobber (match_operand:SI 2 "s_register_operand" "=&r"))])] "" "") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=r,Q,r,o,f,f,f,f,m,!f,!r,r") (match_operand:DF 1 "general_operand" "Q,r,?o,?r,?f,!G,!H,m,f,r,f,??r")) (clobber (match_scratch:SI 2 "=X,X,X,&r,X,X,X,X,X,X,X,X"))] "GET_CODE (operands[0]) != MEM || register_operand (operands[1], DFmode)" "* { REAL_VALUE_TYPE r; rtx ops[3]; switch (which_alternative) { case 0: operands[1] = XEXP (operands[1], 0); return arm_output_asm_insn (\"ldmia\\t%1, {%0, %R0}\\t@ double\", operands); case 1: operands[0] = XEXP (operands[0], 0); return arm_output_asm_insn (\"stmia\\t%0, {%1, %R1}\\t@ double\", operands); case 2: ops[0] = operands[0]; ops[1] = XEXP (XEXP (operands[1], 0), 0); ops[2] = XEXP (XEXP (operands[1], 0), 1); if (!INTVAL (ops[2]) || const_ok_for_arm (INTVAL (ops[2]))) arm_output_asm_insn (\"add\\t%0, %1, %2\", ops); else arm_output_asm_insn (\"sub\\t%0, %1, #%n2\", ops); return arm_output_asm_insn (\"ldmia\\t%0, {%0, %R0}\\t@ double\", operands); case 3: ops[0] = operands[2]; ops[1] = XEXP (XEXP (operands[0], 0), 0); ops[2] = XEXP (XEXP (operands[0], 0), 1); if (!INTVAL (ops[2]) || const_ok_for_arm (INTVAL (ops[2]))) arm_output_asm_insn (\"add\\t%0, %1, %2\", ops); else arm_output_asm_insn (\"sub\\t%0, %1, #%n2\", ops); return arm_output_asm_insn (\"stmia\\t%2, {%1, %R1}\\t@ double\", operands); case 4: case 5: return arm_output_asm_insn (\"mvfd\\t%0, %1\", operands); case 6: REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); r = REAL_VALUE_NEGATE (r); operands[1] = CONST_DOUBLE_FROM_REAL_VALUE (r, GET_MODE (operands[1])); return arm_output_asm_insn (\"mnfd\\t%0, %1\", operands); case 7: return arm_output_asm_insn (\"ldfd\\t%0, %1\", operands); case 8: return arm_output_asm_insn (\"stfd\\t%1, %0\", operands); case 9: return output_mov_double_fpu_from_arm (operands); case 10: return output_mov_double_arm_from_fpu (operands); case 11: return output_move_double (operands); } } " [(set_attr "length" "1,1,2,2,1,1,1,1,1,2,2,2") (set_attr "type" "load,store2,load,store2,float,float,float,f_load,f_store,r_mem_f,f_mem_r,*")]) (define_insn "movxf" [(set (match_operand:XF 0 "general_operand" "=f,f,f,m,f,r,r") (match_operand:XF 1 "general_operand" "fG,H,m,f,r,f,r"))] "ENABLE_XF_PATTERNS" "* { REAL_VALUE_TYPE r; switch (which_alternative) { case 0: return arm_output_asm_insn (\"mvfe\\t%0, %1\", operands); case 1: REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); r = REAL_VALUE_NEGATE (r); operands[1] = CONST_DOUBLE_FROM_REAL_VALUE (r, GET_MODE (operands[1])); return arm_output_asm_insn (\"mnfe\\t%0, %1\", operands); case 2: return arm_output_asm_insn (\"ldfe\\t%0, %1\", operands); case 3: return arm_output_asm_insn (\"stfe\\t%1, %0\", operands); case 4: return output_mov_long_double_fpu_from_arm (operands); case 5: return output_mov_long_double_arm_from_fpu (operands); case 6: return output_mov_long_double_arm_from_arm (operands); } } " [(set_attr "length" "1,1,1,1,2,2,3") (set_attr "type" "float,float,f_load,f_store,r_mem_f,f_mem_r,*")]) ;; load- and store-multiple insns ;; The arm can load/store any set of registers, provided that they are in ;; ascending order; but that is beyond GCC so stick with what it knows. (define_expand "load_multiple" [(match_par_dup 3 [(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" "")) (use (match_operand:SI 2 "" ""))])] "" " /* Support only fixed point registers */ if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 14 || INTVAL (operands[2]) < 2 || GET_CODE (operands[1]) != MEM || GET_CODE (operands[0]) != REG || REGNO (operands[0]) > 14 || REGNO (operands[0]) + INTVAL (operands[2]) > 15) FAIL; operands[3] = arm_gen_load_multiple (REGNO (operands[0]), INTVAL (operands[2]), force_reg (SImode, XEXP (operands[1], 0)), TRUE, FALSE); ") ;; Load multiple with write-back (define_insn "" [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 1 "s_register_operand" "+r") (plus:SI (match_dup 1) (match_operand:SI 2 "immediate_operand" "n"))) (set (match_operand:SI 3 "s_register_operand" "=r") (mem:SI (match_dup 1)))])] "(INTVAL (operands[2]) == 4 * (XVECLEN (operands[0], 0) - 2))" "* { rtx ops[3]; int count = XVECLEN (operands[0], 0); ops[0] = XEXP (SET_SRC (XVECEXP (operands[0], 0, 0)), 0); ops[1] = SET_DEST (XVECEXP (operands[0], 0, 1)); ops[2] = SET_DEST (XVECEXP (operands[0], 0, count - 2)); return arm_output_asm_insn (\"ldmia\\t%0!, {%1-%2}\\t@ load multiple\", ops); } " [(set_attr "type" "load")]) ;; Ordinary load multiple (define_insn "" [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 1 "s_register_operand" "=r") (match_operand:SI 2 "indirect_operand" "Q"))])] "" "* { rtx ops[3]; int count = XVECLEN (operands[0], 0); ops[0] = XEXP (SET_SRC (XVECEXP (operands[0], 0, 0)), 0); ops[1] = SET_DEST (XVECEXP (operands[0], 0, 0)); ops[2] = SET_DEST (XVECEXP (operands[0], 0, count - 1)); return arm_output_asm_insn (\"ldmia\\t%0, {%1-%2}\\t@ load multiple\", ops); } " [(set_attr "type" "load")]) (define_expand "store_multiple" [(match_par_dup 3 [(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" "")) (use (match_operand:SI 2 "" ""))])] "" " /* Support only fixed point registers */ if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 14 || INTVAL (operands[2]) < 2 || GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != MEM || REGNO (operands[1]) > 14 || REGNO (operands[1]) + INTVAL (operands[2]) > 15) FAIL; operands[3] = arm_gen_store_multiple (REGNO (operands[1]), INTVAL (operands[2]), force_reg (SImode, XEXP (operands[0], 0)), TRUE, FALSE); ") ;; Store multiple with write-back (define_insn "" [(match_parallel 0 "store_multiple_operation" [(set (match_operand:SI 1 "s_register_operand" "+r") (plus:SI (match_dup 1) (match_operand:SI 2 "immediate_operand" "n"))) (set (mem:SI (match_dup 1)) (match_operand:SI 3 "s_register_operand" "r"))])] "(INTVAL (operands[2]) == 4 * (XVECLEN (operands[0], 0) - 2))" "* { rtx ops[3]; int count = XVECLEN (operands[0], 0); ops[0] = XEXP (SET_SRC (XVECEXP (operands[0], 0, 0)), 0); ops[1] = SET_SRC (XVECEXP (operands[0], 0, 1)); ops[2] = SET_SRC (XVECEXP (operands[0], 0, count - 2)); return arm_output_asm_insn (\"stmia\\t%0!, {%1-%2}\\t@ str multiple\", ops); } " [(set (attr "type") (cond [(eq (symbol_ref "XVECLEN (operands[0],0)") (const_int 4)) (const_string "store2") (eq (symbol_ref "XVECLEN (operands[0],0)") (const_int 5)) (const_string "store3")] (const_string "store4")))]) ;; Ordinary store multiple (define_insn "" [(match_parallel 0 "store_multiple_operation" [(set (match_operand:SI 2 "indirect_operand" "=Q") (match_operand:SI 1 "s_register_operand" "r"))])] "" "* { rtx ops[3]; int count = XVECLEN (operands[0], 0); ops[0] = XEXP (SET_DEST (XVECEXP (operands[0], 0, 0)), 0); ops[1] = SET_SRC (XVECEXP (operands[0], 0, 0)); ops[2] = SET_SRC (XVECEXP (operands[0], 0, count - 1)); return arm_output_asm_insn (\"stmia\\t%0, {%1-%2}\\t@ str multiple\", ops); } " [(set (attr "type") (cond [(eq (symbol_ref "XVECLEN (operands[0],0)") (const_int 3)) (const_string "store2") (eq (symbol_ref "XVECLEN (operands[0],0)") (const_int 4)) (const_string "store3")] (const_string "store4")))]) ;; Move a block of memory if it is word aligned and MORE than 2 words long. ;; We could let this apply for blocks of less than this, but it clobbers so ;; many registers that there is then probably a better way. ;; If optimizing, output redundant moves with REG_NOTES on them, this ;; produces better code. (define_expand "movstrsi" [(set (match_operand:BLK 0 "general_operand" "=m") (match_operand:BLK 1 "general_operand" "m")) (use (match_operand:SI 2 "immediate_operand" "n")) (use (match_operand:SI 3 "immediate_operand" "n")) (clobber (reg:SI 0)) (clobber (reg:SI 1)) (clobber (reg:SI 2)) (clobber (reg:SI 3)) (clobber (match_scratch:SI 4 "=+r")) (clobber (match_scratch:SI 5 "=+r"))] "" " { int words_to_go; int i, r; rtx const_sxteen = gen_rtx (CONST_INT, SImode, 16); rtx src = gen_reg_rtx (SImode); rtx dst = gen_reg_rtx (SImode); rtx st_src, st_dst, end_src, end_dst, fin_src, fin_dst; extern int optimize; if (GET_CODE (operands[2]) != CONST_INT || GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[2]) % 4 != 0 || INTVAL (operands[2]) < 4 || INTVAL (operands[2]) > 64 || INTVAL (operands[3]) < 4 || INTVAL (operands[3]) % 4 != 0) FAIL; emit_move_insn (dst, st_dst = force_reg (SImode, XEXP (operands[0], 0))); emit_move_insn (src, st_src = force_reg (SImode, XEXP (operands[1], 0))); fin_src = src; fin_dst = dst; for (i = 0, words_to_go = INTVAL (operands[2]) / 4; words_to_go >= 2; i+=4) { emit_insn (arm_gen_load_multiple (0, words_to_go > 4 ? 4 : words_to_go, src, TRUE, TRUE)); emit_insn (arm_gen_store_multiple (0, words_to_go > 4 ? 4 : words_to_go, dst, TRUE, TRUE)); if (optimize) for (r = (words_to_go > 4) ? 3 : words_to_go - 1; r >= 0; r--) { rtx note; note = emit_move_insn (gen_reg_rtx (SImode), gen_rtx (REG, SImode, r)); REG_NOTES (note) = gen_rtx (EXPR_LIST, REG_EQUIV, gen_rtx (MEM, SImode, plus_constant (st_src, 4*(i+r))), REG_NOTES (note)); REG_NOTES (note) = gen_rtx (EXPR_LIST, REG_EQUIV, gen_rtx (MEM, SImode, plus_constant (st_dst, 4*(i+r))), REG_NOTES (note)); } words_to_go -= words_to_go < 4 ? words_to_go : 4; } if (words_to_go) { rtx sreg; emit_move_insn (sreg = gen_reg_rtx (SImode), gen_rtx (MEM, SImode, src)); emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4)); emit_move_insn (gen_rtx (MEM, SImode, dst), sreg); emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4)); } if (optimize) { /* Insns for the REG_NOTES: These notes tell the optimiser where the index registers have got to so that consecutive block moves of contiguous data work efficiently */ end_src = emit_move_insn (fin_src, fin_src); REG_NOTES (end_src) = gen_rtx(EXPR_LIST, REG_EQUAL, plus_constant (st_src, INTVAL (operands[2])), REG_NOTES (end_src)); end_dst = emit_move_insn (fin_dst, fin_dst); REG_NOTES (end_dst) = gen_rtx(EXPR_LIST, REG_EQUAL, plus_constant (st_dst, INTVAL (operands[2])), REG_NOTES (end_dst)); } DONE; } ") ;; Comparison and test insns (define_expand "cmpsi" [(set (reg:CC 24) (compare:CC (match_operand:SI 0 "s_register_operand" "") (match_operand:SI 1 "arm_add_operand" "")))] "" " { arm_compare_op0 = operands[0]; arm_compare_op1 = operands[1]; arm_compare_fp = 0; DONE; } ") (define_expand "cmpsf" [(set (reg:CC 24) (compare:CC (match_operand:SF 0 "s_register_operand" "") (match_operand:SF 1 "fpu_rhs_operand" "")))] "" " { arm_compare_op0 = operands[0]; arm_compare_op1 = operands[1]; arm_compare_fp = 1; DONE; } ") (define_expand "cmpdf" [(set (reg:CC 24) (compare:CC (match_operand:DF 0 "s_register_operand" "") (match_operand:DF 1 "fpu_rhs_operand" "")))] "" " { arm_compare_op0 = operands[0]; arm_compare_op1 = operands[1]; arm_compare_fp = 1; DONE; } ") (define_expand "cmpxf" [(set (reg:CC 24) (compare:CC (match_operand:XF 0 "s_register_operand" "") (match_operand:XF 1 "fpu_rhs_operand" "")))] "ENABLE_XF_PATTERNS" " { arm_compare_op0 = operands[0]; arm_compare_op1 = operands[1]; arm_compare_fp = 1; DONE; } ") (define_insn "" [(set (match_operand 0 "cc_register" "") (compare (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_add_operand" "rL")))] "" "* if (GET_CODE (operands[2]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[2]))) return arm_output_asm_insn (\"cmn\\t%1, #%n2\", operands); return arm_output_asm_insn (\"cmp\\t%1, %2\", operands); " [(set_attr "conds" "set")]) (define_insn "" [(set (match_operand 0 "cc_register" "") (compare (match_operand:SI 1 "s_register_operand" "r") (neg:SI (match_operand:SI 2 "s_register_operand" "r"))))] "" "* return arm_output_asm_insn (\"cmn\\t%1, %2\", operands); " [(set_attr "conds" "set")]) (define_insn "" [(set (match_operand 0 "cc_register" "") (compare (match_operand:SI 1 "s_register_operand" "r") (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "arm_rhs_operand" "rn")])))] "" "* return output_shift_compare (operands, FALSE); " [(set_attr "conds" "set")]) (define_insn "" [(set (match_operand 0 "cc_register" "") (compare (match_operand:SI 1 "s_register_operand" "r") (neg:SI (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "arm_rhs_operand" "rn")]))))] "" "* return output_shift_compare (operands, TRUE); " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CCFP 24) (compare:CCFP (match_operand:SF 0 "s_register_operand" "f,f") (match_operand:SF 1 "fpu_add_operand" "fG,H")))] "" "* { REAL_VALUE_TYPE r; switch (which_alternative) { case 0: return arm_output_asm_insn (\"cmf\\t%0, %1\", operands); case 1: REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); r = REAL_VALUE_NEGATE (r); operands[1] = CONST_DOUBLE_FROM_REAL_VALUE (r, GET_MODE (operands[1])); return arm_output_asm_insn (\"cnf\\t%0, %1\", operands); } } " [(set_attr "conds" "set") (set_attr "type" "f_2_r")]) (define_insn "" [(set (reg:CCFP 24) (compare:CCFP (match_operand:DF 0 "s_register_operand" "f,f") (match_operand:DF 1 "fpu_add_operand" "fG,H")))] "" "* { REAL_VALUE_TYPE r; switch (which_alternative) { case 0: return arm_output_asm_insn (\"cmf\\t%0, %1\", operands); case 1: REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); r = REAL_VALUE_NEGATE (r); operands[1] = CONST_DOUBLE_FROM_REAL_VALUE (r, GET_MODE (operands[1])); return arm_output_asm_insn (\"cnf\\t%0, %1\", operands); } } " [(set_attr "conds" "set") (set_attr "type" "f_2_r")]) (define_insn "" [(set (reg:CCFP 24) (compare:CCFP (float_extend:DF (match_operand:SF 0 "s_register_operand" "f,f")) (match_operand:DF 1 "fpu_add_operand" "fG,H")))] "" "* { REAL_VALUE_TYPE r; switch (which_alternative) { case 0: return arm_output_asm_insn (\"cmf\\t%0, %1\", operands); case 1: REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); r = REAL_VALUE_NEGATE (r); operands[1] = CONST_DOUBLE_FROM_REAL_VALUE (r, GET_MODE (operands[1])); return arm_output_asm_insn (\"cnf\\t%0, %1\", operands); } } " [(set_attr "conds" "set") (set_attr "type" "f_2_r")]) (define_insn "" [(set (reg:CCFP 24) (compare:CCFP (match_operand:DF 0 "s_register_operand" "f") (float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))))] "" "* return arm_output_asm_insn (\"cmf\\t%0, %1\", operands); " [(set_attr "conds" "set") (set_attr "type" "f_2_r")]) (define_insn "" [(set (reg:CCFP 24) (compare:CCFP (match_operand:XF 0 "s_register_operand" "f,f") (match_operand:XF 1 "fpu_add_operand" "fG,H")))] "ENABLE_XF_PATTERNS" "* { REAL_VALUE_TYPE r; switch (which_alternative) { case 0: return arm_output_asm_insn (\"cmf\\t%0, %1\", operands); case 1: REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); r = REAL_VALUE_NEGATE (r); operands[1] = CONST_DOUBLE_FROM_REAL_VALUE (r, GET_MODE (operands[1])); return arm_output_asm_insn (\"cnf\\t%0, %1\", operands); } } " [(set_attr "conds" "set") (set_attr "type" "f_2_r")]) (define_insn "" [(set (reg:CCFPE 24) (compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f") (match_operand:SF 1 "fpu_add_operand" "fG,H")))] "" "* { REAL_VALUE_TYPE r; switch (which_alternative) { case 0: return arm_output_asm_insn (\"cmfe\\t%0, %1\", operands); case 1: REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); r = REAL_VALUE_NEGATE (r); operands[1] = CONST_DOUBLE_FROM_REAL_VALUE (r, GET_MODE (operands[1])); return arm_output_asm_insn (\"cnfe\\t%0, %1\", operands); } } " [(set_attr "conds" "set") (set_attr "type" "f_2_r")]) (define_insn "" [(set (reg:CCFPE 24) (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f,f") (match_operand:DF 1 "fpu_add_operand" "fG,H")))] "" "* { REAL_VALUE_TYPE r; switch (which_alternative) { case 0: return arm_output_asm_insn (\"cmfe\\t%0, %1\", operands); case 1: REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); r = REAL_VALUE_NEGATE (r); operands[1] = CONST_DOUBLE_FROM_REAL_VALUE (r, GET_MODE (operands[1])); return arm_output_asm_insn (\"cnfe\\t%0, %1\", operands); } } " [(set_attr "conds" "set") (set_attr "type" "f_2_r")]) (define_insn "" [(set (reg:CCFPE 24) (compare:CCFPE (float_extend:DF (match_operand:SF 0 "s_register_operand" "f,f")) (match_operand:DF 1 "fpu_add_operand" "fG,H")))] "" "* { REAL_VALUE_TYPE r; switch (which_alternative) { case 0: return arm_output_asm_insn (\"cmfe\\t%0, %1\", operands); case 1: REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); r = REAL_VALUE_NEGATE (r); operands[1] = CONST_DOUBLE_FROM_REAL_VALUE (r, GET_MODE (operands[1])); return arm_output_asm_insn (\"cnfe\\t%0, %1\", operands); } } " [(set_attr "conds" "set") (set_attr "type" "f_2_r")]) (define_insn "" [(set (reg:CCFPE 24) (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f") (float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))))] "" "* return arm_output_asm_insn (\"cmfe\\t%0, %1\", operands); " [(set_attr "conds" "set") (set_attr "type" "f_2_r")]) (define_insn "" [(set (reg:CCFPE 24) (compare:CCFPE (match_operand:XF 0 "s_register_operand" "f,f") (match_operand:XF 1 "fpu_add_operand" "fG,H")))] "ENABLE_XF_PATTERNS" "* { REAL_VALUE_TYPE r; switch (which_alternative) { case 0: return arm_output_asm_insn (\"cmfe\\t%0, %1\", operands); case 1: REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); r = REAL_VALUE_NEGATE (r); operands[1] = CONST_DOUBLE_FROM_REAL_VALUE (r, GET_MODE (operands[1])); return arm_output_asm_insn (\"cnfe\\t%0, %1\", operands); } } " [(set_attr "conds" "set") (set_attr "type" "f_2_r")]) ; This insn allows redundant compares to be removed by cse, nothing should ; ever appear in the output file since (set (reg x) (reg x)) is a no-op that ; is deleted later on. The match_dup will match the mode here, so that ; mode changes of the condition codes aren't lost by this even though we don't ; specify what they are. (define_insn "" [(set (match_operand 0 "cc_register" "") (match_dup 0))] "" "\\t@ deleted compare" [(set_attr "conds" "set") (set_attr "length" "0")]) ;; Conditional branch insns (define_expand "beq" [(set (pc) (if_then_else (eq (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "bne" [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (NE, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "bgt" [(set (pc) (if_then_else (gt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (GT, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "ble" [(set (pc) (if_then_else (le (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (LE, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "bge" [(set (pc) (if_then_else (ge (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (GE, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "blt" [(set (pc) (if_then_else (lt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (LT, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "bgtu" [(set (pc) (if_then_else (gtu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "bleu" [(set (pc) (if_then_else (leu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "bgeu" [(set (pc) (if_then_else (geu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "bltu" [(set (pc) (if_then_else (ltu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") ;; patterns to match conditional branch insns (define_insn "" [(set (pc) (if_then_else (match_operator 1 "comparison_operator" [(reg 24) (const_int 0)]) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { extern int arm_ccfsm_state; if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) { arm_ccfsm_state += 2; return \"\"; } return (arm_output_asm_insn (\"b%d1\\t%l0\", operands)); }" [(set_attr "conds" "use")]) (define_insn "" [(set (pc) (if_then_else (match_operator 1 "comparison_operator" [(reg 24) (const_int 0)]) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { extern int arm_ccfsm_state; if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) { arm_ccfsm_state += 2; return \"\"; } return (arm_output_asm_insn (\"b%D1\\t%l0\", operands)); }" [(set_attr "conds" "use")]) ; scc insns (define_expand "seq" [(set (match_operand:SI 0 "s_register_operand" "=r") (eq:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "sne" [(set (match_operand:SI 0 "s_register_operand" "=r") (ne:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (NE, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "sgt" [(set (match_operand:SI 0 "s_register_operand" "=r") (gt:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (GT, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "sle" [(set (match_operand:SI 0 "s_register_operand" "=r") (le:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (LE, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "sge" [(set (match_operand:SI 0 "s_register_operand" "=r") (ge:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (GE, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "slt" [(set (match_operand:SI 0 "s_register_operand" "=r") (lt:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (LT, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "sgtu" [(set (match_operand:SI 0 "s_register_operand" "=r") (gtu:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "sleu" [(set (match_operand:SI 0 "s_register_operand" "=r") (leu:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "sgeu" [(set (match_operand:SI 0 "s_register_operand" "=r") (geu:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_expand "sltu" [(set (match_operand:SI 0 "s_register_operand" "=r") (ltu:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1, arm_compare_fp); } ") (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (match_operator:SI 1 "comparison_operator" [(reg 24) (const_int 0)]))] "" "* arm_output_asm_insn (\"mov%d1\\t%0, #1\", operands); return arm_output_asm_insn (\"mov%D1\\t%0, #0\", operands); " [(set_attr "conds" "use") (set_attr "length" "2")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (neg:SI (match_operator:SI 1 "comparison_operator" [(reg 24) (const_int 0)])))] "" "* arm_output_asm_insn (\"mvn%d1\\t%0, #0\", operands); return arm_output_asm_insn (\"mov%D1\\t%0, #0\", operands); " [(set_attr "conds" "use") (set_attr "length" "2")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (not:SI (match_operator:SI 1 "comparison_operator" [(reg 24) (const_int 0)])))] "" "* arm_output_asm_insn (\"mvn%d1\\t%0, #1\", operands); return arm_output_asm_insn (\"mov%D1\\t%0, #0\", operands); " [(set_attr "conds" "use") (set_attr "length" "2")]) ;; Jump and linkage insns (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "* { extern int arm_ccfsm_state; if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) { arm_ccfsm_state += 2; return \"\"; } return (arm_output_asm_insn (\"b\\t%l0\", operands)); }") (define_expand "call" [(parallel [(call (match_operand 0 "memory_operand" "") (match_operand 1 "general_operand" "")) (clobber (reg:SI 14))])] "" "") (define_insn "" [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r")) (match_operand 1 "" "g")) (clobber (reg:SI 14))] "" "* return (output_call (operands)); " [(set (attr "conds") (if_then_else (eq_attr "cpu" "arm6") (const_string "clob") (const_string "nocond"))) ;; length is worst case, normally it is only two (set_attr "length" "3") (set_attr "type" "call")]) (define_insn "" [(call (mem:SI (match_operand 0 "memory_operand" "m")) (match_operand 1 "general_operand" "g")) (clobber (reg:SI 14))] "" "* return (output_call_mem (operands)); " [(set (attr "conds") (if_then_else (eq_attr "cpu" "arm6") (const_string "clob") (const_string "nocond"))) (set_attr "length" "3") (set_attr "type" "call")]) (define_expand "call_value" [(parallel [(set (match_operand 0 "" "=rf") (call (match_operand 1 "memory_operand" "m") (match_operand 2 "general_operand" "g"))) (clobber (reg:SI 14))])] "" "") (define_insn "" [(set (match_operand 0 "" "=rf") (call (mem:SI (match_operand:SI 1 "s_register_operand" "r")) (match_operand 2 "general_operand" "g"))) (clobber (reg:SI 14))] "" "* return (output_call (&operands[1])); " [(set (attr "conds") (if_then_else (eq_attr "cpu" "arm6") (const_string "clob") (const_string "nocond"))) (set_attr "length" "3") (set_attr "type" "call")]) (define_insn "" [(set (match_operand 0 "" "=rf") (call (mem:SI (match_operand 1 "memory_operand" "m")) (match_operand 2 "general_operand" "g"))) (clobber (reg:SI 14))] "! CONSTANT_ADDRESS_P (XEXP (operands[1], 0))" "* return (output_call_mem (&operands[1])); " [(set (attr "conds") (if_then_else (eq_attr "cpu" "arm6") (const_string "clob") (const_string "nocond"))) (set_attr "length" "3") (set_attr "type" "call")]) ;; Allow calls to SYMBOL_REFs specially as they are not valid general addresses ;; The 'a' causes the operand to be treated as an address, i.e. no '#' output. (define_insn "" [(call (mem:SI (match_operand:SI 0 "" "i")) (match_operand:SI 1 "general_operand" "g")) (clobber (reg:SI 14))] "GET_CODE (operands[0]) == SYMBOL_REF" "* return (arm_output_asm_insn (\"bl\\t%a0\", operands)); " [(set (attr "conds") (if_then_else (eq_attr "cpu" "arm6") (const_string "clob") (const_string "nocond"))) (set_attr "type" "call")]) (define_insn "" [(set (match_operand 0 "s_register_operand" "=rf") (call (mem:SI (match_operand:SI 1 "" "i")) (match_operand:SI 2 "general_operand" "g"))) (clobber (reg:SI 14))] "GET_CODE(operands[1]) == SYMBOL_REF" "* return (arm_output_asm_insn (\"bl\\t%a1\", operands)); " [(set (attr "conds") (if_then_else (eq_attr "cpu" "arm6") (const_string "clob") (const_string "nocond"))) (set_attr "type" "call")]) ;; Often the return insn will be the same as loading from memory, so set attr (define_insn "return" [(return)] "USE_RETURN_INSN" "* { extern int arm_ccfsm_state; if (arm_ccfsm_state == 2) { arm_ccfsm_state += 2; return \"\"; } return output_return_instruction (NULL, TRUE); }" [(set_attr "type" "load")]) (define_insn "" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(reg 24) (const_int 0)]) (return) (pc)))] "USE_RETURN_INSN" "* { extern int arm_ccfsm_state; if (arm_ccfsm_state == 2) { arm_ccfsm_state += 2; return \"\"; } return output_return_instruction (operands[0], TRUE); }" [(set_attr "conds" "use") (set_attr "type" "load")]) (define_insn "" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(reg 24) (const_int 0)]) (pc) (return)))] "USE_RETURN_INSN" "* { extern int arm_ccfsm_state; if (arm_ccfsm_state == 2) { arm_ccfsm_state += 2; return \"\"; } return output_return_instruction (gen_rtx (reverse_condition (GET_CODE (operands[0])), GET_MODE (operands[0]), XEXP (operands[0], 0), XEXP (operands[0], 1)), TRUE); }" [(set_attr "conds" "use") (set_attr "type" "load")]) ;; Call subroutine returning any type. (define_expand "untyped_call" [(parallel [(call (match_operand 0 "" "") (const_int 0)) (match_operand 1 "" "") (match_operand 2 "" "")])] "" " { int i; emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); for (i = 0; i < XVECLEN (operands[2], 0); i++) { rtx set = XVECEXP (operands[2], 0, i); emit_move_insn (SET_DEST (set), SET_SRC (set)); } /* The optimizer does not know that the call sets the function value registers we stored in the result block. We avoid problems by claiming that all hard registers are used and clobbered at this point. */ emit_insn (gen_blockage ()); DONE; }") ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and ;; all of memory. This blocks insns from being moved across this point. (define_insn "blockage" [(unspec_volatile [(const_int 0)] 0)] "" "" [(set_attr "length" "0") (set_attr "type" "block")]) (define_insn "tablejump" [(set (pc) (match_operand:SI 0 "s_register_operand" "r")) (use (label_ref (match_operand 1 "" "")))] "" "* return arm_output_asm_insn (\"mov\\tpc, %0\\t@ table jump, label %l1\", operands); ") (define_insn "" [(set (pc) (match_operand:SI 0 "memory_operand" "m")) (use (label_ref (match_operand 1 "" "")))] "" "* return arm_output_asm_insn (\"ldr\\tpc, %0\\t@ table jump, label %l1\", operands); " [(set_attr "type" "load")]) (define_insn "indirect_jump" [(set (pc) (match_operand:SI 0 "s_register_operand" "r"))] "" "* return arm_output_asm_insn (\"mov\\tpc, %0\\t@ indirect jump\", operands); ") (define_insn "" [(set (pc) (match_operand:SI 0 "memory_operand" "m"))] "" "* return arm_output_asm_insn (\"ldr\\tpc, %0\\t@ indirect jump\", operands); " [(set_attr "type" "load")]) ;; Misc insns (define_insn "nop" [(const_int 0)] "" "* return arm_output_asm_insn (\"mov\\tr0, r0\\t@ nop\", operands); ") ;; Patterns to allow combination of arithmetic, cond code and shifts (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (match_operator:SI 1 "shiftable_operator" [(match_operator:SI 3 "shift_operator" [(match_operand:SI 4 "s_register_operand" "r") (match_operand:SI 5 "nonmemory_operand" "rI")]) (match_operand:SI 2 "s_register_operand" "r")]))] "" "* return (output_arithmetic_with_shift (operands, TRUE, FALSE)); ") (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator" [(match_operator:SI 3 "shift_operator" [(match_operand:SI 4 "s_register_operand" "r") (match_operand:SI 5 "nonmemory_operand" "rI")]) (match_operand:SI 2 "s_register_operand" "r")]) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (match_op_dup 1 [(match_op_dup 3 [(match_dup 4) (match_dup 5)]) (match_dup 2)]))] "" "* return (output_arithmetic_with_shift (operands, TRUE, TRUE)); " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator" [(match_operator:SI 3 "shift_operator" [(match_operand:SI 4 "s_register_operand" "r") (match_operand:SI 5 "nonmemory_operand" "rI")]) (match_operand:SI 2 "s_register_operand" "r")]) (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] "" "* return (output_arithmetic_with_shift (operands, TRUE, TRUE)); " [(set_attr "conds" "set")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (minus:SI (match_operand:SI 1 "s_register_operand" "r") (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "nonmemory_operand" "rn")])))] "" "* { rtx ops[6]; ops[0] = operands[0]; ops[1] = gen_rtx (MINUS, SImode, operands[1], operands[2]); ops[2] = operands[1]; ops[3] = operands[2]; ops[4] = operands[3]; ops[5] = operands[4]; return output_arithmetic_with_shift (ops, FALSE, FALSE); } ") (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (minus:SI (match_operand:SI 1 "s_register_operand" "r") (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "nonmemory_operand" "rn")])) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) (match_dup 4)])))] "" "* { rtx ops[6]; ops[0] = operands[0]; ops[1] = gen_rtx (MINUS, SImode, operands[1], operands[2]); ops[2] = operands[1]; ops[3] = operands[2]; ops[4] = operands[3]; ops[5] = operands[4]; return output_arithmetic_with_shift (ops, FALSE, TRUE); } " [(set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (minus:SI (match_operand:SI 1 "s_register_operand" "r") (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "nonmemory_operand" "rn")])) (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] "" "* { rtx ops[6]; ops[0] = operands[0]; ops[1] = gen_rtx (MINUS, SImode, operands[1], operands[2]); ops[2] = operands[1]; ops[3] = operands[2]; ops[4] = operands[3]; ops[5] = operands[4]; return output_arithmetic_with_shift (ops, FALSE, TRUE); } " [(set_attr "conds" "set")]) ;; These variants of the above insns can occur if the first operand is the ;; frame pointer and we eliminate that. This is a kludge, but there doesn't ;; seem to be a way around it. Most of the predicates have to be null ;; because the format can be generated part way through reload, so ;; if we don't match it as soon as it becomes available, reload doesn't know ;; how to reload pseudos that haven't got hard registers; the constraints will ;; sort everything out. (define_insn "" [(set (match_operand:SI 0 "" "=&r") (plus:SI (plus:SI (match_operator:SI 5 "shift_operator" [(match_operand:SI 3 "" "r") (match_operand:SI 4 "" "rn")]) (match_operand:SI 2 "" "r")) (match_operand:SI 1 "const_int_operand" "n")))] "reload_in_progress" "* { char instr[100]; sprintf (instr, \"add\\t%%0, %%2, %%3, %s %%4\", shift_instr (GET_CODE (operands[5]), &operands[4])); arm_output_asm_insn (instr, operands); operands[2] = operands[1]; operands[1] = operands[0]; return output_add_immediate (operands); }" ; we have no idea how long the add_immediate is, it could be up to 4. [(set_attr "length" "5")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (plus:SI (plus:SI (match_operator:SI 5 "shift_operator" [(match_operand:SI 3 "" "r") (match_operand:SI 4 "" "rn")]) (match_operand:SI 1 "" "r")) (match_operand:SI 2 "const_int_operand" "n")) (const_int 0))) (set (match_operand:SI 0 "" "=&r") (plus:SI (plus:SI (match_op_dup 5 [(match_dup 3) (match_dup 4)]) (match_dup 1)) (match_dup 2)))] "reload_in_progress" "* { char instr[100]; sprintf (instr, \"adds\\t%%0, %%0, %%3, %s %%4\", shift_instr (GET_CODE (operands[5]), &operands[4])); output_add_immediate (operands); return arm_output_asm_insn (instr, operands); }" [(set_attr "conds" "set") (set_attr "length" "5")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (plus:SI (plus:SI (match_operator:SI 5 "shift_operator" [(match_operand:SI 3 "" "r") (match_operand:SI 4 "" "rn")]) (match_operand:SI 1 "" "r")) (match_operand:SI 2 "const_int_operand" "n")) (const_int 0))) (clobber (match_scratch:SI 0 "=&r"))] "reload_in_progress" "* { char instr[100]; sprintf (instr, \"adds\\t%%0, %%0, %%3, %s %%4\", shift_instr (GET_CODE (operands[5]), &operands[4])); output_add_immediate (operands); return arm_output_asm_insn (instr, operands); }" [(set_attr "conds" "set") (set_attr "length" "5")]) ;; These are similar, but are needed when the mla pattern contains the ;; eliminated register as operand 3. (define_insn "" [(set (match_operand:SI 0 "" "=&r,&r") (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "" "%0,r") (match_operand:SI 2 "" "r,r")) (match_operand:SI 3 "" "r,r")) (match_operand:SI 4 "const_int_operand" "n,n")))] "reload_in_progress" "* arm_output_asm_insn (\"mla\\t%0, %2, %1, %3\", operands); operands[2] = operands[4]; operands[1] = operands[0]; return output_add_immediate (operands); " [(set_attr "length" "5")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (plus:SI (plus:SI (mult:SI (match_operand:SI 3 "" "r") (match_operand:SI 4 "" "r")) (match_operand:SI 1 "" "r")) (match_operand:SI 2 "const_int_operand" "n")) (const_int 0))) (set (match_operand:SI 0 "" "=&r") (plus:SI (plus:SI (mult:SI (match_dup 3) (match_dup 4)) (match_dup 1)) (match_dup 2)))] "reload_in_progress" "* output_add_immediate (operands); return arm_output_asm_insn (\"mlas\\t%0, %3, %4, %0\", operands); " [(set_attr "length" "5") (set_attr "conds" "set")]) (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (plus:SI (plus:SI (mult:SI (match_operand:SI 3 "" "r") (match_operand:SI 4 "" "r")) (match_operand:SI 1 "" "r")) (match_operand:SI 2 "const_int_operand" "n")) (const_int 0))) (clobber (match_scratch:SI 0 "=&r"))] "reload_in_progress" "* output_add_immediate (operands); return arm_output_asm_insn (\"mlas\\t%0, %3, %4, %0\", operands); " [(set_attr "length" "5") (set_attr "conds" "set")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (and:SI (match_operator 1 "comparison_operator" [(reg 24) (const_int 0)]) (match_operand:SI 2 "s_register_operand" "r")))] "" "* arm_output_asm_insn (\"mov%D1\\t%0, #0\", operands); return arm_output_asm_insn (\"and%d1\\t%0, %2, #1\", operands); " [(set_attr "conds" "use") (set_attr "length" "2")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (ior:SI (match_operator 2 "comparison_operator" [(reg 24) (const_int 0)]) (match_operand:SI 1 "s_register_operand" "0,?r")))] "" "* if (which_alternative != 0) arm_output_asm_insn (\"mov%D2\\t%0, %1\", operands); return arm_output_asm_insn (\"orr%d2\\t%0, %1, #1\", operands); " [(set_attr "conds" "use") (set_attr "length" "1,2")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (match_operator 1 "comparison_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_add_operand" "rL")])) (clobber (reg 24))] "" "* if (GET_CODE (operands[1]) == LT && operands[3] == const0_rtx) return arm_output_asm_insn (\"mov\\t%0, %2, lsr #31\", operands); if (GET_CODE (operands[1]) == GE && operands[3] == const0_rtx) { arm_output_asm_insn (\"mvn\\t%0, %2\", operands); return arm_output_asm_insn (\"mov\\t%0, %0, lsr #31\", operands); } if (GET_CODE (operands[1]) == NE) { if (GET_CODE (operands[3]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[3]))) arm_output_asm_insn (\"adds\\t%0, %2, #%n3\", operands); else arm_output_asm_insn (\"subs\\t%0, %2, %3\", operands); return arm_output_asm_insn (\"movne\\t%0, #1\", operands); } if (GET_CODE (operands[3]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[3]))) arm_output_asm_insn (\"cmn\\t%2, #%n3\", operands); else arm_output_asm_insn (\"cmp\\t%2, %3\", operands); arm_output_asm_insn (\"mov%D1\\t%0, #0\", operands); return arm_output_asm_insn (\"mov%d1\\t%0, #1\", operands); " [(set_attr "conds" "clob") (set_attr "length" "3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=&r") (ior:SI (match_operator 1 "comparison_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_rhs_operand" "rI")]) (match_operator 4 "comparison_operator" [(match_operand:SI 5 "s_register_operand" "r") (match_operand:SI 6 "arm_rhs_operand" "rI")]))) (clobber (reg 24))] "" "* { int dominant = comparison_dominates_p (GET_CODE (operands[4]), GET_CODE (operands[1])); arm_output_asm_insn (dominant ? \"cmp\\t%5, %6\" : \"cmp\\t%2, %3\", operands); arm_output_asm_insn (\"mov\\t%0, #0\", operands); if (GET_CODE (operands[1]) == GET_CODE (operands[4]) || comparison_dominates_p (GET_CODE (operands[1]), GET_CODE (operands[4])) || dominant) { arm_output_asm_insn (dominant ? \"cmp%D4\\t%2, %3\" : \"cmp%D1\\t%5,%6\", operands); } else { arm_output_asm_insn (\"mov%d1\\t%0, #1\", operands); arm_output_asm_insn (\"cmp\\t%5, %6\", operands); } return arm_output_asm_insn (dominant ? \"mov%d1\\t%0, #1\" : \"mov%d4\\t%0, #1\", operands); } " [(set_attr "conds" "clob") ; worst case length (set_attr "length" "5")]) (define_split [(set (pc) (if_then_else (match_operator 5 "equality_operator" [(ior:SI (match_operator 6 "comparison_operator" [(match_operand:SI 0 "s_register_operand" "r") (match_operand:SI 1 "arm_add_operand" "rL")]) (match_operator 7 "comparison_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_add_operand" "rL")])) (const_int 0)]) (label_ref (match_operand 4 "" "")) (pc))) (clobber (reg 24))] "(GET_CODE (operands[6]) == GET_CODE (operands[7]) || comparison_dominates_p (GET_CODE (operands[6]), GET_CODE (operands[7])) || comparison_dominates_p (GET_CODE (operands[7]), GET_CODE (operands[6])))" [(set (reg:CC 24) (compare:CC (ior:CC (match_op_dup 6 [(match_dup 0) (match_dup 1)]) (match_op_dup 7 [(match_dup 2) (match_dup 3)])) (const_int 0))) (set (pc) (if_then_else (match_op_dup 5 [(reg:CC 24) (const_int 0)]) (label_ref (match_dup 4)) (pc)))] " { enum rtx_code code = comparison_dominates_p (GET_CODE (operands[6]), GET_CODE (operands[7])) ? GET_CODE (operands[7]) : GET_CODE (operands[6]); if (GET_CODE (operands[5]) == NE) operands[5] = gen_rtx (code, CCmode, XEXP (operands[5], 0), XEXP (operands[5], 1)); else operands[5] = gen_rtx (reverse_condition (code), CCmode, XEXP (operands[5], 0), XEXP (operands[5], 1)); } ") ;; Don't match these patterns if we can use a conditional compare, since they ;; tell the final prescan branch elimator code that full branch inlining ;; can't be done. (define_insn "" [(set (pc) (if_then_else (ne (ior:SI (match_operator 5 "comparison_operator" [(match_operand:SI 0 "s_register_operand" "r") (match_operand:SI 1 "arm_add_operand" "rL")]) (match_operator 6 "comparison_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_rhs_operand" "rL")])) (const_int 0)) (label_ref (match_operand 4 "" "")) (pc))) (clobber (reg 24))] "!(GET_CODE (operands[5]) == GET_CODE (operands[6]) || comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[6])) || comparison_dominates_p (GET_CODE (operands[6]), GET_CODE (operands[5])))" "* { extern int arm_ccfsm_state; if (GET_CODE (operands[1]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[1]))) arm_output_asm_insn (\"cmn\\t%0, #%n1\", operands); else arm_output_asm_insn (\"cmp\\t%0, %1\", operands); arm_output_asm_insn (\"b%d5\\t%l4\", operands); if (GET_CODE (operands[3]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[3]))) arm_output_asm_insn (\"cmn\\t%2, #%n3\", operands); else arm_output_asm_insn (\"cmp\\t%2, %3\", operands); if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) { arm_ccfsm_state += 2; return \"\"; } return arm_output_asm_insn (\"b%d6\\t%l4\", operands); }" [(set_attr "conds" "jump_clob") (set_attr "length" "4")]) (define_insn "" [(set (reg:CC 24) (compare:CC (ior:CC (match_operator 4 "comparison_operator" [(match_operand:SI 0 "s_register_operand" "r") (match_operand:SI 1 "arm_add_operand" "rL")]) (match_operator 5 "comparison_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_add_operand" "rL")])) (const_int 0)))] "(GET_CODE (operands[4]) == GET_CODE (operands[5]) || comparison_dominates_p (GET_CODE (operands[4]), GET_CODE (operands[5])) || comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4])))" "* if (comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]))) { if (GET_CODE (operands[3]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[3]))) arm_output_asm_insn (\"cmn\\t%2, #%n3\", operands); else arm_output_asm_insn (\"cmp\\t%2, %3\", operands); if (GET_CODE (operands[1]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[1]))) return arm_output_asm_insn (\"cmn%D5\\t%0, #%n1\", operands); return arm_output_asm_insn (\"cmp%D5\\t%0, %1\", operands); } if (GET_CODE (operands[1]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[1]))) arm_output_asm_insn (\"cmn\\t%0, #%n1\", operands); else arm_output_asm_insn (\"cmp\\t%0, %1\", operands); if (GET_CODE (operands[3]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[3]))) return arm_output_asm_insn (\"cmn%D4\\t%2, #%n3\", operands); return arm_output_asm_insn (\"cmp%D4\\t%2, %3\", operands); " [(set_attr "conds" "set") (set_attr "length" "2")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (if_then_else (match_operator 3 "equality_operator" [(match_operator 4 "comparison_operator" [(reg 24) (const_int 0)]) (const_int 0)]) (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))] "" "* if (GET_CODE (operands[3]) == NE) { if (which_alternative != 0) arm_output_asm_insn (\"mov%d4\\t%0, %1\", operands); if (which_alternative != 1) arm_output_asm_insn (\"mov%D4\\t%0, %2\", operands); return \"\"; } if (which_alternative != 0) arm_output_asm_insn (\"mov%D4\\t%0, %1\", operands); if (which_alternative != 1) arm_output_asm_insn (\"mov%d4\\t%0, %2\", operands); return \"\"; " [(set_attr "conds" "use") (set_attr "length" "1,1,2")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (match_operator:SI 5 "shiftable_operator" [(match_operator:SI 4 "comparison_operator" [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) (match_operand:SI 1 "s_register_operand" "0,?r")])) (clobber (reg 24))] "" "* { char *instr = arithmetic_instr (operands[5], TRUE); char pattern[100]; if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx) { sprintf (pattern, \"%s\\t%%0, %%1, %%2, lsr #31\", instr); return arm_output_asm_insn (pattern, operands); } arm_output_asm_insn (\"cmp\\t%2, %3\", operands); if (GET_CODE (operands[5]) == AND) arm_output_asm_insn (\"mov%D4\\t%0, #0\", operands); else if (which_alternative != 0) arm_output_asm_insn (\"mov%D4\\t%0, %1\", operands); sprintf (pattern, \"%s%%d4\\t%%0, %%1, #1\", instr); return arm_output_asm_insn (pattern, operands); } " [(set_attr "conds" "clob") (set_attr "length" "3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") (match_operator:SI 4 "comparison_operator" [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) (clobber (reg 24))] "" "* arm_output_asm_insn (\"cmp\\t%2, %3\", operands); if (which_alternative != 0) arm_output_asm_insn (\"mov%D4\\t%0, %1\", operands); return arm_output_asm_insn (\"sub%d4\\t%0, %1, #1\", operands); " [(set_attr "conds" "clob") (set_attr "length" "2,3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=&r") (and:SI (match_operator 1 "comparison_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_rhs_operand" "rI")]) (match_operator 4 "comparison_operator" [(match_operand:SI 5 "s_register_operand" "r") (match_operand:SI 6 "arm_rhs_operand" "rI")]))) (clobber (reg 24))] "" "* { int dominant = comparison_dominates_p (reverse_condition (GET_CODE (operands[1])), reverse_condition (GET_CODE (operands[4]))) ? 1 : comparison_dominates_p (reverse_condition (GET_CODE (operands[4])), reverse_condition (GET_CODE (operands[1]))) ? 2 : 0; arm_output_asm_insn (dominant == 2 ? \"cmp\\t%5, %6\" : \"cmp\\t%2, %3\", operands); arm_output_asm_insn (\"mov\\t%0, #1\", operands); if (GET_CODE (operands[1]) == GET_CODE (operands[4]) || dominant) { arm_output_asm_insn (dominant == 2 ? \"cmp%d4\\t%2, %3\" : \"cmp%d1\\t%5, %6\", operands); } else { arm_output_asm_insn (\"mov%D1\\t%0, #0\", operands); arm_output_asm_insn (\"cmp\\t%5, %6\", operands); } return arm_output_asm_insn (dominant == 2 ? \"mov%D1\\t%0, #0\" : \"mov%D4\\t%0, #0\", operands); } " [(set_attr "conds" "clob") (set_attr "length" "5")]) (define_split [(set (pc) (if_then_else (match_operator 1 "equality_operator" [(and:SI (match_operator 2 "comparison_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "arm_add_operand" "rL")]) (match_operator 0 "comparison_operator" [(match_operand:SI 5 "s_register_operand" "r") (match_operand:SI 6 "arm_add_operand" "rL")])) (const_int 0)]) (label_ref (match_operand 7 "" "")) (pc))) (clobber (reg 24))] "(GET_CODE (operands[2]) == GET_CODE (operands[0]) || comparison_dominates_p (reverse_condition (GET_CODE (operands[2])), reverse_condition (GET_CODE (operands[0]))) || comparison_dominates_p (reverse_condition (GET_CODE (operands[0])), reverse_condition (GET_CODE (operands[2]))))" [(set (reg:CC 24) (compare:CC (ior:CC (match_op_dup 2 [(match_dup 3) (match_dup 4)]) (match_op_dup 0 [(match_dup 5) (match_dup 6)])) (const_int 0))) (set (pc) (if_then_else (match_op_dup 1 [(reg:CC 24) (const_int 0)]) (label_ref (match_dup 7)) (pc)))] " { /* Use DeMorgans law to convert this into an IOR of the inverse conditions This is safe since we only do it for integer comparisons. */ enum rtx_code code = comparison_dominates_p (reverse_condition (GET_CODE (operands[2])), reverse_condition (GET_CODE (operands[0]))) ? GET_CODE (operands[0]) : GET_CODE (operands[2]); operands[2] = gen_rtx (reverse_condition (GET_CODE (operands[2])), GET_MODE (operands[2]), operands[3], operands[4]); operands[0] = gen_rtx (reverse_condition (GET_CODE (operands[0])), GET_MODE (operands[0]), operands[5], operands[6]); if (GET_CODE (operands[1]) == NE) operands[1] = gen_rtx (code, CCmode, XEXP (operands[1], 0), XEXP (operands[1], 1)); else operands[1] = gen_rtx (reverse_condition (code), CCmode, XEXP (operands[1], 0), XEXP (operands[1], 1)); } ") ;; Don't match these patterns if we can use a conditional compare, since they ;; tell the final prescan branch elimator code that full branch inlining ;; can't be done. (define_insn "" [(set (pc) (if_then_else (eq (and:SI (match_operator 1 "comparison_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_add_operand" "rL")]) (match_operator 4 "comparison_operator" [(match_operand:SI 5 "s_register_operand" "r") (match_operand:SI 6 "arm_rhs_operand" "rL")])) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc))) (clobber (reg 24))] "!(GET_CODE (operands[1]) == GET_CODE (operands[4]) || comparison_dominates_p (reverse_condition (GET_CODE (operands[1])), reverse_condition (GET_CODE (operands[4]))) || comparison_dominates_p (reverse_condition (GET_CODE (operands[4])), reverse_condition (GET_CODE (operands[1]))))" "* { extern int arm_ccfsm_state; if (GET_CODE (operands[3]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[3]))) arm_output_asm_insn (\"cmn\\t%2, #%n3\", operands); else arm_output_asm_insn (\"cmp\\t%2, %3\", operands); arm_output_asm_insn (\"b%D1\\t%l0\", operands); if (GET_CODE (operands[6]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[6]))) arm_output_asm_insn (\"cmn\\t%5, #%n6\", operands); else arm_output_asm_insn (\"cmp\\t%5, %6\", operands); if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) { arm_ccfsm_state += 2; return \"\"; } return arm_output_asm_insn (\"b%D4\\t%l0\", operands); }" [(set_attr "conds" "jump_clob") (set_attr "length" "4")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (neg:SI (match_operator 3 "comparison_operator" [(match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rI")]))) (clobber (reg 24))] "" "* if (GET_CODE (operands[3]) == LT && operands[3] == const0_rtx) return arm_output_asm_insn (\"mov\\t%0, %1, asr #31\", operands); if (GET_CODE (operands[3]) == NE) { arm_output_asm_insn (\"subs\\t%0, %1, %2\", operands); return arm_output_asm_insn (\"mvnne\\t%0, #0\", operands); } if (GET_CODE (operands[3]) == GT) { arm_output_asm_insn (\"subs\\t%0, %1, %2\", operands); return arm_output_asm_insn (\"mvnne\\t%0, %0, asr #31\", operands); } arm_output_asm_insn (\"cmp\\t%1, %2\", operands); arm_output_asm_insn (\"mov%D3\\t%0, #0\", operands); return arm_output_asm_insn (\"mvn%d3\\t%0, #0\", operands); " [(set_attr "conds" "clob") (set_attr "length" "3")]) (define_insn "movcond" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (if_then_else:SI (match_operator 5 "comparison_operator" [(match_operand:SI 3 "s_register_operand" "r,r,r") (match_operand:SI 4 "arm_add_operand" "rL,rL,rL")]) (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) (clobber (reg 24))] "" "* if (GET_CODE (operands[5]) == LT && (operands[4] == const0_rtx)) { if (which_alternative != 1 && GET_CODE (operands[4]) == REG) { arm_output_asm_insn (\"ands\\t%0, %1, %3, asr #32\", operands); if (operands[2] == const0_rtx) return \"\"; return arm_output_asm_insn (\"movcc\\t%0, %2\", operands); } else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) { arm_output_asm_insn (\"bics\\t%0, %2, %3, asr #32\", operands); if (operands[1] == const0_rtx) return \"\"; return arm_output_asm_insn (\"movcs\\t%0, %1\", operands); } /* The only case that falls through to here is when both ops 1 & 2 are constants */ } if (GET_CODE (operands[5]) == GE && (operands[4] == const0_rtx)) { if (which_alternative != 1 && GET_CODE (operands[1]) == REG) { arm_output_asm_insn (\"bics\\t%0, %1, %3, asr #32\", operands); if (operands[2] == const0_rtx) return \"\"; return arm_output_asm_insn (\"movcs\\t%0, %2\", operands); } else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) { arm_output_asm_insn (\"ands\\t%0, %2, %3, asr #32\", operands); if (operands[1] == const0_rtx) return \"\"; return arm_output_asm_insn (\"movcc\\t%0, %1\", operands); } /* The only case that falls through to here is when both ops 1 & 2 are constants */ } if (GET_CODE (operands[4]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[4]))) arm_output_asm_insn (\"cmn\\t%3, #%n4\", operands); else arm_output_asm_insn (\"cmp\\t%3, %4\", operands); if (which_alternative != 0) arm_output_asm_insn (\"mov%d5\\t%0, %1\", operands); if (which_alternative != 1) arm_output_asm_insn (\"mov%D5\\t%0, %2\", operands); return \"\"; " [(set_attr "conds" "clob") (set_attr "length" "2,2,3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (if_then_else:SI (match_operator 9 "comparison_operator" [(match_operand:SI 5 "s_register_operand" "r") (match_operand:SI 6 "arm_add_operand" "rL")]) (match_operator:SI 8 "shiftable_operator" [(match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rI")]) (match_operator:SI 7 "shiftable_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "arm_rhs_operand" "rI")]))) (clobber (reg 24))] "" "* { char pattern[100]; if (GET_CODE (operands[6]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[6]))) arm_output_asm_insn (\"cmn\\t%5, #%n6\", operands); else arm_output_asm_insn (\"cmp\\t%5, %6\", operands); sprintf (pattern, \"%s%%d9\\t%%0, %%1, %%2\", arithmetic_instr (operands[8], FALSE)); arm_output_asm_insn (pattern, operands); sprintf (pattern, \"%s%%D9\\t%%0, %%3, %%4\", arithmetic_instr (operands[7], FALSE)); return arm_output_asm_insn (pattern, operands); } " [(set_attr "conds" "clob") (set_attr "length" "3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 6 "comparison_operator" [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_add_operand" "rL,rL")]) (match_operator:SI 7 "shiftable_operator" [(match_operand:SI 4 "s_register_operand" "r,r") (match_operand:SI 5 "arm_rhs_operand" "rI,rI")]) (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm"))) (clobber (reg 24))] "" "* { char pattern[100]; /* If we have an operation where (op x 0) is the identity operation and the condtional operator is LT or GE and we are comparing against zero and everything is in registers then we can do this in two instructions */ if (operands[3] == const0_rtx && GET_CODE (operands[7]) != AND && GET_CODE (operands[5]) == REG && GET_CODE (operands[1]) == REG && REGNO (operands[1]) == REGNO (operands[4]) && REGNO (operands[4]) != REGNO (operands[0])) { if (GET_CODE (operands[6]) == LT) { arm_output_asm_insn (\"and\\t%0, %5, %2, asr #31\", operands); sprintf (pattern, \"%s\\t%%0, %%4, %%0\", arithmetic_instr (operands[7], FALSE)); return arm_output_asm_insn (pattern, operands); } else if (GET_CODE (operands[6]) == GE) { arm_output_asm_insn (\"bic\\t%0, %5, %2, asr #31\", operands); sprintf (pattern, \"%s\\t%%0, %%4, %%0\", arithmetic_instr (operands[7], FALSE)); return arm_output_asm_insn (pattern, operands); } } if (GET_CODE (operands[3]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[3]))) arm_output_asm_insn (\"cmn\\t%2, #%n3\", operands); else arm_output_asm_insn (\"cmp\\t%2, %3\", operands); sprintf (pattern, \"%s%%d6\\t%%0, %%4, %%5\", arithmetic_instr (operands[7], FALSE)); arm_output_asm_insn (pattern, operands); if (which_alternative != 0) { if (GET_CODE (operands[1]) == MEM) arm_output_asm_insn (\"ldr%D6\\t%0, %1\", operands); else arm_output_asm_insn (\"mov%D6\\t%0, %1\", operands); } return \"\"; } " [(set_attr "conds" "clob") (set_attr "length" "2,3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 6 "comparison_operator" [(match_operand:SI 4 "s_register_operand" "r,r") (match_operand:SI 5 "arm_add_operand" "rL,rL")]) (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm") (match_operator:SI 7 "shiftable_operator" [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) (clobber (reg 24))] "" "* { char pattern[100]; /* If we have an operation where (op x 0) is the identity operation and the condtional operator is LT or GE and we are comparing against zero and everything is in registers then we can do this in two instructions */ if (operands[5] == const0_rtx && GET_CODE (operands[7]) != AND && GET_CODE (operands[3]) == REG && GET_CODE (operands[1]) == REG && REGNO (operands[1]) == REGNO (operands[2]) && REGNO (operands[2]) != REGNO (operands[0])) { if (GET_CODE (operands[6]) == GE) { arm_output_asm_insn (\"and\\t%0, %3, %4, asr #31\", operands); sprintf (pattern, \"%s\\t%%0, %%2, %%0\", arithmetic_instr (operands[7], FALSE)); return arm_output_asm_insn (pattern, operands); } else if (GET_CODE (operands[6]) == LT) { arm_output_asm_insn (\"bic\\t%0, %3, %4, asr #31\", operands); sprintf (pattern, \"%s\\t%%0, %%2, %%0\", arithmetic_instr (operands[7], FALSE)); return arm_output_asm_insn (pattern, operands); } } if (GET_CODE (operands[5]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[5]))) arm_output_asm_insn (\"cmn\\t%4, #%n5\", operands); else arm_output_asm_insn (\"cmp\\t%4, %5\", operands); if (which_alternative != 0) { if (GET_CODE (operands[1]) == MEM) arm_output_asm_insn (\"ldr%d6\\t%0, %1\", operands); else arm_output_asm_insn (\"mov%d6\\t%0, %1\", operands); } sprintf (pattern, \"%s%%D6\\t%%0, %%2, %%3\", arithmetic_instr (operands[7], FALSE)); return arm_output_asm_insn (pattern, operands); } " [(set_attr "conds" "clob") (set_attr "length" "2,3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 6 "comparison_operator" [(match_operand:SI 4 "s_register_operand" "r,r") (match_operand:SI 5 "arm_add_operand" "rL,rL")]) (plus:SI (match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_add_operand" "rL,rL")) (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm"))) (clobber (reg 24))] "" "* { if (GET_CODE (operands[5]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[5]))) arm_output_asm_insn (\"cmn\\t%4, #%n5\", operands); else arm_output_asm_insn (\"cmp\\t%4, %5\", operands); if (GET_CODE (operands[3]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[3]))) arm_output_asm_insn (\"sub%d6\\t%0, %2, #%n3\", operands); else arm_output_asm_insn (\"add%d6\\t%0, %2, %3\", operands); if (which_alternative != 0) { if (GET_CODE (operands[1]) == MEM) arm_output_asm_insn (\"ldr%D6\\t%0, %1\", operands); else arm_output_asm_insn (\"mov%D6\\t%0, %1\", operands); } return \"\"; } " [(set_attr "conds" "clob") (set_attr "length" "2,3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 6 "comparison_operator" [(match_operand:SI 4 "s_register_operand" "r,r") (match_operand:SI 5 "arm_add_operand" "rL,rL")]) (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm") (plus:SI (match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_add_operand" "rL,rL")))) (clobber (reg 24))] "" "* { if (GET_CODE (operands[5]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[5]))) arm_output_asm_insn (\"cmn\\t%4, #%n5\", operands); else arm_output_asm_insn (\"cmp\\t%4, %5\", operands); if (GET_CODE (operands[3]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[3]))) arm_output_asm_insn (\"sub%D6\\t%0, %2, #%n3\", operands); else arm_output_asm_insn (\"add%D6\\t%0, %2, %3\", operands); if (which_alternative != 0) { if (GET_CODE (operands[6]) == MEM) arm_output_asm_insn (\"ldr%d6\\t%0, %1\", operands); else arm_output_asm_insn (\"mov%d6\\t%0, %1\", operands); } return \"\"; } " [(set_attr "conds" "clob") (set_attr "length" "2,3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 5 "comparison_operator" [(match_operand:SI 3 "s_register_operand" "r,r") (match_operand:SI 4 "arm_add_operand" "rL,rL")]) (match_operand:SI 1 "arm_rhs_operand" "0,?rI") (not:SI (match_operand:SI 2 "s_register_operand" "r,r")))) (clobber (reg 24))] "" "#" [(set_attr "conds" "clob") (set_attr "length" "2,3")]) ;; if (GET_CODE (operands[3]) == CONST_INT ;; && !const_ok_for_arm (INTVAL (operands[3]))) ;; arm_output_asm_insn (\"cmn\\t%2, #%n3\", operands); ;; else ;; arm_output_asm_insn (\"cmp\\t%2, %3\", operands); ;; if (which_alternative != 0) ;; arm_output_asm_insn (\"mov%d1\\t%0, %4\", operands); ;; return arm_output_asm_insn (\"mvn%D1\\t%0, %5\", operands); (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 5 "comparison_operator" [(match_operand:SI 3 "s_register_operand" "r,r") (match_operand:SI 4 "arm_add_operand" "rL,rL")]) (not:SI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:SI 1 "arm_rhs_operand" "0,?rI"))) (clobber (reg 24))] "" "* { char pattern[100]; if (GET_CODE (operands[30]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[4]))) arm_output_asm_insn (\"cmn\\t%3, #%n4\", operands); else arm_output_asm_insn (\"cmp\\t%3, %4\", operands); if (which_alternative != 0) arm_output_asm_insn (\"mov%D5\\t%0, %1\", operands); return arm_output_asm_insn (\"mvn%d5\\t%0, %2\", operands); } " [(set_attr "conds" "clob") (set_attr "length" "2,3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 6 "comparison_operator" [(match_operand:SI 4 "s_register_operand" "r,r") (match_operand:SI 5 "arm_add_operand" "rL,rL")]) (match_operator:SI 7 "shift_operator" [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_rhs_operand" "rn,rn")]) (match_operand:SI 1 "arm_rhs_operand" "0,?rI"))) (clobber (reg 24))] "" "* { char pattern[100]; if (GET_CODE (operands[5]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[5]))) arm_output_asm_insn (\"cmn\\t%4, #%n5\", operands); else arm_output_asm_insn (\"cmp\\t%4, %5\", operands); if (which_alternative != 0) arm_output_asm_insn (\"mov%D6\\t%0, %1\", operands); sprintf (pattern, \"mov%%d6\\t%%0, %%2, %s %%3\", shift_instr (GET_CODE (operands[7]), &operands[3])); return arm_output_asm_insn (pattern, operands); } " [(set_attr "conds" "clob") (set_attr "length" "2,3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 6 "comparison_operator" [(match_operand:SI 4 "s_register_operand" "r,r") (match_operand:SI 5 "arm_add_operand" "rL,rL")]) (match_operand:SI 1 "arm_rhs_operand" "0,?rI") (match_operator:SI 7 "shift_operator" [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_rhs_operand" "rn,rn")]))) (clobber (reg 24))] "" "* { char pattern[100]; if (GET_CODE (operands[5]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[5]))) arm_output_asm_insn (\"cmn\\t%4, #%n5\", operands); else arm_output_asm_insn (\"cmp\\t%4, %5\", operands); if (which_alternative != 0) arm_output_asm_insn (\"mov%d6\\t%0, %1\", operands); sprintf (pattern, \"mov%%D6\\t%%0, %%2, %s %%3\", shift_instr (GET_CODE (operands[7]), &operands[3])); return arm_output_asm_insn (pattern, operands); } " [(set_attr "conds" "clob") (set_attr "length" "2,3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (if_then_else:SI (match_operator 7 "comparison_operator" [(match_operand:SI 5 "s_register_operand" "r") (match_operand:SI 6 "arm_add_operand" "rL")]) (match_operator:SI 8 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rn")]) (match_operator:SI 9 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "arm_rhs_operand" "rI")]))) (clobber (reg 24))] "" "* { char pattern[100]; if (GET_CODE (operands[6]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[6]))) arm_output_asm_insn (\"cmn\\t%5, #%n6\", operands); else arm_output_asm_insn (\"cmp\\t%5, %6\", operands); sprintf (pattern, \"mov%%d7\\t%%0, %%1, %s %%2\", shift_instr (GET_CODE (operands[8]), &operands[2])); arm_output_asm_insn (pattern, operands); sprintf (pattern, \"mov%%D7\\t%%0, %%3, %s %%4\", shift_instr (GET_CODE (operands[9]), &operands[4])); return arm_output_asm_insn (pattern, operands); } " [(set_attr "conds" "clob") (set_attr "length" "3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (if_then_else:SI (match_operator 6 "comparison_operator" [(match_operand:SI 4 "s_register_operand" "r") (match_operand:SI 5 "arm_add_operand" "rL")]) (not:SI (match_operand:SI 1 "s_register_operand" "r")) (match_operator:SI 7 "shiftable_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_rhs_operand" "rI")]))) (clobber (reg 24))] "" "* { char pattern[100]; if (GET_CODE (operands[5]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[5]))) arm_output_asm_insn (\"cmn\\t%4, #%n5\", operands); else arm_output_asm_insn (\"cmp\\t%4, %5\", operands); arm_output_asm_insn (\"mvn%d6\\t%0, %1\", operands); sprintf (pattern, \"%s%%D6\\t%%0, %%2, %%3\", arithmetic_instr (operands[7], FALSE)); return arm_output_asm_insn (pattern, operands); } " [(set_attr "conds" "clob") (set_attr "length" "3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (if_then_else:SI (match_operator 6 "comparison_operator" [(match_operand:SI 4 "s_register_operand" "r") (match_operand:SI 5 "arm_add_operand" "rL")]) (match_operator:SI 7 "shiftable_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_rhs_operand" "rI")]) (not:SI (match_operand:SI 1 "s_register_operand" "r")))) (clobber (reg 24))] "" "* { char pattern[100]; if (GET_CODE (operands[5]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[5]))) arm_output_asm_insn (\"cmn\\t%4, #%n5\", operands); else arm_output_asm_insn (\"cmp\\t%4, %5\", operands); arm_output_asm_insn (\"mvn%D6\\t%0, %1\", operands); sprintf (pattern, \"%s%%d6\\t%%0, %%2, %%3\", arithmetic_instr (operands[7], FALSE)); return arm_output_asm_insn (pattern, operands); } " [(set_attr "conds" "clob") (set_attr "length" "3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 5 "comparison_operator" [(match_operand:SI 3 "s_register_operand" "r,r") (match_operand:SI 4 "arm_add_operand" "rL,rL")]) (neg:SI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:SI 1 "arm_rhs_operand" "0,?rI"))) (clobber (reg:CC 24))] "" "* if (GET_CODE (operands[4]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[4]))) arm_output_asm_insn (\"cmn\\t%3, #%n4\", operands); else arm_output_asm_insn (\"cmp\\t%3, %4\", operands); if (which_alternative != 0) arm_output_asm_insn (\"mov%D5\\t%0, %1\", operands); return arm_output_asm_insn (\"rsb%d5\\t%0, %2, #0\", operands); " [(set_attr "conds" "clob") (set_attr "length" "2,3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 5 "comparison_operator" [(match_operand:SI 3 "s_register_operand" "r,r") (match_operand:SI 4 "arm_add_operand" "rL,rL")]) (match_operand:SI 1 "arm_rhs_operand" "0,?rI") (neg:SI (match_operand:SI 2 "s_register_operand" "r,r")))) (clobber (reg:CC 24))] "" "* if (GET_CODE (operands[4]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[4]))) arm_output_asm_insn (\"cmn\\t%3, #%n4\", operands); else arm_output_asm_insn (\"cmp\\t%3, %4\", operands); if (which_alternative != 0) arm_output_asm_insn (\"mov%d5\\t%0, %1\", operands); return arm_output_asm_insn (\"rsb%D5\\t%0, %2, #0\", operands); " [(set_attr "conds" "clob") (set_attr "length" "2,3")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (match_operator:SI 1 "shiftable_operator" [(match_operand:SI 2 "memory_operand" "m") (match_operand:SI 3 "memory_operand" "m")])) (clobber (match_scratch:SI 4 "=r"))] "adjacent_mem_locations (operands[2], operands[3])" "* { rtx ldm[3]; rtx arith[3]; char pattern[100]; int val1 = 0, val2 = 0; sprintf (pattern, \"%s\\t%%0, %%1, %%2\", arithmetic_instr (operands[1], FALSE)); if (REGNO (operands[0]) > REGNO (operands[4])) { ldm[1] = operands[4]; ldm[2] = operands[0]; } else { ldm[1] = operands[0]; ldm[2] = operands[4]; } if (GET_CODE (XEXP (operands[2], 0)) != REG) val1 = INTVAL (XEXP (XEXP (operands[2], 0), 1)); if (GET_CODE (XEXP (operands[3], 0)) != REG) val2 = INTVAL (XEXP (XEXP (operands[3], 0), 1)); arith[0] = operands[0]; if (val1 < val2) { arith[1] = ldm[1]; arith[2] = ldm[2]; } else { arith[1] = ldm[2]; arith[2] = ldm[1]; } if (val1 && val2) { rtx ops[3]; ldm[0] = ops[0] = operands[4]; ops[1] = XEXP (XEXP (operands[2], 0), 0); ops[2] = XEXP (XEXP (operands[2], 0), 1); output_add_immediate (ops); if (val1 < val2) arm_output_asm_insn (\"ldmia\\t%0, {%1, %2}\", ldm); else arm_output_asm_insn (\"ldmda\\t%0, {%1, %2}\", ldm); } else if (val1) { ldm[0] = XEXP (operands[3], 0); if (val1 < val2) arm_output_asm_insn (\"ldmda\\t%0, {%1, %2}\", ldm); else arm_output_asm_insn (\"ldmia\\t%0, {%1, %2}\", ldm); } else { ldm[0] = XEXP (operands[2], 0); if (val1 < val2) arm_output_asm_insn (\"ldmia\\t%0, {%1, %2}\", ldm); else arm_output_asm_insn (\"ldmda\\t%0, {%1, %2}\", ldm); } return arm_output_asm_insn (pattern, arith); } " [(set_attr "length" "3") (set_attr "type" "load")]) ;; the arm can support extended pre-inc instructions ;; In all these cases, we use operands 0 and 1 for the register being ;; incremented because those are the operands that local-alloc will ;; tie and these are the pair most likely to be tieable (and the ones ;; that will benefit the most). ;; We reject the frame pointer if it occurs anywhere in these patterns since ;; elimination will cause too many headaches. (define_insn "" [(set (mem:QI (plus:SI (match_operand:SI 1 "s_register_operand" "%0") (match_operand:SI 2 "index_operand" "rJ"))) (match_operand:QI 3 "s_register_operand" "r")) (set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (match_dup 1) (match_dup 2)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "* return arm_output_asm_insn (\"strb\\t%3, [%0, %2]!\", operands); " [(set_attr "type" "store1")]) (define_insn "" [(set (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0") (match_operand:SI 2 "s_register_operand" "r"))) (match_operand:QI 3 "s_register_operand" "r")) (set (match_operand:SI 0 "s_register_operand" "=r") (minus:SI (match_dup 1) (match_dup 2)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "* return arm_output_asm_insn (\"strb\\t%3, [%0, -%2]!\", operands); " [(set_attr "type" "store1")]) (define_insn "" [(set (match_operand:QI 3 "s_register_operand" "=r") (mem:QI (plus:SI (match_operand:SI 1 "s_register_operand" "%0") (match_operand:SI 2 "index_operand" "rJ")))) (set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (match_dup 1) (match_dup 2)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "* return arm_output_asm_insn (\"ldrb\\t%3, [%0, %2]!\", operands); " [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:QI 3 "s_register_operand" "=r") (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0") (match_operand:SI 2 "s_register_operand" "r")))) (set (match_operand:SI 0 "s_register_operand" "=r") (minus:SI (match_dup 1) (match_dup 2)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "* return arm_output_asm_insn (\"ldrb\\t%3, [%0, -%2]!\", operands); " [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:SI 3 "s_register_operand" "=r") (zero_extend:SI (mem:QI (plus:SI (match_operand:SI 1 "s_register_operand" "%0") (match_operand:SI 2 "index_operand" "rJ"))))) (set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (match_dup 1) (match_dup 2)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "* return arm_output_asm_insn (\"ldrb\\t%3, [%0, %2]!\\t@ z_extendqisi\", operands); " [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:SI 3 "s_register_operand" "=r") (zero_extend:SI (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0") (match_operand:SI 2 "s_register_operand" "r"))))) (set (match_operand:SI 0 "s_register_operand" "=r") (minus:SI (match_dup 1) (match_dup 2)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "* return arm_output_asm_insn (\"ldrb\\t%3, [%0, -%2]!\\t@ z_extendqisi\", operands); " [(set_attr "type" "load")]) (define_insn "" [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%0") (match_operand:SI 2 "index_operand" "rJ"))) (match_operand:SI 3 "s_register_operand" "r")) (set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (match_dup 1) (match_dup 2)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "* return arm_output_asm_insn (\"str\\t%3, [%0, %2]!\", operands); " [(set_attr "type" "store1")]) (define_insn "" [(set (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0") (match_operand:SI 2 "s_register_operand" "r"))) (match_operand:SI 3 "s_register_operand" "r")) (set (match_operand:SI 0 "s_register_operand" "=r") (minus:SI (match_dup 1) (match_dup 2)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "* return arm_output_asm_insn (\"str\\t%3, [%0, -%2]!\", operands); " [(set_attr "type" "store1")]) (define_insn "" [(set (match_operand:SI 3 "s_register_operand" "=r") (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%0") (match_operand:SI 2 "index_operand" "rJ")))) (set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (match_dup 1) (match_dup 2)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "* return arm_output_asm_insn (\"ldr\\t%3, [%0, %2]!\", operands); " [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:SI 3 "s_register_operand" "=r") (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0") (match_operand:SI 2 "s_register_operand" "r")))) (set (match_operand:SI 0 "s_register_operand" "=r") (minus:SI (match_dup 1) (match_dup 2)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "* return arm_output_asm_insn (\"ldr\\t%3, [%0, -%2]!\", operands); " [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:HI 3 "s_register_operand" "=r") (mem:HI (plus:SI (match_operand:SI 1 "s_register_operand" "%0") (match_operand:SI 2 "index_operand" "rJ")))) (set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (match_dup 1) (match_dup 2)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "* return arm_output_asm_insn (\"ldr\\t%3, [%0, %2]!\\t@ loadhi\", operands); " [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:HI 3 "s_register_operand" "=r") (mem:HI (minus:SI (match_operand:SI 1 "s_register_operand" "0") (match_operand:SI 2 "s_register_operand" "r")))) (set (match_operand:SI 0 "s_register_operand" "=r") (minus:SI (match_dup 1) (match_dup 2)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "* return arm_output_asm_insn (\"ldr\\t%3, [%0, -%2]!\\t@ loadhi\", operands); " [(set_attr "type" "load")]) (define_insn "" [(set (mem:QI (plus:SI (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "const_shift_operand" "n")]) (match_operand:SI 1 "s_register_operand" "0"))) (match_operand:QI 5 "s_register_operand" "r")) (set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)]) (match_dup 1)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "* { char instr[100]; sprintf (instr, \"strb\\t%%5, [%%0, %%3, %s %%4]!\", shift_instr (GET_CODE (operands[2]), &operands[4])); return arm_output_asm_insn (instr, operands); } " [(set_attr "type" "store1")]) (define_insn "" [(set (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0") (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "const_shift_operand" "n")]))) (match_operand:QI 5 "s_register_operand" "r")) (set (match_operand:SI 0 "s_register_operand" "=r") (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) (match_dup 4)])))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "* { char instr[100]; sprintf (instr, \"strb\\t%%5, [%%0, -%%3, %s %%4]!\", shift_instr (GET_CODE (operands[2]), &operands[4])); return arm_output_asm_insn (instr, operands); } " [(set_attr "type" "store1")]) (define_insn "" [(set (match_operand:QI 5 "s_register_operand" "=r") (mem:QI (plus:SI (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "const_shift_operand" "n")]) (match_operand:SI 1 "s_register_operand" "0")))) (set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)]) (match_dup 1)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "* { char instr[100]; sprintf (instr, \"ldrb\\t%%5, [%%0, %%3, %s %%4]!\", shift_instr (GET_CODE (operands[2]), &operands[4])); return arm_output_asm_insn (instr, operands); } " [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:QI 5 "s_register_operand" "=r") (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0") (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "const_shift_operand" "n")])))) (set (match_operand:SI 0 "s_register_operand" "=r") (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) (match_dup 4)])))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "* { char instr[100]; sprintf (instr, \"ldrb\\t%%5, [%%0, -%%3, %s %%4]!\", shift_instr (GET_CODE (operands[2]), &operands[4])); return arm_output_asm_insn (instr, operands); } " [(set_attr "type" "load")]) (define_insn "" [(set (mem:SI (plus:SI (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "const_shift_operand" "n")]) (match_operand:SI 1 "s_register_operand" "0"))) (match_operand:SI 5 "s_register_operand" "r")) (set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)]) (match_dup 1)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "* { char instr[100]; sprintf (instr, \"str\\t%%5, [%%0, %%3, %s %%4]!\", shift_instr (GET_CODE (operands[2]), &operands[4])); return arm_output_asm_insn (instr, operands); } " [(set_attr "type" "store1")]) (define_insn "" [(set (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0") (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "const_shift_operand" "n")]))) (match_operand:SI 5 "s_register_operand" "r")) (set (match_operand:SI 0 "s_register_operand" "=r") (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) (match_dup 4)])))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "* { char instr[100]; sprintf (instr, \"str\\t%%5, [%%0, -%%3, %s %%4]!\", shift_instr (GET_CODE (operands[2]), &operands[4])); return arm_output_asm_insn (instr, operands); } " [(set_attr "type" "store1")]) (define_insn "" [(set (match_operand:SI 5 "s_register_operand" "=r") (mem:SI (plus:SI (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "const_shift_operand" "n")]) (match_operand:SI 1 "s_register_operand" "0")))) (set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)]) (match_dup 1)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "* { char instr[100]; sprintf (instr, \"ldr\\t%%5, [%%0, %%3, %s %%4]!\", shift_instr (GET_CODE (operands[2]), &operands[4])); return arm_output_asm_insn (instr, operands); } " [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:SI 5 "s_register_operand" "=r") (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0") (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "const_shift_operand" "n")])))) (set (match_operand:SI 0 "s_register_operand" "=r") (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) (match_dup 4)])))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "* { char instr[100]; sprintf (instr, \"ldr\\t%%5, [%%0, -%%3, %s %%4]!\", shift_instr (GET_CODE (operands[2]), &operands[4])); return arm_output_asm_insn (instr, operands); } " [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:HI 5 "s_register_operand" "=r") (mem:HI (plus:SI (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "const_shift_operand" "n")]) (match_operand:SI 1 "s_register_operand" "0")))) (set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)]) (match_dup 1)))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "* { char instr[100]; sprintf (instr, \"ldr\\t%%5, [%%0, %%3, %s %%4]!\\t@ loadhi\", shift_instr (GET_CODE (operands[2]), &operands[4])); return arm_output_asm_insn (instr, operands); } " [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:HI 5 "s_register_operand" "=r") (mem:HI (minus:SI (match_operand:SI 1 "s_register_operand" "0") (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "const_shift_operand" "n")])))) (set (match_operand:SI 0 "s_register_operand" "=r") (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) (match_dup 4)])))] "REGNO (operands[0]) != FRAME_POINTER_REGNUM && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "* { char instr[100]; sprintf (instr, \"ldr\\t%%5, [%%0, -%%3, %s %%4]!\\t@ loadhi\", shift_instr (GET_CODE (operands[2]), &operands[4])); return arm_output_asm_insn (instr, operands); } " [(set_attr "type" "load")]) ; It can also support extended post-inc expressions, but combine doesn't ; try these.... ; It doesn't seem worth adding peepholes for anything but the most common ; cases since, unlike combine, the increment must immediately follow the load ; for this pattern to match. ; When loading we must watch to see that the base register isn't trampled by ; the load. In such cases this isn't a post-inc expression. (define_peephole [(set (mem:QI (match_operand:SI 0 "s_register_operand" "+r")) (match_operand:QI 2 "s_register_operand" "r")) (set (match_dup 0) (plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))] "" "* return arm_output_asm_insn (\"strb\\t%2, [%0], %1\", operands); ") (define_peephole [(set (match_operand:QI 0 "s_register_operand" "=r") (mem:QI (match_operand:SI 1 "s_register_operand" "+r"))) (set (match_dup 1) (plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))] "REGNO(operands[0]) != REGNO(operands[1]) && (GET_CODE (operands[2]) != REG || REGNO(operands[0]) != REGNO (operands[2]))" "* return arm_output_asm_insn (\"ldrb\\t%0, [%1], %2\", operands); ") (define_peephole [(set (mem:SI (match_operand:SI 0 "s_register_operand" "+r")) (match_operand:SI 2 "s_register_operand" "r")) (set (match_dup 0) (plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))] "" "* return arm_output_asm_insn (\"str\\t%2, [%0], %1\", operands); ") (define_peephole [(set (match_operand:HI 0 "s_register_operand" "=r") (mem:HI (match_operand:SI 1 "s_register_operand" "+r"))) (set (match_dup 1) (plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))] "REGNO(operands[0]) != REGNO(operands[1]) && (GET_CODE (operands[2]) != REG || REGNO(operands[0]) != REGNO (operands[2]))" "* return arm_output_asm_insn (\"ldr\\t%0, [%1], %2\\t@ loadhi\", operands); ") (define_peephole [(set (match_operand:SI 0 "s_register_operand" "=r") (mem:SI (match_operand:SI 1 "s_register_operand" "+r"))) (set (match_dup 1) (plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))] "REGNO(operands[0]) != REGNO(operands[1]) && (GET_CODE (operands[2]) != REG || REGNO(operands[0]) != REGNO (operands[2]))" "* return arm_output_asm_insn (\"ldr\\t%0, [%1], %2\", operands); ") ; This pattern is never tried by combine, so do it as a peephole (define_peephole [(set (match_operand:SI 0 "s_register_operand" "=r") (match_operand:SI 1 "s_register_operand" "r")) (set (match_operand 2 "cc_register" "") (compare (match_dup 1) (const_int 0)))] "" "* return arm_output_asm_insn (\"subs\\t%0, %1, #0\", operands); " [(set_attr "conds" "set")]) ; Peepholes to spot possible load- and store-multiples, if the ordering is ; reversed, check that the memory references aren't volatile. (define_peephole [(set (match_operand:SI 0 "s_register_operand" "=r") (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") (const_int 12)))) (set (match_operand:SI 2 "s_register_operand" "=r") (mem:SI (plus:SI (match_dup 1) (const_int 8)))) (set (match_operand:SI 3 "s_register_operand" "=r") (mem:SI (plus:SI (match_dup 1) (const_int 4)))) (set (match_operand:SI 4 "s_register_operand" "=r") (mem:SI (match_dup 1)))] "REGNO (operands[0]) > REGNO (operands[2]) && REGNO (operands[2]) > REGNO (operands[3]) && REGNO (operands[3]) > REGNO (operands[4]) && !(REGNO (operands[1]) == REGNO (operands[0]) || REGNO (operands[1]) == REGNO (operands[2]) || REGNO (operands[1]) == REGNO (operands[3]) || REGNO (operands[1]) == REGNO (operands[4])) && !MEM_VOLATILE_P (SET_SRC (PATTERN (insn))) && !MEM_VOLATILE_P (SET_SRC (PATTERN (prev_nonnote_insn (insn)))) && !MEM_VOLATILE_P (SET_SRC (PATTERN (prev_nonnote_insn (prev_nonnote_insn (insn))))) && !MEM_VOLATILE_P (SET_SRC (PATTERN (prev_nonnote_insn (prev_nonnote_insn (prev_nonnote_insn (insn))))))" "* return arm_output_asm_insn (\"ldmia\\t%1, {%4, %3, %2, %0}\\t@ phole ldm\", operands); ") (define_peephole [(set (match_operand:SI 0 "s_register_operand" "=r") (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") (const_int 8)))) (set (match_operand:SI 2 "s_register_operand" "=r") (mem:SI (plus:SI (match_dup 1) (const_int 4)))) (set (match_operand:SI 3 "s_register_operand" "=r") (mem:SI (match_dup 1)))] "REGNO (operands[0]) > REGNO (operands[2]) && REGNO (operands[2]) > REGNO (operands[3]) && !(REGNO (operands[1]) == REGNO (operands[0]) || REGNO (operands[1]) == REGNO (operands[2]) || REGNO (operands[1]) == REGNO (operands[3])) && !MEM_VOLATILE_P (SET_SRC (PATTERN (insn))) && !MEM_VOLATILE_P (SET_SRC (PATTERN (prev_nonnote_insn (insn)))) && !MEM_VOLATILE_P (SET_SRC (PATTERN (prev_nonnote_insn (prev_nonnote_insn (insn)))))" "* return arm_output_asm_insn (\"ldmia\\t%1, {%3, %2, %0}\\t@ phole ldm\", operands); ") (define_peephole [(set (match_operand:SI 0 "s_register_operand" "=r") (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") (const_int 4)))) (set (match_operand:SI 2 "s_register_operand" "=r") (mem:SI (match_dup 1)))] "REGNO (operands[0]) > REGNO (operands[2]) && !(REGNO (operands[1]) == REGNO (operands[0]) || REGNO (operands[1]) == REGNO (operands[2])) && !MEM_VOLATILE_P (SET_SRC (PATTERN (insn))) && !MEM_VOLATILE_P (SET_SRC (PATTERN (prev_nonnote_insn (insn))))" "* return arm_output_asm_insn (\"ldmia\\t%1, {%2, %0}\\t@ phole ldm\", operands); ") (define_peephole [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") (const_int 12))) (match_operand:SI 0 "s_register_operand" "r")) (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) (match_operand:SI 2 "s_register_operand" "r")) (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) (match_operand:SI 3 "s_register_operand" "r")) (set (mem:SI (match_dup 1)) (match_operand:SI 4 "s_register_operand" "r"))] "REGNO (operands[0]) > REGNO (operands[2]) && REGNO (operands[2]) > REGNO (operands[3]) && REGNO (operands[3]) > REGNO (operands[4]) && !MEM_VOLATILE_P (SET_DEST (PATTERN (insn))) && !MEM_VOLATILE_P (SET_DEST (PATTERN (prev_nonnote_insn (insn)))) && !MEM_VOLATILE_P (SET_DEST (PATTERN (prev_nonnote_insn (prev_nonnote_insn (insn))))) && !MEM_VOLATILE_P (SET_DEST (PATTERN (prev_nonnote_insn (prev_nonnote_insn (prev_nonnote_insn (insn))))))" "* return arm_output_asm_insn (\"stmia\\t%1, {%4, %3, %2, %0}\\t@ phole stm\", operands); ") (define_peephole [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") (const_int 8))) (match_operand:SI 0 "s_register_operand" "r")) (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) (match_operand:SI 2 "s_register_operand" "r")) (set (mem:SI (match_dup 1)) (match_operand:SI 3 "s_register_operand" "r"))] "REGNO (operands[0]) > REGNO (operands[2]) && REGNO (operands[2]) > REGNO (operands[3]) && !MEM_VOLATILE_P (SET_DEST (PATTERN (insn))) && !MEM_VOLATILE_P (SET_DEST (PATTERN (prev_nonnote_insn (insn)))) && !MEM_VOLATILE_P (SET_DEST (PATTERN (prev_nonnote_insn (prev_nonnote_insn (insn)))))" "* return arm_output_asm_insn (\"stmia\\t%1, {%3, %2, %0}\\t@ phole stm\", operands); ") (define_peephole [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") (const_int 4))) (match_operand:SI 0 "s_register_operand" "r")) (set (mem:SI (match_dup 1)) (match_operand:SI 2 "s_register_operand" "r"))] "REGNO (operands[0]) > REGNO (operands[2]) && !MEM_VOLATILE_P (SET_DEST (PATTERN (insn))) && !MEM_VOLATILE_P (SET_DEST (PATTERN (prev_nonnote_insn (insn))))" "* return arm_output_asm_insn (\"stmia\\t%1, {%2, %0}\\t@ phole stm\", operands); ") ;; A call followed by return can be replaced by restoring the regs and ;; jumping to the subroutine, provided we aren't passing the address of ;; any of our local variables. If we call alloca then this is unsafe ;; since restoring the frame frees the memory, which is not what we want. ;; Sometimes the return might have been targeted by the final prescan: ;; if so then emit a propper return insn as well. ;; Unfortunately, if the frame pointer is required, we don't know if the ;; current function has any implicit stack pointer adjustments that will ;; be restored by the return: we can't therefore do a tail call. ;; Another unfortunate that we can't handle is if current_function_args_size ;; is non-zero: in this case elimination of the argument pointer assumed ;; that lr was pushed onto the stack, so eliminating upsets the offset ;; calculations. (define_peephole [(parallel [(call (mem:SI (match_operand:SI 0 "" "i")) (match_operand:SI 1 "general_operand" "g")) (clobber (reg:SI 14))]) (return)] "(GET_CODE (operands[0]) == SYMBOL_REF && USE_RETURN_INSN && !get_frame_size () && !current_function_calls_alloca && !frame_pointer_needed && !current_function_args_size)" "* { extern rtx arm_target_insn; extern int arm_ccfsm_state, arm_current_cc; if (arm_ccfsm_state && arm_target_insn && INSN_DELETED_P (arm_target_insn)) { arm_current_cc ^= 1; output_return_instruction (NULL, TRUE); arm_ccfsm_state = 0; arm_target_insn = NULL; } output_return_instruction (NULL, FALSE); return (arm_output_asm_insn (\"b\\t%a0\", operands)); }" [(set (attr "conds") (if_then_else (eq_attr "cpu" "arm6") (const_string "clob") (const_string "nocond"))) (set_attr "length" "2")]) (define_peephole [(parallel [(set (match_operand 0 "s_register_operand" "=rf") (call (mem:SI (match_operand:SI 1 "" "i")) (match_operand:SI 2 "general_operand" "g"))) (clobber (reg:SI 14))]) (return)] "(GET_CODE (operands[1]) == SYMBOL_REF && USE_RETURN_INSN && !get_frame_size () && !current_function_calls_alloca && !frame_pointer_needed && !current_function_args_size)" "* { extern rtx arm_target_insn; extern int arm_ccfsm_state, arm_current_cc; if (arm_ccfsm_state && arm_target_insn && INSN_DELETED_P (arm_target_insn)) { arm_current_cc ^= 1; output_return_instruction (NULL, TRUE); arm_ccfsm_state = 0; arm_target_insn = NULL; } output_return_instruction (NULL, FALSE); return (arm_output_asm_insn (\"b\\t%a1\", operands)); }" [(set (attr "conds") (if_then_else (eq_attr "cpu" "arm6") (const_string "clob") (const_string "nocond"))) (set_attr "length" "2")]) ;; As above but when this function is not void, we must be returning the ;; result of the called subroutine. (define_peephole [(parallel [(set (match_operand 0 "s_register_operand" "=rf") (call (mem:SI (match_operand:SI 1 "" "i")) (match_operand:SI 2 "general_operand" "g"))) (clobber (reg:SI 14))]) (use (match_dup 0)) (return)] "(GET_CODE (operands[1]) == SYMBOL_REF && USE_RETURN_INSN && !get_frame_size () && !current_function_calls_alloca && !frame_pointer_needed && !current_function_args_size)" "* { extern rtx arm_target_insn; extern int arm_ccfsm_state, arm_current_cc; if (arm_ccfsm_state && arm_target_insn && INSN_DELETED_P (arm_target_insn)) { arm_current_cc ^= 1; output_return_instruction (NULL, TRUE); arm_ccfsm_state = 0; arm_target_insn = NULL; } output_return_instruction (NULL, FALSE); return (arm_output_asm_insn (\"b\\t%a1\", operands)); }" [(set (attr "conds") (if_then_else (eq_attr "cpu" "arm6") (const_string "clob") (const_string "nocond"))) (set_attr "length" "2")]) ;; If calling a subroutine and then jumping back to somewhere else, but not ;; too far away, then we can set the link register with the branch address ;; and jump direct to the subroutine. On return from the subroutine ;; execution continues at the branch; this avoids a prefetch stall. ;; We use the length attribute (via short_branch ()) to establish whether or ;; not this is possible, this is the same asthe sparc does. (define_peephole [(parallel[(call (mem:SI (match_operand:SI 0 "" "i")) (match_operand:SI 1 "general_operand" "g")) (clobber (reg:SI 14))]) (set (pc) (label_ref (match_operand 2 "" "")))] "GET_CODE (operands[0]) == SYMBOL_REF && short_branch (INSN_UID (insn), INSN_UID (operands[2])) && arm_insn_not_targeted (insn)" "* { int backward = arm_backwards_branch (INSN_UID (insn), INSN_UID (operands[2])); #if 0 /* Putting this in means that TARGET_6 code will ONLY run on an arm6 or * above, leaving it out means that the code will still run on an arm 2 or 3 */ if (TARGET_6) { if (backward) arm_output_asm_insn (\"sub\\tlr, pc, #(8 + . -%l2)\", operands); else arm_output_asm_insn (\"add\\tlr, pc, #(%l2 - . -8)\", operands); } else #endif { arm_output_asm_insn (\"mov\\tlr, pc\\t@ protect cc\"); if (backward) arm_output_asm_insn (\"sub\\tlr, lr, #(4 + . -%l2)\", operands); else arm_output_asm_insn (\"add\\tlr, lr, #(%l2 - . -4)\", operands); } return arm_output_asm_insn (\"b\\t%a0\", operands); }" [(set (attr "conds") (if_then_else (eq_attr "cpu" "arm6") (const_string "clob") (const_string "nocond"))) (set (attr "length") (if_then_else (eq_attr "cpu" "arm6") (const_int 2) (const_int 3)))]) (define_peephole [(parallel[(set (match_operand:SI 0 "s_register_operand" "=r") (call (mem:SI (match_operand:SI 1 "" "i")) (match_operand:SI 2 "general_operand" "g"))) (clobber (reg:SI 14))]) (set (pc) (label_ref (match_operand 3 "" "")))] "GET_CODE (operands[0]) == SYMBOL_REF && short_branch (INSN_UID (insn), INSN_UID (operands[3])) && arm_insn_not_targeted (insn)" "* { int backward = arm_backwards_branch (INSN_UID (insn), INSN_UID (operands[3])); #if 0 /* Putting this in means that TARGET_6 code will ONLY run on an arm6 or * above, leaving it out means that the code will still run on an arm 2 or 3 */ if (TARGET_6) { if (backward) arm_output_asm_insn (\"sub\\tlr, pc, #(8 + . -%l3)\", operands); else arm_output_asm_insn (\"add\\tlr, pc, #(%l3 - . -8)\", operands); } else #endif { arm_output_asm_insn (\"mov\\tlr, pc\\t@ protect cc\"); if (backward) arm_output_asm_insn (\"sub\\tlr, lr, #(4 + . -%l3)\", operands); else arm_output_asm_insn (\"add\\tlr, lr, #(%l3 - . -4)\", operands); } return arm_output_asm_insn (\"b\\t%a1\", operands); }" [(set (attr "conds") (if_then_else (eq_attr "cpu" "arm6") (const_string "clob") (const_string "nocond"))) (set (attr "length") (if_then_else (eq_attr "cpu" "arm6") (const_int 2) (const_int 3)))]) (define_split [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(match_operator:SI 1 "shift_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "nonmemory_operand" "rn")]) (match_operand:SI 4 "s_register_operand" "r")]) (label_ref (match_operand 5 "" "")) (pc))) (clobber (reg 24))] "" [(set (reg:CC 24) (compare:CC (match_dup 4) (match_op_dup 1 [(match_dup 2) (match_dup 3)]))) (set (pc) (if_then_else (match_op_dup 0 [(reg 24) (const_int 0)]) (label_ref (match_dup 5)) (pc)))] " operands[0] = gen_rtx (swap_condition (GET_CODE (operands[0])), VOIDmode, operands[1], operands[2]); ") (define_split [(set (match_operand:SI 0 "s_register_operand" "") (and:SI (ge:SI (match_operand:SI 1 "s_register_operand" "") (const_int 0)) (neg:SI (match_operator:SI 2 "comparison_operator" [(match_operand:SI 3 "s_register_operand" "") (match_operand:SI 4 "arm_rhs_operand" "")])))) (clobber (match_operand:SI 5 "s_register_operand" ""))] "" [(set (match_dup 5) (not:SI (ashiftrt:SI (match_dup 1) (const_int 31)))) (set (match_dup 0) (and:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)]) (match_dup 5)))] "") ;; This pattern can be used because cc_noov mode implies that the following ;; branch will be an equality (EQ or NE), so the sign extension is not ;; needed. Combine doesn't eliminate these because by the time it sees the ;; branch it no-longer knows that the data came from memory. (define_insn "" [(set (reg:CC_NOOV 24) (compare:CC_NOOV (ashift:SI (subreg:SI (match_operand:QI 0 "memory_operand" "m") 0) (const_int 24)) (match_operand 1 "immediate_operand" "I"))) (clobber (match_scratch:SI 2 "=r"))] "((unsigned long) INTVAL (operands[1])) == (((unsigned long) INTVAL (operands[1])) >> 24) << 24" "* operands[1] = GEN_INT (((unsigned long) INTVAL (operands[1])) >> 24); arm_output_asm_insn (\"ldrb\\t%2, %0\", operands); return arm_output_asm_insn (\"cmp\\t%2, %1\", operands); " [(set_attr "conds" "set") (set_attr "length" "2") (set_attr "type" "load")]) (define_expand "save_stack_nonlocal" [(match_operand:DI 0 "memory_operand" "") (match_operand:SI 1 "s_register_operand" "")] "" " { /* We also need to save the frame pointer for non-local gotos */ emit_move_insn (operand_subword (operands[0], 0, 0, DImode), hard_frame_pointer_rtx); emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]); DONE; }") (define_expand "restore_stack_nonlocal" [(match_operand:SI 0 "s_register_operand" "") (match_operand:DI 1 "memory_operand" "")] "" " { /* Restore the frame pointer first, the stack pointer second. */ emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode)); emit_move_insn (hard_frame_pointer_rtx, operand_subword (operands[1], 0, 0, DImode)); DONE; }") ;; This split is only used during output to reduce the number of patterns ;; that need assembler instructions adding to them. We allowed the setting ;; of the conditions to be implicit during rtl generation so that ;; the conditional compare patterns would work. However this conflicts to ;; some extend with the conditional data operations, so we have to split them ;; up again here. (define_split [(set (match_operand:SI 0 "s_register_operand" "") (if_then_else:SI (match_operator 1 "comparison_operator" [(match_operand 2 "" "") (match_operand 3 "" "")]) (match_operand 4 "" "") (match_operand 5 "" ""))) (clobber (reg 24))] "reload_completed" [(set (match_dup 6) (match_dup 7)) (set (match_dup 0) (if_then_else:SI (match_op_dup 1 [(match_dup 6) (const_int 0)]) (match_dup 4) (match_dup 5)))] " { enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]), operands[2], operands[3]); operands[6] = gen_rtx (REG, mode, 24); operands[7] = gen_rtx (COMPARE, mode, operands[2], operands[3]); } ") (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 4 "comparison_operator" [(match_operand 3 "cc_register" "") (const_int 0)]) (match_operand:SI 1 "arm_rhs_operand" "0,?rI") (not:SI (match_operand:SI 2 "s_register_operand" "r,r"))))] "" "* if (which_alternative != 0) arm_output_asm_insn (\"mov%d4\\t%0, %1\", operands); return arm_output_asm_insn (\"mvn%D4\\t%0, %2\", operands); " [(set_attr "conds" "use") (set_attr "length" "1,2")]) ;; The next two patterns occur when an AND operation is followed by a ;; scc insn sequence (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") (const_int 1) (match_operand:SI 2 "immediate_operand" "n")))] "" "* operands[2] = GEN_INT (1 << INTVAL (operands[2])); arm_output_asm_insn (\"ands\\t%0, %1, %2\", operands); return arm_output_asm_insn (\"mvnne\\t%0, #0\", operands); " [(set_attr "conds" "clob") (set_attr "length" "2")]) (define_insn "" [(set (match_operand:SI 0 "s_register_operand" "=r") (not:SI (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") (const_int 1) (match_operand:SI 2 "immediate_operand" "n"))))] "" "* operands[2] = GEN_INT (1 << INTVAL (operands[2])); arm_output_asm_insn (\"tst\\t%1, %2\", operands); arm_output_asm_insn (\"mvneq\\t%0, #0\", operands); return arm_output_asm_insn (\"movne\\t%0, #0\", operands); " [(set_attr "conds" "clob") (set_attr "length" "3")]) gcc-2.5.8/config/arm/riscix.h100444 22011 13 10015 5453576761 14520 0ustar kenneruser/* Definitions of target machine for GNU compiler. ARM RISCiX version. Copyright (C) 1993 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rwe11@cl.cam.ac.uk), based on original work by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Translation to find startup files. On RISCiX boxes, gcrt0.o is in /usr/lib. */ #define STARTFILE_SPEC \ "%{pg:/usr/lib/gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}" #ifndef CPP_PREDEFINES #define CPP_PREDEFINES \ "-Darm -Driscix -Dunix -Asystem(unix) -Acpu(arm) -Amachine(arm)" #endif #if 0 #define CPP_PREDEFINES "-Darm -Driscos -Acpu(arm) -Amachine(arm)" #endif #ifndef CPP_SPEC #define CPP_SPEC "%{m6:-D__arm6__} \ %{mbsd:%{pedantic:%e-mbsd and -pedantic incompatible} -D_BSD_C} \ %{mxopen:%{mbsd:%e-mbsd and -mxopen incompatible} \ %{pedantic:%e-mxopen and -pedantic incompatible} -D_XOPEN_C} \ %{!mbsd:%{!mxopen:%{!ansi: -D_BSD_C}}}" #endif /* RISCiX has some wierd symbol name munging, that is done to the object module after assembly, which enables multiple libraries to be supported within one (possibly shared) library. It basically changes the symbol name of certain symbols (for example _bcopy is converted to _$bcopy if using BSD) Symrename's parameters are determined as follows: -mno-symrename Don't run symrename -mbsd symrename -BSD -mxopen symrename -XOPEN -ansi symrename - symrename -BSD */ #ifndef ASM_FINAL_SPEC #if !defined (CROSS_COMPILER) #define ASM_FINAL_SPEC "\ %{!mno-symrename: \ \n /usr/bin/symrename \ -%{mbsd:%{ansi:%e-mbsd and -ansi incompatible}BSD}\ %{mxopen:%{mbsd:%e-mbsd and -mxopen incompatible}\ %{ansi:%e-mxopen and -ansi incompatible}XOPEN}\ %{!mbsd:%{!mxopen:%{!ansi:BSD}}} %{c:%{o*:%*}%{!o*:%b.o}}%{!c:%U.o}}" #endif #endif /* None of these is actually used in cc1, so they modify bit 31 */ #define ARM_EXTRA_TARGET_SWITCHES \ {"bsd", 0x80000000}, {"xopen", 0x80000000}, {"no-symrename", 0x80000000}, /* Run-time Target Specification. */ #define TARGET_VERSION \ fputs (" (ARM/RISCiX)", stderr); /* This is used in ASM_FILE_START */ #define ARM_OS_NAME "RISCiX" #ifdef riscos #define TARGET_WHEN_DEBUGGING 3 #else #define TARGET_WHEN_DEBUGGING 1 #endif /* 'char' is signed by default on RISCiX, unsigned on RISCOS. */ #ifdef riscos #define DEFAULT_SIGNED_CHAR 0 #else #define DEFAULT_SIGNED_CHAR 1 #endif /* Define this if the target system supports the function atexit form the ANSI C standard. If this is not defined, and INIT_SECTION_ASM_OP is not defined, a default exit function will be provided to support C++. The man page only describes on_exit, but atexit is also there. */ #define HAVE_ATEXIT 1 /* Some systems use __main in a way incompatible with its use in gcc, in these cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to give the same symbol without quotes for an alternative entry point. You must define both, or niether. */ #ifndef NAME__MAIN #define NAME__MAIN "__gccmain" #define SYMBOL__MAIN __gccmain #endif #include "arm/arm.h" /* The native RISCiX assembler does not support stabs of any kind; because the native assembler is not used by the compiler, Acorn didn't feel it was necessary to put them in! */ #ifdef DBX_DEBUGGING_INFO #undef DBX_DEBUGGING_INFO #endif gcc-2.5.8/config/arm/riscix1-1.h100444 22011 13 6214 5453576761 14725 0ustar kenneruser/* Definitions of target machine for GNU compiler. ARM RISCiX 1.1x version. Copyright (C) 1993 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rwe11@cl.cam.ac.uk), based on original work by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* RISCix 1.1x is basically the same as 1.2x except that it doesn't have symrename or atexit. */ /* Translation to find startup files. On RISCiX boxes, gcrt0.o is in /usr/lib. */ #define STARTFILE_SPEC \ "%{pg:/usr/lib/gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}" #ifndef CPP_PREDEFINES #define CPP_PREDEFINES "-Darm -Driscix -Dunix -Asystem(unix) -Acpu(arm) -Amachine(arm)" #endif #ifndef CPP_SPEC #define CPP_SPEC "%{m6:-D__arm6__} %{!ansi: -D_BSD_C}" #endif /* Riscix 1.1 doesn't have X/OPEN support, so only accept -mbsd (but ignore it). By not having -mxopen and -mno-symrename, we get warning messages, but everything still compiles. */ /* None of these is actually used in cc1, so they modify bit 31 */ #define ARM_EXTRA_TARGET_SWITCHES \ {"bsd", 0x80000000}, /* Run-time Target Specification. */ #define TARGET_VERSION \ fputs (" (ARM/RISCiX)", stderr); /* This is used in ASM_FILE_START */ #define ARM_OS_NAME "RISCiX" #ifdef riscos #define TARGET_WHEN_DEBUGGING 3 #else #define TARGET_WHEN_DEBUGGING 1 #endif /* 'char' is signed by default on RISCiX, unsigned on RISCOS. */ #ifdef riscos #define DEFAULT_SIGNED_CHAR 0 #else #define DEFAULT_SIGNED_CHAR 1 #endif /* Define this if the target system supports the function atexit form the ANSI C standard. If this is not defined, and INIT_SECTION_ASM_OP is not defined, a default exit function will be provided to support C++. The man page only describes on_exit, but atexit is also there. This seems to be missing in early versions. */ /*#define HAVE_ATEXIT 1 */ /* Some systems use __main in a way incompatible with its use in gcc, in these cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to give the same symbol without quotes for an alternative entry point. You must define both, or niether. */ #ifndef NAME__MAIN #define NAME__MAIN "__gccmain" #define SYMBOL__MAIN __gccmain #endif #include "arm/arm.h" /* The native RISCiX assembler does not support stabs of any kind; because the native assembler is not used by the compiler, Acorn didn't feel it was necessary to put them in! */ #ifdef DBX_DEBUGGING_INFO #undef DBX_DEBUGGING_INFO #endif gcc-2.5.8/config/arm/rix-gas.h100444 22011 13 3030 5453576762 14551 0ustar kenneruser/* Definitions of target machine for GNU compiler. ARM RISCiX(stabs) version. Copyright (C) 1993 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rwe11@cl.cam.ac.uk), based on original work by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "arm/riscix.h" /* The native RISCiX assembler does not support stabs of any kind; because the native assembler is not used by the compiler, Acorn didn't feel it was necessary to put them in! However, this file assumes that we have an assembler that does have stabs, so we put them back in. */ #define DBX_DEBUGGING_INFO /* Unfortunately dbx doesn't understand these */ #define DEFAULT_GDB_EXTENSIONS 0 /* RISCiX dbx doesn't accept xrefs */ #define DBX_NO_XREFS 1 /* dbx wants lbracs before variables */ /* #define DBX_LBRAC_FIRST 1*/ gcc-2.5.8/config/arm/xm-arm.h100444 22011 13 4320 5461056576 14376 0ustar kenneruser/* Configuration for GNU C-compiler for Acorn RISC Machine. Copyright (C) 1991, 1993 Free Software Foundation, Inc. Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* #defines that need visibility everywhere. */ #define FALSE 0 #define TRUE 1 /* This describes the machine the compiler is hosted on. */ #define HOST_BITS_PER_CHAR 8 #define HOST_BITS_PER_SHORT 16 #define HOST_BITS_PER_INT 32 #define HOST_BITS_PER_LONG 32 /* A code distinguishing the floating point format of the host machine. There are three defined values: IEEE_FLOAT_FORMAT, VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */ #define HOST_FLOAT_FORMAT IEEE_FLOAT_FORMAT #define HOST_FLOAT_WORDS_BIG_ENDIAN 1 /* If not compiled with GNU C, use C alloca. */ #ifndef __GNUC__ #define USE_C_ALLOCA #endif /* Define this if the library function putenv is available on your machine */ #define HAVE_PUTENV 1 /* Define this if the library function vprintf is available on your machine */ #define HAVE_VPRINTF 1 /* Define this to be 1 if you know the host compiler supports prototypes, even if it doesn't define __STDC__, or define it to be 0 if you do not want any prototypes when compiling GNU CC. */ #define USE_PROTOTYPES 1 /* target machine dependencies. tm.h is a symbolic link to the actual target specific file. */ #include "tm.h" /* Arguments to use with `exit'. */ #define SUCCESS_EXIT_CODE 0 #define FATAL_EXIT_CODE 33 /* EOF xm-arm.h */ gcc-2.5.8/config/clipper/ 40777 22011 13 0 5502603156 13601 5ustar kennerusergcc-2.5.8/config/clipper/clipper.c100444 22011 13 26152 5417367154 15532 0ustar kenneruser/* Subroutines for insn-output.c for Clipper Copyright (C) 1987, 1988, 1991 Free Software Foundation, Inc. Contributed by Holger Teutsch (holger@hotbso.rhein-main.de) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include "config.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "output.h" #include "insn-attr.h" #include "tree.h" #include "c-tree.h" #include "expr.h" #include "flags.h" #include "machmode.h" extern char regs_ever_live[]; extern int frame_pointer_needed; static int frame_size; /* * compute size of a clipper stack frame where 'lsize' is the required * space for local variables. */ int clipper_frame_size (lsize) int lsize; { int i,size; /* total size of frame */ int save_size; save_size = 0; /* compute size for reg saves */ for (i = 16; i < 32; i++) if (regs_ever_live[i] && !call_used_regs[i]) save_size += 8; for (i = 0; i < 16; i++) if (regs_ever_live[i] && !call_used_regs[i]) save_size += 4; size = lsize + save_size; size = (size + 7) & ~7; /* align to 64 Bit */ return size; } /* * prologue and epilogue output * function is entered with pc pushed, i.e. stack is 32 bit aligned * * current_function_args_size == 0 means that the current function's args * are passed totally in registers i.e fp is not used as ap. * If frame_size is also 0 the current function does not push anything and * can run with misaligned stack -> subq $4,sp / add $4,sp on entry and exit * can be omitted. * */ void output_function_prologue (file, lsize) FILE *file; int lsize; /* size for locals */ { int i, offset; int size; frame_size = size = clipper_frame_size (lsize); if (frame_pointer_needed) { fputs ("\tpushw fp,sp\n", file); fputs ("\tmovw sp,fp\n", file); } else if (size != 0 || current_function_args_size != 0) { size += 4; /* keep stack aligned */ frame_size = size; /* must push data or access args */ } if (size) { if (size < 16) fprintf (file, "\tsubq $%d,sp\n", size); else fprintf (file, "\tsubi $%d,sp\n", size); /* register save slots are relative to sp, because we have small positive displacements and this works whether we have a frame pointer or not */ offset = 0; for (i = 16; i < 32; i++) if (regs_ever_live[i] && !call_used_regs[i]) { if (offset == 0) fprintf (file, "\tstord f%d,(sp)\n", i-16); else fprintf (file, "\tstord f%d,%d(sp)\n", i-16, offset); offset += 8; } for (i = 0; i < 16; i++) if (regs_ever_live[i] && !call_used_regs[i]) { if (offset == 0) fprintf (file, "\tstorw r%d,(sp)\n", i); else fprintf (file, "\tstorw r%d,%d(sp)\n", i, offset); offset += 4; } } } void output_function_epilogue (file, size) FILE *file; int size; /* ignored */ { int i, offset; if (frame_pointer_needed) { offset = -frame_size; for (i = 16; i < 32; i++) if (regs_ever_live[i] && !call_used_regs[i]) { fprintf (file, "\tloadd %d(fp),f%d\n", offset, i-16); offset += 8; } for (i = 0; i < 16; i++) if (regs_ever_live[i] && !call_used_regs[i]) { fprintf (file, "\tloadw %d(fp),r%d\n", offset, i); offset += 4; } fputs ("\tmovw fp,sp\n\tpopw sp,fp\n\tret sp\n", file); } else /* no frame pointer */ { offset = 0; for (i = 16; i < 32; i++) if (regs_ever_live[i] && !call_used_regs[i]) { if (offset == 0) fprintf (file, "\tloadd (sp),f%d\n", i-16); else fprintf (file, "\tloadd %d(sp),f%d\n", offset, i-16); offset += 8; } for (i = 0; i < 16; i++) if (regs_ever_live[i] && !call_used_regs[i]) { if (offset == 0) fprintf (file, "\tloadw (sp),r%d\n", i); else fprintf (file, "\tloadw %d(sp),r%d\n", offset, i); offset += 4; } if (frame_size > 0) { if (frame_size < 16) fprintf (file, "\taddq $%d,sp\n", frame_size); else fprintf (file, "\taddi $%d,sp\n", frame_size); } fputs ("\tret sp\n", file); } } /* * blockmove * * clipper_movstr () */ void clipper_movstr (operands) rtx *operands; { rtx dst,src,cnt,tmp,top,bottom,xops[3]; int align; int fixed; extern FILE *asm_out_file; dst = operands[0]; src = operands[1]; /* don't change this operands[2]; gcc 2.3.3 doesn't honor clobber note */ align = INTVAL (operands[3]); tmp = operands[4]; cnt = operands[5]; if (GET_CODE (operands[2]) == CONST_INT) /* fixed size move */ { if ((fixed = INTVAL (operands[2])) <= 0) abort (); if (fixed <16) output_asm_insn ("loadq %2,%5", operands); else output_asm_insn ("loadi %2,%5", operands); } else { fixed = 0; bottom = (rtx)gen_label_rtx (); /* need a bottom label */ xops[0] = cnt; xops[1] = bottom; output_asm_insn ("movw %2,%5", operands); /* count is scratch reg 5 */ output_asm_insn ("brle %l1", xops); } top = (rtx)gen_label_rtx (); /* top of loop label */ ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (top)); xops[0] = src; xops[1] = tmp; xops[2] = dst; if (fixed && (align & 0x3) == 0) /* word aligned move with known size */ { if (fixed >= 4) { rtx xops1[2]; output_asm_insn( "loadw %a0,%1\n\taddq $4,%0\n\tstorw %1,%a2\n\taddq $4,%2", xops); xops1[0] = cnt; xops1[1] = top; output_asm_insn ("subq $4,%0\n\tbrgt %l1", xops1); } if (fixed & 0x2) { output_asm_insn ("loadh %a0,%1\n\tstorh %1,%a2", xops); if (fixed & 0x1) output_asm_insn ("loadb 2%a0,%1\n\tstorb %1,2%a2", xops); } else if (fixed & 0x1) output_asm_insn ("loadb %a0,%1\n\tstorb %1,%a2", xops); } else { output_asm_insn( "loadb %a0,%1\n\taddq $1,%0\n\tstorb %1,%a2\n\taddq $1,%2", xops); xops[0] = cnt; xops[1] = top; output_asm_insn ("subq $1,%0\n\tbrgt %l1", xops); } if (fixed == 0) ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (bottom)); } print_operand_address (file, addr) FILE *file; register rtx addr; { rtx op0,op1; retry: switch (GET_CODE (addr)) { case REG: fprintf (file, "(%s)", reg_names[REGNO (addr)]); break; case PLUS: /* can be 'symbol + reg' or 'reg + reg' */ op0 = XEXP (addr, 0); op1 = XEXP (addr, 1); if (GET_CODE (op0) == REG && GET_CODE (op1) == REG) { fprintf (file, "[%s](%s)", reg_names[REGNO (op0)], reg_names[REGNO (op1)]); break; } if (GET_CODE (op0) == REG && CONSTANT_ADDRESS_P (op1)) { output_addr_const (file, op1); fprintf (file, "(%s)", reg_names[REGNO (op0)]); break; } if (GET_CODE (op1) == REG && CONSTANT_ADDRESS_P (op0)) { output_addr_const (file, op0); fprintf (file, "(%s)", reg_names[REGNO (op1)]); break; } abort (); /* Oh no */ default: output_addr_const (file, addr); } } char * rev_cond_name (op) rtx op; { switch (GET_CODE (op)) { case EQ: return "ne"; case NE: return "eq"; case LT: return "ge"; case LE: return "gt"; case GT: return "le"; case GE: return "lt"; case LTU: return "geu"; case LEU: return "gtu"; case GTU: return "leu"; case GEU: return "ltu"; default: abort (); } } /* Do what is necessary for `va_start'. The argument is ignored; We fill in an initial va_list. A pointer to this constructor is returned. */ struct rtx_def * clipper_builtin_saveregs (arglist) tree arglist; { extern int current_function_varargs; rtx block, addr, argsize, scratch, r0_addr,r1_addr,f0_addr,f1_addr; /* Allocate the va_list constructor + save area for r0,r1,f0,f1 */ block = assign_stack_local (BLKmode, (6 + 6) * UNITS_PER_WORD, 2 * BITS_PER_WORD); RTX_UNCHANGING_P (block) = 1; RTX_UNCHANGING_P (XEXP (block, 0)) = 1; addr = copy_to_reg (XEXP (block, 0)); f0_addr = gen_rtx (PLUS, Pmode, addr, gen_rtx (CONST_INT, Pmode, 24)); f1_addr = gen_rtx (PLUS, Pmode, addr, gen_rtx (CONST_INT, Pmode, 32)); r0_addr = gen_rtx (PLUS, Pmode, addr, gen_rtx (CONST_INT, Pmode, 40)); r1_addr = gen_rtx (PLUS, Pmode, addr, gen_rtx (CONST_INT, Pmode, 44)); /* Store float regs */ emit_move_insn (gen_rtx (MEM, DFmode, f0_addr), gen_rtx (REG, DFmode, 16)); emit_move_insn (gen_rtx (MEM, DFmode, f1_addr), gen_rtx (REG, DFmode, 17)); /* Store int regs */ emit_move_insn (gen_rtx (MEM, SImode, r0_addr), gen_rtx (REG, SImode, 0)); emit_move_insn (gen_rtx (MEM, SImode, r1_addr), gen_rtx (REG, SImode, 1)); /* Store the arg pointer in the __va_stk member. */ emit_move_insn (gen_rtx (MEM, SImode, addr), copy_to_reg (virtual_incoming_args_rtx)); /* now move addresses of the saved regs into the pointer array */ scratch = gen_reg_rtx (Pmode); emit_move_insn (scratch, r0_addr); emit_move_insn (gen_rtx (MEM, SImode, gen_rtx (PLUS, Pmode, addr, gen_rtx (CONST_INT, Pmode, 4))), scratch); emit_move_insn (scratch, f0_addr); emit_move_insn (gen_rtx (MEM, SImode, gen_rtx (PLUS, Pmode, addr, gen_rtx (CONST_INT, Pmode, 8))), scratch); emit_move_insn (scratch, r1_addr); emit_move_insn (gen_rtx (MEM, SImode, gen_rtx (PLUS, Pmode, addr, gen_rtx (CONST_INT, Pmode, 12))), scratch); emit_move_insn (scratch, f1_addr); emit_move_insn (gen_rtx (MEM, SImode, gen_rtx (PLUS, Pmode, addr, gen_rtx (CONST_INT, Pmode, 16))), scratch); /* Return the address of the va_list constructor, but don't put it in a register. This fails when not optimizing and produces worse code when optimizing. */ return XEXP (block, 0); } /* Return truth value of whether OP can be used as an word register operand. Reject (SUBREG:SI (REG:SF )) */ int int_reg_operand (op, mode) rtx op; enum machine_mode mode; { return (register_operand (op, mode) && (GET_CODE (op) != SUBREG || GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) == MODE_INT)); } /* Return truth value of whether OP can be used as a float register operand. Reject (SUBREG:SF (REG:SI )) )) */ int fp_reg_operand (op, mode) rtx op; enum machine_mode mode; { return (register_operand (op, mode) && (GET_CODE (op) != SUBREG || GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) == MODE_FLOAT)); } gcc-2.5.8/config/clipper/clipper.h100444 22011 13 116074 5473232441 15552 0ustar kenneruser/* Definitions of target machine for GNU compiler. Clipper version. Copyright (C) 1987, 1988, 1991, 1993 Free Software Foundation, Inc. Contributed by Holger Teutsch (holger@hotbso.rhein-main.de) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ extern struct rtx_def *clipper_builtin_saveregs (); extern int clipper_frame_size (); /* Print subsidiary information on the compiler version in use. */ #define TARGET_VERSION fprintf (stderr, " (clipper)"); /* Run-time compilation parameters selecting different hardware subsets. */ extern int target_flags; /* Macros used in the machine description to test the flags. */ /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */ #define TARGET_SWITCHES \ { { "c400", 1 }, \ { "c300", -1 }, \ { "", TARGET_DEFAULT} } #define TARGET_C400 1 #define TARGET_C300 0 /* Default target_flags if no switches specified. */ #ifndef TARGET_DEFAULT #define TARGET_DEFAULT TARGET_C300 #endif /* Omit frame pointer at -O2. Inline functions at -O3. */ #define OPTIMIZATION_OPTIONS(LEVEL) \ { \ if ((LEVEL) >= 2) \ { \ flag_omit_frame_pointer = 1; \ } \ if ((LEVEL) >= 3) \ flag_inline_functions = 1; \ } /* Target machine storage layout */ /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. */ #define BITS_BIG_ENDIAN 0 /* Define this if most significant byte of a word is the lowest numbered. */ #define BYTES_BIG_ENDIAN 0 /* Define this if most significant word of a multiword number is the lowest numbered. */ #define WORDS_BIG_ENDIAN 0 /* Number of bits in an addressable storage unit */ #define BITS_PER_UNIT 8 /* Width in bits of a "word", which is the contents of a machine register. Note that this is not necessarily the width of data type `int'; if using 16-bit ints on a 68000, this would still be 32. But on a machine with 16-bit registers, this would be 16. */ #define BITS_PER_WORD 32 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 4 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ #define POINTER_SIZE 32 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ #define PARM_BOUNDARY 32 /* Largest alignment for stack parameters (if greater than PARM_BOUNDARY). */ #define MAX_PARM_BOUNDARY 64 /* Allocation boundary (in *bits*) for the code of a function. */ #define FUNCTION_BOUNDARY 128 /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 32 /* Every structure's size must be a multiple of this. */ #define STRUCTURE_SIZE_BOUNDARY 8 /* A bitfield declared as `int' forces `int' alignment for the struct. */ #define PCC_BITFIELD_TYPE_MATTERS 1 /* No data type wants to be aligned rounder than this. */ #define BIGGEST_ALIGNMENT 64 /* No structure field wants to be aligned rounder than this. */ #define BIGGEST_FIELD_ALIGNMENT 64 /* Make strcpy of constants fast. */ #define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \ ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN)) /* Make arrays of chars word-aligned for the same reasons. */ #define DATA_ALIGNMENT(TYPE, ALIGN) \ (TREE_CODE (TYPE) == ARRAY_TYPE \ && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) /* Set this nonzero if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 1 /* Let's keep the stack somewhat aligned. */ #define STACK_BOUNDARY 64 /* Define this macro if it is advisible to hold scalars in registers in a wider mode than that declared by the program. In such cases, the value is constrained to be within the bounds of the declared type, but kept valid in the wider mode. The signedness of the extension may differ from that of the type. For Clipper, we always store objects in a full register. */ #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ if (GET_MODE_CLASS (MODE) == MODE_INT \ && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ { \ (UNSIGNEDP) = 0; \ (MODE) = SImode; \ } /* Define this if function arguments should also be promoted using the above procedure. */ /* FIXME: do we loose compatibility to acc if we define this? */ /* #define PROMOTE_FUNCTION_ARGS */ /* Likewise, if the function return value is promoted. */ /* #define PROMOTE_FUNCTION_RETURN */ /* Standard register usage. */ /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. */ #define FIRST_PSEUDO_REGISTER 32 /* 1 for registers that have pervasive standard uses and are not available for the register allocator. On the clipper, these are the FP and SP . */ #define FIXED_REGISTERS \ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,\ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1} /* Default: C300 */ /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. */ #define CALL_USED_REGISTERS \ {1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,\ 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1} /* default: C300 */ /* Zero or more C statements that may conditionally modify two variables `fixed_regs' and `call_used_regs' (both of type `char []') after they have been initialized from the two preceding macros. A C400 has additional floating registers f8 -> f15 */ #define CONDITIONAL_REGISTER_USAGE \ if (target_flags & TARGET_C400) \ { int i; \ for (i = 24; i < 32; i++) fixed_regs[i] = call_used_regs[i] = 0; } /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. On the clipper, fp registers are 64 bits. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ ((REGNO) >= 16 ? 1 \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On the clipper 0-15 may hold any mode but DImode and DFmode must be even. Registers 16-31 hold SFmode and DFmode */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ((REGNO) < 16 \ ? ((MODE) != DImode && (MODE) != DFmode || ((REGNO) & 1) == 0) \ : ((MODE) == SFmode || (MODE) == DFmode)) /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. */ #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2)) /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ /* clipper has extra PC */ /* #define PC_REGNUM */ /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM 15 /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM 14 /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */ #define FRAME_POINTER_REQUIRED \ (! leaf_function_p ()) /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM /* Register in which static-chain is passed to a function. */ #define STATIC_CHAIN_REGNUM 2 /* Register in which address to store a structure value is passed to a function. */ #define STRUCT_VALUE_REGNUM 0 /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. One of the classes must always be named ALL_REGS and include all hard regs. If there is more than one class, another class must be named NO_REGS and contain no registers. The name GENERAL_REGS must be the name of a class (or an alias for another name such as ALL_REGS). This is the class of registers that is allowed by "g" or "r" in a register constraint. Also, registers outside this class are allocated only when instructions express preferences for them. The classes must be numbered in nondecreasing order; that is, a larger-numbered class must never be contained completely in a smaller-numbered class. For any two classes, it is very desirable that there be another class that represents their union. */ /* The clipper has general and FP regs. */ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES}; #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" } /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS {0, 0x0000ffff, 0xffff0000, 0xffffffff} /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ #define REGNO_REG_CLASS(REGNO) ((REGNO) >= 16 ? FLOAT_REGS : GENERAL_REGS) /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS GENERAL_REGS #define BASE_REG_CLASS GENERAL_REGS /* Get reg_class from a letter such as appears in the machine description. */ #define REG_CLASS_FROM_LETTER(C) \ ((C) == 'r' ? GENERAL_REGS : ((C) == 'f' ? FLOAT_REGS: NO_REGS)) /* The letters I, J, K, L and M in a register constraint string can be used to stand for particular ranges of immediate operands. This macro defines what the ranges are. C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. */ #define CONST_OK_FOR_LETTER_P(VALUE, C) 0 /* Similar, but for floating constants, and defining letters G and H. Here VALUE is the CONST_DOUBLE rtx itself. */ #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0 /* Optional extra constraints for this machine. */ /* #define EXTRA_CONSTRAINT(OP, C) */ /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. */ #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ ((CLASS) == FLOAT_REGS \ ? 1 \ : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack makes the stack pointer a smaller address. */ #define STACK_GROWS_DOWNWARD /* Define this if longjmp restores from saved registers rather than from what setjmp saved. */ /* #define LONGJMP_RESTORE_FROM_STACK */ /* Define this if the nominal address of the stack frame is at the high-address end of the local variables; that is, each additional local variable allocated goes at a more negative offset in the frame. */ #define FRAME_GROWS_DOWNWARD /* Offset within stack frame to start allocating local variables at. If FRAME_GROWS_DOWNWARD, this is the offset to the END of the first local allocated. Otherwise, it is the offset to the BEGINNING of the first local allocated. */ #define STARTING_FRAME_OFFSET 0 /* Given an rtx for the address of a frame, return an rtx for the address of the word in the frame that holds the dynamic chain--the previous frame's address. */ #define DYNAMIC_CHAIN_ADDRESS(frame) (frame) /* If we generate an insn to push BYTES bytes, this says how many the stack pointer really advances by. */ /* #define PUSH_ROUNDING(BYTES) (BYTES) */ /* Keep the stack pointer constant throughout the function. */ /* we can't set this for clipper as library calls may have 3 args and we pass only 2 args in regs. */ /* #define ACCUMULATE_OUTGOING_ARGS */ /* Offset of first parameter from the argument pointer register value. size of PC + FP */ #define FIRST_PARM_OFFSET(FNDECL) 8 /* Value is the number of bytes of arguments automatically popped when returning from a subroutine call. FUNTYPE is the data type of the function (as a tree), or for a library call it is an identifier node for the subroutine name. SIZE is the number of bytes of arguments passed on the stack. */ #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0 /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ gen_rtx (REG, TYPE_MODE (VALTYPE), ((TYPE_MODE (VALTYPE) == SFmode ||\ TYPE_MODE (VALTYPE) == DFmode) ? \ 16 : 0)) /* Define how to find the value returned by a library function assuming the value has mode MODE. */ #define LIBCALL_VALUE(MODE) \ gen_rtx (REG, (MODE), ((MODE) == SFmode || (MODE) == DFmode ? 16 : 0)) /* 1 if N is a possible register number for a function value as seen by the caller. */ #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 16) /* 1 if N is a possible register number for function argument passing. */ #define FUNCTION_ARG_REGNO_P(N) \ ((N) == 0 || (N) == 1 || (N) == 16 || (N) == 17) /* Define this if PCC uses the nonreentrant convention for returning structure and union values. */ #define PCC_STATIC_STRUCT_RETURN /* Define a data type for recording info about an argument list during the scan of that argument list. This data type should hold all necessary information about the function itself and about the args processed so far, enough to enable macros such as FUNCTION_ARG to determine where the next arg should go. Clipper uses 2 register 'slots' that pass arguments in r0/r1 or f0/f1. An argument that must be passed in memory (struct... ) leaves that slot free. We pass 'long long' only in registers when both slots are free. Returned structs must be allocated by the caller, the address is passed in r0. struct ss {..} fun (i,j,k) i in r0, j in r1, k on stack fun (s,j,k) s on stack, j in r1, k on stack fun (i,s,k) i in r0, s on stack, k on stack s1 = fun (i,s,k) &s1 in r0, i in r1, s on stack, k on stack We must keep enough information for varargs/stdargs. _clipper_cum_args is a struct of 2 integers, with num = slots used size = size of all stack args = offset to next arg without alignment If we use stdarg.h, size points to the first unnamed arg, see va-clipper.h */ struct _clipper_cum_args { int num; int size; }; #define CUMULATIVE_ARGS struct _clipper_cum_args /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. clipper passes the address of a struct in r0, set num = 1 in this case */ #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ ((CUM).num = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE (FNTYPE))), \ (CUM).size = 0) /* internal helper : size of an argument */ #define CLIPPER_ARG_SIZE(MODE, TYPE) \ ((MODE) != BLKmode \ ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \ : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ do \ { \ int reg = 0; \ \ if ((CUM).num < 2 \ && (GET_MODE_CLASS(MODE)==MODE_INT || GET_MODE_CLASS(MODE)==MODE_FLOAT) \ && (GET_MODE_SIZE (MODE) <= 8) \ && ((MODE) != DImode || (CUM).num == 0)) \ { \ reg = 1; \ if ((MODE) == DImode) \ (CUM).num = 1; \ } \ \ (CUM).num++; \ \ if (! reg) \ { \ int align = FUNCTION_ARG_BOUNDARY (MODE, TYPE) / BITS_PER_UNIT; \ (CUM).size += align - 1; \ (CUM).size &= align - 1; \ (CUM).size += CLIPPER_ARG_SIZE (MODE, TYPE); \ } \ } while (0) /* Define where to put the arguments to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. MODE is the argument's machine mode. TYPE is the data type of the argument (as a tree). This is null for libcalls where that information may not be available. CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called. NAMED is nonzero if this argument is a named parameter (otherwise it is an extra parameter matching an ellipsis). 2 args may go into regs. These must be MODE_INT or MODE_FLOAT but only if they really fit into ONE register. The exception is a DImode arg that occupies both register slots. */ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ (((CUM).num < 2 \ && (GET_MODE_CLASS(MODE)==MODE_INT || GET_MODE_CLASS(MODE)==MODE_FLOAT) \ && (GET_MODE_SIZE (MODE) <= 8) \ && ((MODE) != DImode || (CUM).num == 0)) \ ? gen_rtx (REG, (MODE), \ GET_MODE_CLASS(MODE) == MODE_FLOAT ? (CUM).num+16 : (CUM).num) \ : 0) /* If defined, a C expression that gives the alignment boundary, in bits, of an argument with the specified mode and type. If it is not defined, `PARM_BOUNDARY' is used for all arguments. */ #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_SIZE (MODE)) <= PARM_BOUNDARY \ ? PARM_BOUNDARY : 2 * PARM_BOUNDARY) /* For an arg passed partly in registers and partly in memory, this is the number of registers used. For args passed entirely in registers or entirely in memory, zero. Clipper never passed args partially in regs/mem. */ /* #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 */ /* Generate necessary RTL for __builtin_saveregs(). ARGLIST is the argument list; see expr.c. */ #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) clipper_builtin_saveregs (ARGLIST) /* This macro generates the assembly code for function entry. FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. Refer to the array `regs_ever_live' to determine which registers to save; `regs_ever_live[I]' is nonzero if register number I is ever used in the function. This macro is responsible for knowing which registers should not be saved even if used. */ #define FUNCTION_PROLOGUE(FILE, SIZE) output_function_prologue (FILE,SIZE) /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ #define FUNCTION_PROFILER(FILE, LABELNO) /* FIXME */ /* Output assembler code to FILE to initialize this source file's basic block profiling info, if that has not already been done. */ #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) /* FIXME */ /* Output assembler code to FILE to increment the entry-count for the BLOCKNO'th basic block in this source file. */ #define BLOCK_PROFILER(FILE, BLOCKNO) /* FIXME */ /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, the stack pointer does not matter. The value is tested only in functions that have frame pointers. No definition is equivalent to always zero. */ #define EXIT_IGNORE_STACK 1 /* This macro generates the assembly code for function exit, on machines that need it. If FUNCTION_EPILOGUE is not defined then individual return instructions are generated for each return statement. Args are same as for FUNCTION_PROLOGUE. */ #define FUNCTION_EPILOGUE(FILE, SIZE) output_function_epilogue(FILE,SIZE) /* Store in the variable DEPTH the initial difference between the frame pointer reg contents and the stack pointer reg contents, as of the start of the function body. This depends on the layout of the fixed parts of the stack frame and on how registers are saved. */ #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ DEPTH = clipper_frame_size (get_frame_size ()) /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. */ #define TRAMPOLINE_TEMPLATE(FILE) \ { \ fputs ("\tcall sp,.+4\n", FILE); \ fputs ("\tmovw (sp),r3\n", FILE); \ fputs ("\taddq $4,sp\n", FILE); \ fputs ("\tloadw 32(r3),r2\n", FILE); \ fputs ("\tloadw 36(r3),r3\n", FILE); \ fputs ("\tb (r3)\n", FILE); \ } /* Length in units of the trampoline for entering a nested function. */ #define TRAMPOLINE_SIZE 44 /* Alignment required for a trampoline. 128 is used to find the beginning of a line in the instruction cache and to allow for instruction cache lines of up to 128 bytes. */ #define TRAMPOLINE_ALIGNMENT 128 /* Section in which to place the trampoline. */ #define TRAMPOLINE_SECTION text_section /* Emit RTL insns to initialize the variable parts of a trampoline. FNADDR is an RTX for the address of the function's pure code. CXT is an RTX for the static chain value for the function. */ #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 36)), CXT); \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 40)), FNADDR); \ } /* Addressing modes, and classification of registers for them. */ /* #define HAVE_POST_DECREMENT */ /* #define HAVE_PRE_INCREMENT */ /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. */ #define REGNO_OK_FOR_INDEX_P(regno) \ ((regno) < 16 || (unsigned)reg_renumber[regno] < 16) #define REGNO_OK_FOR_BASE_P(regno) \ ((regno) < 16 || (unsigned)reg_renumber[regno] < 16) /* Maximum number of registers that can appear in a valid memory address. */ #define MAX_REGS_PER_ADDRESS 2 /* 1 if X is an rtx for a constant that is a valid address. */ #define CONSTANT_ADDRESS_P(X) \ (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ || GET_CODE (X) == HIGH) /* Nonzero if the constant value X is a legitimate general operand. It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ #define LEGITIMATE_CONSTANT_P(X) 1 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. The usual definition accepts all pseudo regs; the other rejects them unless they have been allocated suitable hard regs. The symbol REG_OK_STRICT causes the latter definition to be used. Most source files want to accept pseudo regs in the hope that they will get allocated to the class that the insn wants them to be in. Source files for reload pass need to be strict. After reload, it makes no difference, since pseudo regs have been eliminated by then. */ /* clipper doesn't have true indexing */ #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ #define REG_OK_FOR_INDEX_P(X) \ (REGNO (X) < 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER) /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ #define REG_OK_FOR_BASE_P(X) \ (REGNO (X) < 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER) #else /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) (REGNO(X) < 16) /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) (REGNO(X) < 16) #endif /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, except for CONSTANT_ADDRESS_P which is actually machine-independent. */ /* Non-zero if X is an address which can be indirected. */ #define INDIRECTABLE_CONSTANT_ADDRESS_P(X) 0 #define INDIRECTABLE_ADDRESS_P(X) \ (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) /* Go to ADDR if X is a valid address not using indexing. (This much is the easy part.) */ #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ { if (CONSTANT_ADDRESS_P (X)) goto ADDR; \ if (INDIRECTABLE_ADDRESS_P (X)) goto ADDR; } #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { register rtx xfoo = (X); \ GO_IF_NONINDEXED_ADDRESS (xfoo, ADDR); \ if (GET_CODE (xfoo) == PLUS) \ { register rtx xfoo0, xfoo1; \ xfoo0 = XEXP (xfoo, 0); \ xfoo1 = XEXP (xfoo, 1); \ /* handle reg + reg -> [r1](r0) */ \ if (INDIRECTABLE_ADDRESS_P (xfoo0) && INDIRECTABLE_ADDRESS_P (xfoo1)) \ goto ADDR; \ /* Handle (reg) -> xxx(r0) */ \ if (INDIRECTABLE_ADDRESS_P (xfoo0) && CONSTANT_ADDRESS_P (xfoo1)) \ goto ADDR; \ if (INDIRECTABLE_ADDRESS_P (xfoo1) && CONSTANT_ADDRESS_P (xfoo0)) \ goto ADDR; }} /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. OLDX is the address as it was before break_out_memory_refs was called. In some cases it is useful to look at this to decide what needs to be done. MODE and WIN are passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. It is always safe for this macro to do nothing. It exists to recognize opportunities to optimize the output. For the clipper, nothing needs to be done. */ #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {} /* Go to LABEL if ADDR (a legitimate address expression) has an effect that depends on the machine mode it is used for. */ #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {} /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE SImode /* Define this if the case instruction expects the table to contain offsets from the address of the table. Do not define this if the table should contain absolute addresses. */ /* #define CASE_VECTOR_PC_RELATIVE */ /* Define this if the case instruction drops through after the table when the index is out of range. Don't define it if the case insn jumps to the default label instead. */ /* #define CASE_DROPS_THROUGH */ /* Define if operations between registers always perform the operation on the full register even if a narrower mode is specified. */ #define WORD_REGISTER_OPERATIONS /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly done, NIL if none. */ #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND /* Specify the tree operation to be used to convert reals to integers. */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR /* This is the kind of divide that is easiest to do in the general case. */ #define EASY_DIV_EXPR TRUNC_DIV_EXPR /* Define this as 1 if `char' should by default be signed; else as 0. */ #define DEFAULT_SIGNED_CHAR 1 /* This flag, if defined, says the same insns that convert to a signed fixnum also convert validly to an unsigned one. */ #define FIXUNS_TRUNC_LIKE_FIX_TRUNC /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ #define MOVE_MAX 4 /* MOVE_RATIO is the number of move instructions that is better than a block move. Make this large on clipper, since the block move is very inefficient with small blocks, and the hard register needs of the block move require much reload work. */ #define MOVE_RATIO 20 /* Define this if zero-extension is slow (more than one real instruction). */ /* #define SLOW_ZERO_EXTEND */ /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS 0 /* Define if shifts truncate the shift count which implies one can omit a sign-extension or zero-extension of a shift count. */ /* #define SHIFT_COUNT_TRUNCATED */ /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ #define Pmode SImode /* A function address in a call instruction is a byte address (for indexing purposes) so give the MEM rtx a byte's mode. */ #define FUNCTION_MODE QImode /* This machine uses IEEE floats. */ #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT /* Check a `double' value for validity for a particular machine mode. This is defined to avoid crashes outputting certain constants. Since we output the number in hex, the assembler won't choke on it. */ /* #define CHECK_FLOAT_VALUE(MODE,VALUE) */ /* Compute the cost of computing a constant rtl expression RTX whose rtx-code is CODE. The body of this macro is a portion of a switch statement. If the code is computed here, return it with a return statement. Otherwise, break from the switch. */ /* On a Clipper, constants from 0..15 are cheap because they can use the 'quick' mode. */ #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ if (0 <= INTVAL (RTX) && INTVAL(RTX) <= 15 ) return 0; \ return 1; \ case CONST: \ case LABEL_REF: \ case SYMBOL_REF: \ return 3; \ case CONST_DOUBLE: \ return 5; /* Provide the costs of a rtl expression. This is in the body of a switch on CODE. */ #define RTX_COSTS(X,CODE,OUTER_CODE) \ case MULT: \ return COSTS_N_INSNS (4); \ case DIV: \ case UDIV: \ case MOD: \ case UMOD: \ return COSTS_N_INSNS (40); \ case LSHIFT: \ case ASHIFT: \ case LSHIFTRT: \ case ASHIFTRT: \ return COSTS_N_INSNS (2); \ case SIGN_EXTEND: \ return (GET_CODE (XEXP (X,0)) == REG ? COSTS_N_INSNS (3) : 4); /* Specify the cost of a branch insn; roughly the number of extra insns that should be added to avoid a branch */ /* #define BRANCH_COST 0 */ /* Tell final.c how to eliminate redundant test instructions. */ /* Here we define machine-dependent flags and fields in cc_status (see `conditions.h'). No extra ones are needed for the clipper. */ /* Store in cc_status the expressions that the condition codes will describe after execution of an instruction whose pattern is EXP. Do not alter them if the instruction would not alter the cc's. */ #define NOTICE_UPDATE_CC(EXP, INSN) \ { \ enum attr_cc cc = get_attr_cc (INSN); \ rtx dest = SET_DEST (EXP); \ switch (cc) \ { \ case CC_CHANGE0: \ if (GET_CODE (EXP) == PARALLEL) abort(); \ if (cc_status.value1 && rtx_equal_p (dest, cc_status.value1) || \ cc_status.value2 && rtx_equal_p (dest, cc_status.value2)) \ CC_STATUS_INIT; \ break; \ \ case CC_SET1: \ if (GET_CODE (EXP) == PARALLEL) abort(); \ cc_status.flags = 0; \ cc_status.value1 = dest; \ cc_status.value2 = 0; \ break; \ \ case CC_SET2: \ if (GET_CODE (EXP) == PARALLEL) abort(); \ cc_status.flags = 0; \ cc_status.value1 = dest; \ cc_status.value2 = SET_SRC (EXP); \ break; \ \ case CC_UNCHANGED: \ break; \ \ case CC_CLOBBER: \ CC_STATUS_INIT; \ break; \ \ default: \ abort (); \ } \ } /* Control the assembler format that we output. */ /* Output at beginning of assembler file. */ #define ASM_FILE_START(FILE) fprintf (FILE, "#NO_APP\n"); /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ #define ASM_APP_ON "#APP\n" /* Output to assembler file text saying following lines no longer contain unusual constructs. */ #define ASM_APP_OFF "#NO_APP\n" /* Output before read-only data. */ #define TEXT_SECTION_ASM_OP ".text" /* Output before writable data. */ #define DATA_SECTION_ASM_OP ".data" /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ #define REGISTER_NAMES \ {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", \ "r9", "r10", "r11", "r12", "r13", "fp", "sp", \ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", \ "f9", "f10", "f11", "f12", "f13", "f14", "f15" } /* How to renumber registers for dbx and gdb. Clipper needs no change in the numeration. */ #define DBX_REGISTER_NUMBER(REGNO) (REGNO) /* This is how to output the definition of a user-level label named NAME, such as the label on a static function or variable NAME. */ #define ASM_OUTPUT_LABEL(FILE,NAME) \ do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) /* This is how to output a command to make the user-level label named NAME defined for reference from other files. */ #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) /* This is how to output an assembler line defining an `int' constant. */ #define ASM_OUTPUT_INT(FILE,VALUE) \ ( fprintf (FILE, "\t.long "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* Likewise for `char' and `short' constants. */ #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "\t.word "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ( fprintf (FILE, "\t.byte "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* This is how to output an assembler line for a numeric constant byte. */ #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tsubq $8,sp\n\t%s %s,(sp)\n", \ (REGNO) < 16 ? "storw" : "stord", reg_names[REGNO]) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\t%s (sp),%s\n\t\addq $8,sp\n", \ (REGNO) < 16 ? "loadw" : "loadd", reg_names[REGNO]) /* This is how to output an element of a case-vector that is absolute */ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "\t.long .L%d\n", VALUE) /* This is how to output an element of a case-vector that is relative. */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL) /* This is how to output an assembler line that says to advance the location counter by SIZE bytes. */ #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t.space %u\n", (SIZE)) /* This says how to output an assembler line to define a local common symbol. */ #define ASM_OUTPUT_ALIGNED_LOCAL(FILE,NAME,SIZE,ALIGN) \ ( data_section (), \ fputs ("\t.bss\t", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN)/BITS_PER_UNIT)) /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) /* Define the parentheses used to group arithmetic operations in assembler code. */ #define ASM_OPEN_PAREN "(" #define ASM_CLOSE_PAREN ")" /* Define results of standard character escape sequences. */ #define TARGET_BELL 007 #define TARGET_BS 010 #define TARGET_TAB 011 #define TARGET_NEWLINE 012 #define TARGET_VT 013 #define TARGET_FF 014 #define TARGET_CR 015 /* Print an instruction operand X on file FILE. CODE is the code from the %-spec that requested printing this operand; if `%z3' was used to print operand 3, then CODE is 'z'. Clipper operand formatting codes: letter print C reverse branch condition */ #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ ((CODE) == 'C') #define PRINT_OPERAND(FILE, X, CODE) \ { extern char *rev_cond_name (); \ if (CODE == 'C') \ fputs (rev_cond_name (X), FILE); \ else if (GET_CODE (X) == REG) \ fprintf (FILE, "%s", reg_names[REGNO (X)]); \ else if (GET_CODE (X) == MEM) \ output_address (XEXP (X, 0)); \ else { putc ('$', FILE); output_addr_const (FILE, X); }} /* Print a memory operand whose address is X, on file FILE. This uses a function in output-clipper.c. */ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ print_operand_address (FILE, ADDR) /* Define the codes that are matched by predicates in clipper.c */ #define PREDICATE_CODES \ {"int_reg_operand", {SUBREG, REG}}, \ {"fp_reg_operand", {SUBREG, REG}}, gcc-2.5.8/config/clipper/clipper.md100444 22011 13 104737 5473232446 15733 0ustar kenneruser;;- Machine description for GNU compiler, Clipper Version ;; Copyright (C) 1987, 1988, 1991, 1993 Free Software Foundation, Inc. ;; Contributed by Holger Teutsch (holger@hotbso.rhein-main.de) ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ;;- Instruction patterns. When multiple patterns apply, ;;- the first one in the file is chosen. ;;- ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ;;- ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code ;;- updates for most instructions. ;; ;; define attributes ;; ;; instruction type ;; ;; unknown is temporary in order to generate 'cc clobber' until attribute ;; assignment is consistent ;; (define_attr "type" "load,store,arith,fp,branch,unknown" (const_string "unknown")) ;; condition code setting ;; ;; clobber destroyed ;; unchanged ;; set1 set cc_status.value1, e.g. sub r0,r1 ;; set2 set value1 and value2, e.g. mov r0,r1 ;; change0 may be side effect, i.e. load mem,r0 ;; ;; note: loadi and loadq are 'arith' instructions that set the condition codes ;; mul,div,mod do NOT set the condition codes ;; (define_attr "cc" "clobber,unchanged,set1,set2,change0" (cond [(eq_attr "type" "load") (const_string "change0") (eq_attr "type" "store,branch") (const_string "unchanged") (eq_attr "type" "arith") (if_then_else (match_operand:SI 0 "" "") (const_string "set1") (const_string "clobber")) ] (const_string "clobber"))) ;; ;; clipper seems to be a tradional risc processor ;; we define a functional unit 'memory' ;; (define_function_unit "memory" 1 1 (eq_attr "type" "load") 4 0) ;; We don't want to allow a constant operand for test insns because ;; (set (cc0) (const_int foo)) has no mode information. Such insns will ;; be folded while optimizing anyway. (define_insn "tstsi" [(set (cc0) (match_operand:SI 0 "int_reg_operand" "r"))] "" "cmpq $0,%0") (define_insn "cmpsi" [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "r,r,n") (match_operand:SI 1 "nonmemory_operand" "r,n,r")))] "" "* { int val; if (which_alternative == 0) return \"cmpw %1,%0\"; if (which_alternative == 1) { val = INTVAL (operands[1]); if (0 <= val && val < 16) return \"cmpq %1,%0\"; return \"cmpi %1,%0\"; } cc_status.flags |= CC_REVERSED; /* immediate must be first */ val = INTVAL (operands[0]); if (0 <= val && val < 16) return \"cmpq %0,%1\"; return \"cmpi %0,%1\"; }") (define_insn "cmpdf" [(set (cc0) (compare (match_operand:DF 0 "fp_reg_operand" "f") (match_operand:DF 1 "fp_reg_operand" "f")))] "" "cmpd %1,%0") (define_insn "cmpsf" [(set (cc0) (compare (match_operand:SF 0 "fp_reg_operand" "f") (match_operand:SF 1 "fp_reg_operand" "f")))] "" "cmps %1,%0") ;; ;; double and single float move ;; (define_expand "movdf" [(set (match_operand:DF 0 "general_operand" "") (match_operand:DF 1 "general_operand" ""))] "" " { if (GET_CODE (operands[0]) == MEM) { if (GET_CODE (operands[1]) == CONST_DOUBLE) operands[1] = force_reg (DFmode, force_const_mem (DFmode, operands[1])); else if (GET_CODE (operands[1]) != REG) operands[1] = force_reg (DFmode, operands[1]); } else if (GET_CODE (operands[1]) == CONST_DOUBLE) operands[1] = force_const_mem (DFmode, operands[1]); }") ;; ;; provide two patterns with different predicates as we don't want combine ;; to recombine a mem -> mem move ;; (define_insn "" [(set (match_operand:DF 0 "register_operand" "=*rf") (match_operand:DF 1 "nonimmediate_operand" "*rfo"))] "" "* { #define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16) if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) /* f -> f */ return \"movd %1,%0\"; if (GET_CODE (operands[1]) == REG) /* r -> f */ return \"movld %1,%0\"; return \"loadd %1,%0\"; /* m -> f */ } if (FP_REG_P (operands[1])) { if (GET_CODE (operands[0]) == REG) /* f -> r */ return \"movdl %1,%0\"; abort (); } if (GET_CODE (operands[1]) == MEM) /* m -> r */ { rtx xops[4]; xops[0] = operands[0]; xops[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); xops[2] = operands[1]; xops[3] = adj_offsettable_operand (operands[1], 4); output_asm_insn (\"loadw %2,%0\;loadw %3,%1\", xops); return \"\"; } if (GET_CODE (operands[1]) == REG) /* r -> r */ { rtx xops[4]; xops[0] = operands[0]; xops[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); xops[2] = operands[1]; xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); output_asm_insn (\"movw %2,%0\;movw %3,%1\", xops); return \"\"; } abort (); #undef FP_REG_P }") (define_insn "" [(set (match_operand:DF 0 "memory_operand" "=o,m") (match_operand:DF 1 "register_operand" "*rf,f"))] "" "* { rtx xops[4]; if (REGNO (operands[1]) >= 16) /* f -> m */ return \"stord %1,%0\"; xops[0] = operands[0]; /* r -> o */ xops[1] = adj_offsettable_operand (operands[0], 4); xops[2] = operands[1]; xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops); return \"\"; }" [(set_attr "type" "store,store") (set_attr "cc" "clobber,unchanged")]) (define_expand "movsf" [(set (match_operand:SF 0 "general_operand" "") (match_operand:SF 1 "general_operand" ""))] "" " { if (GET_CODE (operands[0]) == MEM) { if (GET_CODE (operands[1]) == CONST_DOUBLE) operands[1] = force_reg (SFmode, force_const_mem (SFmode, operands[1])); else if (GET_CODE (operands[1]) != REG) operands[1] = force_reg (SFmode, operands[1]); } else if (GET_CODE (operands[1]) == CONST_DOUBLE) operands[1] = force_const_mem (SFmode, operands[1]); }") ;; ;; provide two patterns with different predicates as we don't want combine ;; to recombine a mem -> mem move ;; (define_insn "" [(set (match_operand:SF 0 "register_operand" "=*rf") (match_operand:SF 1 "nonimmediate_operand" "*rfm"))] "" "* { #define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16) if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) /* f -> f */ return \"movs %1,%0\"; if (GET_CODE (operands[1]) == REG) /* r -> f */ return \"subq $8,sp\;storw %1,(sp)\;loads (sp),%0\;addq $8,sp\"; return \"loads %1,%0\"; /* m -> f */ } if (FP_REG_P (operands[1])) { if (GET_CODE (operands[0]) == REG) /* f -> r */ return \"subq $8,sp\;stors %1,(sp)\;loadw (sp),%0\;addq $8,sp\"; abort (); } if (GET_CODE (operands[1]) == MEM) /* m -> r */ return \"loadw %1,%0\"; if (GET_CODE (operands[1]) == REG) /* r -> r */ return \"movw %1,%0\"; abort (); #undef FP_REG_P }") (define_insn "" [(set (match_operand:SF 0 "memory_operand" "=m") (match_operand:SF 1 "register_operand" "*rf"))] "" "* { if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) >= 16) return \"stors %1,%0\"; /* f-> m */ return \"storw %1,%0\"; /* r -> m */ }" [(set_attr "type" "store")]) (define_expand "movdi" [(set (match_operand:DI 0 "general_operand" "") (match_operand:DI 1 "general_operand" ""))] "" " { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG) operands[1] = force_reg (DImode, operands[1]); }") ;; If an operand is a MEM but not offsetable, we can't load it into ;; a register, so we must force the third alternative to be the one ;; reloaded. Hence we show the first as more expensive. (define_insn "" [(set (match_operand:DI 0 "register_operand" "=?r,r,r") (match_operand:DI 1 "general_operand" "r,n,o"))] "" "* { rtx xoperands[2],yoperands[2]; xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); if (which_alternative == 0) /* r -> r */ { output_asm_insn (\"movw %1,%0\", operands); xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); output_asm_insn (\"movw %1,%0\", xoperands); return \"\"; } if (which_alternative == 1) /* n -> r */ { if (GET_CODE (operands[1]) == CONST_INT) { output_asm_insn (\"loadi %1,%0\", operands); output_asm_insn (\"loadq $0,%0\", xoperands); return \"\"; } if (GET_CODE (operands[1]) != CONST_DOUBLE) abort (); yoperands[0] = operands[0]; yoperands[1] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (operands[1])); output_asm_insn (\"loadi %1,%0\", yoperands); xoperands[1] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_HIGH (operands[1])); output_asm_insn (\"loadi %1,%0\", xoperands); return \"\"; } /* m -> r */ output_asm_insn (\"loadw %1,%0\", operands); xoperands[1] = adj_offsettable_operand (operands[1], 4); output_asm_insn (\"loadw %1,%0\", xoperands); return \"\"; }" [(set_attr "type" "arith,arith,load") (set_attr "cc" "clobber,clobber,clobber")]) (define_insn "" [(set (match_operand:DI 0 "memory_operand" "=o") (match_operand:DI 1 "register_operand" "r"))] "" "* { rtx xops[4]; xops[0] = operands[0]; xops[1] = adj_offsettable_operand (operands[0], 4); xops[2] = operands[1]; xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops); return \"\"; }" [(set_attr "type" "store") (set_attr "cc" "clobber")]) (define_expand "movsi" [(set (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))] "" " { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG) operands[1] = force_reg (SImode, operands[1]); }") ;; provide 2 patterns with different predicates as 'general_operand' in both ;; positions results in a 'mem -> mem' move from combine that must be reloaded ;; (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (match_operand:SI 1 "general_operand" "r,m,n,i"))] "" "* { int val; if (which_alternative == 0) return \"movw %1,%0\"; /* reg -> reg */ if (which_alternative == 1) return \"loadw %1,%0\"; /* mem -> reg */ if (which_alternative == 2) { val = INTVAL (operands[1]); /* known const ->reg */ if (val == -1) return \"notq $0,%0\"; if (val < 0 || val >= 16) return \"loadi %1,%0\"; return \"loadq %1,%0\"; } if (which_alternative == 3) /* unknown const */ return \"loada %a1,%0\"; }" [(set_attr "type" "arith,load,arith,load") (set_attr "cc" "set2,change0,set1,change0")]) (define_insn "" [(set (match_operand:SI 0 "memory_operand" "=m") (match_operand:SI 1 "int_reg_operand" "r"))] "" "storw %1,%0" [(set_attr "type" "store")]) ;; movhi ;; ;; loadh mem to reg ;; storh reg to mem ;; ;; (define_expand "movhi" [(set (match_operand:HI 0 "general_operand" "") (match_operand:HI 1 "general_operand" ""))] "" " { if (GET_CODE (operands[0]) == MEM && ! register_operand (operands[1], HImode)) operands[1] = force_reg (HImode, operands[1]); }") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r,r,r") (match_operand:HI 1 "general_operand" "r,m,n"))] "" "@ movw %1,%0 loadh %1,%0 loadi %1,%0" [(set_attr "type" "arith,load,arith")]) (define_insn "" [(set (match_operand:HI 0 "memory_operand" "=m") (match_operand:HI 1 "register_operand" "r"))] "" "storh %1,%0" [(set_attr "type" "store")]) ;; movqi ;; ;; loadb mem to reg ;; storb reg to mem ;; (define_expand "movqi" [(set (match_operand:QI 0 "general_operand" "") (match_operand:QI 1 "general_operand" ""))] "" " { if (GET_CODE (operands[0]) == MEM && ! register_operand (operands[1], QImode)) operands[1] = force_reg (QImode, operands[1]); }") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r,r,r") (match_operand:QI 1 "general_operand" "r,m,n"))] "" "@ movw %1,%0 loadb %1,%0 loadi %1,%0" [(set_attr "type" "arith,load,arith")]) (define_insn "" [(set (match_operand:QI 0 "memory_operand" "=m") (match_operand:QI 1 "register_operand" "r"))] "" "storb %1,%0" [(set_attr "type" "store")]) ;; ;; block move ;; (define_expand "movstrsi" [(parallel [(set (match_operand:BLK 0 "memory_operand" "") (match_operand:BLK 1 "memory_operand" "")) (use (match_operand:SI 2 "general_operand" "")) (use (match_operand:SI 3 "const_int_operand" "")) (clobber (match_scratch:SI 4 "")) (clobber (match_scratch:SI 5 "")) (clobber (match_dup 6)) (clobber (match_dup 7))])] "" " { rtx addr0, addr1; addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); operands[6] = addr0; operands[7] = addr1; operands[0] = gen_rtx (MEM, BLKmode, addr0); operands[1] = gen_rtx (MEM, BLKmode, addr1); if (GET_CODE (operands[2]) != CONST_INT) operands[2] = force_reg (SImode, operands[2]); }") ;; ;; there is a problem with this insn in gcc-2.2.3 ;; (clobber (match_dup 2)) does not prevent use of this operand later ;; we always use a scratch register and leave operand 2 unchanged ;; (define_insn "" [(set (mem:BLK (match_operand:SI 0 "register_operand" "r")) (mem:BLK (match_operand:SI 1 "register_operand" "r"))) (use (match_operand:SI 2 "nonmemory_operand" "rn")) (use (match_operand:SI 3 "const_int_operand" "n")) (clobber (match_scratch:SI 4 "=r")) (clobber (match_scratch:SI 5 "=r")) (clobber (match_dup 0)) (clobber (match_dup 1))] "" "* { extern void clipper_movstr (); clipper_movstr (operands); return \"\"; }" [(set_attr "cc" "clobber")]) ;; Extension and truncation insns. (define_insn "extendhisi2" [(set (match_operand:SI 0 "int_reg_operand" "=r,r") (sign_extend:SI (match_operand:HI 1 "general_operand" "0,m")))] "" "@ andi $65535,%0\;xori $32768,%0\;subi $32768,%0 loadh %1,%0" [(set_attr "type" "arith,load")]) (define_insn "extendqihi2" [(set (match_operand:HI 0 "int_reg_operand" "=r,r") (sign_extend:HI (match_operand:QI 1 "general_operand" "0,m")))] "" "@ andi $255,%0\;xori $128,%0\;subi $128,%0 loadb %1,%0" [(set_attr "type" "arith,load") (set_attr "cc" "set1,change0")]) (define_insn "extendqisi2" [(set (match_operand:SI 0 "int_reg_operand" "=r,r") (sign_extend:SI (match_operand:QI 1 "general_operand" "0,m")))] "" "@ andi $255,%0\;xori $128,%0\;subi $128,%0 loadb %1,%0" [(set_attr "type" "arith,load")]) (define_insn "extendsfdf2" [(set (match_operand:DF 0 "fp_reg_operand" "=f") (float_extend:DF (match_operand:SF 1 "fp_reg_operand" "f")))] "" "cnvsd %1,%0") (define_insn "truncdfsf2" [(set (match_operand:SF 0 "fp_reg_operand" "=f") (float_truncate:SF (match_operand:DF 1 "fp_reg_operand" "f")))] "" "cnvds %1,%0") (define_insn "zero_extendhisi2" [(set (match_operand:SI 0 "int_reg_operand" "=r,r") (zero_extend:SI (match_operand:HI 1 "general_operand" "0,m")))] "" "@ andi $65535,%0 loadhu %1,%0" [(set_attr "type" "arith,load")]) (define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "int_reg_operand" "=r,r") (zero_extend:HI (match_operand:QI 1 "general_operand" "0,m")))] "" "@ andi $255,%0 loadbu %1,%0" [(set_attr "type" "arith,load") (set_attr "cc" "clobber,clobber")]) (define_insn "zero_extendqisi2" [(set (match_operand:SI 0 "int_reg_operand" "=r,r") (zero_extend:SI (match_operand:QI 1 "general_operand" "0,m")))] "" "@ andi $255,%0 loadbu %1,%0" [(set_attr "type" "arith,load")]) ;; Fix-to-float conversion insns. (define_insn "floatsisf2" [(set (match_operand:SF 0 "fp_reg_operand" "=f") (float:SF (match_operand:SI 1 "int_reg_operand" "r")))] "" "cnvws %1,%0") (define_insn "floatsidf2" [(set (match_operand:DF 0 "fp_reg_operand" "=f") (float:DF (match_operand:SI 1 "int_reg_operand" "r")))] "" "cnvwd %1,%0") ;; Float-to-fix conversion insns. (define_insn "fix_truncsfsi2" [(set (match_operand:SI 0 "int_reg_operand" "=r") (fix:SI (fix:SF (match_operand:SF 1 "fp_reg_operand" "f"))))] "" "cnvtsw %1,%0") (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "int_reg_operand" "=r") (fix:SI (fix:DF (match_operand:DF 1 "fp_reg_operand" "f"))))] "" "cnvtdw %1,%0") ;;- All kinds of add instructions. (define_insn "adddf3" [(set (match_operand:DF 0 "fp_reg_operand" "=f") (plus:DF (match_operand:DF 1 "fp_reg_operand" "0") (match_operand:DF 2 "fp_reg_operand" "f")))] "" "addd %2,%0" [(set_attr "type" "fp")]) (define_insn "addsf3" [(set (match_operand:SF 0 "fp_reg_operand" "=f") (plus:SF (match_operand:SF 1 "fp_reg_operand" "0") (match_operand:SF 2 "fp_reg_operand" "f")))] "" "adds %2,%0" [(set_attr "type" "fp")]) (define_insn "adddi3" [(set (match_operand:DI 0 "int_reg_operand" "=r") (plus:DI (match_operand:DI 1 "int_reg_operand" "%0") (match_operand:DI 2 "int_reg_operand" "r")))] "" "* { rtx xoperands[4]; xoperands[0] = operands[0]; xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); xoperands[2] = operands[2]; xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1); output_asm_insn (\"addw %2,%0\;addwc %3,%1\", xoperands); return \"\"; }" [(set_attr "type" "arith") (set_attr "cc" "clobber")]) (define_insn "addsi3" [(set (match_operand:SI 0 "int_reg_operand" "=r,r,r") (plus:SI (match_operand:SI 1 "int_reg_operand" "%0,r,r") (match_operand:SI 2 "nonmemory_operand" "rn,0,rn")))] "" "* { if (which_alternative == 2) /* 3 address version */ { if (GET_CODE (operands[2]) == CONST_INT) return \"loada %a2(%1),%0\"; return \"loada [%2](%1),%0\"; } /* 2 address version */ if (GET_CODE (operands[2]) == CONST_INT) { int val = INTVAL (operands[2]); if (val >= 16 || val == 0x80000000) return \"addi %2,%0\"; if (val < 0) /* change to sub */ { rtx xops[2]; val = -val; xops[0] = operands[0]; xops[1] = gen_rtx (CONST_INT, VOIDmode, val); if (val >= 16) output_asm_insn (\"subi %1,%0\", xops); else output_asm_insn (\"subq %1,%0\", xops); return \"\"; } return \"addq %2,%0\"; } if (which_alternative == 0) return \"addw %2,%0\"; return \"addw %1,%0\"; }" [(set_attr "type" "arith,arith,arith") (set_attr "cc" "set1,set1,change0")]) ;;- All kinds of subtract instructions. (define_insn "subdi3" [(set (match_operand:DI 0 "int_reg_operand" "=r") (minus:DI (match_operand:DI 1 "int_reg_operand" "%0") (match_operand:DI 2 "int_reg_operand" "r")))] "" "* { rtx xoperands[4]; xoperands[0] = operands[0]; xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); xoperands[2] = operands[2]; xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1); output_asm_insn (\"subw %2,%0\;subwc %3,%1\", xoperands); return \"\"; }" [(set_attr "type" "arith") (set_attr "cc" "clobber")]) (define_insn "subsi3" [(set (match_operand:SI 0 "int_reg_operand" "=r") (minus:SI (match_operand:SI 1 "int_reg_operand" "0") (match_operand:SI 2 "nonmemory_operand" "rn")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT) { int val = INTVAL (operands[2]); if (val < 0 || val >= 16) return \"subi %2,%0\"; else return \"subq %2,%0\"; } return \"subw %2,%0\"; }" [(set_attr "type" "arith")]) (define_insn "subdf3" [(set (match_operand:DF 0 "fp_reg_operand" "=f") (minus:DF (match_operand:DF 1 "fp_reg_operand" "0") (match_operand:DF 2 "fp_reg_operand" "f")))] "" "subd %2,%0" [(set_attr "type" "fp")]) (define_insn "subsf3" [(set (match_operand:SF 0 "fp_reg_operand" "=f") (minus:SF (match_operand:SF 1 "fp_reg_operand" "0") (match_operand:SF 2 "fp_reg_operand" "f")))] "" "subs %2,%0" [(set_attr "type" "fp")]) ;;- Multiply instructions. (define_insn "muldf3" [(set (match_operand:DF 0 "fp_reg_operand" "=f") (mult:DF (match_operand:DF 1 "fp_reg_operand" "0") (match_operand:DF 2 "fp_reg_operand" "f")))] "" "muld %2,%0" [(set_attr "type" "fp")]) (define_insn "mulsf3" [(set (match_operand:SF 0 "fp_reg_operand" "=f") (mult:SF (match_operand:SF 1 "fp_reg_operand" "0") (match_operand:SF 2 "fp_reg_operand" "f")))] "" "muls %2,%0" [(set_attr "type" "fp")]) (define_insn "mulsidi3" [(set (match_operand:DI 0 "int_reg_operand" "=r") (mult:DI (sign_extend:DI (match_operand:SI 1 "int_reg_operand" "%0")) (sign_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))] "" "mulwx %2,%0" [(set_attr "type" "arith") (set_attr "cc" "clobber")]) (define_insn "umulsidi3" [(set (match_operand:DI 0 "int_reg_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "int_reg_operand" "%0")) (zero_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))] "" "mulwux %2,%0" [(set_attr "type" "arith") (set_attr "cc" "clobber")]) (define_insn "mulsi3" [(set (match_operand:SI 0 "int_reg_operand" "=r") (mult:SI (match_operand:SI 1 "int_reg_operand" "%0") (match_operand:SI 2 "int_reg_operand" "r")))] "" "mulw %2,%0" [(set_attr "type" "arith") (set_attr "cc" "clobber")]) ;;- Divide and mod instructions. (define_insn "divdf3" [(set (match_operand:DF 0 "fp_reg_operand" "=f") (div:DF (match_operand:DF 1 "fp_reg_operand" "0") (match_operand:DF 2 "fp_reg_operand" "f")))] "" "divd %2,%0" [(set_attr "type" "fp")]) (define_insn "divsf3" [(set (match_operand:SF 0 "fp_reg_operand" "=f") (div:SF (match_operand:SF 1 "fp_reg_operand" "0") (match_operand:SF 2 "fp_reg_operand" "f")))] "" "divs %2,%0" [(set_attr "type" "fp")]) (define_insn "divsi3" [(set (match_operand:SI 0 "int_reg_operand" "=r") (div:SI (match_operand:SI 1 "int_reg_operand" "0") (match_operand:SI 2 "int_reg_operand" "r")))] "" "divw %2,%0" [(set_attr "type" "arith") (set_attr "cc" "clobber")]) (define_insn "udivsi3" [(set (match_operand:SI 0 "int_reg_operand" "=r") (udiv:SI (match_operand:SI 1 "int_reg_operand" "0") (match_operand:SI 2 "int_reg_operand" "r")))] "" "divwu %2,%0" [(set_attr "type" "arith") (set_attr "cc" "clobber")]) (define_insn "modsi3" [(set (match_operand:SI 0 "int_reg_operand" "=r") (mod:SI (match_operand:SI 1 "int_reg_operand" "0") (match_operand:SI 2 "int_reg_operand" "r")))] "" "modw %2,%0" [(set_attr "type" "arith") (set_attr "cc" "clobber")]) (define_insn "umodsi3" [(set (match_operand:SI 0 "int_reg_operand" "=r") (umod:SI (match_operand:SI 1 "int_reg_operand" "0") (match_operand:SI 2 "int_reg_operand" "r")))] "" "modwu %2,%0" [(set_attr "type" "arith") (set_attr "cc" "clobber")]) ;; ;; bit and/or instructions ;; (define_insn "andsi3" [(set (match_operand:SI 0 "int_reg_operand" "=r,r") (and:SI (match_operand:SI 1 "int_reg_operand" "%0,0") (match_operand:SI 2 "nonmemory_operand" "r,n")))] "" "@ andw %2,%0 andi %2,%0" [(set_attr "type" "arith")]) (define_insn "iorsi3" [(set (match_operand:SI 0 "int_reg_operand" "=r,r") (ior:SI (match_operand:SI 1 "int_reg_operand" "%0,0") (match_operand:SI 2 "nonmemory_operand" "r,n")))] "" "@ orw %2,%0 ori %2,%0" [(set_attr "type" "arith")]) (define_insn "xorsi3" [(set (match_operand:SI 0 "int_reg_operand" "=r,r") (xor:SI (match_operand:SI 1 "int_reg_operand" "%0,0") (match_operand:SI 2 "nonmemory_operand" "r,n")))] "" "@ xorw %2,%0 xori %2,%0" [(set_attr "type" "arith")]) (define_insn "negdf2" [(set (match_operand:DF 0 "fp_reg_operand" "=f") (neg:DF (match_operand:DF 1 "fp_reg_operand" "f")))] "" "negd %1,%0" [(set_attr "type" "fp")]) (define_insn "negsf2" [(set (match_operand:SF 0 "fp_reg_operand" "=f") (neg:SF (match_operand:SF 1 "fp_reg_operand" "f")))] "" "negs %1,%0" [(set_attr "type" "fp")]) (define_insn "negsi2" [(set (match_operand:SI 0 "int_reg_operand" "=r") (neg:SI (match_operand:SI 1 "int_reg_operand" "r")))] "" "negw %1,%0" [(set_attr "type" "arith")]) (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "int_reg_operand" "=r") (not:SI (match_operand:SI 1 "int_reg_operand" "r")))] "" "notw %1,%0" [(set_attr "type" "arith")]) ;; Right shift on the clipper works by negating the shift count, ;; then emitting a right shift with the shift count negated. This means ;; that all actual shift counts in the RTL will be positive. (define_expand "ashrdi3" [(set (match_operand:DI 0 "int_reg_operand" "") (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "") (match_operand:SI 2 "nonmemory_operand" "")))] "" " { if (GET_CODE (operands[2]) != CONST_INT) operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); }") (define_insn "" [(set (match_operand:DI 0 "int_reg_operand" "=r") (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") (match_operand:SI 2 "const_int_operand" "n")))] "" "shali $%n2,%0" [(set_attr "type" "arith")]) (define_insn "" [(set (match_operand:DI 0 "int_reg_operand" "=r") (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] "" "shal %2,%0" [(set_attr "type" "arith")]) (define_expand "ashrsi3" [(set (match_operand:SI 0 "int_reg_operand" "") (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "") (match_operand:SI 2 "nonmemory_operand" "")))] "" " { if (GET_CODE (operands[2]) != CONST_INT) operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); }") (define_insn "" [(set (match_operand:SI 0 "int_reg_operand" "=r") (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") (match_operand:SI 2 "const_int_operand" "n")))] "" "shai $%n2,%0" [(set_attr "type" "arith")]) (define_insn "" [(set (match_operand:SI 0 "int_reg_operand" "=r") (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] "" "shaw %2,%0" [(set_attr "type" "arith")]) ;; ;; left shift ;; (define_insn "ashldi3" [(set (match_operand:DI 0 "int_reg_operand" "=r,r") (ashift:DI (match_operand:DI 1 "int_reg_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "r,n")))] "" "@ shal %2,%0 shali %2,%0" [(set_attr "type" "arith")]) (define_insn "ashlsi3" [(set (match_operand:SI 0 "int_reg_operand" "=r,r") (ashift:SI (match_operand:SI 1 "int_reg_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "r,n")))] "" "* { int val; if (which_alternative == 0) return \"shaw %2,%0\"; val = INTVAL (operands[2]); if (val == 2) return \"addw %0,%0\;addw %0,%0\"; if (val == 1) return \"addw %0,%0\"; return \"shai %2,%0\"; }" [(set_attr "type" "arith")]) ;; ;; logical shift ;; (define_expand "lshrdi3" [(set (match_operand:DI 0 "int_reg_operand" "") (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "") (match_operand:SI 2 "nonmemory_operand" "")))] "" " { if (GET_CODE (operands[2]) != CONST_INT) operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); }") (define_insn "" [(set (match_operand:DI 0 "int_reg_operand" "=r") (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") (match_operand:SI 2 "const_int_operand" "n")))] "" "shlli $%n2,%0" [(set_attr "type" "arith")]) (define_insn "" [(set (match_operand:DI 0 "int_reg_operand" "=r") (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] "" "shll %2,%0" [(set_attr "type" "arith")]) (define_expand "lshrsi3" [(set (match_operand:SI 0 "int_reg_operand" "") (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "") (match_operand:SI 2 "nonmemory_operand" "")))] "" " { if (GET_CODE (operands[2]) != CONST_INT) operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); }") (define_insn "" [(set (match_operand:SI 0 "int_reg_operand" "=r") (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") (match_operand:SI 2 "const_int_operand" "n")))] "" "shli $%n2,%0" [(set_attr "type" "arith")]) (define_insn "" [(set (match_operand:SI 0 "int_reg_operand" "=r") (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] "" "shlw %2,%0" [(set_attr "type" "arith")]) (define_insn "lshldi3" [(set (match_operand:DI 0 "int_reg_operand" "=r,r") (lshift:DI (match_operand:DI 1 "int_reg_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "r,n")))] "" "@ shll %2,%0 shlli %2,%0" [(set_attr "type" "arith")]) (define_insn "lshlsi3" [(set (match_operand:SI 0 "int_reg_operand" "=r,r") (lshift:SI (match_operand:SI 1 "int_reg_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "r,n")))] "" "@ shlw %2,%0 shli %2,%0" [(set_attr "type" "arith")]) ;; ;; rotate insn ;; (define_expand "rotrdi3" [(set (match_operand:DI 0 "int_reg_operand" "") (rotatert:DI (match_operand:DI 1 "int_reg_operand" "") (match_operand:SI 2 "nonmemory_operand" "")))] "" " { if (GET_CODE (operands[2]) != CONST_INT) operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); }") (define_insn "" [(set (match_operand:DI 0 "int_reg_operand" "=r") (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0") (match_operand:SI 2 "const_int_operand" "n")))] "" "rotli $%n2,%0" [(set_attr "type" "arith")]) (define_insn "" [(set (match_operand:DI 0 "int_reg_operand" "=r") (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0") (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] "" "rotl %2,%0" [(set_attr "type" "arith")]) (define_expand "rotrsi3" [(set (match_operand:SI 0 "int_reg_operand" "") (rotatert:SI (match_operand:SI 1 "int_reg_operand" "") (match_operand:SI 2 "nonmemory_operand" "")))] "" " { if (GET_CODE (operands[2]) != CONST_INT) operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); }") (define_insn "" [(set (match_operand:SI 0 "int_reg_operand" "=r") (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0") (match_operand:SI 2 "const_int_operand" "n")))] "" "roti $%n2,%0" [(set_attr "type" "arith")]) (define_insn "" [(set (match_operand:SI 0 "int_reg_operand" "=r") (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0") (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] "" "rotw %2,%0" [(set_attr "type" "arith")]) (define_insn "rotldi3" [(set (match_operand:DI 0 "int_reg_operand" "=r,r") (rotate:DI (match_operand:DI 1 "int_reg_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "r,n")))] "" "@ rotl %2,%0 rotli %2,%0" [(set_attr "type" "arith")]) (define_insn "rotlsi3" [(set (match_operand:SI 0 "int_reg_operand" "=r,r") (rotate:SI (match_operand:SI 1 "int_reg_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "r,n")))] "" "@ rotw %2,%0 roti %2,%0" [(set_attr "type" "arith")]) ;; ;; jump and branch insns ;; (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "b %l0" [(set_attr "type" "branch")]) (define_insn "tablejump" [(set (pc) (match_operand:SI 0 "register_operand" "r")) (use (label_ref (match_operand 1 "" "")))] "" "b (%0)" [(set_attr "type" "branch")]) (define_insn "beq" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "breq %l0" [(set_attr "type" "branch")]) (define_insn "bne" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "brne %l0" [(set_attr "type" "branch")]) (define_insn "bgt" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "brgt %l0" [(set_attr "type" "branch")]) (define_insn "bgtu" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "brgtu %l0" [(set_attr "type" "branch")]) (define_insn "blt" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "brlt %l0" [(set_attr "type" "branch")]) (define_insn "bltu" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "brltu %l0" [(set_attr "type" "branch")]) (define_insn "bge" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "brge %l0" [(set_attr "type" "branch")]) (define_insn "bgeu" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "brgeu %l0" [(set_attr "type" "branch")]) (define_insn "ble" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "brle %l0" [(set_attr "type" "branch")]) (define_insn "bleu" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "brleu %l0" [(set_attr "type" "branch")]) ;; Recognize reversed jumps. (define_insn "" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(cc0) (const_int 0)]) (pc) (label_ref (match_operand 1 "" ""))))] "" "br%C0 %l1" ; %C0 negates condition [(set_attr "type" "branch")]) ;; ;; call instructions ;; (define_insn "call" [(call (match_operand:QI 0 "general_operand" "m") (match_operand:SI 1 "general_operand" ""))] ;; Operand 1 not used on the clipper. "" "call sp,%0") (define_insn "call_value" [(set (match_operand 0 "" "=rf") (call (match_operand:QI 1 "general_operand" "m") (match_operand:SI 2 "general_operand" "g")))] ;; Operand 2 not used on the clipper "" "call sp,%1") (define_insn "indirect_jump" [(set (pc) (match_operand:SI 0 "register_operand" "r"))] "" "b (%0)" [(set_attr "type" "branch")]) (define_insn "nop" [(const_int 0)] "" "noop" [(set_attr "type" "arith") (set_attr "cc" "unchanged")]) ;; while (--foo >= 0) ;; ;; Combiners for 'decrement test and branch' do not work for clipper. ;; These patters are jump_insns that do not allow output reloads and clipper ;; can only decrement and test registers. ;; gcc-2.5.8/config/clipper/clix.h100444 22011 13 10730 5453234441 15023 0ustar kenneruser/* Definitions of target machine for GNU compiler. Vax sysV version. Copyright (C) 1988 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "clipper/clipper.h" #include "svr3.h" /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Dclipper -Dunix -Asystem(unix) -Asystem(svr3) -Acpu(clipper) -Amachine(clipper)" #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} crtbegin.o%s" #undef ENDFILE_SPEC #define ENDFILE_SPEC "crtend.o%s crtn.o%s" #undef LIB_SPEC #undef HAVE_ATEXIT #define HAVE_ATEXIT #define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ { \ unsigned char *s; \ int i; \ for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++) \ { \ if ((i % 8) == 0) \ fputs ("\n\t.byte\t", (FILE)); \ fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \ } \ fputs ("\n", (FILE)); \ } #undef ASM_OUTPUT_DOUBLE #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ { \ union { int i[2]; double d; } _d_; \ _d_.d = VALUE; \ fprintf (FILE, "\t.long 0x%08x,0x%08x\n", _d_.i[0],_d_.i[1]); \ } #undef ASM_OUTPUT_FLOAT #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ { \ union { int i; float f; } _f_; \ _f_.f = VALUE; \ fprintf (FILE, "\t.long 0x%08x\n", _f_.i); \ } /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #define ASM_OUTPUT_ALIGN(FILE,LOG) \ fprintf(FILE, "\t.align %d\n", 1 << (LOG)) #define ASM_LONG ".long" #define BSS_SECTION_ASM_OP ".bss" #undef INIT_SECTION_ASM_OP #define INIT_SECTION_ASM_OP ".section .init,\"x\"" /* Define a few machine-specific details of the implementation of constructors. The __CTORS_LIST__ goes in the .init section. Define CTOR_LIST_BEGIN and CTOR_LIST_END to contribute to the .init section an instruction to push a word containing 0 (or some equivalent of that). ASM_OUTPUT_CONSTRUCTOR should be defined to push the address of the constructor. */ #define CTOR_LIST_BEGIN \ asm (INIT_SECTION_ASM_OP); \ asm ("subq $8,sp"); \ asm ("loadq $0,r0"); \ asm ("storw r0,(sp)") /* don't need end marker */ #undef CTOR_LIST_END #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ do { \ init_section (); \ fputs ("\tloada ", FILE); \ assemble_name (FILE, NAME); \ fputs (",r0\n\tsubq $8,sp\n\tstorw r0,(sp)\n", FILE); \ } while (0) /* fini psect is 8 aligned */ #define DTOR_LIST_BEGIN \ asm (DTORS_SECTION_ASM_OP); \ func_ptr __DTOR_LIST__[2] = { (func_ptr) (-1), 0 }; /* A C statement (sans semicolon) to output an element in the table of global destructors. */ #undef ASM_OUTPUT_DESTRUCTOR #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ do { \ fini_section (); \ fprintf (FILE, "%s\t ", ASM_LONG); \ assemble_name (FILE, NAME); \ fprintf (FILE, ",0\n"); \ } while (0) /* On clix crt1.o first calls init code and then sets environ and a valid chrclass. Unfortunately stdio routines bomb with unset chrclass. Therefore we set chrclass prior to calling global constructors. */ #undef DO_GLOBAL_CTORS_BODY #define DO_GLOBAL_CTORS_BODY \ do { \ func_ptr *p, *beg = alloca (0); \ _setchrclass (0); \ for (p = beg; *p; p+=2) \ ; \ while (p != beg) \ { p-= 2; (*p) (); } \ } while (0) #undef DO_GLOBAL_DTORS_BODY #define DO_GLOBAL_DTORS_BODY \ func_ptr *f = &__DTOR_LIST__[2]; /* 0,1 contains -1,0 */ \ int n = 0; \ while (*f) \ { \ f+= 2; /* skip over alignment 0 */ \ n++; \ } \ f -= 2; \ while (--n >= 0) \ { \ (*f) (); \ f-= 2; /* skip over alignment 0 */ \ } gcc-2.5.8/config/clipper/t-clix100444 22011 13 42 5354437730 14757 0ustar kenneruserEXTRA_PARTS = crtbegin.o crtend.o gcc-2.5.8/config/clipper/x-clix100444 22011 13 22 5336041212 14743 0ustar kenneruserALLOCA = alloca.o gcc-2.5.8/config/clipper/xm-clix.h100444 22011 13 1637 5413067053 15432 0ustar kenneruser/* Config file for Clipper running Clix, system V. 3.2 clone */ /* #defines that need visibility everywhere. */ #define FALSE 0 #define TRUE 1 /* target machine dependencies. tm.h is a symbolic link to the actual target specific file. */ #include "tm.h" /* This describes the machine the compiler is hosted on. */ #define HOST_BITS_PER_CHAR 8 #define HOST_BITS_PER_SHORT 16 #define HOST_BITS_PER_INT 32 #define HOST_BITS_PER_LONG 32 #define HOST_BITS_PER_LONGLONG 64 /* This machine uses IEEE floats. */ /* #define HOST_FLOAT_FORMAT IEEE_FLOAT_FORMAT */ /* Arguments to use with `exit'. */ #define SUCCESS_EXIT_CODE 0 #define FATAL_EXIT_CODE 33 /* isinf isn't there, but finite is. */ #define isinf(x) (!finite(x)) #define USG #define bcopy(a,b,c) memcpy (b,a,c) #define bzero(a,b) memset (a,0,b) #define bcmp(a,b,c) memcmp (a,b,c) #define index strchr #define rindex strrchr #define TARGET_MEM_FUNCTIONS gcc-2.5.8/config/convex/ 40777 22011 13 0 5502602734 13446 5ustar kennerusergcc-2.5.8/config/convex/convex.c100444 22011 13 36055 5376207021 15233 0ustar kenneruser/* Subroutines for insn-output.c for Convex. Copyright (C) 1988, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 1, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "config.h" #include "tree.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "insn-attr.h" #include "output.h" #include "expr.h" #undef NULL #include /* Tables used in convex.h */ char regno_ok_for_index_p_base[1 + LAST_VIRTUAL_REGISTER + 1]; enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; enum reg_class reg_class_from_letter[256]; /* Target cpu index. */ int target_cpu; /* Boolean to keep track of whether the current section is .text or not. Used by .align handler in convex.h. */ int current_section_is_text; /* Communication between output_compare and output_condjump. */ static rtx cmp_operand0, cmp_operand1; static char cmp_modech; /* Forwards */ static rtx frame_argblock; static int frame_argblock_size; static rtx convert_arg_pushes (); static void expand_movstr_call (); /* Here from OVERRIDE_OPTIONS at startup. Initialize constant tables. */ init_convex () { int regno; /* Set A and S reg classes. */ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) if (A_REGNO_P (regno)) { regno_ok_for_index_p[regno] = 1; regno_reg_class[regno] = INDEX_REGS; } else { regno_ok_for_index_p[regno] = 0; regno_reg_class[regno] = S_REGS; } /* Can't index off the stack pointer, register 0. */ regno_ok_for_index_p[STACK_POINTER_REGNUM] = 0; regno_reg_class[STACK_POINTER_REGNUM] = SP_REGS; /* Can't index off aliases of the stack pointer. */ regno_ok_for_index_p[VIRTUAL_INCOMING_ARGS_REGNUM] = 1; regno_ok_for_index_p[VIRTUAL_STACK_VARS_REGNUM] = 1; regno_ok_for_index_p[VIRTUAL_STACK_DYNAMIC_REGNUM] = 0; regno_ok_for_index_p[VIRTUAL_OUTGOING_ARGS_REGNUM] = 0; /* Can't index off hard reg -1 == pseudos not assigned */ regno_ok_for_index_p[-1] = 0; /* Set reg class letters */ reg_class_from_letter['a'] = A_REGS; reg_class_from_letter['A'] = INDEX_REGS; reg_class_from_letter['d'] = S_REGS; /* Turn off floating point exception enables in the psw. */ psw_disable_float (); } psw_disable_float () { #if __convex__ && __GNUC__ register int *p; asm ("mov fp,%0" : "=a" (p)); while (p) { p[1] &= ~0x1000c400; p = (int *) p[2]; } #endif } /* Here to output code for a compare insn. Output nothing, just record the operands and their mode. */ char * output_cmp (operand0, operand1, modech) rtx operand0, operand1; char modech; { cmp_operand0 = operand0; cmp_operand1 = operand1; cmp_modech = modech; return ""; } /* Output code for a conditional jump. The preceding instruction is necessarily a compare. Output two instructions, for example eq.w a1,a2 jbra.t L5 for (cmpsi a1 a2) (beq L5) */ char * output_condjump (label, cond, jbr_sense) rtx label; char *cond; char jbr_sense; { rtx operands[3]; char cmp_op[4]; char buf[80]; char jbr_regch; strcpy (cmp_op, cond); /* [BL] mean the value is being compared against immediate 0. Use neg.x, which produces the same carry that eq.x #0 would if it existed. In this case operands[1] is a scratch register, not a compare operand. */ if (cmp_modech == 'B' || cmp_modech == 'L') { cmp_modech = cmp_modech - 'A' + 'a'; strcpy (cmp_op, "neg"); } /* [WH] mean the value being compared resulted from "add.[wh] #-1,rk" when rk was nonnegative -- we can omit equality compares against -1 or inequality compares against 0. */ else if (cmp_modech == 'W' || cmp_modech == 'H') { if (! strcmp (cmp_op, "eq") && cmp_operand1 == constm1_rtx) jbr_sense ^= 't' ^ 'f'; else if (! strcmp (cmp_op, "lt") && cmp_operand1 == const0_rtx) ; else cmp_modech = cmp_modech - 'A' + 'a'; } /* Constant must be first; swap operands if necessary. If lt, le, ltu, leu are swapped, change to le, lt, leu, ltu and reverse the sense of the jump. */ if (! REG_P (cmp_operand1)) { operands[0] = cmp_operand1; operands[1] = cmp_operand0; if (cmp_op[0] == 'l') { cmp_op[1] ^= 'e' ^ 't'; jbr_sense ^= 't' ^ 'f'; } } else { operands[0] = cmp_operand0; operands[1] = cmp_operand1; } operands[2] = label; if (S_REG_P (operands[1])) jbr_regch = 's'; else if (A_REG_P (operands[1])) jbr_regch = 'a'; else abort (); if (cmp_modech == 'W' || cmp_modech == 'H') sprintf (buf, "jbr%c.%c %%l2", jbr_regch, jbr_sense); else sprintf (buf, "%s.%c %%0,%%1\n\tjbr%c.%c %%l2", cmp_op, cmp_modech, jbr_regch, jbr_sense); output_asm_insn (buf, operands); return ""; } /* Return 1 if OP is valid for cmpsf. In IEEE mode, +/- zero compares are not handled by the immediate versions of eq.s and on some machines, lt.s, and le.s. So disallow 0.0 as the immediate operand of xx.s compares in IEEE mode. */ int nonmemory_cmpsf_operand (op, mode) rtx op; enum machine_mode mode; { #if _IEEE_FLOAT_ if (op == CONST0_RTX (SFmode)) return 0; #endif return nonmemory_operand (op, mode); } /* Convex /bin/as does not like unary minus in some contexts. Simplify CONST addresses to remove it. */ rtx simplify_for_convex (x) rtx x; { switch (GET_CODE (x)) { case MINUS: if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) < 0) { PUT_CODE (x, PLUS); XEXP (x, 1) = GEN_INT (- INTVAL (XEXP (x, 1))); } break; case CONST: return simplify_for_convex (XEXP (x, 0)); } return x; } /* Routines to separate CONST_DOUBLEs into component parts. */ int const_double_high_int (x) rtx x; { if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) return CONST_DOUBLE_LOW (x); else return CONST_DOUBLE_HIGH (x); } int const_double_low_int (x) rtx x; { if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) return CONST_DOUBLE_HIGH (x); else return CONST_DOUBLE_LOW (x); } /* Inline block copy. */ void expand_movstr (operands) rtx *operands; { rtx dest = operands[0]; rtx src = operands[1]; int align = INTVAL (operands[3]); int nregs, maxsize; unsigned len; enum machine_mode mode; rtx reg, load, store, prev_store, prev_store_2; int size; /* Decide how many regs to use, depending on load latency, and what size pieces to move, depending on whether machine does unaligned loads and stores efficiently. */ if (TARGET_C1) { /* ld.l latency is 4, no alignment problems. */ nregs = 3, maxsize = 8; } else if (TARGET_C2) { /* loads are latency 2 if we avoid ld.l not at least word aligned. */ if (align >= 4) nregs = 2, maxsize = 8; else nregs = 2, maxsize = 4; } else if (TARGET_C34) { /* latency is 4 if aligned, horrible if not. */ nregs = 3, maxsize = align; } else if (TARGET_C38) { /* latency is 2 if at least word aligned, 3 or 4 if unaligned. */ if (align >= 4) nregs = 2, maxsize = 8; else nregs = 3, maxsize = 8; } else abort (); /* Caller is not necessarily prepared for us to fail in this expansion. So fall back by generating memcpy call here. */ if (GET_CODE (operands[2]) != CONST_INT || (len = INTVAL (operands[2])) > (unsigned) 32 * maxsize) { expand_movstr_call (operands); return; } reg = 0; prev_store = prev_store_2 = 0; while (len > 0) { if (len >= 8 && maxsize >= 8) mode = DImode; else if (len >= 4 && maxsize >= 4) mode = SImode; else if (len >= 2 && maxsize >= 2) mode = HImode; else mode = QImode; /* If no temp pseudo to reuse, or not the right mode, make one */ if (! reg || GET_MODE (reg) != mode) reg = gen_reg_rtx (mode); /* Get src and dest in the right mode */ if (GET_MODE (src) != mode) src = change_address (src, mode, 0), dest = change_address (dest, mode, 0); /* Make load and store patterns for this piece */ load = gen_rtx (SET, VOIDmode, reg, src); store = gen_rtx (SET, VOIDmode, dest, reg); /* Emit the load and the store from last time. When we emit a store, we can reuse its temp reg. */ emit_insn (load); if (prev_store) { reg = SET_SRC (prev_store); emit_insn (prev_store); } else reg = 0; /* Queue up the store, for next time or the time after that. */ if (nregs == 2) prev_store = store; else prev_store = prev_store_2, prev_store_2 = store; /* Advance to next piece. */ size = GET_MODE_SIZE (mode); src = adj_offsettable_operand (src, size); dest = adj_offsettable_operand (dest, size); len -= size; } /* Finally, emit the last stores. */ if (prev_store) emit_insn (prev_store); if (prev_store_2) emit_insn (prev_store_2); } static void expand_movstr_call (operands) rtx *operands; { emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0, VOIDmode, 3, XEXP (operands[0], 0), Pmode, XEXP (operands[1], 0), Pmode, operands[2], SImode); } #if _IEEE_FLOAT_ #define MAX_FLOAT 3.4028234663852886e+38 #define MIN_FLOAT 1.1754943508222875e-38 #else #define MAX_FLOAT 1.7014117331926443e+38 #define MIN_FLOAT 2.9387358770557188e-39 #endif void check_float_value (mode, dp) enum machine_mode mode; REAL_VALUE_TYPE *dp; { REAL_VALUE_TYPE d = *dp; if (mode == SFmode) { if (d > MAX_FLOAT) { error ("magnitude of constant too large for `float'"); *dp = MAX_FLOAT; } else if (d < -MAX_FLOAT) { error ("magnitude of constant too large for `float'"); *dp = -MAX_FLOAT; } else if ((d > 0 && d < MIN_FLOAT) || (d < 0 && d > -MIN_FLOAT)) { warning ("`float' constant truncated to zero"); *dp = 0.0; } } } /* Output the label at the start of a function. Precede it with the number of formal args so debuggers will have some idea of how many args to print. */ void asm_declare_function_name (file, name, decl) FILE *file; char *name; tree decl; { tree parms; int nargs = list_length (DECL_ARGUMENTS (decl)); char *p, c; extern char *version_string; static char vers[4]; int i; p = version_string; for (i = 0; i < 3; ) { c = *p; if (c - '0' < (unsigned) 10) vers[i++] = c; if (c == 0 || c == ' ') vers[i++] = '0'; else p++; } fprintf (file, "\tds.b \"g%s\"\n", vers); if (nargs < 100) fprintf (file, "\tds.b \"+%02d\\0\"\n", nargs); else fprintf (file, "\tds.b \"+00\\0\"\n"); ASM_OUTPUT_LABEL (file, name); } /* Print an instruction operand X on file FILE. CODE is the code from the %-spec that requested printing this operand; if `%z3' was used to print operand 3, then CODE is 'z'. */ /* Convex codes: %u prints a CONST_DOUBLE's high word %v prints a CONST_DOUBLE's low word %z prints a CONST_INT shift count as a multiply operand -- viz. 1 << n. */ print_operand (file, x, code) FILE *file; rtx x; char code; { long u[2]; REAL_VALUE_TYPE d; switch (GET_CODE (x)) { case REG: fprintf (file, "%s", reg_names[REGNO (x)]); break; case MEM: output_address (XEXP (x, 0)); break; case CONST_DOUBLE: REAL_VALUE_FROM_CONST_DOUBLE (d, x); switch (GET_MODE (x)) { case DFmode: #if 0 /* doesn't work, produces dfloats */ REAL_VALUE_TO_TARGET_DOUBLE (d, u); #else { union { double d; int i[2]; } t; t.d = d; u[0] = t.i[0]; u[1] = t.i[1]; } #endif if (code == 'u') fprintf (file, "#%#x", u[0]); else if (code == 'v') fprintf (file, "#%#x", u[1]); else outfloat (file, d, "%.17e", "#", ""); break; case SFmode: outfloat (file, d, "%.9e", "#", ""); break; default: if (code == 'u') fprintf (file, "#%d", CONST_DOUBLE_HIGH (x)); else fprintf (file, "#%d", CONST_DOUBLE_LOW (x)); } break; default: if (code == 'z') { if (GET_CODE (x) != CONST_INT) abort (); fprintf (file, "#%d", 1 << INTVAL (x)); } else { putc ('#', file); output_addr_const (file, x); } } } /* Print a memory operand whose address is X, on file FILE. */ print_operand_address (file, addr) FILE *file; rtx addr; { rtx index = 0; rtx offset = 0; if (GET_CODE (addr) == MEM) { fprintf (file, "@"); addr = XEXP (addr, 0); } switch (GET_CODE (addr)) { case REG: index = addr; break; case PLUS: index = XEXP (addr, 0); if (REG_P (index)) offset = XEXP (addr, 1); else { offset = XEXP (addr, 0); index = XEXP (addr, 1); if (! REG_P (index)) abort (); } break; default: offset = addr; break; } if (offset) output_addr_const (file, offset); if (index) fprintf (file, "(%s)", reg_names[REGNO (index)]); } /* Output a float to FILE, value VALUE, format FMT, preceded by PFX and followed by SFX. */ outfloat (file, value, fmt, pfx, sfx) FILE *file; REAL_VALUE_TYPE value; char *fmt, *pfx, *sfx; { char buf[64]; fputs (pfx, file); REAL_VALUE_TO_DECIMAL (value, fmt, buf); fputs (buf, file); fputs (sfx, file); } /* Here during RTL generation of return. If we are at the final return in a function, go through the function and replace pushes with stores into a frame arg block. This is similar to what ACCUMULATE_OUTGOING_ARGS does, but we must index off the frame pointer, not the stack pointer, and the calling sequence does not require the arg block to be at the top of the stack. */ replace_arg_pushes () { /* Doesn't work yet. */ } /* Output the insns needed to do a call. operands[] are 0 - MEM, the place to call 1 - CONST_INT, the number of bytes in the arg list 2 - CONST_INT, the number of arguments 3 - CONST_INT, the number of bytes to pop 4 - address of the arg list. */ char * output_call (insn, operands) rtx insn, *operands; { if (operands[4] == stack_pointer_rtx) output_asm_insn ("mov sp,ap", operands); else abort (); if (TARGET_ARGCOUNT) output_asm_insn ("pshea %a2", operands); output_asm_insn ("calls %0", operands); output_asm_insn ("ld.w 12(fp),ap", operands); if (operands[4] == stack_pointer_rtx && operands[3] != const0_rtx) output_asm_insn ("add.w %3,sp", operands); return ""; } /* Here after reloading, before the second scheduling pass. */ emit_ap_optimizations () { /* Removed for now. */ } gcc-2.5.8/config/convex/convex.h100444 22011 13 145772 5461322731 15270 0ustar kenneruser/* Definitions of target machine for GNU compiler. Convex version. Copyright (C) 1988, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Standard GCC variables that we reference. */ extern int target_flags; /* Convex machine-specific flags -mc1 target instruction set, libraries, scheduling -mc2 -mc32 -mc34 -mc38 -margcount use standard calling sequence, with arg count word -mno-argcount don't push arg count, depend on symbol table -margcount-nop place arg count in a nop instruction (faster than push) -mvolatile-cache use data cache for volatile mem refs (default) -mvolatile-nocache bypass data cache for volatile mem refs -mlong32 cc- and libc-compatible 32-bit longs -mlong64 64-bit longs */ /* Macro to define tables used to set -mXXX flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */ #ifndef TARGET_DEFAULT #error Use one of convex1.h, convex2.h, etc. #endif #define TARGET_SWITCHES \ { { "c1", 001 }, \ { "c2", 002 }, \ { "c32", 004 }, \ { "c34", 010 }, \ { "c38", 020 }, \ { "argcount", 0100 }, \ { "argcount-nop", 0200 }, \ { "no-argcount", -0300 }, \ { "volatile-cache", -0400 }, \ { "no-volatile-cache", 0400 }, \ { "volatile-nocache", 0400 }, \ { "long64", 01000 }, \ { "long32", -01000 }, \ { "", TARGET_DEFAULT }} /* Macros used in the machine description to test the flags. */ #define TARGET_C1 (target_cpu == 0) #define TARGET_C2 (target_cpu == 1) #define TARGET_C34 (target_cpu == 2) #define TARGET_C38 (target_cpu == 3) #define TARGET_ARGCOUNT (target_flags & 0100) #define TARGET_ARGCOUNT_NOP (target_flags & 0200) #define TARGET_LONG64 (target_flags & 01000) #define TARGET_VOLATILE_NOCACHE (target_flags & 0400) #define OVERRIDE_OPTIONS \ { \ extern int dollars_in_ident; \ init_convex (); \ /* To compile system header files, allow $ in identifiers even if -ansi */ \ dollars_in_ident = 1; \ if ((target_flags & 077) != (TARGET_DEFAULT & 077)) \ target_flags &= ~TARGET_DEFAULT; \ if (target_flags & 001) \ target_cpu = 0; \ else if (target_flags & 006) \ target_cpu = 1; \ else if (target_flags & 010) \ target_cpu = 2; \ else if (target_flags & 020) \ target_cpu = 3; \ } /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Dconvex -Dunix -Asystem(unix) -Acpu(convex) -Amachine(convex)" /* Print subsidiary information on the compiler version in use. */ #define TARGET_VERSION fprintf (stderr, " (convex)"); /* Target-dependent specs. Some libraries come in c1 and c2+ versions; use the appropriate ones. Make a target-dependent __convex_cxx__ define to relay the target cpu to the program being compiled. */ #if TARGET_DEFAULT & 1 /* C1 default */ #if _IEEE_FLOAT_ #define CPP_SPEC \ "%{!mc2:%{!mc32:%{!mc34:%{!mc38:-D__convex_c1__}}}} \ %{mc2:-D__convex_c2__} \ %{mc32:-D__convex_c32__} \ %{mc34:-D__convex_c34__} \ %{mc38:-D__convex_c38__} \ %{fno-builtin:-D__NO_INLINE} \ -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \ -D_IEEE_FLOAT_ \ %{.S:-P} \ %{!traditional:-D__stdc__} \ %{!traditional:-D_LONGLONG} \ %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \ %{!ansi:-D_POSIX_SOURCE} \ %{!ansi:-D_CONVEX_SOURCE}" #else #define CPP_SPEC \ "%{!mc2:%{!mc32:%{!mc34:%{!mc38:-D__convex_c1__}}}} \ %{mc2:-D__convex_c2__} \ %{mc32:-D__convex_c32__} \ %{mc34:-D__convex_c34__} \ %{mc38:-D__convex_c38__} \ %{fno-builtin:-D__NO_INLINE} \ -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \ -D_CONVEX_FLOAT_ \ %{.S:-P} \ %{!traditional:-D__stdc__} \ %{!traditional:-D_LONGLONG} \ %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \ %{!ansi:-D_POSIX_SOURCE} \ %{!ansi:-D_CONVEX_SOURCE}" #endif #define LIB_SPEC \ "%{!mc2:%{!mc32:%{!mc34:%{!mc38:-lC1%{traditional:_old}%{p:_p}%{pg:_p}}}}} \ %{mc2:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ %{mc32:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ %{mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ %{mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ -lc%{traditional:_old}%{p:_p}%{pg:_p}" #endif #if TARGET_DEFAULT & 2 /* C2 default */ #if _IEEE_FLOAT_ #define CPP_SPEC \ "%{mc1:-D__convex_c1__} \ %{!mc1:%{!mc32:%{!mc34:%{!mc38:-D__convex_c2__}}}} \ %{mc32:-D__convex_c32__} \ %{mc34:-D__convex_c34__} \ %{mc38:-D__convex_c38__} \ %{fno-builtin:-D__NO_INLINE} \ -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \ -D_IEEE_FLOAT_ \ %{.S:-P} \ %{!traditional:-D__stdc__} \ %{!traditional:-D_LONGLONG} \ %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \ %{!ansi:-D_POSIX_SOURCE} \ %{!ansi:-D_CONVEX_SOURCE}" #else #define CPP_SPEC \ "%{mc1:-D__convex_c1__} \ %{!mc1:%{!mc32:%{!mc34:%{!mc38:-D__convex_c2__}}}} \ %{mc32:-D__convex_c32__} \ %{mc34:-D__convex_c34__} \ %{mc38:-D__convex_c38__} \ %{fno-builtin:-D__NO_INLINE} \ -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \ -D_CONVEX_FLOAT_ \ %{.S:-P} \ %{!traditional:-D__stdc__} \ %{!traditional:-D_LONGLONG} \ %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \ %{!ansi:-D_POSIX_SOURCE} \ %{!ansi:-D_CONVEX_SOURCE}" #endif #define LIB_SPEC \ "%{mc1:-lC1%{traditional:_old}%{p:_p}%{pg:_p}} \ %{!mc1:%{!mc32:%{!mc34:%{!mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}}}} \ %{mc32:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ %{mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ %{mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ -lc%{traditional:_old}%{p:_p}%{pg:_p}" #endif #if TARGET_DEFAULT & 4 /* C32 default */ #if _IEEE_FLOAT_ #define CPP_SPEC \ "%{mc1:-D__convex_c1__} \ %{mc2:-D__convex_c2__} \ %{!mc1:%{!mc2:%{!mc34:%{!mc38:-D__convex_c32__}}}} \ %{mc34:-D__convex_c34__} \ %{mc38:-D__convex_c38__} \ %{fno-builtin:-D__NO_INLINE} \ -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \ -D_IEEE_FLOAT_ \ %{.S:-P} \ %{!traditional:-D__stdc__} \ %{!traditional:-D_LONGLONG} \ %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \ %{!ansi:-D_POSIX_SOURCE} \ %{!ansi:-D_CONVEX_SOURCE}" #else #define CPP_SPEC \ "%{mc1:-D__convex_c1__} \ %{mc2:-D__convex_c2__} \ %{!mc1:%{!mc2:%{!mc34:%{!mc38:-D__convex_c32__}}}} \ %{mc34:-D__convex_c34__} \ %{mc38:-D__convex_c38__} \ %{fno-builtin:-D__NO_INLINE} \ -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \ -D_CONVEX_FLOAT_ \ %{.S:-P} \ %{!traditional:-D__stdc__} \ %{!traditional:-D_LONGLONG} \ %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \ %{!ansi:-D_POSIX_SOURCE} \ %{!ansi:-D_CONVEX_SOURCE}" #endif #define LIB_SPEC \ "%{mc1:-lC1%{traditional:_old}%{p:_p}%{pg:_p}} \ %{mc2:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ %{!mc1:%{!mc2:%{!mc34:%{!mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}}}} \ %{mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ %{mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ -lc%{traditional:_old}%{p:_p}%{pg:_p}" #endif #if TARGET_DEFAULT & 010 /* C34 default */ #if _IEEE_FLOAT_ #define CPP_SPEC \ "%{mc1:-D__convex_c1__} \ %{mc2:-D__convex_c2__} \ %{mc32:-D__convex_c32__} \ %{!mc1:%{!mc2:%{!mc32:%{!mc38:-D__convex_c34__}}}} \ %{mc38:-D__convex_c38__} \ %{fno-builtin:-D__NO_INLINE} \ -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \ -D_IEEE_FLOAT_ \ %{.S:-P} \ %{!traditional:-D__stdc__} \ %{!traditional:-D_LONGLONG} \ %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \ %{!ansi:-D_POSIX_SOURCE} \ %{!ansi:-D_CONVEX_SOURCE}" #else #define CPP_SPEC \ "%{mc1:-D__convex_c1__} \ %{mc2:-D__convex_c2__} \ %{mc32:-D__convex_c32__} \ %{!mc1:%{!mc2:%{!mc32:%{!mc38:-D__convex_c34__}}}} \ %{mc38:-D__convex_c38__} \ %{fno-builtin:-D__NO_INLINE} \ -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \ -D_CONVEX_FLOAT_ \ %{.S:-P} \ %{!traditional:-D__stdc__} \ %{!traditional:-D_LONGLONG} \ %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \ %{!ansi:-D_POSIX_SOURCE} \ %{!ansi:-D_CONVEX_SOURCE}" #endif #define LIB_SPEC \ "%{mc1:-lC1%{traditional:_old}%{p:_p}%{pg:_p}} \ %{mc2:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ %{mc32:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ %{!mc1:%{!mc2:%{!mc32:%{!mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}}}} \ %{mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ -lc%{traditional:_old}%{p:_p}%{pg:_p}" #endif #if TARGET_DEFAULT & 020 /* C38 default */ #if _IEEE_FLOAT_ #define CPP_SPEC \ "%{mc1:-D__convex_c1__} \ %{mc2:-D__convex_c2__} \ %{mc32:-D__convex_c32__} \ %{mc34:-D__convex_c34__} \ %{fno-builtin:-D__NO_INLINE} \ -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \ -D_IEEE_FLOAT_ \ %{!mc1:%{!mc2:%{!mc32:%{!mc34:-D__convex_c38__}}}} \ %{.S:-P} \ %{!traditional:-D__stdc__} \ %{!traditional:-D_LONGLONG} \ %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \ %{!ansi:-D_POSIX_SOURCE} \ %{!ansi:-D_CONVEX_SOURCE}" #else #define CPP_SPEC \ "%{mc1:-D__convex_c1__} \ %{mc2:-D__convex_c2__} \ %{mc32:-D__convex_c32__} \ %{mc34:-D__convex_c34__} \ %{fno-builtin:-D__NO_INLINE} \ -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \ -D_CONVEX_FLOAT_ \ %{!mc1:%{!mc2:%{!mc32:%{!mc34:-D__convex_c38__}}}} \ %{.S:-P} \ %{!traditional:-D__stdc__} \ %{!traditional:-D_LONGLONG} \ %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \ %{!ansi:-D_POSIX_SOURCE} \ %{!ansi:-D_CONVEX_SOURCE}" #endif #define LIB_SPEC \ "%{mc1:-lC1%{traditional:_old}%{p:_p}%{pg:_p}} \ %{mc2:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ %{mc32:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ %{mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \ %{!mc1:%{!mc2:%{!mc32:%{!mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}}}} \ -lc%{traditional:_old}%{p:_p}%{pg:_p}" #endif #if _IEEE_FLOAT_ /* ieee default */ #define ASM_SPEC "-fi" #define LINK_SPEC \ "-E%{traditional:no}posix \ -X \ %{F} %{M*} %{y*} \ -fi \ -A__iob=___ap$iob \ -A_use_libc_sema=___ap$use_libc_sema \ %{traditional:-A___gcc_cleanup=__cleanup} \ %{!traditional:-A___gcc_cleanup=___ap$do_registered_functions} \ -L/usr/lib" #define STARTFILE_SPEC \ "%{!pg:%{!p:/usr/lib/crt/crt0.o}} \ %{!pg:%{p:/usr/lib/crt/mcrt0.o}} \ %{pg:/usr/lib/crt/gcrt0.o} \ /usr/lib/crt/fpmode_i.o" #else /* native default */ #define ASM_SPEC "-fn" #define LINK_SPEC \ "-E%{traditional:no}posix \ -X \ %{F} %{M*} %{y*} \ -fn \ -A__iob=___ap$iob \ -A_use_libc_sema=___ap$use_libc_sema \ %{traditional:-A___gcc_cleanup=__cleanup} \ %{!traditional:-A___gcc_cleanup=___ap$do_registered_functions} \ -L/usr/lib" #define STARTFILE_SPEC \ "%{!pg:%{!p:/usr/lib/crt/crt0.o}} \ %{!pg:%{p:/usr/lib/crt/mcrt0.o}} \ %{pg:/usr/lib/crt/gcrt0.o}" #endif /* Use /path/libgcc.a instead of -lgcc, makes bootstrap work more smoothly. */ #define LINK_LIBGCC_SPECIAL_1 /* Allow $ in identifiers. */ #define DOLLARS_IN_IDENTIFIERS 2 /* Since IEEE support was added to gcc, most things seem to like it better if we disable exceptions and check afterward for infinity. */ #if __convex__ #if _IEEE_FLOAT_ #define REAL_VALUE_ISNAN(x) 0 #define REAL_VALUE_ISINF(x) ((*(short *) &(x) & 0x7ff0) == 0x7ff0) #else #define REAL_VALUE_ISNAN(x) 0 #define REAL_VALUE_ISINF(x) ((*(short *) &(x) & 0xfff0) == 0x8000) #endif #endif /* Target machine storage layout */ /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. */ #define BITS_BIG_ENDIAN 1 /* Define this if most significant byte of a word is the lowest numbered. */ #define BYTES_BIG_ENDIAN 1 /* Define this if most significant word of a multiword number is numbered. */ #define WORDS_BIG_ENDIAN 1 /* Number of bits in an addressable storage unit */ #define BITS_PER_UNIT 8 /* Width in bits of a "word", which is the contents of a machine register. Note that this is not necessarily the width of data type `int'; if using 16-bit ints on a 68000, this would still be 32. But on a machine with 16-bit registers, this would be 16. */ #define BITS_PER_WORD 64 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 8 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ #define POINTER_SIZE 32 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ #define PARM_BOUNDARY 32 /* Boundary (in *bits*) on which stack pointer should be aligned. */ #define STACK_BOUNDARY 64 /* Allocation boundary (in *bits*) for the code of a function. */ #define FUNCTION_BOUNDARY 16 /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 32 /* Every structure's size must be a multiple of this. */ #define STRUCTURE_SIZE_BOUNDARY 8 /* A bitfield declared as `int' forces `int' alignment for the struct. */ #define PCC_BITFIELD_TYPE_MATTERS 1 /* No data type wants to be aligned rounder than this. */ /* beware of doubles in structs -- 64 is incompatible with cc */ #define BIGGEST_ALIGNMENT 32 /* Set this nonzero if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 0 /* Define sizes of basic C types to conform to ordinary usage -- these types depend on BITS_PER_WORD otherwise. */ #define CHAR_TYPE_SIZE 8 #define SHORT_TYPE_SIZE 16 #define INT_TYPE_SIZE 32 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) #define LONG_LONG_TYPE_SIZE 64 #define FLOAT_TYPE_SIZE 32 #define DOUBLE_TYPE_SIZE 64 #define LONG_DOUBLE_TYPE_SIZE 64 /* This prevents cexp.c from depending on LONG_TYPE_SIZE. */ #define MAX_LONG_TYPE_SIZE 64 /* Declare the standard types used by builtins to match convex stddef.h -- with int rather than long. */ #define SIZE_TYPE "unsigned int" #define PTRDIFF_TYPE "int" /* Standard register usage. */ /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. */ #define FIRST_PSEUDO_REGISTER 16 /* 1 for registers that have pervasive standard uses and are not available for the register allocator. For Convex, these are AP, FP, and SP. */ #define FIXED_REGISTERS \ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1 } /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. */ #define CALL_USED_REGISTERS \ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } /* List the order in which to allocate registers. Each register must be listed once, even those in FIXED_REGISTERS. For Convex, put S0 (the return register) last. */ #define REG_ALLOC_ORDER \ { 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 0, 8, 14, 15 } /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On Convex, S registers can hold any type, A registers any nonfloat. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ (S_REGNO_P (REGNO) \ || (GET_MODE_SIZE (MODE) <= 4 && (MODE) != SFmode)) /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. */ #define MODES_TIEABLE_P(MODE1, MODE2) \ ((GET_MODE_SIZE (MODE1) <= 4 && (MODE1) != SFmode) \ == (GET_MODE_SIZE (MODE2) <= 4 && (MODE2) != SFmode)) /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ #define S0_REGNUM 0 #define A0_REGNUM 8 /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM A0_REGNUM /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM (A0_REGNUM + 7) /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */ #define FRAME_POINTER_REQUIRED 1 /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM (A0_REGNUM + 6) /* Register in which static-chain is passed to a function. Use S0, not an A reg, because this rare use would otherwise prevent an A reg from being available to global-alloc across calls. */ #define STATIC_CHAIN_REGNUM S0_REGNUM /* Register in which address to store a structure value is passed to a function. */ #define STRUCT_VALUE_REGNUM (A0_REGNUM + 1) /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. One of the classes must always be named ALL_REGS and include all hard regs. If there is more than one class, another class must be named NO_REGS and contain no registers. The name GENERAL_REGS must be the name of a class (or an alias for another name such as ALL_REGS). This is the class of registers that is allowed by "g" or "r" in a register constraint. Also, registers outside this class are allocated only when instructions express preferences for them. The classes must be numbered in nondecreasing order; that is, a larger-numbered class must never be contained completely in a smaller-numbered class. For any two classes, it is very desirable that there be another class that represents their union. */ /* Convex has classes A (address) and S (scalar). A is further divided into SP_REGS (stack pointer) and INDEX_REGS. SI_REGS is S_REGS + INDEX_REGS -- all the regs except SP. */ enum reg_class { NO_REGS, S_REGS, INDEX_REGS, SP_REGS, A_REGS, SI_REGS, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Since GENERAL_REGS is the same class as ALL_REGS, don't give it a different class number; just make it an alias. */ #define GENERAL_REGS ALL_REGS /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ {"NO_REGS", "S_REGS", "INDEX_REGS", "SP_REGS", "A_REGS", "SI_REGS", \ "ALL_REGS" } /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS \ { 0, 0x00ff, 0xfe00, 0x0100, 0xff00, 0xfeff, 0xffff } /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ #define REGNO_REG_CLASS(REGNO) (regno_reg_class[REGNO]) #define S_REGNO_P(REGNO) (((REGNO) - S0_REGNUM) < (unsigned) 8) #define A_REGNO_P(REGNO) (((REGNO) - A0_REGNUM) < (unsigned) 8) #define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X))) #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X))) /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS INDEX_REGS #define BASE_REG_CLASS INDEX_REGS /* Get reg_class from a letter such as appears in the machine description. */ /* a => A_REGS d => S_REGS ('s' is taken) A => INDEX_REGS (i.e., A_REGS except sp) */ #define REG_CLASS_FROM_LETTER(C) \ reg_class_from_letter[(unsigned char) (C)] /* The letters I, J, K, L and M in a register constraint string can be used to stand for particular ranges of immediate operands. This macro defines what the ranges are. C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. */ /* 'I' is used to pass any CONST_INT and reject any CONST_DOUBLE. CONST_DOUBLE integers are handled by G and H constraint chars. */ #define CONST_OK_FOR_LETTER_P(VALUE, C) 1 /* Similar, but for floating constants, and defining letters G and H. Here VALUE is the CONST_DOUBLE rtx itself. */ /* Convex uses G, H: value usable in ld.d (low word 0) or ld.l (high word all sign) */ #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ (((C) == 'G' && LD_D_P (VALUE)) || \ ((C) == 'H' && LD_L_P (VALUE)) || \ 0) #define LD_D_P(X) (const_double_low_int (X) == 0) #define LD_L_P(X) (const_double_low_int (X) >= 0 \ ? const_double_high_int (X) == 0 \ : const_double_high_int (X) == -1) /* Optional extra constraints for this machine. For Convex, 'Q' means that OP is a volatile MEM. For volatile scalars, we use instructions that bypass the data cache. */ #define EXTRA_CONSTRAINT(OP, C) \ ((C) == 'Q' ? (GET_CODE (OP) == MEM && MEM_VOLATILE_P (OP) \ && ! TARGET_C1 && TARGET_VOLATILE_NOCACHE) \ : 0) /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. */ /* Put 2-word constants that can't be immediate operands into memory. */ #define PREFERRED_RELOAD_CLASS(X,CLASS) \ ((GET_CODE (X) != CONST_DOUBLE \ || GET_MODE (X) == SFmode \ || LD_L_P (X) || LD_D_P (X)) ? (CLASS) : NO_REGS) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) + 7) / 8) /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack makes the stack pointer a smaller address. */ #define STACK_GROWS_DOWNWARD /* Define this if the nominal address of the stack frame is at the high-address end of the local variables; that is, each additional local variable allocated goes at a more negative offset in the frame. */ #define FRAME_GROWS_DOWNWARD /* Define this if should default to -fcaller-saves. */ #define DEFAULT_CALLER_SAVES /* Offset within stack frame to start allocating local variables at. If FRAME_GROWS_DOWNWARD, this is the offset to the END of the first local allocated. Otherwise, it is the offset to the BEGINNING of the first local allocated. */ #define STARTING_FRAME_OFFSET 0 /* If we generate an insn to push BYTES bytes, this says how many the stack pointer really advances by. */ #define PUSH_ROUNDING(BYTES) (((BYTES) + 3) & ~3) /* Offset of first parameter from the argument pointer register value. */ #define FIRST_PARM_OFFSET(FNDECL) 0 /* Value is the number of bytes of arguments automatically popped when returning from a subroutine call. FUNTYPE is the data type of the function (as a tree), or for a library call it is an identifier node for the subroutine name. SIZE is the number of bytes of arguments passed on the stack. */ #define RETURN_POPS_ARGS(FUNTYPE, SIZE) (SIZE) /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ gen_rtx (REG, TYPE_MODE (VALTYPE), S0_REGNUM) /* Define how to find the value returned by a library function assuming the value has mode MODE. */ #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, S0_REGNUM) /* Define this if PCC uses the nonreentrant convention for returning structure and union values. */ #define PCC_STATIC_STRUCT_RETURN /* 1 if N is a possible register number for a function value. On the Convex, S0 is the only register thus used. */ #define FUNCTION_VALUE_REGNO_P(N) ((N) == S0_REGNUM) /* 1 if N is a possible register number for function argument passing. */ #define FUNCTION_ARG_REGNO_P(N) 0 /* Define a data type for recording info about an argument list during the scan of that argument list. This data type should hold all necessary information about the function itself and about the args processed so far, enough to enable macros such as FUNCTION_ARG to determine where the next arg should go. */ /* On convex, simply count the arguments in case TARGET_ARGCOUNT is set. */ #define CUMULATIVE_ARGS int /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ ((CUM) = 0) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ ((CUM) += 1) /* Define where to put the arguments to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. MODE is the argument's machine mode. TYPE is the data type of the argument (as a tree). This is null for libcalls where that information may not be available. CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called. NAMED is nonzero if this argument is a named parameter (otherwise it is an extra parameter matching an ellipsis). Convex: all args go on the stack. But return the arg count as the "next arg register" to be passed to gen_call. */ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ ((MODE) == VOIDmode ? gen_rtx (CONST_INT, VOIDmode, (CUM)) : 0) /* This macro generates the assembly code for function entry. FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. Refer to the array `regs_ever_live' to determine which registers to save; `regs_ever_live[I]' is nonzero if register number I is ever used in the function. This macro is responsible for knowing which registers should not be saved even if used. */ #define FUNCTION_PROLOGUE(FILE, SIZE) \ { \ int size = ((SIZE) + 7) & -8; \ if (size != 0) \ fprintf (FILE, "\tsub.w #%d,sp\n", size); \ } /* This macro generates the assembly code for function exit, on machines that need it. If FUNCTION_EPILOGUE is not defined then individual return instructions are generated for each return statement. Args are same as for FUNCTION_PROLOGUE. */ #define FUNCTION_EPILOGUE(FILE, SIZE) \ { \ /* Follow function with a zero to stop c34 icache prefetching. */ \ fprintf (FILE, "\tds.h 0\n"); \ } /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. */ /* On convex, the code for a trampoline is ld.w #,s0 jmp */ #define TRAMPOLINE_TEMPLATE(FILE) \ { \ fprintf (FILE, "\tld.w #69696969,s0\n"); \ fprintf (FILE, "\tjmp 52525252\n"); \ } /* Length in units of the trampoline for entering a nested function. */ #define TRAMPOLINE_SIZE 12 /* Emit RTL insns to initialize the variable parts of a trampoline. FNADDR is an RTX for the address of the function's pure code. CXT is an RTX for the static chain value for the function. */ #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ emit_move_insn (gen_rtx (MEM, Pmode, plus_constant (TRAMP, 2)), CXT); \ emit_move_insn (gen_rtx (MEM, Pmode, plus_constant (TRAMP, 8)), FNADDR); \ emit_call_insn (gen_call_pop (gen_rtx (MEM, QImode, \ gen_rtx (SYMBOL_REF, Pmode, \ "__enable_execute_stack")), \ const0_rtx, const0_rtx, const0_rtx)); \ } /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ #define FUNCTION_PROFILER(FILE, LABELNO) \ fprintf (FILE, "\tldea LP%d,a1\n\tcallq mcount\n", (LABELNO)); /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, the stack pointer does not matter. The value is tested only in functions that have frame pointers. No definition is equivalent to always zero. */ #define EXIT_IGNORE_STACK 1 /* Store in the variable DEPTH the initial difference between the frame pointer reg contents and the stack pointer reg contents, as of the start of the function body. This depends on the layout of the fixed parts of the stack frame and on how registers are saved. */ #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ { (DEPTH) = (get_frame_size () + 7) & -8; } /* Addressing modes, and classification of registers for them. */ /* #define HAVE_POST_INCREMENT */ /* #define HAVE_POST_DECREMENT */ /* #define HAVE_PRE_DECREMENT */ /* #define HAVE_PRE_INCREMENT */ /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. */ #define REGNO_OK_FOR_INDEX_P(regno) \ ((regno) <= LAST_VIRTUAL_REGISTER \ ? regno_ok_for_index_p[regno] \ : regno_ok_for_index_p[reg_renumber[regno]]) #define REGNO_OK_FOR_BASE_P(regno) REGNO_OK_FOR_INDEX_P (regno) /* Maximum number of registers that can appear in a valid memory address. */ #define MAX_REGS_PER_ADDRESS 1 /* 1 if X is an rtx for a constant that is a valid address. */ #define CONSTANT_ADDRESS_P(X) \ (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ || GET_CODE (X) == HIGH) /* Nonzero if the constant value X is a legitimate general operand. It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ /* For convex, bounce 2-word constants that can't be immediate operands. */ #define LEGITIMATE_CONSTANT_P(X) \ (GET_CODE (X) != CONST_DOUBLE \ || GET_MODE (X) == SFmode \ || LD_L_P (X) || LD_D_P (X)) /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. The usual definition accepts all pseudo regs; the other rejects them unless they have been allocated suitable hard regs. The symbol REG_OK_STRICT causes the latter definition to be used. Most source files want to accept pseudo regs in the hope that they will get allocated to the class that the insn wants them to be in. Source files for reload pass need to be strict. After reload, it makes no difference, since pseudo regs have been eliminated by then. */ #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ #define REG_OK_FOR_INDEX_P(X) \ (REGNO (X) > LAST_VIRTUAL_REGISTER || regno_ok_for_index_p[REGNO (X)]) /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X) #else /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) #endif /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. For Convex, valid addresses are indirectable or (MEM indirectable) where indirectable is const, reg, (PLUS reg const) We don't use indirection since with insn scheduling, load + indexing is better. */ /* 1 if X is an address that we could indirect through. */ #define INDIRECTABLE_ADDRESS_P(X) \ (CONSTANT_ADDRESS_P (X) \ || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ || (GET_CODE (X) == PLUS \ && GET_CODE (XEXP (X, 0)) == REG \ && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ || (GET_CODE (X) == PLUS \ && GET_CODE (XEXP (X, 1)) == REG \ && REG_OK_FOR_BASE_P (XEXP (X, 1)) \ && CONSTANT_ADDRESS_P (XEXP (X, 0)))) /* Go to ADDR if X is a valid address. */ #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { register rtx xfoob = (X); \ if (INDIRECTABLE_ADDRESS_P (xfoob)) \ goto ADDR; \ if (GET_CODE (xfoob) == PRE_DEC && XEXP (xfoob, 0) == stack_pointer_rtx) \ goto ADDR; \ } /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. OLDX is the address as it was before break_out_memory_refs was called. In some cases it is useful to look at this to decide what needs to be done. MODE and WIN are passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. It is always safe for this macro to do nothing. It exists to recognize opportunities to optimize the output. For Convex, nothing needs to be done. */ #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {} /* Go to LABEL if ADDR (a legitimate address expression) has an effect that depends on the machine mode it is used for. */ #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {} /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE SImode /* Define this if the case instruction expects the table to contain offsets from the address of the table. Do not define this if the table should contain absolute addresses. */ /* #define CASE_VECTOR_PC_RELATIVE */ /* Define this if the case instruction drops through after the table when the index is out of range. Don't define it if the case insn jumps to the default label instead. */ /* #define CASE_DROPS_THROUGH */ /* Specify the tree operation to be used to convert reals to integers. */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR /* This is the kind of divide that is easiest to do in the general case. */ #define EASY_DIV_EXPR TRUNC_DIV_EXPR /* Define this as 1 if `char' should by default be signed; else as 0. */ #define DEFAULT_SIGNED_CHAR 1 /* This flag, if defined, says the same insns that convert to a signed fixnum also convert validly to an unsigned one. */ #define FIXUNS_TRUNC_LIKE_FIX_TRUNC /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ #define MOVE_MAX 8 /* Define this if zero-extension is slow (more than one real instruction). */ /* #define SLOW_ZERO_EXTEND */ /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS (! TARGET_C2) /* Define if shifts truncate the shift count which implies one can omit a sign-extension or zero-extension of a shift count. */ /* #define SHIFT_COUNT_TRUNCATED */ /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 /* On Convex, it is as good to call a constant function address as to call an address kept in a register. */ #define NO_FUNCTION_CSE /* When a prototype says `char' or `short', really pass an `int'. */ #define PROMOTE_PROTOTYPES /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ #define Pmode SImode /* A function address in a call instruction is a byte address (for indexing purposes) so give the MEM rtx a byte's mode. */ #define FUNCTION_MODE QImode /* Compute the cost of computing a constant rtl expression RTX whose rtx-code is CODE. The body of this macro is a portion of a switch statement. If the code is computed here, return it with a return statement. Otherwise, break from the switch. */ #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST: \ case LABEL_REF: \ case SYMBOL_REF: \ case CONST_INT: \ case CONST_DOUBLE: \ return 0; /* Provide the costs of a rtl expression. This is in the body of a switch on CODE. */ #define RTX_COSTS(RTX,CODE,OUTER_CODE) \ case PLUS: \ if (regno_pointer_flag != 0 \ && GET_CODE (XEXP (RTX, 0)) == REG \ && REGNO_POINTER_FLAG (REGNO (XEXP (RTX, 0))) \ && GET_CODE (XEXP (RTX, 1)) == CONST_INT) \ return 0; \ else break; \ case MULT: \ return 4 * (char) (0x03060403 >> target_cpu * 8); \ case LSHIFT: \ case ASHIFT: \ case LSHIFTRT: \ case ASHIFTRT: \ return 4 * (char) (0x03010403 >> target_cpu * 8); \ case MEM: \ return 5; /* Compute the cost of an address. This is meant to approximate the size and/or execution delay of an insn using that address. If the cost is approximated by the RTL complexity, including CONST_COSTS above, as is usually the case for CISC machines, this macro should not be defined. For aggressively RISCy machines, only one insn format is allowed, so this macro should be a constant. The value of this macro only matters for valid addresses. */ #define ADDRESS_COST(RTX) 0 /* Specify the cost of a branch insn; roughly the number of extra insns that should be added to avoid a branch. */ #define BRANCH_COST 0 /* Adjust the cost of dependences. */ #define ADJUST_COST(INSN,LINK,DEP,COST) \ { \ /* Antidependencies don't block issue. */ \ if (REG_NOTE_KIND (LINK) != 0) \ (COST) = 0; \ /* C38 situations where delay depends on context */ \ else if (TARGET_C38 \ && GET_CODE (PATTERN (INSN)) == SET \ && GET_CODE (PATTERN (DEP)) == SET) \ { \ enum attr_type insn_type = get_attr_type (INSN); \ enum attr_type dep_type = get_attr_type (DEP); \ /* index register must be ready one cycle early */ \ if (insn_type == TYPE_MLDW || insn_type == TYPE_MLDL \ || (insn_type == TYPE_MST \ && reg_mentioned_p (SET_DEST (PATTERN (DEP)), \ SET_SRC (PATTERN (INSN))))) \ (COST) += 1; \ /* alu forwarding off alu takes two */ \ if (dep_type == TYPE_ALU \ && insn_type != TYPE_ALU \ && ! (insn_type == TYPE_MST \ && SET_DEST (PATTERN (DEP)) == SET_SRC (PATTERN (INSN)))) \ (COST) += 1; \ } \ } /* Convex uses Vax or IEEE floats. Follow the host format. */ #define TARGET_FLOAT_FORMAT HOST_FLOAT_FORMAT /* But must prevent real.c from constructing Vax dfloats */ #define REAL_VALUE_ATOF(X,S) atof (X) extern double atof(); /* Check a `double' value for validity for a particular machine mode. */ #define CHECK_FLOAT_VALUE(mode, d) \ check_float_value ((mode), &(d)) /* Tell final.c how to eliminate redundant test instructions. */ /* Here we define machine-dependent flags and fields in cc_status (see `conditions.h'). No extra ones are needed for convex. */ /* Store in cc_status the expressions that the condition codes will describe after execution of an instruction whose pattern is EXP. Do not alter them if the instruction would not alter the cc's. */ #define NOTICE_UPDATE_CC(EXP,INSN) {} /* Control the assembler format that we output. */ /* Output at beginning of assembler file. */ #if _IEEE_FLOAT_ #define ASM_FILE_START(FILE) fprintf (FILE, ";NO_APP\n.fpmode ieee\n") #else #define ASM_FILE_START(FILE) fprintf (FILE, ";NO_APP\n.fpmode native\n") #endif /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ #define ASM_APP_ON ";APP\n" /* Output to assembler file text saying following lines no longer contain unusual constructs. */ #define ASM_APP_OFF ";NO_APP\n" /* Alignment with Convex's assembler goes like this: .text can be .aligned up to a halfword. .data and .bss can be .aligned up to a longword. .lcomm is not supported, explicit declarations in .bss must be used instead. We get alignment for word and longword .text data by conventionally using .text 2 for word-aligned data and .text 3 for longword-aligned data. This requires that the data's size be a multiple of its alignment, which seems to be always true. */ /* Output before read-only data. */ #define TEXT_SECTION_ASM_OP (current_section_is_text = 1, ".text") /* Output before writable data. */ #define DATA_SECTION_ASM_OP (current_section_is_text = 0, ".data") /* Output before uninitialized data. */ #define BSS_SECTION_ASM_OP (current_section_is_text = 0, ".bss") /* Define the .bss section for ASM_OUTPUT_LOCAL to use. */ #define EXTRA_SECTIONS in_bss #define EXTRA_SECTION_FUNCTIONS \ void \ bss_section () \ { \ if (in_section != in_bss) \ { \ fprintf (asm_out_file, "%s\n", BSS_SECTION_ASM_OP); \ in_section = in_bss; \ } \ } /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if (current_section_is_text && (LOG) > 1) \ fprintf (FILE, ".text %d\n", LOG); \ else if (current_section_is_text) \ fprintf (FILE, ".text\n.align %d\n", 1 << (LOG)); \ else \ fprintf (FILE, ".align %d\n", 1 << (LOG)) /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ #define REGISTER_NAMES \ { \ "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \ "sp", "a1", "a2", "a3", "a4", "a5", "ap", "fp", \ } /* This is BSD, so it wants DBX format. */ #define DBX_DEBUGGING_INFO /* How to renumber registers for dbx and gdb. */ #define DBX_REGISTER_NUMBER(REGNO) (REGNO) /* Do not break .stabs pseudos into continuations. */ #define DBX_CONTIN_LENGTH 0 /* This is the char to use for continuation (in case we need to turn continuation back on). */ #define DBX_CONTIN_CHAR '?' /* Don't use stab extensions until GDB v4 port is available for convex. */ #define DEFAULT_GDB_EXTENSIONS 0 #define DBX_NO_XREFS /* This is how to output the definition of a user-level label named NAME, such as the label on a static function or variable NAME. */ #define ASM_OUTPUT_LABEL(FILE,NAME) \ do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) /* This is how to output a command to make the user-level label named NAME defined for reference from other files. */ #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) /* This is how to output a reference to a user-level label named NAME. */ #define ASM_OUTPUT_LABELREF(FILE,NAME) \ fprintf (FILE, "_%s", NAME) /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, "%s%d:\n", PREFIX, NUM) /* Put case tables in .text 2, where they will be word-aligned */ #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \ ASM_OUTPUT_ALIGN (FILE, 2); \ ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM) #define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \ ASM_OUTPUT_ALIGN (FILE, 1) /* This is how to store into the string LABEL the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ sprintf (LABEL, "*%s%d", PREFIX, NUM) /* This is how to output an assembler line defining a `double' constant. */ #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ outfloat (FILE, VALUE, "%.17e", "\tds.d ", "\n") /* This is how to output an assembler line defining a `float' constant. */ #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ outfloat (FILE, VALUE, "%.9e", "\tds.s ", "\n") /* This is how to output an assembler line defining an `int' constant. */ #define ASM_OUTPUT_INT(FILE,VALUE) \ { \ fprintf (FILE, "\tds.w "); \ output_addr_const (FILE, simplify_for_convex (VALUE)); \ fprintf (FILE, "\n"); \ } /* Likewise for a `long long int' constant. */ #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ { \ if (GET_CODE (VALUE) == CONST_DOUBLE) \ fprintf (FILE, "\tds.w %d,%d\n", \ const_double_high_int (VALUE), const_double_low_int (VALUE)); \ else if (GET_CODE (VALUE) == CONST_INT) \ { \ int val = INTVAL (VALUE); \ fprintf (FILE, "\tds.w %d,%d\n", val < 0 ? -1 : 0, val); \ } \ else \ abort (); \ } /* Likewise for `char' and `short' constants. */ #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "\tds.h "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ( fprintf (FILE, "\tds.b "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* This is how to output an assembler line for a numeric constant byte. */ #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf (FILE, "\tds.b %#x\n", (VALUE)) /* This is how to output a string */ #define ASM_OUTPUT_ASCII(FILE,STR,SIZE) do { \ int i; \ fprintf ((FILE), "\tds.b \""); \ for (i = 0; i < (SIZE); i++) { \ register int c = (STR)[i] & 0377; \ if (c >= ' ' && c < 0177 && c != '\\' && c != '"') \ putc (c, (FILE)); \ else \ fprintf ((FILE), "\\%03o", c);} \ fprintf ((FILE), "\"\n");} while (0) /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tpsh.%c %s\n", \ S_REGNO_P (REGNO) ? 'l' : 'w', \ reg_names[REGNO]) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tpop.%c %s\n", \ S_REGNO_P (REGNO) ? 'l' : 'w', \ reg_names[REGNO]) /* This is how to output an element of a case-vector that is absolute. */ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "\tds.w L%d\n", VALUE) /* This is how to output an element of a case-vector that is relative. (not used on Convex) */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\tds.w L%d-L%d\n", VALUE, REL) /* This is how to output an assembler line that says to advance the location counter by SIZE bytes. */ #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\tds.b %u(0)\n", (SIZE)) /* This says how to output an assembler line to define a global common symbol. */ #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fputs (".comm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (ROUNDED))) /* This says how to output an assembler line to define a local common symbol. */ #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( bss_section (), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ":\tbs.b %u\n", (ROUNDED))) /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) /* Output an arg count before function entries. */ #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ asm_declare_function_name (FILE, NAME, DECL) /* Define the parentheses used to group arithmetic operations in assembler code. */ #define ASM_OPEN_PAREN "(" #define ASM_CLOSE_PAREN ")" /* Define results of standard character escape sequences. */ #define TARGET_BELL 007 #define TARGET_BS 010 #define TARGET_TAB 011 #define TARGET_NEWLINE 012 #define TARGET_VT 013 #define TARGET_FF 014 #define TARGET_CR 015 /* Print an instruction operand X on file FILE. CODE is the code from the %-spec that requested printing this operand; if `%z3' was used to print operand 3, then CODE is 'z'. */ #define PRINT_OPERAND(FILE, X, CODE) \ print_operand (FILE, X, CODE) /* Print a memory operand whose address is X, on file FILE. */ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ print_operand_address (FILE, ADDR) /* Definitions for g++. */ /* Do not put out GNU stabs for constructors and destructors. ld bounces them. */ #define FASCIST_ASSEMBLER /* Convex user addresses are negative, so use positive numbers to mean `vtable index'. */ #define VTABLE_USES_MASK #define VINDEX_MAX ((unsigned) 0x80000000) #define SET_DECL_VINDEX(DECL, INDEX) \ (DECL_VINDEX (DECL) = (INDEX)) /* __gcc_cleanup is loader-aliased to __ap$do_registered_functions if we are linking against standard libc, 0 if old (-traditional) libc. */ #define EXIT_BODY \ { \ extern void __gcc_cleanup (); \ if (__gcc_cleanup != _cleanup) \ __gcc_cleanup (); \ _cleanup (); \ } /* cexp.y uses LONG_TYPE_SIZE which depends on target_flags, which it doesn't have. Until some better way exists, provide a def here. */ #ifdef YYBISON int target_flags; #endif /* Header for convex.c. Here at the end so we can use types defined above. */ extern int target_cpu; extern int current_section_is_text; extern enum reg_class regno_reg_class[]; extern enum reg_class reg_class_from_letter[]; extern char regno_ok_for_index_p_base[]; #define regno_ok_for_index_p (regno_ok_for_index_p_base + 1) extern int const_double_low_int (); extern int const_double_high_int (); extern char *output_cmp (); extern char *output_condjump (); extern char *output_call (); extern void gen_ap_for_call (); extern void check_float_value (); extern void asm_declare_function_name (); gcc-2.5.8/config/convex/convex.md100444 22011 13 157744 5466672603 15456 0ustar kenneruser;;- Machine description for GNU compiler ;;- Convex Version ;; Copyright (C) 1988, 1993 Free Software Foundation, Inc. ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ;; Attribute specifications ; Target CPU (define_attr "cpu" "c1,c32,c34,c38" (const (symbol_ref "(enum attr_cpu) target_cpu"))) ;; Instruction classification (define_attr "type" "alu,xalu,mldw,mldl,mldb,mst,adds,addd,mulw,mull,muls,muld,divw,divl,divs,divd,shfw,shfl,cvts,cvtd" (const_string "alu")) ;; Instruction times (define_function_unit "mem" 1 0 (and (eq_attr "cpu" "c1") (eq_attr "type" "mldw")) 2 0) (define_function_unit "mem" 1 0 (and (eq_attr "cpu" "c1") (eq_attr "type" "mldl")) 4 0) (define_function_unit "mem" 1 0 (and (eq_attr "cpu" "c32") (eq_attr "type" "mldw,mldl")) 2 0) (define_function_unit "mem" 1 0 (and (eq_attr "cpu" "c34") (eq_attr "type" "mldw,mldl")) 4 0) (define_function_unit "mem" 1 0 (and (eq_attr "cpu" "c38") (eq_attr "type" "mldw,mldl")) 2 0) (define_function_unit "mem" 1 0 (and (eq_attr "cpu" "c32") (eq_attr "type" "mldb")) 9 0) (define_function_unit "mem" 1 0 (and (eq_attr "cpu" "c34") (eq_attr "type" "mldb")) 36 0) (define_function_unit "mem" 1 0 (and (eq_attr "cpu" "c38") (eq_attr "type" "mldb")) 21 0) (define_function_unit "mem" 1 0 (and (eq_attr "cpu" "c1") (eq_attr "type" "xalu")) 1 0) (define_function_unit "mem" 1 0 (and (eq_attr "cpu" "c32") (eq_attr "type" "xalu")) 1 0) (define_function_unit "mem" 1 0 (and (eq_attr "cpu" "c34") (eq_attr "type" "xalu")) 5 0) (define_function_unit "mem" 1 0 (and (eq_attr "cpu" "c38") (eq_attr "type" "xalu")) 2 0) (define_function_unit "add" 1 0 (and (eq_attr "cpu" "c1") (eq_attr "type" "adds,addd")) 3 2) (define_function_unit "add" 1 0 (and (eq_attr "cpu" "c32") (eq_attr "type" "adds,addd")) 2 1) (define_function_unit "add" 1 0 (and (eq_attr "cpu" "c34") (eq_attr "type" "adds,addd")) 5 2) (define_function_unit "add" 1 0 (and (eq_attr "cpu" "c38") (eq_attr "type" "adds,addd")) 2 1) (define_function_unit "mul" 1 0 (and (eq_attr "cpu" "c1") (eq_attr "type" "mulw,muls")) 3 2) (define_function_unit "mul" 1 0 (and (eq_attr "cpu" "c32") (eq_attr "type" "mulw,muls")) 4 2) (define_function_unit "mul" 1 0 (and (eq_attr "cpu" "c34") (eq_attr "type" "mulw,muls")) 6 2) (define_function_unit "mul" 1 0 (and (eq_attr "cpu" "c38") (eq_attr "type" "mulw,muls")) 3 2) (define_function_unit "mul" 1 0 (and (eq_attr "cpu" "c1") (eq_attr "type" "mull,muld")) 4 3) (define_function_unit "mul" 1 0 (and (eq_attr "cpu" "c32") (eq_attr "type" "mull")) 10 7) (define_function_unit "mul" 1 0 (and (eq_attr "cpu" "c32") (eq_attr "type" "muld")) 5 2) (define_function_unit "mul" 1 0 (and (eq_attr "cpu" "c34") (eq_attr "type" "mull,muld")) 7 3) (define_function_unit "mul" 1 0 (and (eq_attr "cpu" "c38") (eq_attr "type" "mull,muld")) 4 3) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c1") (eq_attr "type" "divw")) 24 24) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c32") (eq_attr "type" "divw")) 44 6) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c34") (eq_attr "type" "divw")) 14 10) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c38") (eq_attr "type" "divw")) 11 10) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c1") (eq_attr "type" "divl")) 41 42) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c32") (eq_attr "type" "divl")) 76 5) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c34") (eq_attr "type" "divl")) 22 18) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c38") (eq_attr "type" "divl")) 19 18) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c1") (eq_attr "type" "divs")) 22 22) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c32") (eq_attr "type" "divs")) 8 6) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c34") (eq_attr "type" "divs")) 13 9) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c38") (eq_attr "type" "divs")) 10 9) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c1") (eq_attr "type" "divd")) 37 38) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c32") (eq_attr "type" "divd")) 12 8) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c34") (eq_attr "type" "divd")) 20 16) (define_function_unit "div" 1 0 (and (eq_attr "cpu" "c38") (eq_attr "type" "divd")) 17 16) (define_function_unit "misc" 1 0 (and (eq_attr "cpu" "c1") (eq_attr "type" "cvts,cvtd")) 4 3) (define_function_unit "misc" 1 0 (and (eq_attr "cpu" "c32") (eq_attr "type" "cvts")) 9 7) (define_function_unit "misc" 1 0 (and (eq_attr "cpu" "c32") (eq_attr "type" "cvtd")) 9 6) (define_function_unit "misc" 1 0 (and (eq_attr "cpu" "c34") (eq_attr "type" "cvts")) 6 2) (define_function_unit "misc" 1 0 (and (eq_attr "cpu" "c34") (eq_attr "type" "cvtd")) 6 1) (define_function_unit "misc" 1 0 (and (eq_attr "cpu" "c38") (eq_attr "type" "cvts,cvtd")) 3 1) (define_function_unit "misc" 1 0 (and (eq_attr "cpu" "c1") (eq_attr "type" "shfw,shfl")) 3 2) (define_function_unit "misc" 1 0 (and (eq_attr "cpu" "c32") (eq_attr "type" "shfw")) 7 5) (define_function_unit "misc" 1 0 (and (eq_attr "cpu" "c32") (eq_attr "type" "shfl")) 7 4) (define_function_unit "misc" 1 0 (and (eq_attr "cpu" "c38") (eq_attr "type" "shfw,shfl")) 3 1) (define_function_unit "mystery_latch" 1 1 (and (eq_attr "type" "!alu,mldw,mldl,adds,addd") (eq_attr "cpu" "c32")) 2 2) ;(define_function_unit "ip" 1 1 ; (and (eq_attr "cpu" "c1") ; (eq_attr "type" "divw,divl,divs,divd,xalu")) 2 2) ;(define_function_unit "ip" 1 1 ; (and (eq_attr "cpu" "c1") ; (eq_attr "type" "!divw,divl,divs,divd,xalu")) 1 1) ;(define_function_unit "ip" 1 1 ; (and (eq_attr "cpu" "c32") ; (eq_attr "type" "mull,muld,divl,divd,shfl,cvtd,xalu")) 2 2) ;(define_function_unit "ip" 1 1 ; (and (eq_attr "cpu" "c32") ; (eq_attr "type" "!mull,muld,divl,divd,shfl,cvtd,xalu")) 1 1) ;(define_function_unit "ip" 1 1 ; (and (eq_attr "cpu" "c34") ; (eq_attr "type" "addd,mull,muld,divl,divd,cvtd,xalu")) 2 2) ;(define_function_unit "ip" 1 1 ; (and (eq_attr "cpu" "c34") ; (eq_attr "type" "!addd,mull,muld,divl,divd,cvtd,xalu")) 1 1) ;; Make the first thing a real insn in case of genattrtab bug (define_insn "nop" [(const_int 0)] "" "nop") ;; Moves (define_expand "movdf" [(set (match_operand:DF 0 "general_operand" "") (match_operand:DF 1 "general_operand" ""))] "" "if (GET_CODE (operands[0]) != REG) operands[1] = force_reg (DFmode, operands[1]);") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=d,d,d,d,d,<,m") (match_operand:DF 1 "general_operand" "d,Q,m,G,H,d,d"))] "register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode)" "@ mov %1,%0 ldb.d %1,%0 ld.d %1,%0 ld.d %u1,%0 ld.l %v1,%0 psh.l %1 st.d %1,%0" [(set_attr "type" "alu,mldb,mldl,alu,alu,alu,mst")]) ;; This is here so we can load any result of RTL constant folding ;; but do not use it on constants that can be loaded from memory. ;; It is never better and can be worse. (define_insn "" [(set (match_operand:DF 0 "register_operand" "=d") (match_operand:DF 1 "const_double_operand" "F"))] "CONST_DOUBLE_MEM (operands[1]) == const0_rtx" "ld.u %u1,%0\;ld.w %v1,%0" [(set_attr "type" "xalu")]) (define_expand "movsf" [(set (match_operand:SF 0 "general_operand" "") (match_operand:SF 1 "general_operand" ""))] "" "if (GET_CODE (operands[0]) != REG) operands[1] = force_reg (SFmode, operands[1]);") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=d,d,d,d,<,m") (match_operand:SF 1 "general_operand" "d,Q,m,F,d,d"))] "register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)" "@ mov.s %1,%0 ldb.s %1,%0 ld.s %1,%0 ld.s %1,%0 psh.w %1 st.s %1,%0" [(set_attr "type" "alu,mldb,mldw,alu,alu,mst")]) (define_expand "movdi" [(set (match_operand:DI 0 "general_operand" "") (match_operand:DI 1 "general_operand" ""))] "" "if (GET_CODE (operands[0]) != REG) operands[1] = force_reg (DImode, operands[1]);") (define_insn "" [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,d,<,m") (match_operand:DI 1 "general_operand" "d,Q,m,G,HI,d,d"))] "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)" "@ mov %1,%0 ldb.l %1,%0 ld.l %1,%0 ld.d %u1,%0 ld.l %1,%0 psh.l %1 st.l %1,%0" [(set_attr "type" "alu,mldb,mldl,alu,alu,alu,mst")]) ;; This is here so we can load any result of RTL constant folding ;; but do not use it on constants that can be loaded from memory. ;; It is never better and can be worse. (define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (match_operand:DI 1 "const_double_operand" "F"))] "CONST_DOUBLE_MEM (operands[1]) == const0_rtx" "ld.u %u1,%0\;ld.w %v1,%0" [(set_attr "type" "xalu")]) (define_expand "movsi" [(set (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))] "" "if (GET_CODE (operands[0]) != REG) operands[1] = force_reg (SImode, operands[1]);") (define_insn "" [(set (match_operand:SI 0 "push_operand" "=<,<") (match_operand:SI 1 "nonmemory_operand" "Ad,i"))] "" "@ psh.w %1 pshea %a1") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d,r,d,r,r,m") (match_operand:SI 1 "general_operand" "d,r,Q,m,i,r"))] "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)" "@ mov.w %1,%0 mov %1,%0 ldb.w %1,%0 ld.w %1,%0 ld.w %1,%0 st.w %1,%0" [(set_attr "type" "alu,alu,mldb,mldw,alu,mst")]) (define_expand "movstrictsi" [(set (strict_low_part (match_operand:SI 0 "general_operand" "")) (match_operand:SI 1 "general_operand" ""))] "" "if (GET_CODE (operands[0]) != REG) operands[1] = force_reg (SImode, operands[1]);") (define_insn "" [(set (strict_low_part (match_operand:SI 0 "general_operand" "=d,r,d,r,r,m")) (match_operand:SI 1 "general_operand" "d,r,Q,m,i,r"))] "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)" "@ mov.w %1,%0 mov %1,%0 ldb.w %1,%0 ld.w %1,%0 ld.w %1,%0 st.w %1,%0" [(set_attr "type" "alu,alu,mldb,mldw,alu,mst")]) (define_expand "movhi" [(set (match_operand:HI 0 "general_operand" "") (match_operand:HI 1 "general_operand" ""))] "" "if (GET_CODE (operands[0]) != REG) operands[1] = force_reg (HImode, operands[1]);") (define_insn "" [(set (match_operand:HI 0 "general_operand" "=d,r,d,r,r,<,m") (match_operand:HI 1 "general_operand" "d,r,Q,m,i,Ad,r"))] "register_operand (operands[0], HImode) || register_operand (operands[1], HImode)" "@ mov.w %1,%0 mov %1,%0 ldb.h %1,%0 ld.h %1,%0 ld.w %1,%0 psh.w %1 st.h %1,%0" [(set_attr "type" "alu,alu,mldb,mldw,alu,alu,mst")]) (define_expand "movqi" [(set (match_operand:QI 0 "general_operand" "") (match_operand:QI 1 "general_operand" ""))] "" "if (GET_CODE (operands[0]) != REG) operands[1] = force_reg (QImode, operands[1]);") (define_insn "" [(set (match_operand:QI 0 "general_operand" "=d,r,d,r,r,<,m") (match_operand:QI 1 "general_operand" "d,r,Q,m,i,Ad,r"))] "register_operand (operands[0], QImode) || register_operand (operands[1], QImode)" "@ mov.w %1,%0 mov %1,%0 ldb.b %1,%0 ld.b %1,%0 ld.w %1,%0 psh.w %1 st.b %1,%0" [(set_attr "type" "alu,alu,mldb,mldw,alu,alu,mst")]) ;; Expand block moves manually to get code that pipelines the loads. (define_expand "movstrsi" [(set (match_operand:BLK 0 "memory_operand" "=m") (match_operand:BLK 1 "memory_operand" "m")) (use (match_operand:SI 2 "const_int_operand" "i")) (use (match_operand:SI 3 "const_int_operand" "i"))] "" " expand_movstr (operands); DONE; ") ;; Extension and truncation insns. ;; Those for integer source operand ;; are ordered widest source type first. (define_insn "truncsiqi2" [(set (match_operand:QI 0 "register_operand" "=d,a") (truncate:QI (match_operand:SI 1 "register_operand" "d,a")))] "" "cvtw.b %1,%0") (define_insn "truncsihi2" [(set (match_operand:HI 0 "register_operand" "=d,a") (truncate:HI (match_operand:SI 1 "register_operand" "d,a")))] "" "cvtw.h %1,%0") (define_insn "trunchiqi2" [(set (match_operand:QI 0 "register_operand" "=r") (truncate:QI (match_operand:HI 1 "register_operand" "0")))] "" "") (define_insn "truncdisi2" [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI (match_operand:DI 1 "register_operand" "d")))] "" "cvtl.w %1,%0") (define_insn "extendsidi2" [(set (match_operand:DI 0 "register_operand" "=d") (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))] "" "cvtw.l %1,%0") (define_insn "extendhisi2" [(set (match_operand:SI 0 "register_operand" "=d,a") (sign_extend:SI (match_operand:HI 1 "register_operand" "d,a")))] "" "cvth.w %1,%0") (define_insn "extendqihi2" [(set (match_operand:HI 0 "register_operand" "=d,a") (sign_extend:HI (match_operand:QI 1 "register_operand" "d,a")))] "" "cvtb.w %1,%0") (define_insn "extendqisi2" [(set (match_operand:SI 0 "register_operand" "=d,a") (sign_extend:SI (match_operand:QI 1 "register_operand" "d,a")))] "" "cvtb.w %1,%0") (define_insn "extendsfdf2" [(set (match_operand:DF 0 "register_operand" "=d") (float_extend:DF (match_operand:SF 1 "register_operand" "d")))] "" "cvts.d %1,%0" [(set_attr "type" "cvts")]) (define_insn "truncdfsf2" [(set (match_operand:SF 0 "register_operand" "=d") (float_truncate:SF (match_operand:DF 1 "register_operand" "d")))] "" "cvtd.s %1,%0" [(set_attr "type" "cvtd")]) (define_insn "zero_extendhisi2" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))] "" "and #0xffff,%0") (define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "=r") (zero_extend:HI (match_operand:QI 1 "register_operand" "0")))] "" "and #0xff,%0") (define_insn "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))] "" "and #0xff,%0") (define_insn "zero_extendsidi2" [(set (match_operand:DI 0 "register_operand" "=d") (zero_extend:DI (match_operand:SI 1 "register_operand" "0")))] "" "ld.u #0,%0") ;; Fix-to-float conversion insns. ;; Note that the ones that start with SImode come first. ;; That is so that an operand that is a CONST_INT ;; (and therefore lacks a specific machine mode). ;; will be recognized as SImode (which is always valid) ;; rather than as QImode or HImode. (define_insn "floatsisf2" [(set (match_operand:SF 0 "register_operand" "=d") (float:SF (match_operand:SI 1 "register_operand" "d")))] "" "cvtw.s %1,%0" [(set_attr "type" "cvts")]) (define_insn "floatdisf2" [(set (match_operand:SF 0 "register_operand" "=d") (float:SF (match_operand:DI 1 "register_operand" "d")))] "" "cvtl.s %1,%0" [(set_attr "type" "cvtd")]) (define_insn "floatsidf2" [(set (match_operand:DF 0 "register_operand" "=d") (float:DF (match_operand:SI 1 "register_operand" "d")))] "! TARGET_C1" "cvtw.d %1,%0" [(set_attr "type" "cvts")]) (define_insn "floatdidf2" [(set (match_operand:DF 0 "register_operand" "=d") (float:DF (match_operand:DI 1 "register_operand" "d")))] "" "cvtl.d %1,%0" [(set_attr "type" "cvtd")]) ;; These are a little slower than gcc's normal way of doing unsigned ;; DI floats (if the DI number is "negative") but they avoid double ;; rounding and they avoid explicit constants. (define_expand "floatunsdidf2" [(set (match_operand:DF 0 "register_operand" "=d") (float:DF (match_operand:DI 1 "register_operand" "d"))) (set (cc0) (compare:DI (match_dup 3) (match_dup 1))) (set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_dup 4)) (pc))) (set (match_dup 2) (lshiftrt:DI (match_dup 1) (const_int 1))) (set (match_dup 0) (float:DF (match_dup 2))) (set (match_dup 0) (plus:DF (match_dup 0) (match_dup 0))) (match_dup 4) (set (match_dup 0) (match_dup 0))] "" " { operands[2] = gen_reg_rtx (DImode); operands[3] = force_reg (DImode, const0_rtx); operands[4] = gen_label_rtx (); }") (define_expand "floatunsdisf2" [(set (match_operand:SF 0 "register_operand" "=d") (float:SF (match_operand:DI 1 "register_operand" "d"))) (set (cc0) (compare:DI (match_dup 3) (match_dup 1))) (set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_dup 4)) (pc))) (set (match_dup 2) (lshiftrt:DI (match_dup 1) (const_int 1))) (set (match_dup 0) (float:SF (match_dup 2))) (set (match_dup 0) (plus:SF (match_dup 0) (match_dup 0))) (match_dup 4) (set (match_dup 0) (match_dup 0))] "" " { operands[2] = gen_reg_rtx (DImode); operands[3] = force_reg (DImode, const0_rtx); operands[4] = gen_label_rtx (); }") ;; These patterns are identical to gcc's default action ;; if DI->DF and DI->SF are not present. There are here ;; only to prevent SI->*F from promoting to DI->*F. (define_expand "floatunssidf2" [(set (match_dup 2) (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) (set (match_operand:DF 0 "register_operand" "") (float:DF (match_dup 2)))] "" "operands[2] = gen_reg_rtx (DImode);") (define_expand "floatunssisf2" [(set (match_dup 2) (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) (set (match_operand:SF 0 "register_operand" "") (float:SF (match_dup 2)))] "" "operands[2] = gen_reg_rtx (DImode);") ;; Float-to-fix conversion insns. (define_insn "fix_truncsfsi2" [(set (match_operand:SI 0 "register_operand" "=d") (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "d"))))] "" "cvts.w %1,%0" [(set_attr "type" "cvts")]) (define_insn "fix_truncsfdi2" [(set (match_operand:DI 0 "register_operand" "=d") (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "d"))))] "" "cvts.l %1,%0" [(set_attr "type" "cvts")]) (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "register_operand" "=d") (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] "" "cvtd.l %1,%0" [(set_attr "type" "cvtd")]) (define_insn "fix_truncdfdi2" [(set (match_operand:DI 0 "register_operand" "=d") (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] "" "cvtd.l %1,%0" [(set_attr "type" "cvtd")]) ;;- All kinds of add instructions. (define_insn "adddf3" [(set (match_operand:DF 0 "register_operand" "=d") (plus:DF (match_operand:DF 1 "register_operand" "%0") (match_operand:DF 2 "register_operand" "d")))] "" "add.d %2,%0" [(set_attr "type" "addd")]) (define_insn "addsf3" [(set (match_operand:SF 0 "register_operand" "=d") (plus:SF (match_operand:SF 1 "register_operand" "%0") (match_operand:SF 2 "nonmemory_operand" "dF")))] "" "add.s %2,%0" [(set_attr "type" "adds")]) (define_insn "adddi3" [(set (match_operand:DI 0 "register_operand" "=d") (plus:DI (match_operand:DI 1 "register_operand" "%0") (match_operand:DI 2 "register_operand" "d")))] "" "add.l %2,%0") (define_expand "addsi3" [(set (match_operand:SI 0 "register_operand" "") (plus:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "nonmemory_operand" "")))] "" "") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=a") (plus:SI (match_operand:SI 1 "register_operand" "%A") (match_operand:SI 2 "immediate_operand" "i")))] "operands[1] == frame_pointer_rtx || operands[1] == arg_pointer_rtx" "ldea %a2(%1),%0") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=a") (plus:SI (match_operand:SI 1 "register_operand" "%a") (match_operand:SI 2 "nonmemory_operand" "ri")))] "operands[1] == stack_pointer_rtx && operands[0] != stack_pointer_rtx" "mov %1,%0\;add.w %2,%0") (define_insn "" [(set (match_operand:SI 0 "push_operand" "=<") (plus:SI (match_operand:SI 1 "register_operand" "A") (match_operand:SI 2 "immediate_operand" "i")))] "operands[1] != stack_pointer_rtx" "pshea %a2(%1)" [(set_attr "type" "mst")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d,a,a") (plus:SI (match_operand:SI 1 "register_operand" "%0,0,A") (match_operand:SI 2 "nonmemory_operand" "di,ri,i")))] "TARGET_C1" "@ add.w %2,%0 add.w %2,%0 ldea %a2(%1),%0") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d,a,r") (plus:SI (match_operand:SI 1 "register_operand" "%0,0,A") (match_operand:SI 2 "nonmemory_operand" "di,ri,i")))] "" "@ add.w %2,%0 add.w %2,%0 ldea %a2(%1),%0") (define_insn "addhi3" [(set (match_operand:HI 0 "register_operand" "=d,a") (plus:HI (match_operand:HI 1 "register_operand" "%0,0") (match_operand:HI 2 "nonmemory_operand" "di,ai")))] "" "add.h %2,%0") (define_insn "addqi3" [(set (match_operand:QI 0 "register_operand" "=d,d") (plus:QI (match_operand:QI 1 "register_operand" "%0,0") (match_operand:QI 2 "nonmemory_operand" "d,i")))] "" "@ add.b %2,%0 add.w %2,%0") ;;- All kinds of subtract instructions. (define_insn "subdf3" [(set (match_operand:DF 0 "register_operand" "=d") (minus:DF (match_operand:DF 1 "register_operand" "0") (match_operand:DF 2 "register_operand" "d")))] "" "sub.d %2,%0" [(set_attr "type" "addd")]) (define_insn "subsf3" [(set (match_operand:SF 0 "register_operand" "=d") (minus:SF (match_operand:SF 1 "register_operand" "0") (match_operand:SF 2 "nonmemory_operand" "dF")))] "" "sub.s %2,%0" [(set_attr "type" "adds")]) (define_insn "subdi3" [(set (match_operand:DI 0 "register_operand" "=d") (minus:DI (match_operand:DI 1 "register_operand" "0") (match_operand:DI 2 "register_operand" "d")))] "" "sub.l %2,%0") (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=d,a,?d,?a") (minus:SI (match_operand:SI 1 "nonmemory_operand" "0,0,di,ai") (match_operand:SI 2 "nonmemory_operand" "di,ai,0,0")))] "" "@ sub.w %2,%0 sub.w %2,%0 sub.w %1,%0\;neg.w %0,%0 sub.w %1,%0\;neg.w %0,%0") (define_insn "subhi3" [(set (match_operand:HI 0 "register_operand" "=d,a") (minus:HI (match_operand:HI 1 "register_operand" "0,0") (match_operand:HI 2 "nonmemory_operand" "di,ai")))] "" "sub.h %2,%0") (define_insn "subqi3" [(set (match_operand:QI 0 "register_operand" "=d,d") (minus:QI (match_operand:QI 1 "register_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "d,i")))] "" "@ sub.b %2,%0 sub.w %2,%0") ;;- Multiply instructions. (define_insn "muldf3" [(set (match_operand:DF 0 "register_operand" "=d") (mult:DF (match_operand:DF 1 "register_operand" "%0") (match_operand:DF 2 "register_operand" "d")))] "" "mul.d %2,%0" [(set_attr "type" "muld")]) (define_insn "mulsf3" [(set (match_operand:SF 0 "register_operand" "=d") (mult:SF (match_operand:SF 1 "register_operand" "%0") (match_operand:SF 2 "nonmemory_operand" "dF")))] "" "mul.s %2,%0" [(set_attr "type" "muls")]) (define_insn "muldi3" [(set (match_operand:DI 0 "register_operand" "=d") (mult:DI (match_operand:DI 1 "register_operand" "%0") (match_operand:DI 2 "register_operand" "d")))] "" "mul.l %2,%0" [(set_attr "type" "mull")]) (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=d,a") (mult:SI (match_operand:SI 1 "register_operand" "%0,0") (match_operand:SI 2 "nonmemory_operand" "di,ai")))] "" "mul.w %2,%0" [(set_attr "type" "mulw")]) (define_insn "mulhi3" [(set (match_operand:HI 0 "register_operand" "=d,a") (mult:HI (match_operand:HI 1 "register_operand" "%0,0") (match_operand:HI 2 "nonmemory_operand" "di,ai")))] "" "mul.h %2,%0" [(set_attr "type" "mulw")]) (define_insn "mulqi3" [(set (match_operand:QI 0 "register_operand" "=d,d") (mult:QI (match_operand:QI 1 "register_operand" "%0,0") (match_operand:QI 2 "nonmemory_operand" "d,i")))] "" "@ mul.b %2,%0 mul.w %2,%0" [(set_attr "type" "mulw,mulw")]) ;;- Divide instructions. (define_insn "divdf3" [(set (match_operand:DF 0 "register_operand" "=d") (div:DF (match_operand:DF 1 "register_operand" "0") (match_operand:DF 2 "register_operand" "d")))] "" "div.d %2,%0" [(set_attr "type" "divd")]) (define_insn "divsf3" [(set (match_operand:SF 0 "register_operand" "=d") (div:SF (match_operand:SF 1 "register_operand" "0") (match_operand:SF 2 "nonmemory_operand" "dF")))] "" "div.s %2,%0" [(set_attr "type" "divs")]) (define_insn "divdi3" [(set (match_operand:DI 0 "register_operand" "=d") (div:DI (match_operand:DI 1 "register_operand" "0") (match_operand:DI 2 "register_operand" "d")))] "" "div.l %2,%0" [(set_attr "type" "divl")]) (define_expand "udivsi3" [(set (match_dup 3) (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) (set (match_dup 4) (zero_extend:DI (match_operand:SI 2 "register_operand" ""))) (set (match_dup 3) (div:DI (match_dup 3) (match_dup 4))) (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 0))] "" "operands[3] = gen_reg_rtx (DImode); operands[4] = gen_reg_rtx (DImode); ") (define_insn "udivdi3" [(set (match_operand:DI 0 "register_operand" "=d") (udiv:DI (match_operand:DI 1 "register_operand" "d") (match_operand:DI 2 "register_operand" "d")))] "" "psh.l %2\;psh.l %1\;callq udiv64\;pop.l %0\;add.w #8,sp") (define_insn "divsi3" [(set (match_operand:SI 0 "register_operand" "=d,a") (div:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "di,ai")))] "" "div.w %2,%0" [(set_attr "type" "divw")]) (define_insn "divhi3" [(set (match_operand:HI 0 "register_operand" "=d,a") (div:HI (match_operand:HI 1 "register_operand" "0,0") (match_operand:HI 2 "nonmemory_operand" "di,ai")))] "" "div.h %2,%0" [(set_attr "type" "divw")]) (define_insn "divqi3" [(set (match_operand:QI 0 "register_operand" "=d") (div:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "register_operand" "d")))] "" "div.b %2,%0" [(set_attr "type" "divw")]) ;;- Bit clear instructions. (define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (and:DI (match_operand:DI 1 "register_operand" "%0") (match_operand:DI 2 "" "")))] "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) || (GET_CODE (operands[2]) == CONST_DOUBLE && CONST_DOUBLE_HIGH (operands[2]) == -1)" "and %2,%0") (define_insn "anddi3" [(set (match_operand:DI 0 "register_operand" "=d") (and:DI (match_operand:DI 1 "register_operand" "%0") (match_operand:DI 2 "register_operand" "d")))] "" "and %2,%0") (define_insn "andsi3" [(set (match_operand:SI 0 "register_operand" "=d,a") (and:SI (match_operand:SI 1 "register_operand" "%0,0") (match_operand:SI 2 "nonmemory_operand" "di,ai")))] "" "and %2,%0") (define_insn "andhi3" [(set (match_operand:HI 0 "register_operand" "=d,a") (and:HI (match_operand:HI 1 "register_operand" "%0,0") (match_operand:HI 2 "nonmemory_operand" "di,ai")))] "" "and %2,%0") (define_insn "andqi3" [(set (match_operand:QI 0 "register_operand" "=d,a") (and:QI (match_operand:QI 1 "register_operand" "%0,0") (match_operand:QI 2 "nonmemory_operand" "di,ai")))] "" "and %2,%0") ;;- Bit set instructions. (define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (ior:DI (match_operand:DI 1 "register_operand" "%0") (match_operand:DI 2 "" "")))] "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0) || (GET_CODE (operands[2]) == CONST_DOUBLE && CONST_DOUBLE_HIGH (operands[2]) == 0)" "or %2,%0") (define_insn "iordi3" [(set (match_operand:DI 0 "register_operand" "=d") (ior:DI (match_operand:DI 1 "register_operand" "%0") (match_operand:DI 2 "register_operand" "d")))] "" "or %2,%0") (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=d,a") (ior:SI (match_operand:SI 1 "register_operand" "%0,0") (match_operand:SI 2 "nonmemory_operand" "di,ai")))] "" "or %2,%0") (define_insn "iorhi3" [(set (match_operand:HI 0 "register_operand" "=d,a") (ior:HI (match_operand:HI 1 "register_operand" "%0,0") (match_operand:HI 2 "nonmemory_operand" "di,ai")))] "" "or %2,%0") (define_insn "iorqi3" [(set (match_operand:QI 0 "register_operand" "=d,a") (ior:QI (match_operand:QI 1 "register_operand" "%0,0") (match_operand:QI 2 "nonmemory_operand" "di,ai")))] "" "or %2,%0") ;;- xor instructions. (define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (xor:DI (match_operand:DI 1 "register_operand" "%0") (match_operand:DI 2 "" "")))] "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0) || (GET_CODE (operands[2]) == CONST_DOUBLE && CONST_DOUBLE_HIGH (operands[2]) == 0)" "xor %2,%0") (define_insn "xordi3" [(set (match_operand:DI 0 "register_operand" "=d") (xor:DI (match_operand:DI 1 "register_operand" "%0") (match_operand:DI 2 "register_operand" "d")))] "" "xor %2,%0") (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=d,a") (xor:SI (match_operand:SI 1 "register_operand" "%0,0") (match_operand:SI 2 "nonmemory_operand" "di,ai")))] "" "xor %2,%0") (define_insn "xorhi3" [(set (match_operand:HI 0 "register_operand" "=d,a") (xor:HI (match_operand:HI 1 "register_operand" "%0,0") (match_operand:HI 2 "nonmemory_operand" "di,ai")))] "" "xor %2,%0") (define_insn "xorqi3" [(set (match_operand:QI 0 "register_operand" "=d,a") (xor:QI (match_operand:QI 1 "register_operand" "%0,0") (match_operand:QI 2 "nonmemory_operand" "di,ai")))] "" "xor %2,%0") (define_insn "negdf2" [(set (match_operand:DF 0 "register_operand" "=d") (neg:DF (match_operand:DF 1 "register_operand" "d")))] "" "neg.d %1,%0" [(set_attr "type" "addd")]) (define_insn "negsf2" [(set (match_operand:SF 0 "register_operand" "=d") (neg:SF (match_operand:SF 1 "register_operand" "d")))] "" "neg.s %1,%0" [(set_attr "type" "adds")]) (define_insn "negdi2" [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (match_operand:DI 1 "register_operand" "d")))] "" "neg.l %1,%0") (define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=d,a") (neg:SI (match_operand:SI 1 "register_operand" "d,a")))] "" "neg.w %1,%0") (define_insn "neghi2" [(set (match_operand:HI 0 "register_operand" "=d,a") (neg:HI (match_operand:HI 1 "register_operand" "d,a")))] "" "neg.h %1,%0") (define_insn "negqi2" [(set (match_operand:QI 0 "register_operand" "=d") (neg:QI (match_operand:QI 1 "register_operand" "d")))] "" "neg.b %1,%0") (define_insn "one_cmpldi2" [(set (match_operand:DI 0 "register_operand" "=d") (not:DI (match_operand:DI 1 "register_operand" "d")))] "" "not %1,%0") (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "=d,a") (not:SI (match_operand:SI 1 "register_operand" "d,a")))] "" "not %1,%0") (define_insn "one_cmplhi2" [(set (match_operand:HI 0 "register_operand" "=d,a") (not:HI (match_operand:HI 1 "register_operand" "d,a")))] "" "not %1,%0") (define_insn "one_cmplqi2" [(set (match_operand:QI 0 "register_operand" "=d,a") (not:QI (match_operand:QI 1 "register_operand" "d,a")))] "" "not %1,%0") ;;- Shifts ;; ;; The extreme profusion of patterns here is due to the different-speed ;; shifts on different machines, and the C1's lack of word shift S-register ;; instructions. ;; SImode ;; Logical left 1, 1 cycle on all machines via add (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (lshift:SI (match_operand:SI 1 "register_operand" "0") (const_int 1)))] "" "add.w %0,%0") ;; C34 general shift is 1 cycle (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d,a") (lshift:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "di,ai")))] "TARGET_C34" "@ shf.w %2,%0 shf %2,%0" [(set_attr "type" "shfw,shfw")]) ;; else shift left 0..7 is 1 cycle if we use an A register (define_insn "" [(set (match_operand:SI 0 "register_operand" "=a,?d") (lshift:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "immediate_operand" "ai,di")))] "TARGET_C1 && INTVAL (operands[2]) < (unsigned) 8" "@ shf %2,%0 shf %2,%0" [(set_attr "type" "alu,shfl")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=a,?d") (lshift:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "immediate_operand" "ai,di")))] "INTVAL (operands[2]) < (unsigned) 8" "@ shf %2,%0 shf.w %2,%0" [(set_attr "type" "alu,shfw")]) ;; else general left shift (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d,a") (lshift:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "di,ai")))] "TARGET_C1" "@ shf %2,%0 shf %2,%0" [(set_attr "type" "shfl,shfw")]) ;; (but C2 shift left by a constant can is faster via multiply) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (lshift:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "const_int_operand" "i")))] "TARGET_C2 && INTVAL (operands[2]) < (unsigned) 32" "mul.w %z2,%0" [(set_attr "type" "mulw")]) (define_insn "lshlsi3" [(set (match_operand:SI 0 "register_operand" "=d,a") (lshift:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "di,ai")))] "" "@ shf.w %2,%0 shf %2,%0" [(set_attr "type" "shfw,shfw")]) ;; Arithmetic left 1, 1 cycle on all machines via add (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ashift:SI (match_operand:SI 1 "register_operand" "0") (const_int 1)))] "" "add.w %0,%0") ;; C34 general shift is 1 cycle (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d,a") (ashift:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "di,ai")))] "TARGET_C34" "@ shf.w %2,%0 shf %2,%0" [(set_attr "type" "shfw,shfw")]) ;; else shift left 0..7 is 1 cycle if we use an A register (define_insn "" [(set (match_operand:SI 0 "register_operand" "=a,?d") (ashift:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "immediate_operand" "ai,di")))] "TARGET_C1 && INTVAL (operands[2]) < (unsigned) 8" "@ shf %2,%0 shf %2,%0" [(set_attr "type" "alu,shfl")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=a,?d") (ashift:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "immediate_operand" "ai,di")))] "INTVAL (operands[2]) < (unsigned) 8" "@ shf %2,%0 shf.w %2,%0" [(set_attr "type" "alu,shfw")]) ;; else general left shift (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d,a") (ashift:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "di,ai")))] "TARGET_C1" "@ shf %2,%0 shf %2,%0" [(set_attr "type" "shfl,shfw")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ashift:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "const_int_operand" "i")))] "TARGET_C2 && INTVAL (operands[2]) < (unsigned) 32" "mul.w %z2,%0" [(set_attr "type" "mulw")]) (define_insn "ashlsi3" [(set (match_operand:SI 0 "register_operand" "=d,a") (ashift:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "di,ai")))] "" "@ shf.w %2,%0 shf %2,%0" [(set_attr "type" "shfw,shfw")]) ;; Logical right, general ;; The hardware wants the negative of the shift count (define_expand "lshrsi3" [(set (match_operand:SI 0 "register_operand" "") (lshiftrt:SI (match_operand:SI 1 "register_operand" "") (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))] "" "operands[2] = negate_rtx (SImode, operands[2]);") ;; C1 lacks word shift S reg (define_insn "" [(set (match_operand:SI 0 "register_operand" "=a,?d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") (neg:SI (match_operand:SI 2 "nonmemory_operand" "ai,di"))))] "TARGET_C1" "@ shf %2,%0 ld.u #0,%0\;shf %2,%0" [(set_attr "type" "shfw,shfl")]) ;; general case (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d,a") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") (neg:SI (match_operand:SI 2 "nonmemory_operand" "di,ai"))))] "" "@ shf.w %2,%0 shf %2,%0" [(set_attr "type" "shfw,shfw")]) ;; Patterns without neg produced by constant folding (define_insn "" [(set (match_operand:SI 0 "register_operand" "=a,?d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "immediate_operand" "i,i")))] "TARGET_C1" "@ shf #%n2,%0 ld.u #0,%0\;shf #%n2,%0" [(set_attr "type" "shfw,shfl")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d,a") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "immediate_operand" "i,i")))] "" "@ shf.w #%n2,%0 shf #%n2,%0" [(set_attr "type" "shfw,shfw")]) ;; Arithmetic right, general ;; Sign-extend to 64 bits, then shift that. Works for 0..32. (define_expand "ashrsi3" [(set (match_operand:SI 0 "register_operand" "") (ashiftrt:SI (match_operand:SI 1 "register_operand" "") (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))] "" "operands[2] = negate_rtx (SImode, operands[2]);") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d,&d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d") (neg:SI (match_operand:SI 2 "nonmemory_operand" "di,di"))))] "" "cvtw.l %1,%0\;shf %2,%0" [(set_attr "type" "shfl,shfl")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "immediate_operand" "i")))] "" "cvtw.l %1,%0\;shf #%n2,%0" [(set_attr "type" "shfl")]) ;; DImode ;; Logical left, 1-cycle (define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (lshift:DI (match_operand:DI 1 "register_operand" "0") (const_int 1)))] "" "add.l %0,%0") ;; Logical left, general (define_insn "lshldi3" [(set (match_operand:DI 0 "register_operand" "=d") (lshift:DI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "nonmemory_operand" "di")))] "" "shf %2,%0" [(set_attr "type" "shfl")]) ;; Arithmetic left, 1-cycle (define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (ashift:DI (match_operand:DI 1 "register_operand" "0") (const_int 1)))] "" "add.l %0,%0") ;; Arithmetic left, general (define_insn "ashldi3" [(set (match_operand:DI 0 "register_operand" "=d") (ashift:DI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "nonmemory_operand" "di")))] "" "shf %2,%0" [(set_attr "type" "shfl")]) ;; Can omit zero- or sign-extend if shift is 32 or more. (define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0")) (match_operand:SI 2 "const_int_operand" "i")))] "INTVAL (operands[2]) >= 32" "shf %2,%0" [(set_attr "type" "shfl")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (ashift:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "0")) (match_operand:SI 2 "const_int_operand" "i")))] "INTVAL (operands[2]) >= 32" "shf %2,%0" [(set_attr "type" "shfl")]) ;; Logical right, general (define_expand "lshrdi3" [(set (match_operand:DI 0 "register_operand" "") (lshiftrt:DI (match_operand:DI 1 "register_operand" "") (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))] "" "operands[2] = negate_rtx (SImode, operands[2]);") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))] "" "shf %2,%0" [(set_attr "type" "shfl")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "" "shf #%n2,%0" [(set_attr "type" "shfl")]) ;; Arithmetic right, general ;; Use ;; ((a >> b) ^ signbit) - signbit ;; where signbit is (1 << 63) >> b ;; Works for 0..63. Does not work for 64; unfortunate but legal. (define_expand "ashrdi3" [(set (match_operand:DI 0 "register_operand" "") (lshiftrt:DI (match_operand:DI 1 "register_operand" "") (neg:SI (match_operand:SI 2 "nonmemory_operand" "")))) (set (match_dup 3) (lshiftrt:DI (match_dup 3) (neg:SI (match_dup 2)))) (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 3))) (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 3)))] "" " { if (GET_CODE (operands[2]) == CONST_INT) switch (INTVAL (operands[2])) { case 32: emit_insn (gen_ashrdi3_32 (operands[0], operands[1])); DONE; } operands[2] = negate_rtx (SImode, operands[2]); operands[3] = force_reg (DImode, immed_double_const (0, 1 << 31, DImode)); }") ;; Arithmetic right 32, a common case that can save a couple of insns. (define_expand "ashrdi3_32" [(set (match_operand:DI 0 "register_operand" "") (lshiftrt:DI (match_operand:DI 1 "register_operand" "") (const_int 32))) (set (match_dup 0) (sign_extend:DI (subreg:SI (match_dup 0) 0)))] "" "") ;; __builtin instructions (define_insn "sqrtdf2" [(set (match_operand:DF 0 "register_operand" "=d") (sqrt:DF (match_operand:DF 1 "register_operand" "0")))] "! TARGET_C1 && flag_fast_math" "sqrt.d %0" [(set_attr "type" "divd")]) (define_insn "sqrtsf2" [(set (match_operand:SF 0 "register_operand" "=d") (sqrt:SF (match_operand:SF 1 "register_operand" "0")))] "! TARGET_C1 && flag_fast_math" "sqrt.s %0" [(set_attr "type" "divs")]) (define_insn "sindf2" [(set (match_operand:DF 0 "register_operand" "=d") (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))] "! TARGET_C1 && flag_fast_math" "sin.d %0") (define_insn "sinsf2" [(set (match_operand:SF 0 "register_operand" "=d") (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))] "! TARGET_C1 && flag_fast_math" "sin.s %0") (define_insn "cosdf2" [(set (match_operand:DF 0 "register_operand" "=d") (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))] "! TARGET_C1 && flag_fast_math" "cos.d %0") (define_insn "cossf2" [(set (match_operand:SF 0 "register_operand" "=d") (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))] "! TARGET_C1 && flag_fast_math" "cos.s %0") (define_insn "ftruncdf2" [(set (match_operand:DF 0 "register_operand" "=d") (fix:DF (match_operand:DF 1 "register_operand" "d")))] "! TARGET_C1" "frint.d %1,%0" [(set_attr "type" "cvtd")]) (define_insn "ftruncsf2" [(set (match_operand:SF 0 "register_operand" "=d") (fix:SF (match_operand:SF 1 "register_operand" "d")))] "! TARGET_C1" "frint.s %1,%0" [(set_attr "type" "cvts")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d")) (const_int 1)))] "" "tzc %1,%0\;le.w #32,%0\;jbrs.f L0%=\;ld.w #-1,%0\\nL0%=:") (define_expand "ffssi2" [(set (match_operand:SI 0 "register_operand" "=d") (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d")) (const_int 1))) (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))] "" "") (define_insn "abssf2" [(set (match_operand:SF 0 "register_operand" "=d") (abs:SF (match_operand:SF 1 "register_operand" "0")))] "" "and #0x7fffffff,%0") (define_expand "absdf2" [(set (subreg:DI (match_operand:DF 0 "register_operand" "=d") 0) (and:DI (subreg:DI (match_operand:DF 1 "register_operand" "d") 0) (match_dup 2)))] "" "operands[2] = force_reg (DImode, immed_double_const (-1, 0x7fffffff, DImode));") ;;- Compares (define_insn "cmpdi" [(set (cc0) (compare (match_operand:DI 0 "register_operand" "d") (match_operand:DI 1 "register_operand" "d")))] "" "* return output_cmp (operands[0], operands[1], 'l');") (define_insn "" [(set (cc0) (match_operand:DI 0 "register_operand" "d")) (clobber (match_scratch:DI 1 "=d"))] "next_insn_tests_no_inequality (insn)" "* return output_cmp (operands[0], operands[1], 'L');") (define_insn "cmpsi" [(set (cc0) (compare (match_operand:SI 0 "register_operand" "d,a") (match_operand:SI 1 "nonmemory_operand" "di,ai")))] "" "* return output_cmp (operands[0], operands[1], 'w');") (define_insn "cmphi" [(set (cc0) (compare (match_operand:HI 0 "register_operand" "d,a") (match_operand:HI 1 "nonmemory_operand" "di,ai")))] "" "* return output_cmp (operands[0], operands[1], 'h');") ; cmpqi is intentionally omitted. ; ; gcc will sign-extend or zero-extend the operands to the next ; wider mode, HImode. ; ; For reg .cmp. constant, we just go with the halfword immediate ; instruction. Perhaps the widening insn can be cse'd or combined away. ; If not, we're still as good as loading a byte constant into a register ; to do a reg-reg byte compare. ; ; The following patterns pick up cases that can use reg .cmp. reg after all. (define_insn "" [(set (cc0) (compare (sign_extend:HI (match_operand:QI 0 "register_operand" "d")) (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))))] "" "* return output_cmp (operands[0], operands[1], 'b');") (define_insn "" [(set (cc0) (compare (ashift:HI (subreg:HI (match_operand:QI 0 "register_operand" "d") 0) (const_int 8)) (ashift:HI (subreg:HI (match_operand:QI 1 "register_operand" "d") 0) (const_int 8))))] "" "* return output_cmp (operands[0], operands[1], 'b');") (define_insn "" [(set (cc0) (compare (match_operand:QI 0 "register_operand" "d") (match_operand:QI 1 "register_operand" "d")))] "" "* return output_cmp (operands[0], operands[1], 'b');") (define_insn "" [(set (cc0) (match_operand:QI 0 "register_operand" "d,a")) (clobber (match_scratch:QI 1 "=d,a"))] "next_insn_tests_no_inequality (insn)" "* return output_cmp (operands[0], operands[1], 'B');") (define_insn "" [(set (cc0) (subreg (match_operand:QI 0 "register_operand" "d,a") 0)) (clobber (match_scratch:QI 1 "=d,a"))] "next_insn_tests_no_inequality (insn)" "* return output_cmp (operands[0], operands[1], 'B');") (define_insn "" [(set (cc0) (zero_extend (subreg (match_operand:QI 0 "register_operand" "d,a") 0))) (clobber (match_scratch:QI 1 "=d,a"))] "next_insn_tests_no_inequality (insn)" "* return output_cmp (operands[0], operands[1], 'B');") (define_insn "cmpdf" [(set (cc0) (compare (match_operand:DF 0 "register_operand" "d") (match_operand:DF 1 "register_operand" "d")))] "" "* return output_cmp (operands[0], operands[1], 'd');") (define_insn "cmpsf" [(set (cc0) (compare (match_operand:SF 0 "register_operand" "d") (match_operand:SF 1 "nonmemory_cmpsf_operand" "dF")))] "" "* return output_cmp (operands[0], operands[1], 's');") ;; decrement-and-set-cc0 insns. ;; ;; The most important case where we can use the carry bit from an ;; arithmetic insn to eliminate a redundant compare is the decrement in ;; constructs like while (n--) and while (--n >= 0). ;; ;; We do it with combine patterns instead of NOTICE_UPDATE_CC because ;; the decrement needs to be kept at the end of the block during scheduling. ;; ;; These patterns must have memory alternatives because reload refuses ;; to do output reloads for an insn that sets cc0 (since it does not ;; want to clobber cc0 with its moves). Convex moves do not clobber ;; cc0, but there is no evident way to get reload to know that. (define_insn "" [(set (cc0) (match_operand:SI 0 "register_operand" "+r,*m")) (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))] "next_insn_tests_no_inequality (insn)" "* { if (which_alternative == 0) { output_cmp (operands[0], constm1_rtx, 'W'); return \"add.w #-1,%0\"; } else { output_cmp (gen_rtx (REG, SImode, 7), constm1_rtx, 'W'); return \"psh.w s7\;ld.w %0,s7\;add.w #-1,s7\;st.w s7,%0\;pop.w s7\"; } }") (define_insn "" [(set (cc0) (plus:SI (match_operand:SI 0 "register_operand" "+r,*m") (const_int -1))) (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))] "find_reg_note (next_cc0_user (insn), REG_NONNEG, 0)" "* { if (which_alternative == 0) { output_cmp (operands[0], const0_rtx, 'W'); return \"add.w #-1,%0\"; } else { output_cmp (gen_rtx (REG, SImode, 7), const0_rtx, 'W'); return \"psh.w s7\;ld.w %0,s7\;add.w #-1,s7\;st.w s7,%0\;pop.w s7\"; } }") (define_insn "" [(set (cc0) (match_operand:HI 0 "register_operand" "+r,*m")) (set (match_dup 0) (plus:HI (match_dup 0) (const_int -1)))] "next_insn_tests_no_inequality (insn)" "* { if (which_alternative == 0) { output_cmp (operands[0], constm1_rtx, 'W'); return \"add.w #-1,%0\"; } else { output_cmp (gen_rtx (REG, HImode, 7), constm1_rtx, 'W'); return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\"; } }") (define_insn "" [(set (cc0) (plus:HI (match_operand:HI 0 "register_operand" "+r,*m") (const_int -1))) (set (match_dup 0) (plus:HI (match_dup 0) (const_int -1)))] "find_reg_note (next_cc0_user (insn), REG_NONNEG, 0)" "* { if (which_alternative == 0) { output_cmp (operands[0], const0_rtx, 'W'); return \"add.w #-1,%0\"; } else { output_cmp (gen_rtx (REG, HImode, 7), const0_rtx, 'W'); return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\"; } }") ;;- Jumps (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "jbr %l0") (define_insn "beq" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return output_condjump (operands[0], \"eq\", 't'); ") (define_insn "bne" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return output_condjump (operands[0], \"eq\", 'f'); ") (define_insn "bgt" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return output_condjump (operands[0], \"le\", 'f'); ") (define_insn "bgtu" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return output_condjump (operands[0], \"leu\", 'f'); ") (define_insn "blt" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return output_condjump (operands[0], \"lt\", 't'); ") (define_insn "bltu" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return output_condjump (operands[0], \"ltu\", 't'); ") (define_insn "bge" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return output_condjump (operands[0], \"lt\", 'f'); ") (define_insn "bgeu" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return output_condjump (operands[0], \"ltu\", 'f'); ") (define_insn "ble" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return output_condjump (operands[0], \"le\", 't'); ") (define_insn "bleu" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return output_condjump (operands[0], \"leu\", 't'); ") (define_insn "" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return output_condjump (operands[0], \"eq\", 'f'); ") (define_insn "" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return output_condjump (operands[0], \"eq\", 't'); ") (define_insn "" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return output_condjump (operands[0], \"le\", 't'); ") (define_insn "" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return output_condjump (operands[0], \"leu\", 't'); ") (define_insn "" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return output_condjump (operands[0], \"lt\", 'f'); ") (define_insn "" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return output_condjump (operands[0], \"ltu\", 'f'); ") (define_insn "" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return output_condjump (operands[0], \"lt\", 't'); ") (define_insn "" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return output_condjump (operands[0], \"ltu\", 't'); ") (define_insn "" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return output_condjump (operands[0], \"le\", 'f'); ") (define_insn "" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return output_condjump (operands[0], \"leu\", 'f'); ") ;;- Calls (define_expand "call_pop" [(parallel [(call (match_operand:QI 0 "memory_operand" "m") (match_operand:SI 1 "const_int_operand" "i")) (match_operand:SI 2 "const_int_operand" "i") (match_operand:SI 3 "const_int_operand" "i") (reg:SI 8)])] "" "") (define_insn "" [(call (match_operand:QI 0 "memory_operand" "m") (match_operand:SI 1 "const_int_operand" "i")) (match_operand:SI 2 "const_int_operand" "i") (match_operand:SI 3 "const_int_operand" "i") (match_operand:SI 4 "" "")] "" "* return output_call (insn, &operands[0]);") (define_expand "call_value_pop" [(parallel [(set (match_operand 0 "" "=g") (call (match_operand:QI 1 "memory_operand" "m") (match_operand:SI 2 "const_int_operand" "i"))) (match_operand:SI 3 "const_int_operand" "i") (match_operand:SI 4 "const_int_operand" "i") (reg:SI 8)])] "" "") (define_insn "" [(set (match_operand 0 "" "=g") (call (match_operand:QI 1 "memory_operand" "m") (match_operand:SI 2 "const_int_operand" "i"))) (match_operand:SI 3 "const_int_operand" "i") (match_operand:SI 4 "const_int_operand" "i") (match_operand:SI 5 "" "")] "" "* return output_call (insn, &operands[1]); ") ;; Call subroutine returning any type. (define_expand "untyped_call" [(parallel [(call (match_operand 0 "" "") (const_int 0)) (match_operand 1 "" "") (match_operand 2 "" "")])] "" " { int i; emit_call_insn (gen_call_pop (operands[0], const0_rtx, const0_rtx, const0_rtx)); for (i = 0; i < XVECLEN (operands[2], 0); i++) { rtx set = XVECEXP (operands[2], 0, i); emit_move_insn (SET_DEST (set), SET_SRC (set)); } /* The optimizer does not know that the call sets the function value registers we stored in the result block. We avoid problems by claiming that all hard registers are used and clobbered at this point. */ emit_insn (gen_blockage ()); DONE; }") ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and ;; all of memory. This blocks insns from being moved across this point. (define_insn "blockage" [(unspec_volatile [(const_int 0)] 0)] "" "") (define_expand "return" [(return)] "" " replace_arg_pushes (); ") (define_insn "" [(return)] "" "rtn") (define_expand "prologue" [(const_int 0)] "" " { emit_ap_optimizations (); DONE; }") (define_insn "tablejump" [(set (pc) (match_operand:SI 0 "address_operand" "p")) (use (label_ref (match_operand 1 "" "")))] "" "jmp %a0") (define_insn "indirect_jump" [(set (pc) (match_operand:SI 0 "address_operand" "p"))] "" "jmp %a0") gcc-2.5.8/config/convex/convex1.h100444 22011 13 132 5372446645 15261 0ustar kenneruser/* tm.h file for a Convex C1. */ #define TARGET_DEFAULT 001 #include "convex/convex.h" gcc-2.5.8/config/convex/convex2.h100444 22011 13 132 5372446652 15260 0ustar kenneruser/* tm.h file for a Convex C2. */ #define TARGET_DEFAULT 002 #include "convex/convex.h" gcc-2.5.8/config/convex/convex32.h100444 22011 13 135 5372446654 15350 0ustar kenneruser/* tm.h file for a Convex C32xx. */ #define TARGET_DEFAULT 004 #include "convex/convex.h" gcc-2.5.8/config/convex/convex34.h100444 22011 13 135 5372446656 15354 0ustar kenneruser/* tm.h file for a Convex C34xx. */ #define TARGET_DEFAULT 010 #include "convex/convex.h" gcc-2.5.8/config/convex/convex38.h100444 22011 13 135 5372446660 15353 0ustar kenneruser/* tm.h file for a Convex C38xx. */ #define TARGET_DEFAULT 020 #include "convex/convex.h" gcc-2.5.8/config/convex/fixinc.convex100666 22011 13 22022 5376206362 16273 0ustar kenneruser # This is a shell archive. Remove anything before this line, # then unpack it by saving it in a file and typing "sh file". # # Wrapped by on Fri Mar 12 08:41:28 CST 1993 # Contents: include/ include/limits.h include/math.h include/stddef.h # include/stdlib.h echo mkdir - include mkdir include chmod u=rwx,g=rwx,o=rx include echo x - include/limits.h sed 's/^@//' > "include/limits.h" <<'@//E*O*F include/limits.h//' #ifndef _LIMITS_H #define _LIMITS_H #include_next /* Minimum and maximum values a `char' can hold. */ #ifdef __CHAR_UNSIGNED__ #undef CHAR_MIN #define CHAR_MIN 0 #undef CHAR_MAX #define CHAR_MAX 255 #endif #endif /* _LIMITS_H */ @//E*O*F include/limits.h// chmod u=rw,g=rw,o=r include/limits.h echo x - include/math.h sed 's/^@//' > "include/math.h" <<'@//E*O*F include/math.h//' #ifndef _MATH_H #define _MATH_H #include_next #undef HUGE_VAL #if _IEEE_FLOAT_ #define HUGE_VAL 1.79769313486231570e+308 #else #define HUGE_VAL 8.98846567431157854e+307 #endif #if __OPTIMIZE__ && ! __NO_INLINE #define frexp(x,y) __inline_frexp ((x), (y)) #define ldexp(x,y) __inline_ldexp ((x), (y)) #define irint(x) __inline_irint (x) #define frexpf(x,y) __inline_frexpf ((x), (y)) #define ldexpf(x,y) __inline_ldexpf ((x), (y)) #define irintf(x) __inline_irintf (x) #if __convex_c2__ || __convex_c32__ || __convex_c34__ || __convex_c38__ #define atan(x) __inline_atan (x) #define ceil(x) __inline_ceil (x) #define cos(x) __inline_cos (x) #define exp(x) __inline_exp (x) #define floor(x) __inline_floor (x) #define log(x) __inline_log (x) #define log10(x) __inline_log10 (x) #define modf(x,y) __inline_modf ((x), (y)) #define rint(x) __inline_rint (x) #define sin(x) __inline_sin (x) #define sqrt(x) __inline_sqrt (x) #define atanf(x) __inline_atanf (x) #define ceilf(x) __inline_ceilf (x) #define cosf(x) __inline_cosf (x) #define expf(x) __inline_expf (x) #define floorf(x) __inline_floorf (x) #define logf(x) __inline_logf (x) #define log10f(x) __inline_log10f (x) #define modff(x,y) __inline_modff ((x), (y)) #define rintf(x) __inline_rintf (x) #define sinf(x) __inline_sinf (x) #define sqrtf(x) __inline_sqrtf (x) #endif /* __convex_c[23*]__ */ #endif /* __OPTIMIZE__ */ static __inline__ __const__ double __inline_atan (double x) { double z; __asm__ ("atan.d %0" : "=d" (z) : "0" (x)); return z; } static __inline__ __const__ float __inline_atanf (float x) { float z; __asm__ ("atan.s %0" : "=d" (z) : "0" (x)); return z; } static __inline__ __const__ double __inline_cos (double x) { double z; __asm__ ("cos.d %0" : "=d" (z) : "0" (x)); return z; } static __inline__ __const__ float __inline_cosf (float x) { float z; __asm__ ("cos.s %0" : "=d" (z) : "0" (x)); return z; } static __inline__ __const__ double __inline_exp (double x) { double z; __asm__ ("exp.d %0" : "=d" (z) : "0" (x)); return z; } static __inline__ __const__ float __inline_expf (float x) { float z; __asm__ ("exp.s %0" : "=d" (z) : "0" (x)); return z; } static __inline__ __const__ double __inline_log (double x) { double z; __asm__ ("ln.d %0" : "=d" (z) : "0" (x)); return z; } static __inline__ __const__ float __inline_logf (float x) { float z; __asm__ ("ln.s %0" : "=d" (z) : "0" (x)); return z; } static __inline__ __const__ double __inline_sin (double x) { double z; __asm__ ("sin.d %0" : "=d" (z) : "0" (x)); return z; } static __inline__ __const__ float __inline_sinf (float x) { float z; __asm__ ("sin.s %0" : "=d" (z) : "0" (x)); return z; } static __inline__ __const__ double __inline_sqrt (double x) { double z; __asm__ ("sqrt.d %0" : "=d" (z) : "0" (x)); return z; } static __inline__ __const__ float __inline_sqrtf (float x) { float z; __asm__ ("sqrt.s %0" : "=d" (z) : "0" (x)); return z; } static __inline__ __const__ double __inline_ceil (double x) { double z; __asm__ ("frint.d %1,%0" : "=d" (z) : "d" (x)); if (z < x) z += 1.0; return z; } static __inline__ __const__ float __inline_ceilf (float x) { float z; __asm__ ("frint.s %1,%0" : "=d" (z) : "d" (x)); if (z < x) z += 1.0F; return z; } static __inline__ __const__ double __inline_floor (double x) { double z; __asm__ ("frint.d %1,%0" : "=d" (z) : "d" (x)); if (z > x) z -= 1.0; return z; } static __inline__ __const__ float __inline_floorf (float x) { float z; __asm__ ("frint.s %1,%0" : "=d" (z) : "d" (x)); if (z > x) z -= 1.0F; return z; } static __inline__ __const__ double __inline_log10 (double x) { return 0.43429448190325182765 * __inline_log (x); } static __inline__ __const__ float __inline_log10f (float x) { return 0.43429448190325182765F * __inline_logf (x); } static __inline__ double __inline_modf (double x, double *np) { double intpart; __asm__ ("frint.d %1,%0" : "=d" (intpart) : "d" (x)); *np = intpart; return x - intpart; } static __inline__ float __inline_modff (float x, float *np) { float intpart; __asm__ ("frint.s %1,%0" : "=d" (intpart) : "d" (x)); *np = intpart; return x - intpart; } static __inline__ double __inline_frexp (double x, int *np) { union u { double d; unsigned long long ll; } u; if ((u.d = x) == 0) *np = 0; else { #if _IEEE_FLOAT_ *np = ((u.ll >> 52) & 03777) - 01776; u.ll = (u.ll & 0x800fffffffffffffLL) | 0x3fe0000000000000LL; #else *np = ((u.ll >> 52) & 03777) - 02000; u.ll = (u.ll & 0x800fffffffffffffLL) | 0x4000000000000000LL; #endif } return u.d; } static __inline__ float __inline_frexpf (float x, int *np) { union u { float f; unsigned int i; } u; if ((u.f = x) == 0) *np = 0; else { #if _IEEE_FLOAT_ *np = ((u.i >> 23) & 0377) - 0176; u.i = (u.i & 0x807fffff) | 0x3f000000; #else *np = ((u.i >> 23) & 0377) - 0200; u.i = (u.i & 0x807fffff) | 0x40000000; #endif } return u.f; } static __inline__ double __inline_ldexp (double x, int n) { extern int errno; union { double d; long long ll; unsigned sexp : 12; } u; if ((u.d = x) != 0) { int exp = n + (u.sexp & 03777); long long nn = (long long) n << 52; #if _IEEE_FLOAT_ if (exp <= 0) u.ll &= 0x8000000000000000LL, errno = 34; else if (exp > 03776) u.ll = u.ll & 0x8000000000000000LL | 0x7fefffffffffffffLL, errno = 34; #else if (exp <= 0) u.ll = 0, errno = 34; else if (exp > 03777) u.ll |= 0x7fffffffffffffffLL, errno = 34; #endif else u.ll += nn; } return u.d; } static __inline__ float __inline_ldexpf (float x, int n) { extern int errno; union { float f; int i; unsigned sexp : 9; } u; if ((u.f = x) != 0) { int exp = n + (u.sexp & 0377); int nn = n << 23; #if _IEEE_FLOAT_ if (exp <= 0) u.i &= 0x80000000, errno = 34; else if (exp > 0376) u.i = u.i & 0x80000000 | 0x7f7fffff, errno = 34; #else if (exp <= 0) u.i = 0, errno = 34; else if (exp > 0377) u.i |= 0x7fffffff, errno = 34; #endif else u.i += nn; } return u.f; } static __inline__ __const__ double __inline_rint (double x) { double z; union { double d; unsigned long long ll; } u; u.d = x; #if _IEEE_FLOAT_ u.ll = (u.ll & 0x8000000000000000LL) | 0x3fe0000000000000LL; #else u.ll = (u.ll & 0x8000000000000000LL) | 0x4000000000000000LL; #endif __asm__ ("frint.d %1,%0" : "=d" (z) : "d" (x + u.d)); return z; } static __inline__ __const__ float __inline_rintf (float x) { float z; union { float f; unsigned int i; } u; u.f = x; #if _IEEE_FLOAT_ u.i = (u.i & 0x80000000) | 0x3f000000; #else u.i = (u.i & 0x80000000) | 0x40000000; #endif __asm__ ("frint.s %1,%0" : "=d" (z) : "d" (x + u.f)); return z; } static __inline__ __const__ int __inline_irint (double x) { union { double d; unsigned long long ll; } u; u.d = x; #if _IEEE_FLOAT_ u.ll = (u.ll & 0x8000000000000000LL) | 0x3fe0000000000000LL; #else u.ll = (u.ll & 0x8000000000000000LL) | 0x4000000000000000LL; #endif return x + u.d; } static __inline__ __const__ int __inline_irintf (float x) { union { float f; unsigned int i; } u; u.f = x; #if _IEEE_FLOAT_ u.i = (u.i & 0x80000000) | 0x3f000000; #else u.i = (u.i & 0x80000000) | 0x40000000; #endif return x + u.f; } #endif /* _MATH_H */ @//E*O*F include/math.h// chmod u=rw,g=rw,o=r include/math.h echo x - include/stddef.h sed 's/^@//' > "include/stddef.h" <<'@//E*O*F include/stddef.h//' #ifndef _STDDEF_H #define _STDDEF_H #ifndef __WCHAR_T #define __WCHAR_T #ifdef __GNUG__ /* In C++, wchar_t is a distinct basic type, and we can expect __wchar_t to be defined by cc1plus. */ typedef __wchar_t wchar_t; #else /* In C, cpp tells us which type to make an alias for. */ typedef __WCHAR_TYPE__ wchar_t; #endif #endif /* __WCHAR_T */ #include_next #endif /* _STDDEF_H */ @//E*O*F include/stddef.h// chmod u=rw,g=rw,o=r include/stddef.h echo x - include/stdlib.h sed 's/^@//' > "include/stdlib.h" <<'@//E*O*F include/stdlib.h//' #ifndef _STDLIB_H #define _STDLIB_H #if _CONVEX_SOURCE #define alloca __non_builtin_alloca #include_next #undef alloca #else #include_next #endif /* _CONVEX_SOURCE */ #endif /* _STDLIB_H */ @//E*O*F include/stdlib.h// chmod u=rw,g=rw,o=r include/stdlib.h exit 0 gcc-2.5.8/config/convex/x-convex100444 22011 13 215 5372446662 15220 0ustar kenneruser# ld can make exe's c2-only if this lib is searched even though not loaded CCLIBFLAGS = -tm c1 # Use -pcc to avoid surprises. CC = cc -pcc gcc-2.5.8/config/convex/xm-convex.h100444 22011 13 3227 5413067022 15632 0ustar kenneruser/* Configuration for GNU C-compiler for Convex. Copyright (C) 1989, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* #defines that need visibility everywhere. */ #define FALSE 0 #define TRUE 1 /* target machine dependencies. tm.h is a symbolic link to the actual target specific file. */ #include "tm.h" /* This describes the machine the compiler is hosted on. */ #define HOST_BITS_PER_CHAR 8 #define HOST_BITS_PER_SHORT 16 #define HOST_BITS_PER_INT 32 #define HOST_BITS_PER_LONG 32 #define HOST_BITS_PER_LONGLONG 64 /* Arguments to use with `exit'. */ #define SUCCESS_EXIT_CODE 0 #define FATAL_EXIT_CODE 33 /* Convex ships /tmp as a separate file system - thus it usually has more free space than /usr/tmp */ #define P_tmpdir "/tmp/" /* Use memcpy and memset -- either would work but these get inlined. */ #define bcopy(a,b,c) memcpy (b,a,c) #define bzero(a,b) memset (a,0,b) /* Convex uses Vax or IEEE floats. Both formats have Vax semantics. */ #define HOST_FLOAT_FORMAT VAX_FLOAT_FORMAT gcc-2.5.8/config/elxsi/ 40777 22011 13 0 5502602736 13272 5ustar kennerusergcc-2.5.8/config/elxsi/elxsi.c100444 22011 13 7045 5277012505 14655 0ustar kenneruser/* Subroutines for insn-output.c for GNU compiler. Elxsi version. Copyright (C) 1987, 1992 Free Software Foundation, Inc This port, done by Mike Stump in 1988, and is the first 64 bit port of GNU CC. Based upon the VAX port. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 1, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include "config.h" #include "rtl.h" extern char *reg_names[]; rtx cmp_op0=0, cmp_op1=0; /* table of relations for compares and branches */ char *cmp_tab[] = { "gt", "gt", "eq", "eq", "ge", "ge", "lt", "lt", "ne", "ne", "le", "le" }; /* type is the index into the above table */ /* s is "" for signed, or "u" for unsigned */ char *cmp_jmp(s, type, where) char *s; rtx where; { rtx br_ops[3]; char template[50]; char *f = ""; char *bits = "64"; if (GET_MODE (cmp_op0) == SFmode) f = "f", bits = "32"; if (GET_MODE (cmp_op0) == DFmode) f = "f"; br_ops[0] = where; br_ops[1] = cmp_op0; br_ops[2] = cmp_op1; if (cmp_op1) sprintf(template, "%scmp%s.br.%s\t%%1,%%2:j%s\t%%l0", f, s, bits, cmp_tab[type]); else if (*f) sprintf(template, "fcmp.br.%s\t%%1,=0:j%s\t%%l0", bits, cmp_tab[type]); else if (*s) /* can turn the below in to a jmp ... */ sprintf(template, "cmpu.br.64\t%%1,=0:j%s\t%%l0", s, cmp_tab[type]); else sprintf(template, "jmp.%s\t%%1,%%l0", cmp_tab[type+1]); output_asm_insn(template, br_ops); return ""; } char *cmp_set(s, type, reg) char *s, *type; rtx reg; { rtx br_ops[3]; char template[50]; char *f = ""; char *bits = "64"; if (GET_MODE (cmp_op0) == SFmode) f = "f", bits = "32"; else if (GET_MODE (cmp_op0) == DFmode) f = "f"; else if (GET_MODE (cmp_op0) == SImode) bits = "32"; else if (GET_MODE (cmp_op0) == HImode) bits = "16"; else if (GET_MODE (cmp_op0) == QImode) bits = "8"; br_ops[0] = reg; br_ops[1] = cmp_op0; br_ops[2] = cmp_op1; if (cmp_op1) sprintf(template, "%scmp%s.%s\t%%0,%%1,%%2:%s", f, s, bits, type); else sprintf(template, "%scmp%s.%s\t%%0,%%1,=0:%s", f, s, bits, type); output_asm_insn(template, br_ops); return ""; } print_operand_address (file, addr) FILE *file; register rtx addr; { register rtx reg1, reg2, breg, ireg; rtx offset; retry: switch (GET_CODE (addr)) { case MEM: if (GET_CODE (XEXP (addr, 0)) == REG) fprintf (file, "%s", reg_names[REGNO (addr)]); else abort(); break; case REG: fprintf (file, "[%s]", reg_names[REGNO (addr)]); break; case PLUS: reg1 = 0; reg2 = 0; ireg = 0; breg = 0; offset = 0; if (GET_CODE (XEXP (addr, 0)) == REG) { offset = XEXP (addr, 1); addr = XEXP (addr, 0); } else if (GET_CODE (XEXP (addr, 1)) == REG) { offset = XEXP (addr, 0); addr = XEXP (addr, 1); } fprintf (file, "[%s]", reg_names[REGNO (addr)]); output_address (offset); break; default: output_addr_const (file, addr); } } gcc-2.5.8/config/elxsi/elxsi.h100444 22011 13 105572 5453234454 14733 0ustar kenneruser/* Definitions of target machine for GNU compiler. Elxsi version. Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc. This port, done by Mike Stump in 1988, and is the first 64 bit port of GNU CC. Based upon the VAX port. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 1, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Delxsi -Dunix -Asystem(unix) -Acpu(elxsi) -Amachine(elxsi)" /* Print subsidiary information on the compiler version in use. */ #define TARGET_VERSION fprintf (stderr, " (elxsi)"); /* Run-time compilation parameters selecting different hardware subsets. */ extern int target_flags; /* Macros used in the machine description to test the flags. */ /* Nonzero if compiling code that Unix assembler can assemble. */ #define TARGET_UNIX_ASM (target_flags & 1) /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */ #define TARGET_SWITCHES \ { {"unix", 1}, \ {"embos", -1}, \ { "", TARGET_DEFAULT}} /* Default target_flags if no switches specified. */ #ifndef TARGET_DEFAULT #define TARGET_DEFAULT 1 #endif /* Target machine storage layout */ /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. This is not true on the vax. */ #define BITS_BIG_ENDIAN 0 /* Define this if most significant byte of a word is the lowest numbered. */ #define BYTES_BIG_ENDIAN 1 /* Define this if most significant word of a multiword number is numbered. */ #define WORDS_BIG_ENDIAN 1 /* Number of bits in an addressable storage unit */ #define BITS_PER_UNIT 8 /* Width in bits of a "word", which is the contents of a machine register. Note that this is not necessarily the width of data type `int'; if using 16-bit ints on a 68000, this would still be 32. But on a machine with 16-bit registers, this would be 16. */ #define BITS_PER_WORD 64 #define Rmode DImode #define INT_TYPE_SIZE 32 #define LONG_TYPE_SIZE 32 #define LONG_LONG_TYPE_SIZE 64 #define FLOAT_TYPE_SIZE 32 #define DOUBLE_TYPE_SIZE 64 #define LONG_DOUBLE_TYPE_SIZE 64 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 8 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ #define POINTER_SIZE 32 /* Allocation boundary (in *bits*) for storing pointers in memory. */ #define POINTER_BOUNDARY 32 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ #define PARM_BOUNDARY 32 /* Allocation boundary (in *bits*) for the code of a function. */ #define FUNCTION_BOUNDARY 8 /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 8 /* Every structure's size must be a multiple of this. */ #define STRUCTURE_SIZE_BOUNDARY 32 /* A bitfield declared as `int' forces `int' alignment for the struct. */ #define PCC_BITFIELD_TYPE_MATTERS 1 /* No data type wants to be aligned rounder than this. */ #define BIGGEST_ALIGNMENT 32 /* Define this if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 0 /* Standard register usage. */ /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. */ #define FIRST_PSEUDO_REGISTER 16 /* 1 for registers that have pervasive standard uses and are not available for the register allocator. On the elxsi, these is the .r15 (aka .sp). */ #define FIXED_REGISTERS {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1} /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. */ #define CALL_USED_REGISTERS {1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1} /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. On the vax, all registers are one word long. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) 1 /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. */ #define MODES_TIEABLE_P(MODE1, MODE2) 1 /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM 15 /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM 14 /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */ #define FRAME_POINTER_REQUIRED 0 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ { int regno; \ int offset = 0; \ for( regno=0; regno < FIRST_PSEUDO_REGISTER; regno++ ) \ if( regs_ever_live[regno] && !call_used_regs[regno] ) \ offset += 8; \ (DEPTH) = (offset + ((get_frame_size() + 3) & ~3) ); \ (DEPTH) = 0; \ } /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM 14 /* Register in which static-chain is passed to a function. */ #define STATIC_CHAIN_REGNUM 0 /* Register in which address to store a structure value is passed to a function. */ #define STRUCT_VALUE_REGNUM 1 /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. One of the classes must always be named ALL_REGS and include all hard regs. If there is more than one class, another class must be named NO_REGS and contain no registers. The name GENERAL_REGS must be the name of a class (or an alias for another name such as ALL_REGS). This is the class of registers that is allowed by "g" or "r" in a register constraint. Also, registers outside this class are allocated only when instructions express preferences for them. The classes must be numbered in nondecreasing order; that is, a larger-numbered class must never be contained completely in a smaller-numbered class. For any two classes, it is very desirable that there be another class that represents their union. */ /* The vax has only one kind of registers, so NO_REGS and ALL_REGS are the only classes. */ enum reg_class { NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ {"NO_REGS", "GENERAL_REGS", "ALL_REGS" } /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS {0, 0x07fff, 0xffff} /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ #define REGNO_REG_CLASS(REGNO) (REGNO == 15 ? ALL_REGS : GENERAL_REGS) /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS GENERAL_REGS #define BASE_REG_CLASS GENERAL_REGS /* Get reg_class from a letter such as appears in the machine description. */ #define REG_CLASS_FROM_LETTER(C) NO_REGS /* The letters I, J, K, L and M in a register constraint string can be used to stand for particular ranges of immediate operands. This macro defines what the ranges are. C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. */ #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? (VALUE) >=-16 && (VALUE) <=15 : 0) /* Similar, but for floating constants, and defining letters G and H. Here VALUE is the CONST_DOUBLE rtx itself. */ #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1 /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. */ #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ /* On the vax, this is always the size of MODE in words, since all registers are the same size. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack makes the stack pointer a smaller address. */ #define STACK_GROWS_DOWNWARD /* Define this if the nominal address of the stack frame is at the high-address end of the local variables; that is, each additional local variable allocated goes at a more negative offset in the frame. */ #define FRAME_GROWS_DOWNWARD /* Offset within stack frame to start allocating local variables at. If FRAME_GROWS_DOWNWARD, this is the offset to the END of the first local allocated. Otherwise, it is the offset to the BEGINNING of the first local allocated. */ #define STARTING_FRAME_OFFSET -4 /* Offset of first parameter from the argument pointer register value. */ #define FIRST_PARM_OFFSET(FNDECL) 4 /* Value is 1 if returning from a function call automatically pops the arguments described by the number-of-args field in the call. FUNTYPE is the data type of the function (as a tree), or for a library call it is an identifier node for the subroutine name. On the Vax, the RET insn always pops all the args for any function. */ #define RETURN_POPS_ARGS(FUNTYPE,SIZE) (SIZE) /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */ /* On the Vax the return value is in R0 regardless. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ gen_rtx (REG, TYPE_MODE (VALTYPE), 0) /* Define how to find the value returned by a library function assuming the value has mode MODE. */ /* On the Vax the return value is in R0 regardless. */ #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0) /* Define this if PCC uses the nonreentrant convention for returning structure and union values. */ #define PCC_STATIC_STRUCT_RETURN /* 1 if N is a possible register number for a function value. On the Vax, R0 is the only register thus used. */ #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) /* 1 if N is a possible register number for function argument passing. On the Vax, no registers are used in this way. */ #define FUNCTION_ARG_REGNO_P(N) 0 /* Define a data type for recording info about an argument list during the scan of that argument list. This data type should hold all necessary information about the function itself and about the args processed so far, enough to enable macros such as FUNCTION_ARG to determine where the next arg should go. On the vax, this is a single integer, which is a number of bytes of arguments scanned so far. */ #define CUMULATIVE_ARGS int /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. On the vax, the offset starts at 0. */ #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,x) \ ((CUM) = 0) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ ((CUM) += ((MODE) != BLKmode \ ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ : (int_size_in_bytes (TYPE) + 3) & ~3)) /* Define where to put the arguments to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. MODE is the argument's machine mode. TYPE is the data type of the argument (as a tree). This is null for libcalls where that information may not be available. CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called. NAMED is nonzero if this argument is a named parameter (otherwise it is an extra parameter matching an ellipsis). */ /* On the vax all args are pushed. */ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0 /* This macro generates the assembly code for function entry. FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. Refer to the array `regs_ever_live' to determine which registers to save; `regs_ever_live[I]' is nonzero if register number I is ever used in the function. This macro is responsible for knowing which registers should not be saved even if used. */ #define FUNCTION_PROLOGUE(FILE, SIZE) \ { register int regno; \ register int cnt = 0; \ extern char call_used_regs[]; \ /* the below two lines are a HACK, and should be deleted, but \ for now are very much needed (1.35) */ \ if (frame_pointer_needed) \ regs_ever_live[14]=1, call_used_regs[14]=0; \ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \ if (regs_ever_live[regno] && !call_used_regs[regno]) \ cnt+=8; \ if ((SIZE)+cnt) \ fprintf (FILE, "\tadd.64\t.sp,=%d\n", -(SIZE)-cnt); \ cnt = 0; \ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \ if (regs_ever_live[regno] && !call_used_regs[regno]) \ fprintf (FILE, "\tst.64\t.r%d,[.sp]%d\n", regno, (cnt+=8)-12); \ if (frame_pointer_needed) \ fprintf (FILE, "\tadd.64\t.r14,.sp,=%d\n", (SIZE)+cnt); \ } /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ #define FUNCTION_PROFILER(FILE, LABELNO) \ fprintf (FILE, "\tld.64\t.r0,.LP%d\n\tcall\tmcount\n", (LABELNO)); /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, the stack pointer does not matter. The value is tested only in functions that have frame pointers. No definition is equivalent to always zero. */ #define EXIT_IGNORE_STACK 0 /* This macro generates the assembly code for function exit, on machines that need it. If FUNCTION_EPILOGUE is not defined then individual return instructions are generated for each return statement. Args are same as for FUNCTION_PROLOGUE. */ #define FUNCTION_EPILOGUE(FILE, SIZE) \ { register int regno; \ register int cnt = 0; \ extern char call_used_regs[]; \ extern int current_function_calls_alloca; \ /* this conditional is ONLY here because there is a BUG; \ EXIT_IGNORE_STACK is ignored itself when the first part of \ the condition is true! (atleast in version 1.35) */ \ /* the 8*10 is for 64 bits of .r5 - .r14 */ \ if (current_function_calls_alloca || (SIZE)>=(256-8*10)) { \ /* use .r4 as a temporary! Ok for now.... */ \ fprintf (FILE, "\tld.64\t.r4,.r14\n"); \ for (regno = FIRST_PSEUDO_REGISTER-1; regno >= 0; --regno) \ if (regs_ever_live[regno] && !call_used_regs[regno]) \ cnt+=8; \ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno) \ if (regs_ever_live[regno] && !call_used_regs[regno]) \ fprintf (FILE, "\tld.64\t.r%d,[.r14]%d\n", regno, \ -((cnt-=8) + 8)-4-(SIZE)); \ fprintf (FILE, "\tld.64\t.sp,.r4\n\texit\t0\n"); \ } else { \ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno) \ if (regs_ever_live[regno] && !call_used_regs[regno]) \ fprintf (FILE, "\tld.64\t.r%d,[.sp]%d\n", regno, (cnt+=8)-12); \ fprintf (FILE, "\texit\t%d\n", (SIZE)+cnt); \ } } /* If the memory address ADDR is relative to the frame pointer, correct it to be relative to the stack pointer instead. This is for when we don't use a frame pointer. ADDR should be a variable name. */ #define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH) \ { int offset = -1; \ rtx regs = stack_pointer_rtx; \ if (ADDR == frame_pointer_rtx) \ offset = 0; \ else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx \ && GET_CODE (XEXP (ADDR, 0)) == CONST_INT) \ offset = INTVAL (XEXP (ADDR, 0)); \ else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \ && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \ offset = INTVAL (XEXP (ADDR, 1)); \ else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \ { rtx other_reg = XEXP (ADDR, 1); \ offset = 0; \ regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \ else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \ { rtx other_reg = XEXP (ADDR, 0); \ offset = 0; \ regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \ if (offset >= 0) \ { int regno; \ extern char call_used_regs[]; \ offset += 4; /* I don't know why??? */ \ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ offset += 8; \ ADDR = plus_constant (regs, offset + (DEPTH)); } } /* Addressing modes, and classification of registers for them. */ /* #define HAVE_POST_INCREMENT */ /* #define HAVE_POST_DECREMENT */ /* #define HAVE_PRE_DECREMENT */ /* #define HAVE_PRE_INCREMENT */ /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. */ #define REGNO_OK_FOR_INDEX_P(regno) \ ((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0) #define REGNO_OK_FOR_BASE_P(regno) \ ((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0) /* Maximum number of registers that can appear in a valid memory address. */ #define MAX_REGS_PER_ADDRESS 2 /* 1 if X is an rtx for a constant that is a valid address. */ #define CONSTANT_ADDRESS_P(X) \ (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ || GET_CODE (X) == HIGH) /* Nonzero if the constant value X is a legitimate general operand. It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ #define LEGITIMATE_CONSTANT_P(X) \ (GET_CODE (X) != CONST_DOUBLE) /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. The usual definition accepts all pseudo regs; the other rejects them unless they have been allocated suitable hard regs. The symbol REG_OK_STRICT causes the latter definition to be used. Most source files want to accept pseudo regs in the hope that they will get allocated to the class that the insn wants them to be in. Source files for reload pass need to be strict. After reload, it makes no difference, since pseudo regs have been eliminated by then. */ #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ #define REG_OK_FOR_INDEX_P(X) 1 /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ #define REG_OK_FOR_BASE_P(X) 1 #else /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) #endif /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. CONSTANT_ADDRESS_P is actually machine-independent. */ #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { \ if (GET_CODE (X) == REG) goto ADDR; \ if (CONSTANT_ADDRESS_P (X)) goto ADDR; \ if (GET_CODE (X) == PLUS) \ { \ /* Handle [index]
represented with index-sum outermost */\ if (GET_CODE (XEXP (X, 0)) == REG \ && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ && GET_CODE (XEXP (X, 1)) == CONST_INT) \ goto ADDR; \ if (GET_CODE (XEXP (X, 1)) == REG \ && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ && GET_CODE (XEXP (X, 0)) == CONST_INT) \ goto ADDR; \ } \ } /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. OLDX is the address as it was before break_out_memory_refs was called. In some cases it is useful to look at this to decide what needs to be done. MODE and WIN are passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. It is always safe for this macro to do nothing. It exists to recognize opportunities to optimize the output. For the vax, nothing needs to be done. */ #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {} /* Go to LABEL if ADDR (a legitimate address expression) has an effect that depends on the machine mode it is used for. */ #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE SImode /* Define this if the case instruction expects the table to contain offsets from the address of the table. Do not define this if the table should contain absolute addresses. */ /* #define CASE_VECTOR_PC_RELATIVE */ /* Specify the tree operation to be used to convert reals to integers. */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR /* This is the kind of divide that is easiest to do in the general case. */ #define EASY_DIV_EXPR TRUNC_DIV_EXPR /* Define this as 1 if `char' should by default be signed; else as 0. */ #define DEFAULT_SIGNED_CHAR 1 /* This flag, if defined, says the same insns that convert to a signed fixnum also convert validly to an unsigned one. */ #define FIXUNS_TRUNC_LIKE_FIX_TRUNC /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ #define MOVE_MAX 8 /* Define this if zero-extension is slow (more than one real instruction). */ /* #define SLOW_ZERO_EXTEND */ /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS 0 /* Define if shifts truncate the shift count which implies one can omit a sign-extension or zero-extension of a shift count. */ /* #define SHIFT_COUNT_TRUNCATED */ /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ #define Pmode SImode /* A function address in a call instruction is a byte address (for indexing purposes) so give the MEM rtx a byte's mode. */ #define FUNCTION_MODE QImode /* Compute the cost of computing a constant rtl expression RTX whose rtx-code is CODE. The body of this macro is a portion of a switch statement. If the code is computed here, return it with a return statement. Otherwise, break from the switch. */ #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ /* Constant zero is super cheap due to clr instruction. */ \ if (RTX == const0_rtx) return 0; \ if ((unsigned) INTVAL (RTX) < 077) return 1; \ case CONST: \ case LABEL_REF: \ case SYMBOL_REF: \ return 3; \ case CONST_DOUBLE: \ return 5; /* * We can use the BSD C library routines for the gnulib calls that are * still generated, since that's what they boil down to anyways. */ /* #define UDIVSI3_LIBCALL "*udiv" */ /* #define UMODSI3_LIBCALL "*urem" */ /* Check a `double' value for validity for a particular machine mode. */ /* Note that it is very hard to accidentally create a number that fits in a double but not in a float, since their ranges are almost the same. */ #define CHECK_FLOAT_VALUE(mode, d) \ if ((mode) == SFmode) \ { \ if ((d) > 1.7014117331926443e+38) \ { error ("magnitude of constant too large for `float'"); \ (d) = 1.7014117331926443e+38; } \ else if ((d) < -1.7014117331926443e+38) \ { error ("magnitude of constant too large for `float'"); \ (d) = -1.7014117331926443e+38; } \ else if (((d) > 0) && ((d) < 2.9387358770557188e-39)) \ { warning ("`float' constant truncated to zero"); \ (d) = 0.0; } \ else if (((d) < 0) && ((d) > -2.9387358770557188e-39)) \ { warning ("`float' constant truncated to zero"); \ (d) = 0.0; } \ } /* Tell final.c how to eliminate redundant test instructions. */ /* Here we define machine-dependent flags and fields in cc_status (see `conditions.h'). No extra ones are needed for the vax. */ /* Store in cc_status the expressions that the condition codes will describe after execution of an instruction whose pattern is EXP. Do not alter them if the instruction would not alter the cc's. */ #define NOTICE_UPDATE_CC(EXP, INSN) \ CC_STATUS_INIT; /* Control the assembler format that we output. */ /* Output the name of the file we are compiling. */ #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ do { fprintf (STREAM, "\t.file\t"); \ output_quoted_string (STREAM, NAME); \ fprintf (STREAM, "\n"); \ } while (0) /* Output at beginning of assembler file. */ #define ASM_FILE_START(FILE) fprintf (FILE, ""); /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ #define ASM_APP_ON "" /* Output to assembler file text saying following lines no longer contain unusual constructs. */ #define ASM_APP_OFF "" /* Output before read-only data. */ #define TEXT_SECTION_ASM_OP "\t.inst" /* Output before writable data. */ #define DATA_SECTION_ASM_OP "\t.var" /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ #define REGISTER_NAMES \ {".r0", ".r1", ".r2", ".r3", ".r4", ".r5", ".r6", ".r7", ".r8", \ ".r9", ".r10", ".r11", ".r12", ".r13", ".r14", ".sp"} /* This is BSD, so it wants DBX format. */ /* #define DBX_DEBUGGING_INFO */ /* How to renumber registers for dbx and gdb. Vax needs no change in the numeration. */ #define DBX_REGISTER_NUMBER(REGNO) (REGNO) /* Do not break .stabs pseudos into continuations. */ #define DBX_CONTIN_LENGTH 0 /* This is the char to use for continuation (in case we need to turn continuation back on). */ #define DBX_CONTIN_CHAR '?' /* Don't use the `xsfoo;' construct in DBX output; this system doesn't support it. */ #define DBX_NO_XREFS /* This is how to output the definition of a user-level label named NAME, such as the label on a static function or variable NAME. */ #define ASM_OUTPUT_LABEL(FILE,NAME) \ do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) /* This is how to output a command to make the user-level label named NAME defined for reference from other files. */ #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ do { fputs ("\t.extdef\t", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) /* This is how to output a reference to a user-level label named NAME. */ #define ASM_OUTPUT_LABELREF(FILE,NAME) \ fprintf (FILE, "%s", NAME) /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, ".%s%d:\n", PREFIX, NUM) /* This is how to store into the string LABEL the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ sprintf (LABEL, ".%s%d", PREFIX, NUM) /* This is how to output an assembler line defining a `double' constant. It is .dfloat or .gfloat, depending. */ #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ { union {double d; int i[2]; } tem; \ tem.d = (VALUE); \ fprintf (FILE, "\t.data\t%d{32}, %d{32}\n", tem.i[0], tem.i[1]); } /* This is how to output an assembler line defining a `float' constant. */ #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ { union {float f; int i; } tem; \ tem.f = (VALUE); \ fprintf (FILE, "\t.data %d{32}\n", tem.i); } /* This is how to output an assembler line defining an `int' constant. */ #define ASM_OUTPUT_INT(FILE,VALUE) \ ( \ fprintf (FILE, "\t.data\t"), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "{32}\n")) #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ { \ fprintf (FILE, "\t.data\t"); \ if (GET_CODE (VALUE) == CONST_DOUBLE) \ { \ fprintf (FILE, "%d", CONST_DOUBLE_HIGH (VALUE)); \ fprintf (FILE, "{32}, "); \ fprintf (FILE, "%d", CONST_DOUBLE_LOW (VALUE)); \ fprintf (FILE, "{32}\n"); \ } else if (GET_CODE (VALUE) == CONST_INT) \ { \ int val = INTVAL (VALUE); \ fprintf (FILE, "%d", val < 0 ? -1 : 0); \ fprintf (FILE, "{32}, "); \ fprintf (FILE, "%d", val); \ fprintf (FILE, "{32}\n"); \ } else abort (); \ } /* Likewise for `char' and `short' constants. */ #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "\t.data\t"), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "{16}\n")) #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ( fprintf (FILE, "\t.data\t"), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "{8}\n")) /* This is how to output an assembler line for a numeric constant byte. */ #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf (FILE, "\t.data\t%d{8}\n", (VALUE)) /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tsubi.64\t4,.sp\n\tst.32\t%s,[.sp]\n", reg_names[REGNO]) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tld.32\t%s,[.sp]\n\taddi.64\t4,.sp\n", reg_names[REGNO]) /* This is how to output an element of a case-vector that is absolute. (The Vax does not use such vectors, but we must define this macro anyway.) */ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "\t.data .L%d{32}\n", VALUE) /* This is how to output an element of a case-vector that is relative. */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\t.data .L%d-.L%d{32}\n", VALUE, REL) /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if (LOG!=0) fprintf (FILE, "\t.align\t%d\n", (LOG)); else 0 /* This is how to output an assembler line that says to advance the location counter by SIZE bytes. */ #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t.space %d\n", (SIZE)) /* This says how to output an assembler line to define a global common symbol. */ #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fputs (".comm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%d\n", (ROUNDED))) /* This says how to output an assembler line to define a local common symbol. */ #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( fputs (".bss ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%d,%d\n", (SIZE),(ROUNDED))) /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) /* Define the parentheses used to group arithmetic operations in assembler code. */ #define ASM_OPEN_PAREN "(" #define ASM_CLOSE_PAREN ")" /* Define results of standard character escape sequences. */ #define TARGET_BELL 007 #define TARGET_BS 010 #define TARGET_TAB 011 #define TARGET_NEWLINE 012 #define TARGET_VT 013 #define TARGET_FF 014 #define TARGET_CR 015 /* Print an instruction operand X on file FILE. CODE is the code from the %-spec that requested printing this operand; if `%z3' was used to print operand 3, then CODE is 'z'. */ #define PRINT_OPERAND(FILE, X, CODE) \ { \ if (CODE == 'r' && GET_CODE (X) == MEM && GET_CODE (XEXP (X, 0)) == REG) \ fprintf (FILE, "%s", reg_names[REGNO (XEXP (X, 0))]); \ else if (GET_CODE (X) == REG) \ fprintf (FILE, "%s", reg_names[REGNO (X)]); \ else if (GET_CODE (X) == MEM) \ output_address (XEXP (X, 0)); \ else \ { \ /*debug_rtx(X);*/ \ putc ('=', FILE); \ output_addr_const (FILE, X); } \ } /* Print a memory operand whose address is X, on file FILE. This uses a function in output-vax.c. */ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ print_operand_address (FILE, ADDR) /* Functions used in the md file. */ extern char *cmp_set(); extern char *cmp_jmp(); /* These are stubs, and have yet to bee written. */ #define TRAMPOLINE_SIZE 26 #define TRAMPOLINE_TEMPLATE(FILE) #define INITIALIZE_TRAMPOLINE(TRAMP,FNADDR,CXT) gcc-2.5.8/config/elxsi/elxsi.md100444 22011 13 115634 5331076440 15076 0ustar kenneruser;;- Machine description for GNU compiler ;;- Elxsi Version ;; Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc. ;; This port done by Mike Stump in 1988, and is the first ;; 64 bit port of GNU CC. ;; Based upon the VAX port. ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 1, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ;;- Instruction patterns. When multiple patterns apply, ;;- the first one in the file is chosen. ;;- ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ;;- ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code ;;- updates for most instructions. (define_insn "" [(set (reg:SI 15) (plus:SI (reg:SI 15) (match_operand:SI 0 "general_operand" "g")))] "" "add.64\\t.sp,%0") (define_insn "" [(set (reg:SI 15) (plus:SI (match_operand:SI 0 "general_operand" "g") (reg:SI 15)))] "" "add.64\\t.sp,%0") (define_insn "" [(set (match_operand:SI 0 "register_operand" "r") (plus:SI (reg:SI 15) (match_operand:SI 1 "general_operand" "g")))] "" "ld.32\\t%0,.sp\;add.64\\t%0,%1") (define_insn "" [(set (match_operand:SI 0 "register_operand" "r") (plus:SI (match_operand:SI 1 "general_operand" "g") (reg:SI 15)))] "" "ld.32\\t%0,.sp\;add.64\\t%0,%1") (define_insn "" [(set (reg:SI 15) (minus:SI (reg:SI 15) (match_operand:SI 0 "general_operand" "g")))] "" "sub.64\\t.sp,%0") (define_insn "" [(set (reg:SI 15) (match_operand:SI 0 "general_operand" "rm"))] "" "ld.32\\t.sp,%0") (define_insn "" [(set (match_operand:SI 0 "general_operand" "m,r") (reg:SI 15))] "" "* if (which_alternative == 0) return \"st.32\\t.sp,%0\"; return \"ld.32\\t%0,.sp\"; ") ; tstdi is first test insn so that it is the one to match ; a constant argument. (define_insn "tstdi" [(set (cc0) (match_operand:DI 0 "register_operand" "r"))] "" "* extern rtx cmp_op0, cmp_op1; cmp_op0=operands[0]; cmp_op1=0; return \";\\ttstdi\\t%0\"; ") (define_insn "tstdf" [(set (cc0) (match_operand:DF 0 "register_operand" "r"))] "" "* extern rtx cmp_op0, cmp_op1; cmp_op0=operands[0]; cmp_op1=0; return \";\\ttstdf\\t%0\"; ") (define_insn "tstsf" [(set (cc0) (match_operand:SF 0 "register_operand" "r"))] "" "* extern rtx cmp_op0, cmp_op1; cmp_op0=operands[0]; cmp_op1=0; return \";\\ttstsf\\t%0\"; ") (define_insn "cmpdi" [(set (cc0) (compare (match_operand:DI 0 "register_operand" "r") (match_operand:DI 1 "general_operand" "rm")))] "" "* extern rtx cmp_op0, cmp_op1; cmp_op0=operands[0]; cmp_op1=operands[1]; return \";\\tcmpdi\\t%0,%1\"; ") (define_insn "cmpdf" [(set (cc0) (compare (match_operand:DF 0 "register_operand" "r") (match_operand:DF 1 "general_operand" "rm")))] "" "* extern rtx cmp_op0, cmp_op1; cmp_op0=operands[0]; cmp_op1=operands[1]; return \";\\tcmpdf\\t%0,%1\"; ") (define_insn "cmpsf" [(set (cc0) (compare (match_operand:SF 0 "register_operand" "r") (match_operand:SF 1 "general_operand" "rm")))] "" "* extern rtx cmp_op0, cmp_op1; cmp_op0=operands[0]; cmp_op1=operands[1]; return \";\\tcmpsf\\t%0,%1\"; ") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (eq (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "general_operand" "g")))] "" "cmp.64\\t%0,%1,%2:eq") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ne (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "general_operand" "g")))] "" "cmp.64\\t%0,%1,%2:ne") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (le (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "general_operand" "g")))] "" "cmp.64\\t%0,%1,%2:le") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (leu (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "general_operand" "g")))] "" "cmpu.64\\t%0,%1,%2:le") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (lt (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "general_operand" "g")))] "" "cmp.64\\t%0,%1,%2:lt") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ltu (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "general_operand" "g")))] "" "cmpu.64\\t%0,%1,%2:lt") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ge (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "general_operand" "g")))] "" "cmp.64\\t%0,%1,%2:ge") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (geu (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "general_operand" "g")))] "" "cmpu.64\\t%0,%1,%2:ge") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (gt (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "general_operand" "g")))] "" "cmp.64\\t%0,%1,%2:gt") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (gtu (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "general_operand" "g")))] "" "cmpu.64\\t%0,%1,%2:gt") (define_insn "seq" [(set (match_operand:DI 0 "register_operand" "=r") (eq (cc0) (const_int 0)))] "" "* return cmp_set(\"\", \"eq\", operands[0]); ") (define_insn "sne" [(set (match_operand:DI 0 "register_operand" "=r") (ne (cc0) (const_int 0)))] "" "* return cmp_set(\"\", \"ne\", operands[0]); ") (define_insn "sle" [(set (match_operand:DI 0 "register_operand" "=r") (le (cc0) (const_int 0)))] "" "* return cmp_set(\"\", \"le\", operands[0]); ") (define_insn "sleu" [(set (match_operand:DI 0 "register_operand" "=r") (leu (cc0) (const_int 0)))] "" "* return cmp_set(\"u\", \"le\", operands[0]); ") (define_insn "slt" [(set (match_operand:DI 0 "register_operand" "=r") (lt (cc0) (const_int 0)))] "" "* return cmp_set(\"\", \"lt\", operands[0]); ") (define_insn "sltu" [(set (match_operand:DI 0 "register_operand" "=r") (ltu (cc0) (const_int 0)))] "" "* return cmp_set(\"u\", \"lt\", operands[0]); ") (define_insn "sge" [(set (match_operand:DI 0 "register_operand" "=r") (ge (cc0) (const_int 0)))] "" "* return cmp_set(\"\", \"ge\", operands[0]); ") (define_insn "sgeu" [(set (match_operand:DI 0 "register_operand" "=r") (geu (cc0) (const_int 0)))] "" "* return cmp_set(\"u\", \"ge\", operands[0]); ") (define_insn "sgt" [(set (match_operand:DI 0 "register_operand" "=r") (gt (cc0) (const_int 0)))] "" "* return cmp_set(\"\", \"gt\", operands[0]); ") (define_insn "sgtu" [(set (match_operand:DI 0 "register_operand" "=r") (gtu (cc0) (const_int 0)))] "" "* return cmp_set(\"u\", \"gt\", operands[0]); ") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (eq (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "general_operand" "m")))] "" "cmp.32\\t%0,%1,%2:eq") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ne (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "general_operand" "m")))] "" "cmp.32\\t%0,%1,%2:ne") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (le (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "general_operand" "m")))] "" "cmp.32\\t%0,%1,%2:le") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (leu (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "general_operand" "m")))] "" "cmpu.32\\t%0,%1,%2:le") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (lt (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "general_operand" "m")))] "" "cmp.32\\t%0,%1,%2:lt") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ltu (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "general_operand" "m")))] "" "cmpu.32\\t%0,%1,%2:lt") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ge (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "general_operand" "m")))] "" "cmp.32\\t%0,%1,%2:ge") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (geu (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "general_operand" "m")))] "" "cmpu.32\\t%0,%1,%2:ge") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (gt (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "general_operand" "m")))] "" "cmp.32\\t%0,%1,%2:gt") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (gtu (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "general_operand" "m")))] "" "cmpu.32\\t%0,%1,%2:gt") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (eq (match_operand:HI 1 "register_operand" "r") (match_operand:HI 2 "general_operand" "m")))] "" "cmp.16\\t%0,%1,%2:eq") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (ne (match_operand:HI 1 "register_operand" "r") (match_operand:HI 2 "general_operand" "m")))] "" "cmp.16\\t%0,%1,%2:ne") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (le (match_operand:HI 1 "register_operand" "r") (match_operand:HI 2 "general_operand" "m")))] "" "cmp.16\\t%0,%1,%2:le") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (leu (match_operand:HI 1 "register_operand" "r") (match_operand:HI 2 "general_operand" "m")))] "" "cmpu.16\\t%0,%1,%2:le") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (lt (match_operand:HI 1 "register_operand" "r") (match_operand:HI 2 "general_operand" "m")))] "" "cmp.16\\t%0,%1,%2:lt") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (ltu (match_operand:HI 1 "register_operand" "r") (match_operand:HI 2 "general_operand" "m")))] "" "cmpu.16\\t%0,%1,%2:lt") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (ge (match_operand:HI 1 "register_operand" "r") (match_operand:HI 2 "general_operand" "m")))] "" "cmp.16\\t%0,%1,%2:ge") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (geu (match_operand:HI 1 "register_operand" "r") (match_operand:HI 2 "general_operand" "m")))] "" "cmpu.16\\t%0,%1,%2:ge") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (gt (match_operand:HI 1 "register_operand" "r") (match_operand:HI 2 "general_operand" "m")))] "" "cmp.16\\t%0,%1,%2:gt") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (gtu (match_operand:HI 1 "register_operand" "r") (match_operand:HI 2 "general_operand" "m")))] "" "cmpu.16\\t%0,%1,%2:gt") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") (eq (match_operand:QI 1 "register_operand" "r") (match_operand:QI 2 "general_operand" "m")))] "" "cmp.8\\t%0,%1,%2:eq") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") (ne (match_operand:QI 1 "register_operand" "r") (match_operand:QI 2 "general_operand" "m")))] "" "cmp.8\\t%0,%1,%2:ne") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") (le (match_operand:QI 1 "register_operand" "r") (match_operand:QI 2 "general_operand" "m")))] "" "cmp.8\\t%0,%1,%2:le") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") (leu (match_operand:QI 1 "register_operand" "r") (match_operand:QI 2 "general_operand" "m")))] "" "cmpu.8\\t%0,%1,%2:le") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") (lt (match_operand:QI 1 "register_operand" "r") (match_operand:QI 2 "general_operand" "m")))] "" "cmp.8\\t%0,%1,%2:lt") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") (ltu (match_operand:QI 1 "register_operand" "r") (match_operand:QI 2 "general_operand" "m")))] "" "cmpu.8\\t%0,%1,%2:lt") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") (ge (match_operand:QI 1 "register_operand" "r") (match_operand:QI 2 "general_operand" "m")))] "" "cmp.8\\t%0,%1,%2:ge") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") (geu (match_operand:QI 1 "register_operand" "r") (match_operand:QI 2 "general_operand" "m")))] "" "cmpu.8\\t%0,%1,%2:ge") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") (gt (match_operand:QI 1 "register_operand" "r") (match_operand:QI 2 "general_operand" "m")))] "" "cmp.8\\t%0,%1,%2:gt") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") (gtu (match_operand:QI 1 "register_operand" "r") (match_operand:QI 2 "general_operand" "m")))] "" "cmpu.8\\t%0,%1,%2:gt") (define_insn "movdf" [(set (match_operand:DF 0 "general_operand" "=r,m") (match_operand:DF 1 "general_operand" "rm,r"))] "" "* { if (which_alternative == 0) return \"ld.64\\t%0,%1\"; return \"st.64\\t%1,%0\"; }") (define_insn "movsf" [(set (match_operand:SF 0 "general_operand" "=r,m") (match_operand:SF 1 "general_operand" "rm,r"))] "" "* { if (which_alternative == 0) return \"ld.32\\t%0,%1\"; return \"st.32\\t%1,%0\"; }") (define_insn "movdi" [(set (match_operand:DI 0 "general_operand" "=r,m,rm") (match_operand:DI 1 "general_operand" "g,r,I"))] "" "* if (which_alternative == 0) return \"ld.64\\t%0,%1\"; else if (which_alternative == 1) return \"st.64\\t%1,%0\"; else if (GET_CODE(operands[1])==CONST_INT) { if (INTVAL(operands[1]) >= 0) return \"sti.64\\t%c1,%0\"; else return \"stin.64\\t%n1,%0\"; } ") (define_insn "movsi" [(set (match_operand:SI 0 "general_operand" "=r,m,r") (match_operand:SI 1 "general_operand" "rm,rI,i"))] "" "* if (which_alternative == 0) return \"ld.32\\t%0,%1\"; else if (which_alternative == 1) { if (GET_CODE(operands[1])==CONST_INT) { if (INTVAL(operands[1]) >= 0) return \"sti.32\\t%c1,%0\"; else return \"stin.32\\t%n1,%0\"; } return \"st.32\\t%1,%0\"; } else return \"ld.64\\t%0,%1 ; I only want 32\"; ") (define_insn "movhi" [(set (match_operand:HI 0 "general_operand" "=r,m,r") (match_operand:HI 1 "general_operand" "m,rI,ri"))] "" "* { if (which_alternative == 0) return \"ld.16\\t%0,%1\"; if (which_alternative == 2) return \"ld.64\\t%0,%1\\t; I only want 16\"; if (GET_CODE(operands[1])==CONST_INT) { if (INTVAL(operands[1]) >= 0) return \"sti.16\\t%c1,%0\"; else return \"stin.16\\t%n1,%0\"; } return \"st.16\\t%1,%0\"; }") (define_insn "movqi" [(set (match_operand:QI 0 "general_operand" "=r,m,r") (match_operand:QI 1 "general_operand" "m,rI,ri"))] "" "* { if (which_alternative == 0) return \"ld.8\\t%0,%1\"; if (which_alternative == 2) return \"ld.64\\t%0,%1\\t; I only want 8\"; if (GET_CODE(operands[1])==CONST_INT) { if (INTVAL(operands[1]) >= 0) return \"sti.8\\t%c1,%0\"; else return \"stin.8\\t%n1,%0\"; } return \"st.8\\t%1,%0\"; }") ;; Extension and truncation insns. ;; Those for integer source operand ;; are ordered widest source type first. (define_insn "truncdfsf2" [(set (match_operand:SF 0 "register_operand" "=r") (truncate:SF (match_operand:DF 1 "general_operand" "rm")))] "" "cvt.ds\\t%0,%1") (define_insn "truncdiqi2" [(set (match_operand:QI 0 "general_operand" "=r,m,r") (truncate:QI (match_operand:DI 1 "general_operand" "m,r,0")))] "" "* { if (which_alternative == 0) return \"ld.8\\t%0,%1\"; else if (which_alternative == 1) return \"st.8\\t%1,%0\"; return \"\"; }") (define_insn "truncdihi2" [(set (match_operand:HI 0 "general_operand" "=r,m,r") (truncate:HI (match_operand:DI 1 "general_operand" "m,r,0")))] "" "* { if (which_alternative == 0) return \"ld.16\\t%0,%1\"; if (which_alternative == 1) return \"st.16\\t%1,%0\"; return \"\"; }") (define_insn "truncdisi2" [(set (match_operand:SI 0 "general_operand" "=r,m") (truncate:SI (match_operand:DI 1 "general_operand" "rm,r")))] "" "* { if (which_alternative == 0) return \"ld.32\\t%0,%1\"; return \"st.32\\t%1,%0\"; }") (define_insn "truncsiqi2" [(set (match_operand:QI 0 "general_operand" "=r,m,r") (truncate:QI (match_operand:SI 1 "general_operand" "m,r,0")))] "" "* { if (which_alternative == 0) return \"ld.8\\t%0,%1\"; if (which_alternative == 1) return \"st.8\\t%1,%0\"; return \"\"; }") (define_insn "truncsihi2" [(set (match_operand:HI 0 "general_operand" "=r,m,r") (truncate:HI (match_operand:SI 1 "general_operand" "m,r,0")))] "" "* { if (which_alternative == 0) return \"ld.16\\t%0,%1\"; if (which_alternative == 1) return \"st.16\\t%1,%0\"; return \"\"; }") (define_insn "trunchiqi2" [(set (match_operand:QI 0 "general_operand" "=r,m,r") (truncate:QI (match_operand:HI 1 "general_operand" "m,r,0")))] "" "* { if (which_alternative == 0) return \"ld.8\\t%0,%1\"; if (which_alternative == 1) return \"st.8\\t%1,%0\"; return \"\"; }") (define_insn "extendsfdf2" [(set (match_operand:DF 0 "register_operand" "=r") (sign_extend:DF (match_operand:SF 1 "general_operand" "rm")))] "" "cvt.sd\\t%0,%1") (define_insn "extendsidi2" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (match_operand:SI 1 "general_operand" "rm")))] "" "ld.32\\t%0,%1") (define_insn "extendhisi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (sign_extend:SI (match_operand:HI 1 "general_operand" "m,r")))] "" "* if (which_alternative==0) return \"ld.16\\t%0,%1\"; return \"extract\\t%0,%1:bit 48,16\"; ") (define_insn "extendhidi2" [(set (match_operand:DI 0 "register_operand" "=r,r") (sign_extend:DI (match_operand:HI 1 "general_operand" "m,r")))] "" "* if (which_alternative==0) return \"ld.16\\t%0,%1\"; return \"extract\\t%0,%1:bit 48,16\"; ") (define_insn "extendqihi2" [(set (match_operand:HI 0 "register_operand" "=r,r") (sign_extend:HI (match_operand:QI 1 "general_operand" "m,r")))] "" "* if (which_alternative==0) return \"ld.8\\t%0,%1\"; return \"extract\\t%0,%1:bit 56,8\"; ") (define_insn "extendqisi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (sign_extend:SI (match_operand:QI 1 "general_operand" "m,r")))] "" "* if (which_alternative==0) return \"ld.8\\t%0,%1\"; return \"extract\\t%0,%1:bit 56,8\"; ") (define_insn "extendqidi2" [(set (match_operand:DI 0 "register_operand" "=r,r") (sign_extend:DI (match_operand:QI 1 "general_operand" "m,r")))] "" "* if (which_alternative==0) return \"ld.8\\t%0,%1\"; return \"extract\\t%0,%1:bit 56,8\"; ") (define_insn "zero_extendsidi2" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))] "" "ldz.32\\t%0,%1") (define_insn "zero_extendhisi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (zero_extend:SI (match_operand:HI 1 "general_operand" "m,r")))] "" "* if (which_alternative==0) return \"ldz.16\\t%0,%1\"; return \"extractz\\t%0,%1:bit 48,16\"; ") (define_insn "zero_extendhidi2" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (match_operand:HI 1 "general_operand" "m,r")))] "" "* if (which_alternative==0) return \"ldz.16\\t%0,%1\"; return \"extractz\\t%0,%1:bit 48,16\"; ") (define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "=r,r") (zero_extend:HI (match_operand:QI 1 "general_operand" "m,r")))] "" "* if (which_alternative==0) return \"ldz.8\\t%0,%1\"; return \"extractz\\t%0,%1:bit 56,8\"; ") (define_insn "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (zero_extend:SI (match_operand:QI 1 "general_operand" "m,r")))] "" "* if (which_alternative==0) return \"ldz.8\\t%0,%1\"; return \"extractz\\t%0,%1:bit 56,8\"; ") (define_insn "zero_extendqidi2" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (match_operand:QI 1 "general_operand" "m,r")))] "" "* if (which_alternative==0) return \"ldz.8\\t%0,%1\"; return \"extractz\\t%0,%1:bit 56,8\"; ") (define_insn "lshldi3" [(set (match_operand:DI 0 "register_operand" "=r") (lshift:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "general_operand" "rn")))] "" "sll\\t%0,%1,%2") (define_insn "ashrdi3" [(set (match_operand:DI 0 "register_operand" "=r") (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "general_operand" "rn")))] "" "sra\\t%0,%1,%2") (define_insn "lshrdi3" [(set (match_operand:DI 0 "register_operand" "=r") (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "general_operand" "rn")))] "" "srl\\t%0,%1,%2") (define_insn "ashldi3" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "general_operand" "rn")))] "" "sla\\t%0,%1,%2") (define_insn "anddi3" [(set (match_operand:DI 0 "register_operand" "=r,r") (and:DI (match_operand:DI 1 "general_operand" "%0,r") (match_operand:DI 2 "general_operand" "g,g")))] "1 /*which_alternative == 0 || check356(operands[2])*/" "* if (which_alternative == 0) return \"and\\t%0,%2\"; return \"and\\t%0,%1,%2\"; ") (define_insn "iordi3" [(set (match_operand:DI 0 "register_operand" "=r,r") (ior:DI (match_operand:DI 1 "general_operand" "%0,r") (match_operand:DI 2 "general_operand" "g,g")))] "1 /*which_alternative == 0 || check356(operands[2])*/" "* if (which_alternative == 0) return \"or\\t%0,%2\"; return \"or\\t%0,%1,%2\"; ") (define_insn "xordi3" [(set (match_operand:DI 0 "register_operand" "=r,r") (xor:DI (match_operand:DI 1 "general_operand" "%0,r") (match_operand:DI 2 "general_operand" "g,g")))] "1 /*which_alternative == 0 || check356(operands[2])*/" "* if (which_alternative == 0) return \"xor\\t%0,%2\"; return \"xor\\t%0,%1,%2\"; ") (define_insn "one_cmpldi2" [(set (match_operand:DI 0 "register_operand" "=r") (not:DI (match_operand:DI 1 "general_operand" "rm")))] "" "not\\t%0,%1") ;; gcc 2.1 does not widen ~si into ~di. (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "=r") (not:DI (match_operand:SI 1 "register_operand" "r")))] "" "not\\t%0,%1") (define_insn "negdi2" [(set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_operand:DI 1 "general_operand" "rm")))] "" "neg.64\\t%0,%1") (define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (neg:SI (match_operand:SI 1 "general_operand" "m,r")))] "" "* if (which_alternative == 0) return \"neg.32\\t%0,%1\"; return \"neg.64\\t%0,%1 ; I only want 32\"; ") (define_insn "neghi2" [(set (match_operand:HI 0 "register_operand" "=r,r") (neg:HI (match_operand:HI 1 "general_operand" "m,r")))] "" "* if (which_alternative == 0) return \"neg.16\\t%0,%1\"; return \"neg.64\\t%0,%1 ; I only want 16\"; ") (define_insn "adddf3" [(set (match_operand:DF 0 "register_operand" "=r") (plus:DF (match_operand:DF 1 "general_operand" "%0") (match_operand:DF 2 "general_operand" "rm")))] "" "fadd.64\\t%0,%2") (define_insn "addsf3" [(set (match_operand:SF 0 "register_operand" "=r") (plus:SF (match_operand:SF 1 "general_operand" "%0") (match_operand:SF 2 "general_operand" "rm")))] "" "fadd.32\\t%0,%2") ;; There is also an addi.64 4,.r0'' optimization (define_insn "adddi3" [(set (match_operand:DI 0 "register_operand" "=r,r") (plus:DI (match_operand:DI 1 "general_operand" "%0,r") (match_operand:DI 2 "general_operand" "g,g")))] "1 /*which_alternative == 0 || check356(operands[2])*/" "* if (which_alternative == 0) return \"add.64\\t%0,%2\"; return \"add.64\\t%0,%1,%2\"; ") (define_insn "addsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (plus:SI (match_operand:SI 1 "general_operand" "%0,r,0") (match_operand:SI 2 "general_operand" "m,m,g")))] "1 /*which_alternative != 1 || check356(operands[2])*/" "* if (which_alternative == 0) return \"add.32\\t%0,%2\"; if (which_alternative == 1) return \"add.32\\t%0,%1,%2\"; return \"add.64\\t%0,%2 ; I only want 32\"; ") (define_insn "addhi3" [(set (match_operand:HI 0 "register_operand" "=r,r,r") (plus:HI (match_operand:HI 1 "general_operand" "%0,r,0") (match_operand:HI 2 "general_operand" "m,m,g")))] "1 /*which_alternative != 1 || check356(operands[2])*/" "* if (which_alternative == 0) return \"add.16\\t%0,%2\"; if (which_alternative == 1) return \"add.16\\t%0,%1,%2\"; return \"add.64\\t%0,%2 ; I only want 16\"; ") (define_insn "subdf3" [(set (match_operand:DF 0 "register_operand" "=r") (minus:DF (match_operand:DF 1 "general_operand" "0") (match_operand:DF 2 "general_operand" "rm")))] "" "fsub.64\\t%0,%2") (define_insn "subsf3" [(set (match_operand:SF 0 "register_operand" "=r") (minus:SF (match_operand:SF 1 "general_operand" "0") (match_operand:SF 2 "general_operand" "rm")))] "" "fsub.32\\t%0,%2") (define_insn "subdi3" [(set (match_operand:DI 0 "register_operand" "=r,r,r") (minus:DI (match_operand:DI 1 "general_operand" "0,g,r") (match_operand:DI 2 "general_operand" "g,r,g")))] "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" "* if (which_alternative == 0) return \"sub.64\\t%0,%2\"; else if (which_alternative == 1) return \"subr.64\\t%0,%2,%1\"; else return \"sub.64\\t%0,%1,%2\"; ") (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (minus:SI (match_operand:SI 1 "general_operand" "0,m,r,0") (match_operand:SI 2 "general_operand" "m,r,m,g")))] "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" "* if (which_alternative == 0) return \"sub.32\\t%0,%2\"; else if (which_alternative == 1) return \"subr.32\\t%0,%2,%1\"; else if (which_alternative == 2) return \"sub.32\\t%0,%1,%2\"; else return \"sub.64\\t%0,%2 ; I only want 32\"; ") (define_insn "subhi3" [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") (minus:HI (match_operand:HI 1 "general_operand" "0,m,r,0") (match_operand:HI 2 "general_operand" "m,r,m,g")))] "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" "* if (which_alternative == 0) return \"sub.16\\t%0,%2\"; else if (which_alternative == 1) return \"subr.16\\t%0,%2,%1\"; else if (which_alternative == 2) return \"sub.16\\t%0,%1,%2\"; else return \"sub.64\\t%0,%2 ; I only want 16\"; ") (define_insn "muldf3" [(set (match_operand:DF 0 "register_operand" "=r") (mult:DF (match_operand:DF 1 "general_operand" "%0") (match_operand:DF 2 "general_operand" "rm")))] "" "fmul.64\\t%0,%2") (define_insn "mulsf3" [(set (match_operand:SF 0 "register_operand" "=r") (mult:SF (match_operand:SF 1 "general_operand" "%0") (match_operand:SF 2 "general_operand" "rm")))] "" "fmul.32\\t%0,%2") (define_insn "muldi3" [(set (match_operand:DI 0 "register_operand" "=r,r") (mult:DI (match_operand:DI 1 "general_operand" "%0,r") (match_operand:DI 2 "general_operand" "g,g")))] "1 /*which_alternative == 0 || check356(operands[2])*/" "* if (which_alternative == 0) return \"mul.64\\t%0,%2\"; return \"mul.64\\t%0,%1,%2\"; ") (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (mult:SI (match_operand:SI 1 "general_operand" "%0,r,0") (match_operand:SI 2 "general_operand" "m,m,g")))] "1 /*which_alternative == 0 || check356(operands[2])*/" "* if (which_alternative == 0) return \"mul.32\\t%0,%2\"; else if (which_alternative == 1) return \"mul.32\\t%0,%1,%2\"; else return \"mul.64\\t%0,%2 ; I only want 32\"; ") (define_insn "mulhi3" [(set (match_operand:HI 0 "register_operand" "=r,r,r") (mult:HI (match_operand:HI 1 "general_operand" "%0,r,0") (match_operand:HI 2 "general_operand" "m,m,g")))] "1 /*which_alternative == 0 || check356(operands[2])*/" "* if (which_alternative == 0) return \"mul.16\\t%0,%2\"; else if (which_alternative == 1) return \"mul.16\\t%0,%1,%2\"; else return \"mul.64\\t%0,%2 ; I only want 16\"; ") (define_insn "divdf3" [(set (match_operand:DF 0 "register_operand" "=r") (div:DF (match_operand:DF 1 "general_operand" "0") (match_operand:DF 2 "general_operand" "rm")))] "" "fdiv.64\\t%0,%2") (define_insn "divsf3" [(set (match_operand:SF 0 "register_operand" "=r") (div:SF (match_operand:SF 1 "general_operand" "0") (match_operand:SF 2 "general_operand" "rm")))] "" "fdiv.32\\t%0,%2") (define_insn "divdi3" [(set (match_operand:DI 0 "register_operand" "=r,r,r") (div:DI (match_operand:DI 1 "general_operand" "0,g,r") (match_operand:DI 2 "general_operand" "g,r,g")))] "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" "* if (which_alternative == 0) return \"div.64\\t%0,%2\"; else if (which_alternative == 1) return \"divr.64\\t%0,%2,%1\"; else return \"div.64\\t%0,%1,%2\"; ") (define_insn "divsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (div:SI (match_operand:SI 1 "general_operand" "0,m,r,0") (match_operand:SI 2 "general_operand" "m,r,m,g")))] "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" "* /* We don't ignore high bits. */ if (0) { if (which_alternative == 0) return \"div.32\\t%0,%2\"; else if (which_alternative == 1) return \"divr.32\\t%0,%2,%1\"; else if (which_alternative == 2) return \"div.32\\t%0,%1,%2\"; else return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\"; } else { if (which_alternative == 0) return \"ld.32\\t%0,%0\;div.32\\t%0,%2\"; else if (which_alternative == 1) return \"ld.32\\t%2,%2\;divr.32\\t%0,%2,%1\"; else if (which_alternative == 2) return \"ld.32\\t%1,%1\;div.32\\t%0,%1,%2\"; else return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\"; } ") (define_insn "divhi3" [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") (div:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0") (match_operand:HI 2 "general_operand" "m,r,m,r,i")))] "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" "* if (which_alternative == 0) return \"extract\\t%0,%0:bit 48,16\;div.16\\t%0,%2\"; else if (which_alternative == 1) return \"extract\\t%2,%2:bit 48,16\;divr.16\\t%0,%2,%1\"; else if (which_alternative == 2) return \"extract\\t%1,%1:bit 48,16\;div.16\\t%0,%1,%2\"; else if (which_alternative == 3) return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;div.64\\t%0,%2 ; I only want 16\"; else return \"extract\\t%0,%0:bit 48,16\;div.64\\t%0,%2 ; I only want 16\"; ") (define_insn "modhi3" [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") (mod:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0") (match_operand:HI 2 "general_operand" "m,r,m,r,i")))] "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" "* if (which_alternative == 0) return \"extract\\t%0,%0:bit 48,16\;rem.16\\t%0,%2\"; else if (which_alternative == 1) return \"extract\\t%2,%2:bit 48,16\;remr.16\\t%0,%2,%1\"; else if (which_alternative == 2) return \"extract\\t%1,%1:bit 48,16\;rem.16\\t%0,%1,%2\"; else if (which_alternative == 3) return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\"; else return \"extract\\t%0,%0:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\"; ") (define_insn "moddi3" [(set (match_operand:DI 0 "register_operand" "=r,r,r") (mod:DI (match_operand:DI 1 "general_operand" "0,g,r") (match_operand:DI 2 "general_operand" "g,r,g")))] "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" "* if (which_alternative == 0) return \"rem.64\\t%0,%2\"; else if (which_alternative == 1) return \"remr.64\\t%0,%2,%1\"; else return \"rem.64\\t%0,%1,%2\"; ") (define_insn "modsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (mod:SI (match_operand:SI 1 "general_operand" "0,m,r,0") (match_operand:SI 2 "general_operand" "m,r,m,g")))] "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" "* /* There is a micro code bug with the below... */ if (0) { if (which_alternative == 0) return \"rem.32\\t%0,%2\"; else if (which_alternative == 1) return \"remr.32\\t%0,%2,%1\"; else if (which_alternative == 2) return \"rem.32\\t%0,%1,%2\"; else return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\"; } else { if (which_alternative == 0) return \"ld.32\\t%0,%0\;rem.32\\t%0,%2\"; else if (which_alternative == 1) return \"ld.32\\t%2,%2\;remr.32\\t%0,%2,%1\"; else if (which_alternative == 2) return \"ld.32\\t%1,%1\;rem.32\\t%0,%1,%2\"; else return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\"; } ") (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "jmp\\t%l0") (define_insn "indirect_jump" [(set (pc) (match_operand:SI 0 "register_operand" "r"))] "" ;; Maybe %l0 is better, maybe we can relax register only. "verify this before use ld.32\\t.r0,%0\;br.reg\\t.r0") (define_insn "beq" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return cmp_jmp(\"\", 2, operands[0]); ") (define_insn "bne" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return cmp_jmp(\"\", 8, operands[0]); ") (define_insn "bgt" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return cmp_jmp(\"\", 0, operands[0]); ") (define_insn "bgtu" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return cmp_jmp(\"u\", 0, operands[0]); ") (define_insn "blt" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return cmp_jmp(\"\", 6, operands[0]); ") (define_insn "bltu" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return cmp_jmp(\"u\", 6, operands[0]); ") (define_insn "bge" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return cmp_jmp(\"\", 4, operands[0]); ") (define_insn "bgeu" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return cmp_jmp(\"u\", 4, operands[0]); ") (define_insn "ble" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return cmp_jmp(\"\", 10, operands[0]); ") (define_insn "bleu" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return cmp_jmp(\"u\", 10, operands[0]); ") (define_insn "" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return cmp_jmp(\"\", 8, operands[0]); ") (define_insn "" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return cmp_jmp(\"\", 2, operands[0]); ") (define_insn "" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return cmp_jmp(\"\", 10, operands[0]); ") (define_insn "" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return cmp_jmp(\"u\", 10, operands[0]); ") (define_insn "" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return cmp_jmp(\"\", 4, operands[0]); ") (define_insn "" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return cmp_jmp(\"u\", 4, operands[0]); ") (define_insn "" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return cmp_jmp(\"\", 6, operands[0]); ") (define_insn "" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return cmp_jmp(\"u\", 6, operands[0]); ") (define_insn "" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return cmp_jmp(\"\", 0, operands[0]); ") (define_insn "" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return cmp_jmp(\"u\", 0, operands[0]); ") ;; Note that operand 1 is total size of args, in bytes, ;; and what the call insn wants is the number of words. (define_insn "call" [(call (match_operand:QI 0 "general_operand" "m") (match_operand:QI 1 "general_operand" "g"))] "" "* if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == REG) if (REGNO (XEXP (operands[0], 0)) != 0) return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\"; else return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\"; else return \"add.64\\t.sp,=-4\;call\\t%0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\"; ") (define_insn "call_value" [(set (match_operand 0 "" "g") (call (match_operand:QI 1 "general_operand" "m") (match_operand:QI 2 "general_operand" "g")))] "" "* if (GET_CODE (operands[1]) == MEM && GET_CODE (XEXP (operands[1], 0)) == REG) if (REGNO (XEXP (operands[1], 0)) != 0) return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\"; else return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\"; else return \"add.64\\t.sp,=-4\;call\\t%1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\"; ") (define_insn "tablejump" [(set (pc) (match_operand:SI 0 "register_operand" "r")) (use (label_ref (match_operand 1 "" "")))] "" "br.reg\\t%0") (define_insn "nop" [(const_int 0)] "" "nop") gcc-2.5.8/config/elxsi/x-elxsi100444 22011 13 367 5305304012 14646 0ustar kenneruser# Our make needs a little help... MAKE=make # We don't support -g yet, so don't try and use it. CFLAGS = LIBGCC2_CFLAGS = -O2 $(GCC_CFLAGS) # Hide xmalloc so that it does not conflict with the one in libc.a, Ick! X_CFLAGS = -Dxmalloc=my_xmalloc gcc-2.5.8/config/elxsi/xm-elxsi.h100444 22011 13 2352 5413066775 15312 0ustar kenneruser/* Configuration for GNU C-compiler for Elxsi. Copyright (C) 1987, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 1, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* #defines that need visibility everywhere. */ #define FALSE 0 #define TRUE 1 /* target machine dependencies. tm.h is a symbolic link to the actual target specific file. */ #include "tm.h" /* This describes the machine the compiler is hosted on. */ #define HOST_BITS_PER_CHAR 8 #define HOST_BITS_PER_SHORT 16 #define HOST_BITS_PER_INT 32 #define HOST_BITS_PER_LONG 32 /* Arguments to use with `exit'. */ #define SUCCESS_EXIT_CODE 0 #define FATAL_EXIT_CODE 33 gcc-2.5.8/config/fx80/ 40777 22011 13 0 5502602740 12726 5ustar kennerusergcc-2.5.8/config/fx80/fx80.c100444 22011 13 21244 5235132013 13763 0ustar kenneruser/* Subroutines for insn-output.c for Alliant FX computers. Copyright (C) 1989,1991 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Some output-actions in alliant.md need these. */ #include #include "config.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "output.h" #include "insn-attr.h" /* Index into this array by (register number >> 3) to find the smallest class which contains that register. */ enum reg_class regno_reg_class[] = { DATA_REGS, ADDR_REGS, FP_REGS }; static rtx find_addr_reg (); char * output_btst (operands, countop, dataop, insn, signpos) rtx *operands; rtx countop, dataop; rtx insn; int signpos; { operands[0] = countop; operands[1] = dataop; if (GET_CODE (countop) == CONST_INT) { register int count = INTVAL (countop); /* If COUNT is bigger than size of storage unit in use, advance to the containing unit of same size. */ if (count > signpos) { int offset = (count & ~signpos) / 8; count = count & signpos; operands[1] = dataop = adj_offsettable_operand (dataop, offset); } if (count == signpos) cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N; else cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N; /* These three statements used to use next_insns_test_no... but it appears that this should do the same job. */ if (count == 31 && next_insn_tests_no_inequality (insn)) return "tst%.l %1"; if (count == 15 && next_insn_tests_no_inequality (insn)) return "tst%.w %1"; if (count == 7 && next_insn_tests_no_inequality (insn)) return "tst%.b %1"; cc_status.flags = CC_NOT_NEGATIVE; } return "btst %0,%1"; } /* Return the best assembler insn template for moving operands[1] into operands[0] as a fullword. */ static char * singlemove_string (operands) rtx *operands; { if (operands[1] != const0_rtx) return "mov%.l %1,%0"; if (! ADDRESS_REG_P (operands[0])) return "clr%.l %0"; return "sub%.l %0,%0"; } /* Output assembler code to perform a doubleword move insn with operands OPERANDS. */ char * output_move_double (operands) rtx *operands; { enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1; rtx latehalf[2]; rtx addreg0 = 0, addreg1 = 0; /* First classify both operands. */ if (REG_P (operands[0])) optype0 = REGOP; else if (offsettable_memref_p (operands[0])) optype0 = OFFSOP; else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) optype0 = POPOP; else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) optype0 = PUSHOP; else if (GET_CODE (operands[0]) == MEM) optype0 = MEMOP; else optype0 = RNDOP; if (REG_P (operands[1])) optype1 = REGOP; else if (CONSTANT_P (operands[1])) optype1 = CNSTOP; else if (offsettable_memref_p (operands[1])) optype1 = OFFSOP; else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) optype1 = POPOP; else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) optype1 = PUSHOP; else if (GET_CODE (operands[1]) == MEM) optype1 = MEMOP; else optype1 = RNDOP; /* Check for the cases that the operand constraints are not supposed to allow to happen. Abort if we get one, because generating code for these cases is painful. */ if (optype0 == RNDOP || optype1 == RNDOP) abort (); /* If one operand is decrementing and one is incrementing decrement the former register explicitly and change that operand into ordinary indexing. */ if (optype0 == PUSHOP && optype1 == POPOP) { operands[0] = XEXP (XEXP (operands[0], 0), 0); output_asm_insn ("subq%.l %#8,%0", operands); operands[0] = gen_rtx (MEM, DImode, operands[0]); optype0 = OFFSOP; } if (optype0 == POPOP && optype1 == PUSHOP) { operands[1] = XEXP (XEXP (operands[1], 0), 0); output_asm_insn ("subq%.l %#8,%1", operands); operands[1] = gen_rtx (MEM, DImode, operands[1]); optype1 = OFFSOP; } /* If an operand is an unoffsettable memory ref, find a register we can increment temporarily to make it refer to the second word. */ if (optype0 == MEMOP) addreg0 = find_addr_reg (XEXP (operands[0], 0)); if (optype1 == MEMOP) addreg1 = find_addr_reg (XEXP (operands[1], 0)); /* Ok, we can do one word at a time. Normally we do the low-numbered word first, but if either operand is autodecrementing then we do the high-numbered word first. In either case, set up in LATEHALF the operands to use for the high-numbered word and in some cases alter the operands in OPERANDS to be suitable for the low-numbered word. */ if (optype0 == REGOP) latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); else if (optype0 == OFFSOP) latehalf[0] = adj_offsettable_operand (operands[0], 4); else latehalf[0] = operands[0]; if (optype1 == REGOP) latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); else if (optype1 == OFFSOP) latehalf[1] = adj_offsettable_operand (operands[1], 4); else if (optype1 == CNSTOP) { if (GET_CODE (operands[1]) == CONST_DOUBLE) split_double (operands[1], &operands[1], &latehalf[1]); else if (CONSTANT_P (operands[1])) { latehalf[1] = operands[1]; operands[1] = const0_rtx; } } else latehalf[1] = operands[1]; /* If insn is effectively movd N(sp),-(sp) then we will do the high word first. We should use the adjusted operand 1 (which is N+4(sp)) for the low word as well, to compensate for the first decrement of sp. */ if (optype0 == PUSHOP && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) operands[1] = latehalf[1]; /* If one or both operands autodecrementing, do the two words, high-numbered first. */ /* Likewise, the first move would clobber the source of the second one, do them in the other order. This happens only for registers; such overlap can't happen in memory unless the user explicitly sets it up, and that is an undefined circumstance. */ if (optype0 == PUSHOP || optype1 == PUSHOP || (optype0 == REGOP && optype1 == REGOP && REGNO (operands[0]) == REGNO (latehalf[1]))) { /* Make any unoffsettable addresses point at high-numbered word. */ if (addreg0) output_asm_insn ("addql %#4,%0", &addreg0); if (addreg1) output_asm_insn ("addql %#4,%0", &addreg1); /* Do that word. */ output_asm_insn (singlemove_string (latehalf), latehalf); /* Undo the adds we just did. */ if (addreg0) output_asm_insn ("subql %#4,%0", &addreg0); if (addreg1) output_asm_insn ("subql %#4,%0", &addreg1); /* Do low-numbered word. */ return singlemove_string (operands); } /* Normal case: do the two words, low-numbered first. */ output_asm_insn (singlemove_string (operands), operands); /* Make any unoffsettable addresses point at high-numbered word. */ if (addreg0) output_asm_insn ("addql %#4,%0", &addreg0); if (addreg1) output_asm_insn ("addql %#4,%0", &addreg1); /* Do that word. */ output_asm_insn (singlemove_string (latehalf), latehalf); /* Undo the adds we just did. */ if (addreg0) output_asm_insn ("subql %#4,%0", &addreg0); if (addreg1) output_asm_insn ("subql %#4,%0", &addreg1); return ""; } /* Return a REG that occurs in ADDR with coefficient 1. ADDR can be effectively incremented by incrementing REG. */ static rtx find_addr_reg (addr) rtx addr; { while (GET_CODE (addr) == PLUS) { if (GET_CODE (XEXP (addr, 0)) == REG) addr = XEXP (addr, 0); else if (GET_CODE (XEXP (addr, 1)) == REG) addr = XEXP (addr, 1); else if (CONSTANT_P (XEXP (addr, 0))) addr = XEXP (addr, 1); else if (CONSTANT_P (XEXP (addr, 1))) addr = XEXP (addr, 0); else abort (); } if (GET_CODE (addr) == REG) return addr; abort (); } int standard_SunFPA_constant_p (x) rtx x; { return( 0 ); } gcc-2.5.8/config/fx80/fx80.h100444 22011 13 153415 5456242435 14035 0ustar kenneruser/* Definitions of target machine for GNU compiler. Alliant FX version. Copyright (C) 1989 Free Software Foundation, Inc. Adapted from m68k.h by Paul Petersen (petersen@uicsrd.csrd.uiuc.edu) and Joe Weening (weening@gang-of-four.stanford.edu). This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* This file is based on m68k.h, simplified by removing support for the Sun FPA and other things not applicable to the Alliant. Some remnants of these features remain. */ /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Dmc68000 -Dalliant -Dunix -Asystem(unix) -Acpu(m68k) -Amachine(m68k)" /* Print subsidiary information on the compiler version in use. */ #define TARGET_VERSION fprintf (stderr, " (Alliant)"); /* Run-time compilation parameters selecting different hardware subsets. The Alliant IP is an mc68020. (Older mc68010-based IPs are no longer supported.) The Alliant CE is 68020-compatible, and also has floating point, vector and concurrency instructions. Although the IP doesn't have floating point, it emulates it in the operating system. Using this generally is faster than running code compiled with -msoft-float, because the soft-float code still uses (simulated) FP registers and ends up emulating several fmove{s,d} instructions per call. So I don't recommend using soft-float for any Alliant code. -- JSW */ extern int target_flags; /* Macros used in the machine description to test the flags. */ /* Compile for a 68020 (not a 68000 or 68010). */ #define TARGET_68020 (target_flags & 1) /* Compile CE insns for floating point (not library calls). */ #define TARGET_CE (target_flags & 2) /* Compile using 68020 bitfield insns. */ #define TARGET_BITFIELD (target_flags & 4) /* Compile with 16-bit `int'. */ #define TARGET_SHORT (target_flags & 040) /* Default 3 means compile 68020 and CE instructions. We don't use bitfield instructions because there appears to be a bug in the implementation of bfins on the CE. */ #define TARGET_DEFAULT 3 /* Define __HAVE_CE__ in preprocessor according to the -m flags. This will control the use of inline FP insns in certain macros. Also inform the program which CPU this is for. */ #if TARGET_DEFAULT & 02 /* -mce is the default */ #define CPP_SPEC \ "%{!msoft-float:-D__HAVE_CE__ }\ %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}" #else /* -msoft-float is the default */ #define CPP_SPEC \ "%{mce:-D__HAVE_CE__ }\ %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}" #endif /* Link with libg.a when debugging, for dbx's sake. */ #define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} " /* Make the linker remove temporary labels, since the Alliant assembler doesn't. */ #define LINK_SPEC "-X" /* Every structure or union's size must be a multiple of 2 bytes. */ #define STRUCTURE_SIZE_BOUNDARY 16 /* This is BSD, so it wants DBX format. */ #define DBX_DEBUGGING_INFO /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */ #define TARGET_SWITCHES \ { { "68020", 5}, \ { "c68020", 5}, \ { "bitfield", 4}, \ { "68000", -7}, \ { "c68000", -7}, \ { "soft-float", -2}, \ { "nobitfield", -4}, \ { "short", 040}, \ { "noshort", -040}, \ { "", TARGET_DEFAULT}} /* target machine storage layout */ /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. This is true for 68020 insns such as bfins and bfexts. We make it true always by avoiding using the single-bit insns except in special cases with constant bit numbers. */ #define BITS_BIG_ENDIAN 1 /* Define this if most significant byte of a word is the lowest numbered. */ /* That is true on the 68000. */ #define BYTES_BIG_ENDIAN 1 /* Define this if most significant word of a multiword number is the lowest numbered. */ /* For 68000 we can decide arbitrarily since there are no machine instructions for them. */ #define WORDS_BIG_ENDIAN 0 /* number of bits in an addressable storage unit */ #define BITS_PER_UNIT 8 /* Width in bits of a "word", which is the contents of a machine register. Note that this is not necessarily the width of data type `int'; if using 16-bit ints on a 68000, this would still be 32. But on a machine with 16-bit registers, this would be 16. */ #define BITS_PER_WORD 32 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 4 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ #define POINTER_SIZE 32 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) /* Boundary (in *bits*) on which stack pointer should be aligned. */ #define STACK_BOUNDARY 16 /* Allocation boundary (in *bits*) for the code of a function. */ #define FUNCTION_BOUNDARY 16 /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 16 /* No data type wants to be aligned rounder than this. */ #define BIGGEST_ALIGNMENT 16 /* Set this non-zero if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 1 /* Define number of bits in most basic integer type. (If undefined, default is BITS_PER_WORD). */ #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) /* Define these to avoid dependence on meaning of `int'. Note that WCHAR_TYPE_SIZE is used in cexp.y, where TARGET_SHORT is not available. */ #define WCHAR_TYPE "long int" #define WCHAR_TYPE_SIZE 32 /* Standard register usage. */ /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. For the Alliant, we give the data registers numbers 0-7, the address registers numbers 010-017, and the floating point registers numbers 020-027. */ #define FIRST_PSEUDO_REGISTER 24 /* 1 for registers that have pervasive standard uses and are not available for the register allocator. On the Alliant, these are a0 (argument pointer), a6 (frame pointer) and a7 (stack pointer). */ #define FIXED_REGISTERS \ {0, 0, 0, 0, 0, 0, 0, 0, \ 1, 0, 0, 0, 0, 0, 1, 1, \ 0, 0, 0, 0, 0, 0, 0, 0 } /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. The Alliant calling sequence allows a function to use any register, so we include them all here. */ #define CALL_USED_REGISTERS \ {1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1 } /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. On the Alliant, ordinary registers hold 32 bits worth; for the FP registers, a single register is always enough for any floating-point value. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On the Alliant, the cpu registers can hold any mode but the FP registers can hold only floating point. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ((REGNO) < 16 || GET_MODE_CLASS (MODE) == MODE_FLOAT \ || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. */ #define MODES_TIEABLE_P(MODE1, MODE2) \ (((MODE1) == SFmode || (MODE1) == DFmode \ || (MODE1) == SCmode || (MODE1) == DCmode) \ == ((MODE2) == SFmode || (MODE2) == DFmode \ || (MODE2) == SCmode || (MODE2) == DCmode)) /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ /* m68000 pc isn't overloaded on a register. */ /* #define PC_REGNUM */ /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM 15 /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM 14 /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */ /* Set for now on Alliant until we find a way to make this work with their calling sequence. */ #define FRAME_POINTER_REQUIRED 1 /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM 8 /* Register in which static-chain is passed to a function. */ #define STATIC_CHAIN_REGNUM 10 /* Register in which address to store a structure value is passed to a function. */ #define STRUCT_VALUE_REGNUM 9 /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. One of the classes must always be named ALL_REGS and include all hard regs. If there is more than one class, another class must be named NO_REGS and contain no registers. The name GENERAL_REGS must be the name of a class (or an alias for another name such as ALL_REGS). This is the class of registers that is allowed by "g" or "r" in a register constraint. Also, registers outside this class are allocated only when instructions express preferences for them. The classes must be numbered in nondecreasing order; that is, a larger-numbered class must never be contained completely in a smaller-numbered class. For any two classes, it is very desirable that there be another class that represents their union. */ /* The Alliant has three kinds of registers, so eight classes would be a complete set. One of them is not needed. */ enum reg_class { NO_REGS, FP_REGS, DATA_REGS, DATA_OR_FP_REGS, ADDR_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ { "NO_REGS", "FP_REGS", "DATA_REGS", "DATA_OR_FP_REGS", \ "ADDR_REGS", "GENERAL_REGS", "ALL_REGS" } /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS \ { \ 0, /* NO_REGS */ \ 0x00ff0000, /* FP_REGS */ \ 0x000000ff, /* DATA_REGS */ \ 0x00ff00ff, /* DATA_OR_FP_REGS */ \ 0x0000ff00, /* ADDR_REGS */ \ 0x0000ffff, /* GENERAL_REGS */ \ 0x00ffffff /* ALL_REGS */ \ } /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ extern enum reg_class regno_reg_class[]; #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3]) /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS GENERAL_REGS #define BASE_REG_CLASS ADDR_REGS /* Get reg_class from a letter such as appears in the machine description. */ #define REG_CLASS_FROM_LETTER(C) \ ((C) == 'a' ? ADDR_REGS : \ ((C) == 'd' ? DATA_REGS : \ ((C) == 'f' ? FP_REGS : \ NO_REGS))) /* The letters I, J, K, L and M in a register constraint string can be used to stand for particular ranges of immediate operands. This macro defines what the ranges are. C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. For the 68000, `I' is used for the range 1 to 8 allowed as immediate shift counts and in addq. `J' is used for the range of signed numbers that fit in 16 bits. `K' is for numbers that moveq can't handle. `L' is for range -8 to -1, range of values that can be added with subq. */ #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \ (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \ (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \ (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : 0) #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0 /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. On the 68000 series, use a data reg if possible when the value is a constant in the range where moveq could be used and we ensure that QImodes are reloaded into data regs. */ #define PREFERRED_RELOAD_CLASS(X,CLASS) \ ((GET_CODE (X) == CONST_INT \ && (unsigned) (INTVAL (X) + 0x80) < 0x100 \ && (CLASS) != ADDR_REGS) \ ? DATA_REGS \ : GET_MODE (X) == QImode \ ? DATA_REGS \ : (CLASS)) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ /* On the 68000, this is the size of MODE in words, except in the FP regs, where a single reg is always enough. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ ((CLASS) == FP_REGS ? 1 \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Moves between fp regs and other regs are two insns. */ #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS)) \ ? 4 : 2) /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack makes the stack pointer a smaller address. */ #define STACK_GROWS_DOWNWARD /* Define this if the nominal address of the stack frame is at the high-address end of the local variables; that is, each additional local variable allocated goes at a more negative offset in the frame. */ #define FRAME_GROWS_DOWNWARD /* The Alliant uses -fcaller-saves by default. */ #define DEFAULT_CALLER_SAVES /* Offset within stack frame to start allocating local variables at. If FRAME_GROWS_DOWNWARD, this is the offset to the END of the first local allocated. Otherwise, it is the offset to the BEGINNING of the first local allocated. */ #define STARTING_FRAME_OFFSET -4 /* If we generate an insn to push BYTES bytes, this says how many the stack pointer really advances by. On the 68000, sp@- in a byte insn really pushes a word. */ #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1) /* Offset of first parameter from the argument pointer register value. */ #define FIRST_PARM_OFFSET(FNDECL) 0 /* Value is the number of bytes of arguments automatically popped when returning from a subroutine call. FUNTYPE is the data type of the function (as a tree), or for a library call it is an identifier node for the subroutine name. SIZE is the number of bytes of arguments passed on the stack. On the Alliant we define this as SIZE and make the calling sequence (in alliant.md) pop the args. This wouldn't be necessary if we could add to the pending stack adjustment the size of the argument descriptors that are pushed after the arguments. */ #define RETURN_POPS_ARGS(FUNTYPE,SIZE) (SIZE) /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */ /* On the Alliant the return value is in FP0 if real, else D0. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ (TREE_CODE (VALTYPE) == REAL_TYPE \ ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \ : gen_rtx (REG, TYPE_MODE (VALTYPE), 0)) /* Define how to find the value returned by a library function assuming the value has mode MODE. */ /* On the Alliant the return value is in FP0 if real, else D0. The Alliant library functions for floating-point emulation return their values both in FP0 and in D0/D1. But since not all libgcc functions return the results of these directly, we cannot assume that D0/D1 contain the values we expect on return from a libgcc function. */ #define LIBCALL_VALUE(MODE) \ (((MODE) == DFmode || (MODE) == SFmode) \ ? gen_rtx (REG, MODE, 16) \ : gen_rtx (REG, MODE, 0)) /* 1 if N is a possible register number for a function value. On the Alliant, D0 and FP0 are the only registers thus used. (No need to mention D1 when used as a pair with D0.) */ #define FUNCTION_VALUE_REGNO_P(N) (((N) & ~16) == 0) /* Define this if PCC uses the nonreentrant convention for returning structure and union values. */ #define PCC_STATIC_STRUCT_RETURN /* 1 if N is a possible register number for function argument passing. On the Alliant, no registers are used in this way. */ #define FUNCTION_ARG_REGNO_P(N) 0 /* Define a data type for recording info about an argument list during the scan of that argument list. This data type should hold all necessary information about the function itself and about the args processed so far, enough to enable macros such as FUNCTION_ARG to determine where the next arg should go. On the Alliant, this is a single integer, which is a number of bytes of arguments scanned so far. */ #define CUMULATIVE_ARGS int /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. On the Alliant, the offset starts at 0. */ #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ ((CUM) = 0) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ ((CUM) += ((MODE) != BLKmode \ ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ : (int_size_in_bytes (TYPE) + 3) & ~3)) /* Define where to put the arguments to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. MODE is the argument's machine mode. TYPE is the data type of the argument (as a tree). This is null for libcalls where that information may not be available. CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called. NAMED is nonzero if this argument is a named parameter (otherwise it is an extra parameter matching an ellipsis). */ /* On the Alliant all args are pushed. */ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0 /* For an arg passed partly in registers and partly in memory, this is the number of registers used. For args passed entirely in registers or entirely in memory, zero. */ #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 /* This macro generates the assembly code for function entry. FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. Refer to the array `regs_ever_live' to determine which registers to save; `regs_ever_live[I]' is nonzero if register number I is ever used in the function. This macro is responsible for knowing which registers should not be saved even if used. The Alliant uses caller-saves, so this macro is very simple. */ #define FUNCTION_PROLOGUE(FILE, SIZE) \ { int fsize = ((SIZE) - STARTING_FRAME_OFFSET + 3) & -4; \ if (frame_pointer_needed) \ { \ if (fsize < 0x8000) \ fprintf(FILE,"\tlinkw a6,#%d\n", -fsize); \ else if (TARGET_68020) \ fprintf(FILE,"\tlinkl a6,#%d\n", -fsize); \ else \ fprintf(FILE,"\tlinkw a6,#0\n\tsubl #%d,sp\n", fsize); \ fprintf(FILE, "\tmovl a0,a6@(-4)\n" ); }} /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ #define FUNCTION_PROFILER(FILE, LABELNO) \ fprintf (FILE, "\tjbsr __mcount_\n") /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, the stack pointer does not matter. The value is tested only in functions that have frame pointers. No definition is equivalent to always zero. */ #define EXIT_IGNORE_STACK 1 /* This macro generates the assembly code for function exit, on machines that need it. If FUNCTION_EPILOGUE is not defined then individual return instructions are generated for each return statement. Args are same as for FUNCTION_PROLOGUE. The function epilogue should not depend on the current stack pointer! It should use the frame pointer only. This is mandatory because of alloca; we also take advantage of it to omit stack adjustments before returning. */ #define FUNCTION_EPILOGUE(FILE, SIZE) \ { if (frame_pointer_needed) \ fprintf (FILE, "\tunlk a6\n"); \ fprintf (FILE, "\trts\n"); } /* Store in the variable DEPTH the initial difference between the frame pointer reg contents and the stack pointer reg contents, as of the start of the function body. This depends on the layout of the fixed parts of the stack frame and on how registers are saved. */ #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ { \ int regno; \ int offset = -4; \ for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ offset += 12; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ offset += 4; \ (DEPTH) = offset - ((get_frame_size () + 3) & -4); \ } /* Addressing modes, and classification of registers for them. */ #define HAVE_POST_INCREMENT /* #define HAVE_POST_DECREMENT */ #define HAVE_PRE_DECREMENT /* #define HAVE_PRE_INCREMENT */ /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. */ #define REGNO_OK_FOR_INDEX_P(REGNO) \ ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) #define REGNO_OK_FOR_BASE_P(REGNO) \ (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) #define REGNO_OK_FOR_DATA_P(REGNO) \ ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) #define REGNO_OK_FOR_FP_P(REGNO) \ (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) /* Now macros that check whether X is a register and also, strictly, whether it is in a specified class. These macros are specific to the 68000, and may be used only in code for printing assembler insns and in conditions for define_optimization. */ /* 1 if X is a data register. */ #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) /* 1 if X is an fp register. */ #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) /* 1 if X is an address register */ #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) /* Maximum number of registers that can appear in a valid memory address. */ #define MAX_REGS_PER_ADDRESS 2 /* Recognize any constant value that is a valid address. */ #define CONSTANT_ADDRESS_P(X) \ (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ || GET_CODE (X) == HIGH) /* Nonzero if the constant value X is a legitimate general operand. It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ /* Alliant FP instructions don't take immediate operands, so this forces them into memory. */ #define LEGITIMATE_CONSTANT_P(X) (GET_CODE (X) != CONST_DOUBLE) /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. The usual definition accepts all pseudo regs; the other rejects them unless they have been allocated suitable hard regs. The symbol REG_OK_STRICT causes the latter definition to be used. Most source files want to accept pseudo regs in the hope that they will get allocated to the class that the insn wants them to be in. Source files for reload pass need to be strict. After reload, it makes no difference, since pseudo regs have been eliminated by then. */ #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) #else /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) #endif /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ #define INDIRECTABLE_1_ADDRESS_P(X) \ (CONSTANT_ADDRESS_P (X) \ || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ && REG_P (XEXP (X, 0)) \ && REG_OK_FOR_BASE_P (XEXP (X, 0))) \ || (GET_CODE (X) == PLUS \ && REG_P (XEXP (X, 0)) && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ && GET_CODE (XEXP (X, 1)) == CONST_INT \ && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; } #define GO_IF_INDEXABLE_BASE(X, ADDR) \ { if (GET_CODE (X) == LABEL_REF) goto ADDR; \ if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR; } #define GO_IF_INDEXING(X, ADDR) \ { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } #define GO_IF_INDEXED_ADDRESS(X, ADDR) \ { GO_IF_INDEXING (X, ADDR); \ if (GET_CODE (X) == PLUS) \ { if (GET_CODE (XEXP (X, 1)) == CONST_INT \ && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100) \ { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \ if (GET_CODE (XEXP (X, 0)) == CONST_INT \ && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100) \ { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } } #define LEGITIMATE_INDEX_REG_P(X) \ ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ || (GET_CODE (X) == SIGN_EXTEND \ && GET_CODE (XEXP (X, 0)) == REG \ && GET_MODE (XEXP (X, 0)) == HImode \ && REG_OK_FOR_INDEX_P (XEXP (X, 0)))) #define LEGITIMATE_INDEX_P(X) \ (LEGITIMATE_INDEX_REG_P (X) \ || (TARGET_68020 && GET_CODE (X) == MULT \ && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ && GET_CODE (XEXP (X, 1)) == CONST_INT \ && (INTVAL (XEXP (X, 1)) == 2 \ || INTVAL (XEXP (X, 1)) == 4 \ || INTVAL (XEXP (X, 1)) == 8))) #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ GO_IF_INDEXED_ADDRESS (X, ADDR); } /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. OLDX is the address as it was before break_out_memory_refs was called. In some cases it is useful to look at this to decide what needs to be done. MODE and WIN are passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. It is always safe for this macro to do nothing. It exists to recognize opportunities to optimize the output. For the 68000, we handle X+REG by loading X into a register R and using R+REG. R will go in an address reg and indexing will be used. However, if REG is a broken-out memory address or multiplication, nothing needs to be done because REG can certainly go in an address reg. */ #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ { register int ch = (X) != (OLDX); \ if (GET_CODE (X) == PLUS) \ { if (GET_CODE (XEXP (X, 0)) == MULT) \ ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0); \ if (GET_CODE (XEXP (X, 1)) == MULT) \ ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0); \ if (ch && GET_CODE (XEXP (X, 1)) == REG \ && GET_CODE (XEXP (X, 0)) == REG) \ goto WIN; \ if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ if (GET_CODE (XEXP (X, 0)) == REG \ || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \ && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \ { register rtx temp = gen_reg_rtx (Pmode); \ register rtx val = force_operand (XEXP (X, 1), 0); \ emit_move_insn (temp, val); \ XEXP (X, 1) = temp; \ goto WIN; } \ else if (GET_CODE (XEXP (X, 1)) == REG \ || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \ && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \ { register rtx temp = gen_reg_rtx (Pmode); \ register rtx val = force_operand (XEXP (X, 0), 0); \ emit_move_insn (temp, val); \ XEXP (X, 0) = temp; \ goto WIN; }}} /* Go to LABEL if ADDR (a legitimate address expression) has an effect that depends on the machine mode it is used for. On the 68000, only predecrement and postincrement address depend thus (the amount of decrement or increment being the length of the operand). */ #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE HImode /* Define this if the tablejump instruction expects the table to contain offsets from the address of the table. Do not define this if the table should contain absolute addresses. */ #define CASE_VECTOR_PC_RELATIVE /* Specify the tree operation to be used to convert reals to integers. */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR /* This is the kind of divide that is easiest to do in the general case. */ #define EASY_DIV_EXPR TRUNC_DIV_EXPR /* Define this as 1 if `char' should by default be signed; else as 0. */ #define DEFAULT_SIGNED_CHAR 1 /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ #define MOVE_MAX 4 /* Define this if zero-extension is slow (more than one real instruction). */ #define SLOW_ZERO_EXTEND /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS 0 /* Define this to be nonzero if shift instructions ignore all but the low-order few bits. */ #define SHIFT_COUNT_TRUNCATED 1 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 /* We assume that the store-condition-codes instructions store 0 for false and some other value for true. This is the value stored for true. */ #define STORE_FLAG_VALUE -1 /* When a prototype says `char' or `short', really pass an `int'. */ #define PROMOTE_PROTOTYPES /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ #define Pmode SImode /* A function address in a call instruction is a byte address (for indexing purposes) so give the MEM rtx a byte's mode. */ #define FUNCTION_MODE QImode /* Compute the cost of computing a constant rtl expression RTX whose rtx-code is CODE. The body of this macro is a portion of a switch statement. If the code is computed here, return it with a return statement. Otherwise, break from the switch. */ #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ /* Constant zero is super cheap due to clr instruction. */ \ if (RTX == const0_rtx) return 0; \ if ((unsigned) INTVAL (RTX) < 077) return 1; \ case CONST: \ case LABEL_REF: \ case SYMBOL_REF: \ return 3; \ case CONST_DOUBLE: \ return 5; /* Check a `double' value for validity for a particular machine mode. This is defined to avoid crashes outputting certain constants. */ #define CHECK_FLOAT_VALUE(mode, d) \ if ((mode) == SFmode) \ { \ if ((d) > 3.4028234663852890e+38) \ { warning ("magnitude of value too large for `float'"); \ (d) = 3.4028234663852890e+38; } \ else if ((d) < -3.4028234663852890e+38) \ { warning ("magnitude of value too large for `float'"); \ (d) = -3.4028234663852890e+38; } \ else if (((d) > 0) && ((d) < 1.1754943508222873e-38)) \ (d) = 0.0; \ else if (((d) < 0) && ((d) > -1.1754943508222873e-38)) \ (d) = 0.0; \ } /* Tell final.c how to eliminate redundant test instructions. */ /* Here we define machine-dependent flags and fields in cc_status (see `conditions.h'). */ /* On the Alliant, floating-point instructions do not modify the ordinary CC register. Only fcmp and ftest instructions modify the floating-point CC register. We should actually keep track of what both kinds of CC registers contain, but for now we only consider the most recent instruction that has set either register. */ /* Set if the cc value came from a floating point test, so a floating point conditional branch must be output. */ #define CC_IN_FP 04000 /* Store in cc_status the expressions that the condition codes will describe after execution of an instruction whose pattern is EXP. Do not alter them if the instruction would not alter the cc's. */ /* On the 68000, all the insns to store in an address register fail to set the cc's. However, in some cases these instructions can make it possibly invalid to use the saved cc's. In those cases we clear out some or all of the saved cc's so they won't be used. */ #define NOTICE_UPDATE_CC(EXP, INSN) \ { \ if (GET_CODE (EXP) == SET) \ { if (ADDRESS_REG_P (SET_DEST (EXP)) || FP_REG_P (SET_DEST (EXP))) \ { if (cc_status.value1 \ && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value1)) \ cc_status.value1 = 0; \ if (cc_status.value2 \ && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value2)) \ cc_status.value2 = 0; } \ else if (GET_CODE (SET_SRC (EXP)) == MOD \ || GET_CODE (SET_SRC (EXP)) == UMOD \ || (GET_CODE (SET_SRC (EXP)) == TRUNCATE \ && (GET_CODE (XEXP (SET_SRC (EXP))) == MOD \ || GET_CODE (XEXP (SET_SRC (EXP))) == UMOD))) \ /* The swap insn produces cc's that don't correspond to the \ result. */ \ CC_STATUS_INIT; \ else if (SET_DEST (EXP) != cc0_rtx \ && (FP_REG_P (SET_SRC (EXP)) \ || GET_CODE (SET_SRC (EXP)) == FIX \ || GET_CODE (SET_SRC (EXP)) == FLOAT_TRUNCATE \ || GET_CODE (SET_SRC (EXP)) == FLOAT_EXTEND)) \ { CC_STATUS_INIT; } \ /* A pair of move insns doesn't produce a useful overall cc. */ \ else if (!FP_REG_P (SET_DEST (EXP)) \ && !FP_REG_P (SET_SRC (EXP)) \ && GET_MODE_SIZE (GET_MODE (SET_SRC (EXP))) > 4 \ && (GET_CODE (SET_SRC (EXP)) == REG \ || GET_CODE (SET_SRC (EXP)) == MEM \ || GET_CODE (SET_SRC (EXP)) == CONST_DOUBLE))\ { CC_STATUS_INIT; } \ else if (GET_CODE (SET_SRC (EXP)) == CALL) \ { CC_STATUS_INIT; } \ else if (XEXP (EXP, 0) != pc_rtx) \ { cc_status.flags = 0; \ cc_status.value1 = XEXP (EXP, 0); \ cc_status.value2 = XEXP (EXP, 1); } } \ else if (GET_CODE (EXP) == PARALLEL \ && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \ { \ if (ADDRESS_REG_P (XEXP (XVECEXP (EXP, 0, 0), 0))) \ CC_STATUS_INIT; \ else if (XEXP (XVECEXP (EXP, 0, 0), 0) != pc_rtx) \ { cc_status.flags = 0; \ cc_status.value1 = XEXP (XVECEXP (EXP, 0, 0), 0); \ cc_status.value2 = XEXP (XVECEXP (EXP, 0, 0), 1); } } \ else CC_STATUS_INIT; \ if (cc_status.value2 != 0 \ && ADDRESS_REG_P (cc_status.value2) \ && GET_MODE (cc_status.value2) == QImode) \ CC_STATUS_INIT; \ if (cc_status.value2 != 0) \ switch (GET_CODE (cc_status.value2)) \ { case PLUS: case MINUS: case MULT: \ case DIV: case UDIV: case MOD: case UMOD: case NEG: \ case ASHIFT: case LSHIFT: case ASHIFTRT: case LSHIFTRT: \ case ROTATE: case ROTATERT: \ if (GET_MODE (cc_status.value2) != VOIDmode) \ cc_status.flags |= CC_NO_OVERFLOW; \ break; \ case ZERO_EXTEND: \ /* (SET r1 (ZERO_EXTEND r2)) on this machine ends with a move insn moving r2 in r2's mode. Thus, the cc's are set for r2. This can set N bit spuriously. */ \ cc_status.flags |= CC_NOT_NEGATIVE; } \ if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \ && cc_status.value2 \ && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \ cc_status.value2 = 0; \ if ((cc_status.value1 && FP_REG_P (cc_status.value1)) \ || (cc_status.value2 && FP_REG_P (cc_status.value2))) \ cc_status.flags = CC_IN_FP; } #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ { if (cc_prev_status.flags & CC_IN_FP) \ return FLOAT; \ if (cc_prev_status.flags & CC_NO_OVERFLOW) \ return NO_OV; \ return NORMAL; } /* Control the assembler format that we output. */ /* Output at beginning of assembler file. */ #define ASM_FILE_START(FILE) \ fprintf (FILE, "#NO_APP\n"); /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ #define ASM_APP_ON "#APP\n" /* Output to assembler file text saying following lines no longer contain unusual constructs. */ #define ASM_APP_OFF "#NO_APP\n" /* Output before read-only data. */ #define TEXT_SECTION_ASM_OP ".text" /* Output before writable data. */ #define DATA_SECTION_ASM_OP ".data" /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ #define REGISTER_NAMES \ {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" } /* How to renumber registers for dbx and gdb. On the Sun-3, the floating point registers have numbers 18 to 25, not 16 to 23 as they do in the compiler. */ /* (On the Alliant, dbx isn't working yet at all. */ #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) /* This is how to output the definition of a user-level label named NAME, such as the label on a static function or variable NAME. */ #define ASM_OUTPUT_LABEL(FILE,NAME) \ do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) /* This is how to output a command to make the user-level label named NAME defined for reference from other files. */ #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) /* This is how to output a reference to a user-level label named NAME. `assemble_name' uses this. */ #define ASM_OUTPUT_LABELREF(FILE,NAME) \ fprintf (FILE, "_%s", NAME) /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, "%s%d:\n", PREFIX, NUM) /* This is how to store into the string LABEL the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ sprintf (LABEL, "*%s%d", PREFIX, NUM) /* This is how to output an assembler line defining a `double' constant. */ #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { union { double d; long v[2];} tem; \ tem.d = (VALUE); \ fprintf (FILE, "\t.long 0x%x,0x%x\n", tem.v[0], tem.v[1]); \ } while (0) /* This is how to output an assembler line defining a `float' constant. */ #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { union { float f; long l;} tem; \ tem.f = (VALUE); \ fprintf (FILE, "\t.long 0x%x\n", tem.l); \ } while (0) /* This is how to output an assembler line defining an `int' constant. */ #define ASM_OUTPUT_INT(FILE,VALUE) \ ( fprintf (FILE, "\t.long "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* Likewise for `char' and `short' constants. */ #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "\t.word "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ( fprintf (FILE, "\t.byte "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #define ASM_OUTPUT_ASCII(FILE,PTR,SIZE) \ { int i; unsigned char *pp = (unsigned char *) (PTR); \ fprintf((FILE), "\t.byte %d", (unsigned int)*pp++); \ for (i = 1; i < (SIZE); ++i, ++pp) { \ if ((i % 8) == 0) \ fprintf((FILE), "\n\t.byte %d", (unsigned int) *pp); \ else \ fprintf((FILE), ",%d", (unsigned int) *pp); } \ fprintf ((FILE), "\n"); } /* This is how to output an assembler line for a numeric constant byte. */ #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tmovl %s,sp@-\n", reg_names[REGNO]) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tmovl sp@+,%s\n", reg_names[REGNO]) /* This is how to output an element of a case-vector that is absolute. (The 68000 does not use such vectors, but we must define this macro anyway.) */ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "\t.long L%d\n", VALUE) /* This is how to output an element of a case-vector that is relative. */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL) /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG) == 1) \ fprintf (FILE, "\t.even\n"); \ else if ((LOG) != 0) \ fprintf (FILE, "\t.align %dn", (LOG)); #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t. = . + %u\n", (SIZE)) /* This says how to output an assembler line to define a global common symbol. */ #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fputs ("\t.comm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (ROUNDED))) /* This says how to output an assembler line to define a local common symbol. */ #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( fputs ("\t.lcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (ROUNDED))) /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) /* Define the parentheses used to group arithmetic operations in assembler code. */ #define ASM_OPEN_PAREN "(" #define ASM_CLOSE_PAREN ")" /* Define results of standard character escape sequences. */ #define TARGET_BELL 007 #define TARGET_BS 010 #define TARGET_TAB 011 #define TARGET_NEWLINE 012 #define TARGET_VT 013 #define TARGET_FF 014 #define TARGET_CR 015 /* Print operand X (an rtx) in assembler syntax to file FILE. CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. For `%' followed by punctuation, CODE is the punctuation and X is null. On the Alliant, we use several CODE characters: '.' for dot needed in Motorola-style opcode names. '-' for an operand pushing on the stack: sp@-, -(sp) or -(%sp) depending on the style of syntax. '+' for an operand pushing on the stack: sp@+, (sp)+ or (%sp)+ depending on the style of syntax. '@' for a reference to the top word on the stack: sp@, (sp) or (%sp) depending on the style of syntax. '#' for an immediate operand prefix (# in MIT and Motorola syntax but & in SGS syntax). '!' for the cc register (used in an `and to cc' insn). 'b' for byte insn (no effect, on the Sun; this is for the ISI). 'd' to force memory addressing to be absolute, not relative. 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), or print pair of registers as rx:ry. */ #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ || (CODE) == '+' || (CODE) == '@' || (CODE) == '!') #define PRINT_OPERAND(FILE, X, CODE) \ { int i; \ if (CODE == '.') ; \ else if (CODE == '#') fprintf (FILE, "#"); \ else if (CODE == '-') fprintf (FILE, "sp@-"); \ else if (CODE == '+') fprintf (FILE, "sp@+"); \ else if (CODE == '@') fprintf (FILE, "sp@"); \ else if (CODE == '!') fprintf (FILE, "cc"); \ else if ((X) == 0 ) ; \ else if (GET_CODE (X) == REG) \ { if (REGNO (X) < 16 && (CODE == 'y' || CODE == 'x') && GET_MODE (X) == DFmode) \ fprintf (FILE, "%s,%s", reg_names[REGNO (X)], reg_names[REGNO (X)+1]); \ else \ fprintf (FILE, "%s", reg_names[REGNO (X)]); \ } \ else if (GET_CODE (X) == MEM) \ { \ output_address (XEXP (X, 0)); \ if (CODE == 'd' && ! TARGET_68020 \ && CONSTANT_ADDRESS_P (XEXP (X, 0)) \ && !(GET_CODE (XEXP (X, 0)) == CONST_INT \ && INTVAL (XEXP (X, 0)) < 0x8000 \ && INTVAL (XEXP (X, 0)) >= -0x8000)) \ fprintf (FILE, ":l"); \ } \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \ { union { double d; int i[2]; } u; \ union { float f; int i; } u1; \ u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \ u1.f = u.d; \ if (CODE == 'f') \ fprintf (FILE, "#0r%.9g", u1.f); \ else \ fprintf (FILE, "#0x%x", u1.i); } \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != DImode) \ { union { double d; int i[2]; } u; \ u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \ fprintf (FILE, "#0r%.20g", u.d); } \ else { putc ('#', FILE); output_addr_const (FILE, X); }} /* Note that this contains a kludge that knows that the only reason we have an address (plus (label_ref...) (reg...)) is in the insn before a tablejump, and we know that m68k.md generates a label LInnn: on such an insn. */ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ { register rtx reg1, reg2, breg, ireg; \ register rtx addr = ADDR; \ static char *sz = ".BW.L...D"; \ rtx offset; \ switch (GET_CODE (addr)) \ { \ case REG: \ fprintf (FILE, "%s@", reg_names[REGNO (addr)]); \ break; \ case PRE_DEC: \ fprintf (FILE, "%s@-", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case POST_INC: \ fprintf (FILE, "%s@+", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case PLUS: \ reg1 = 0; reg2 = 0; \ ireg = 0; breg = 0; \ offset = 0; \ if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \ { \ offset = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \ { \ offset = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) != PLUS) ; \ else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == MULT) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == MULT) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == REG) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == REG) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \ || GET_CODE (addr) == SIGN_EXTEND) \ { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \ /* for OLD_INDEXING \ else if (GET_CODE (addr) == PLUS) \ { \ if (GET_CODE (XEXP (addr, 0)) == REG) \ { \ reg2 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == REG) \ { \ reg2 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ } \ */ \ if (offset != 0) { if (addr != 0) abort (); addr = offset; } \ if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \ || GET_CODE (reg1) == MULT)) \ || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \ { breg = reg2; ireg = reg1; } \ else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \ { breg = reg1; ireg = reg2; } \ if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \ { int scale = 1; \ if (GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:W", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (XEXP (ireg, 0))]); \ else \ fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (ireg)]); \ fprintf (FILE, ":%c", sz[scale]); \ putc (']', FILE); \ break; } \ if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF) \ { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (breg)]); \ break; } \ if (ireg != 0 || breg != 0) \ { int scale = 1; \ if (breg == 0) \ abort (); \ if (addr && GET_CODE (addr) == LABEL_REF) abort (); \ fprintf (FILE, "%s@", reg_names[REGNO (breg)]); \ if (addr != 0) { \ putc( '(', FILE ); \ output_addr_const (FILE, addr); \ if (ireg != 0) { \ if (GET_CODE(addr) == CONST_INT) { \ int size_of = 1, val = INTVAL(addr); \ if (val < -0x8000 || val >= 0x8000) \ size_of = 4; \ else if (val < -0x80 || val >= 0x80) \ size_of = 2; \ fprintf(FILE, ":%c", sz[size_of]); \ } \ else \ fprintf(FILE, ":L"); } \ putc( ')', FILE ); } \ if (ireg != 0) { \ putc ('[', FILE); \ if (ireg != 0 && GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "%s:W", reg_names[REGNO (XEXP (ireg, 0))]); \ else if (ireg != 0) \ fprintf (FILE, "%s:L", reg_names[REGNO (ireg)]); \ fprintf (FILE, ":%c", sz[scale]); \ putc (']', FILE); \ } \ break; \ } \ else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \ { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (reg1)]); \ break; } \ default: \ if (GET_CODE (addr) == CONST_INT \ && INTVAL (addr) < 0x8000 \ && INTVAL (addr) >= -0x8000) \ fprintf (FILE, "%d:W", INTVAL (addr)); \ else \ output_addr_const (FILE, addr); \ }} /* Local variables: version-control: t End: */ gcc-2.5.8/config/fx80/fx80.md100444 22011 13 211757 5353602273 14206 0ustar kenneruser;;- Machine description for GNU C compiler for Alliant FX systems ;; Copyright (C) 1989 Free Software Foundation, Inc. ;; Adapted from m68k.md by Paul Petersen (petersen@uicsrd.csrd.uiuc.edu) ;; and Joe Weening (weening@gang-of-four.stanford.edu). ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ;;- instruction definitions ;;- @@The original PO technology requires these to be ordered by speed, ;;- @@ so that assigner will pick the fastest. ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ;;- When naming insn's (operand 0 of define_insn) be careful about using ;;- names from other targets machine descriptions. ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code ;;- updates for most instructions. ;;- Operand classes for the register allocator: ;;- 'a' one of the address registers can be used. ;;- 'd' one of the data registers can be used. ;;- 'f' one of the CE floating point registers can be used ;;- 'r' either a data or an address register can be used. ;;- Immediate integer operand constraints: ;;- 'I' 1 .. 8 ;;- 'J' -32768 .. 32767 ;;- 'K' -128 .. 127 ;;- 'L' -8 .. -1 ;;- Some remnants of constraint codes for the m68k ('x','y','G','H') ;;- may remain in the insn definitions. ;;- Some of these insn's are composites of several Alliant op codes. ;;- The assembler (or final @@??) insures that the appropriate one is ;;- selected. ;; We don't want to allow a constant operand for test insns because ;; (set (cc0) (const_int foo)) has no mode information. Such insns will ;; be folded while optimizing anyway. (define_insn "tstsi" [(set (cc0) (match_operand:SI 0 "nonimmediate_operand" "rm"))] "" "* { if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) return \"tst%.l %0\"; /* If you think that the 68020 does not support tstl a0, reread page B-167 of the 68020 manual more carefully. */ /* On an address reg, cmpw may replace cmpl. */ return \"cmp%.w %#0,%0\"; }") (define_insn "tsthi" [(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "rm"))] "" "* { if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) return \"tst%.w %0\"; return \"cmp%.w %#0,%0\"; }") (define_insn "tstqi" [(set (cc0) (match_operand:QI 0 "nonimmediate_operand" "dm"))] "" "tst%.b %0") (define_insn "tstsf" [(set (cc0) (match_operand:SF 0 "nonimmediate_operand" "fm"))] "TARGET_CE" "* { cc_status.flags = CC_IN_FP; return \"ftest%.s %0\"; }") (define_insn "tstdf" [(set (cc0) (match_operand:DF 0 "nonimmediate_operand" "fm"))] "TARGET_CE" "* { cc_status.flags = CC_IN_FP; return \"ftest%.d %0\"; }") ;; compare instructions. ;; A composite of the cmp, cmpa, & cmpi m68000 op codes. (define_insn "cmpsi" [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>") (match_operand:SI 1 "general_operand" "mr,Ksr,>")))] "" "* { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) return \"cmpm%.l %1,%0\"; if (REG_P (operands[1]) || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) { cc_status.flags |= CC_REVERSED; return \"cmp%.l %d0,%d1\"; } return \"cmp%.l %d1,%d0\"; }") (define_insn "cmphi" [(set (cc0) (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m") (match_operand:HI 1 "general_operand" "d,rnm,m,n")))] "" "* { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) return \"cmpm%.w %1,%0\"; if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1])) || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) { cc_status.flags |= CC_REVERSED; return \"cmp%.w %d0,%d1\"; } return \"cmp%.w %d1,%d0\"; }") (define_insn "cmpqi" [(set (cc0) (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>") (match_operand:QI 1 "general_operand" "dm,nd,>")))] "" "* { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) return \"cmpm%.b %1,%0\"; if (REG_P (operands[1]) || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) { cc_status.flags |= CC_REVERSED; return \"cmp%.b %d0,%d1\"; } return \"cmp%.b %d1,%d0\"; }") (define_insn "cmpdf" [(set (cc0) (compare (match_operand:DF 0 "nonimmediate_operand" "f,m") (match_operand:DF 1 "nonimmediate_operand" "fm,f")))] "TARGET_CE" "* { cc_status.flags = CC_IN_FP; if (FP_REG_P (operands[0])) return \"fcmp%.d %1,%0\"; cc_status.flags |= CC_REVERSED; return \"fcmp%.d %0,%1\"; }") (define_insn "cmpsf" [(set (cc0) (compare (match_operand:SF 0 "nonimmediate_operand" "f,m") (match_operand:SF 1 "nonimmediate_operand" "fm,f")))] "TARGET_CE" "* { cc_status.flags = CC_IN_FP; if (FP_REG_P (operands[0])) return \"fcmp%.s %1,%0\"; cc_status.flags |= CC_REVERSED; return \"fcmp%.s %0,%1\"; }") ;; Recognizers for btst instructions. (define_insn "" [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do") (const_int 1) (minus:SI (const_int 7) (match_operand:SI 1 "general_operand" "di"))))] "" "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") (define_insn "" [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d") (const_int 1) (minus:SI (const_int 31) (match_operand:SI 1 "general_operand" "di"))))] "" "* { return output_btst (operands, operands[1], operands[0], insn, 31); }") ;; The following two patterns are like the previous two ;; except that they use the fact that bit-number operands ;; are automatically masked to 3 or 5 bits. (define_insn "" [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do") (const_int 1) (minus:SI (const_int 7) (and:SI (match_operand:SI 1 "general_operand" "d") (const_int 7)))))] "" "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") (define_insn "" [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d") (const_int 1) (minus:SI (const_int 31) (and:SI (match_operand:SI 1 "general_operand" "d") (const_int 31)))))] "" "* { return output_btst (operands, operands[1], operands[0], insn, 31); }") ;; Nonoffsettable mem refs are ok in this one pattern ;; since we don't try to adjust them. (define_insn "" [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "md") (const_int 1) (match_operand:SI 1 "general_operand" "i")))] "GET_CODE (operands[1]) == CONST_INT && (unsigned) INTVAL (operands[1]) < 8" "* { operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1])); return output_btst (operands, operands[1], operands[0], insn, 7); }") (define_insn "" [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "do") (const_int 1) (match_operand:SI 1 "general_operand" "i")))] "GET_CODE (operands[1]) == CONST_INT" "* { if (GET_CODE (operands[0]) == MEM) { operands[0] = adj_offsettable_operand (operands[0], INTVAL (operands[1]) / 8); operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]) % 8); return output_btst (operands, operands[1], operands[0], insn, 7); } operands[1] = gen_rtx (CONST_INT, VOIDmode, 31 - INTVAL (operands[1])); return output_btst (operands, operands[1], operands[0], insn, 31); }") ;; move instructions ;; A special case in which it is not desirable ;; to reload the constant into a data register. (define_insn "" [(set (match_operand:SI 0 "push_operand" "=m") (match_operand:SI 1 "general_operand" "J"))] "GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000" "* { if (operands[1] == const0_rtx) return \"clr%.l %0\"; return \"pea %a1\"; }") ;This is never used. ;(define_insn "swapsi" ; [(set (match_operand:SI 0 "general_operand" "r") ; (match_operand:SI 1 "general_operand" "r")) ; (set (match_dup 1) (match_dup 0))] ; "" ; "exg %1,%0") ;; Special case of fullword move when source is zero. ;; The reason this is special is to avoid loading a zero ;; into a data reg with moveq in order to store it elsewhere. (define_insn "" [(set (match_operand:SI 0 "general_operand" "=a,g") (const_int 0))] "" "@ sub%.l %0,%0 clr%.l %0") ;; General case of fullword move. The register constraints ;; force integer constants in range for a moveq to be reloaded ;; if they are headed for memory. (define_insn "movsi" ;; Notes: make sure no alternative allows g vs g. ;; We don't allow f-regs since fixed point cannot go in them. ;; We do allow y and x regs since fixed point is allowed in them. [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m") (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))] "" "* { if (GET_CODE (operands[1]) == CONST_INT) { if (operands[1] == const0_rtx && (DATA_REG_P (operands[0]) || GET_CODE (operands[0]) == MEM)) return \"clr%.l %0\"; else if (DATA_REG_P (operands[0]) && INTVAL (operands[1]) < 128 && INTVAL (operands[1]) >= -128) return \"moveq %1,%0\"; else if (ADDRESS_REG_P (operands[0]) && INTVAL (operands[1]) < 0x8000 && INTVAL (operands[1]) >= -0x8000) return \"mov%.w %1,%0\"; else if (push_operand (operands[0], SImode) && INTVAL (operands[1]) < 0x8000 && INTVAL (operands[1]) >= -0x8000) return \"pea %a1\"; } else if ((GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST) && push_operand (operands[0], SImode)) return \"pea %a1\"; else if ((GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST) && ADDRESS_REG_P (operands[0])) return \"lea %a1,%0\"; return \"mov%.l %1,%0\"; }") (define_insn "movhi" [(set (match_operand:HI 0 "general_operand" "=g") (match_operand:HI 1 "general_operand" "g"))] "" "* { if (GET_CODE (operands[1]) == CONST_INT) { if (operands[1] == const0_rtx && (DATA_REG_P (operands[0]) || GET_CODE (operands[0]) == MEM)) return \"clr%.w %0\"; else if (DATA_REG_P (operands[0]) && INTVAL (operands[1]) < 128 && INTVAL (operands[1]) >= -128) { return \"moveq %1,%0\"; } else if (INTVAL (operands[1]) < 0x8000 && INTVAL (operands[1]) >= -0x8000) return \"mov%.w %1,%0\"; } else if (CONSTANT_P (operands[1])) return \"mov%.l %1,%0\"; /* Recognize the insn before a tablejump, one that refers to a table of offsets. Such an insn will need to refer to a label on the insn. So output one. Use the label-number of the table of offsets to generate this label. */ if (GET_CODE (operands[1]) == MEM && GET_CODE (XEXP (operands[1], 0)) == PLUS && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF || GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF) && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) != PLUS) { rtx labelref; if (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF) labelref = XEXP (XEXP (operands[1], 0), 0); else labelref = XEXP (XEXP (operands[1], 0), 1); ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\", CODE_LABEL_NUMBER (XEXP (labelref, 0))); } return \"mov%.w %1,%0\"; }") (define_insn "movstricthi" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) (match_operand:HI 1 "general_operand" "rmn"))] "" "* { if (operands[1] == const0_rtx) return \"clr%.w %0\"; return \"mov%.w %1,%0\"; }") (define_insn "movqi" [(set (match_operand:QI 0 "general_operand" "=d,*a,m,m,?*a") (match_operand:QI 1 "general_operand" "dmi*a,d*a,dmi,?*a,m"))] "" "* { rtx xoperands[4]; if (ADDRESS_REG_P (operands[0]) && GET_CODE (operands[1]) == MEM) { xoperands[1] = operands[1]; xoperands[2] = gen_rtx (MEM, QImode, gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx)); xoperands[3] = stack_pointer_rtx; /* Just pushing a byte puts it in the high byte of the halfword. */ /* We must put it in the low half, the second byte. */ output_asm_insn (\"subq%.w %#2,%3\;mov%.b %1,%2\", xoperands); return \"mov%.w %+,%0\"; } if (ADDRESS_REG_P (operands[1]) && GET_CODE (operands[0]) == MEM) { xoperands[0] = operands[0]; xoperands[1] = operands[1]; xoperands[2] = gen_rtx (MEM, QImode, gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx)); xoperands[3] = stack_pointer_rtx; output_asm_insn (\"mov%.w %1,%-\;mov%.b %2,%0\;addq%.w %#2,%3\", xoperands); return \"\"; } if (operands[1] == const0_rtx) return \"clr%.b %0\"; if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == -1) return \"st %0\"; if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) return \"mov%.l %1,%0\"; if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) return \"mov%.w %1,%0\"; return \"mov%.b %1,%0\"; }") (define_insn "movstrictqi" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) (match_operand:QI 1 "general_operand" "dmn"))] "" "* { if (operands[1] == const0_rtx) return \"clr%.b %0\"; return \"mov%.b %1,%0\"; }") ;; Floating-point moves on a CE are faster using an FP register than ;; with movl instructions. (Especially for double floats, but also ;; for single floats, even though it takes an extra instruction.) But ;; on an IP, the FP registers are simulated and so should be avoided. ;; We do this by using define_expand for movsf and movdf, and using ;; different constraints for each target type. The constraints for ;; TARGET_CE allow general registers because they sometimes need to ;; hold floats, but they are not preferable. (define_expand "movsf" [(set (match_operand:SF 0 "general_operand" "") (match_operand:SF 1 "nonimmediate_operand" ""))] "" "") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=f,m,!*r,!f*m") (match_operand:SF 1 "nonimmediate_operand" "fm,f,f*r*m,*r"))] "TARGET_CE" "* { if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) return \"fmove%.s %1,%0\"; if (REG_P (operands[1])) return \"mov%.l %1,%-\;fmove%.s %+,%0\"; return \"fmove%.s %1,%0\"; } if (FP_REG_P (operands[1])) { if (REG_P (operands[0])) return \"fmove%.s %1,%-\;mov%.l %+,%0\"; return \"fmove%.s %1,%0\"; } return \"mov%.l %1,%0\"; }") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=frm") (match_operand:SF 1 "nonimmediate_operand" "frm"))] "!TARGET_CE" "* { if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) return \"fmove%.s %1,%0\"; if (REG_P (operands[1])) return \"mov%.l %1,%-\;fmove%.s %+,%0\"; return \"fmove%.s %1,%0\"; } if (FP_REG_P (operands[1])) { if (REG_P (operands[0])) return \"fmove%.s %1,%-\;mov%.l %+,%0\"; return \"fmove%.s %1,%0\"; } return \"mov%.l %1,%0\"; }") (define_expand "movdf" [(set (match_operand:DF 0 "general_operand" "") (match_operand:DF 1 "nonimmediate_operand" ""))] "" "") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=f,m,!*r,!f*m") (match_operand:DF 1 "nonimmediate_operand" "fm,f,f*r*m,*r"))] "TARGET_CE" "* { if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) return \"fmove%.d %1,%0\"; if (REG_P (operands[1])) { rtx xoperands[2]; xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); output_asm_insn (\"mov%.l %1,%-\", xoperands); output_asm_insn (\"mov%.l %1,%-\", operands); return \"fmove%.d %+,%0\"; } return \"fmove%.d %1,%0\"; } else if (FP_REG_P (operands[1])) { if (REG_P (operands[0])) { output_asm_insn (\"fmove%.d %1,%-\;mov%.l %+,%0\", operands); operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); return \"mov%.l %+,%0\"; } return \"fmove%.d %1,%0\"; } return output_move_double (operands); }") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=frm") (match_operand:DF 1 "nonimmediate_operand" "frm"))] "!TARGET_CE" "* { if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) return \"fmove%.d %1,%0\"; if (REG_P (operands[1])) { rtx xoperands[2]; xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); output_asm_insn (\"mov%.l %1,%-\", xoperands); output_asm_insn (\"mov%.l %1,%-\", operands); return \"fmove%.d %+,%0\"; } return \"fmove%.d %1,%0\"; } else if (FP_REG_P (operands[1])) { if (REG_P (operands[0])) { output_asm_insn (\"fmove%.d %1,%-\;mov%.l %+,%0\", operands); operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); return \"mov%.l %+,%0\"; } return \"fmove%.d %1,%0\"; } return output_move_double (operands); }") (define_insn "movdi" [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>") (match_operand:DI 1 "general_operand" "r,m,roi<>"))] "" "* { return output_move_double (operands); } ") ;; This goes after the move instructions ;; because the move instructions are better (require no spilling) ;; when they can apply. It goes before the add/sub insns ;; so we will prefer it to them. (define_insn "pushasi" [(set (match_operand:SI 0 "push_operand" "=m") (match_operand:SI 1 "address_operand" "p"))] "" "pea %a1") ;; truncation instructions (define_insn "truncsiqi2" [(set (match_operand:QI 0 "general_operand" "=dm,d") (truncate:QI (match_operand:SI 1 "general_operand" "doJ,i")))] "" "* { if (GET_CODE (operands[0]) == REG) return \"mov%.l %1,%0\"; if (GET_CODE (operands[1]) == MEM) operands[1] = adj_offsettable_operand (operands[1], 3); return \"mov%.b %1,%0\"; }") (define_insn "trunchiqi2" [(set (match_operand:QI 0 "general_operand" "=dm,d") (truncate:QI (match_operand:HI 1 "general_operand" "doJ,i")))] "" "* { if (GET_CODE (operands[0]) == REG && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[1]) == CONST_INT)) return \"mov%.w %1,%0\"; if (GET_CODE (operands[0]) == REG) return \"mov%.l %1,%0\"; if (GET_CODE (operands[1]) == MEM) operands[1] = adj_offsettable_operand (operands[1], 1); return \"mov%.b %1,%0\"; }") (define_insn "truncsihi2" [(set (match_operand:HI 0 "general_operand" "=dm,d") (truncate:HI (match_operand:SI 1 "general_operand" "roJ,i")))] "" "* { if (GET_CODE (operands[0]) == REG) return \"mov%.l %1,%0\"; if (GET_CODE (operands[1]) == MEM) operands[1] = adj_offsettable_operand (operands[1], 2); return \"mov%.w %1,%0\"; }") ;; zero extension instructions (define_expand "zero_extendhisi2" [(set (match_operand:SI 0 "register_operand" "") (const_int 0)) (set (strict_low_part (subreg:HI (match_dup 0) 0)) (match_operand:HI 1 "general_operand" ""))] "" "operands[1] = make_safe_from (operands[1], operands[0]);") (define_expand "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "") (const_int 0)) (set (strict_low_part (subreg:QI (match_dup 0) 0)) (match_operand:QI 1 "general_operand" ""))] "" "operands[1] = make_safe_from (operands[1], operands[0]);") (define_expand "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "") (const_int 0)) (set (strict_low_part (subreg:QI (match_dup 0) 0)) (match_operand:QI 1 "general_operand" ""))] "" " operands[1] = make_safe_from (operands[1], operands[0]); ") ;; Patterns to recognize zero-extend insns produced by the combiner. (define_insn "" [(set (match_operand:SI 0 "general_operand" "=do<>") (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] "" "* { if (DATA_REG_P (operands[0])) { if (GET_CODE (operands[1]) == REG && REGNO (operands[0]) == REGNO (operands[1])) return \"and%.l %#0xFFFF,%0\"; if (reg_mentioned_p (operands[0], operands[1])) return \"mov%.w %1,%0\;and%.l %#0xFFFF,%0\"; return \"clr%.l %0\;mov%.w %1,%0\"; } else if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) return \"mov%.w %1,%0\;clr%.w %0\"; else if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == POST_INC) return \"clr%.w %0\;mov%.w %1,%0\"; else { output_asm_insn (\"clr%.w %0\", operands); operands[0] = adj_offsettable_operand (operands[0], 2); return \"mov%.w %1,%0\"; } }") (define_insn "" [(set (match_operand:HI 0 "general_operand" "=do<>") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "dm")))] "" "* { if (DATA_REG_P (operands[0])) { if (GET_CODE (operands[1]) == REG && REGNO (operands[0]) == REGNO (operands[1])) return \"and%.w %#0xFF,%0\"; if (reg_mentioned_p (operands[0], operands[1])) return \"mov%.b %1,%0\;and%.w %#0xFF,%0\"; return \"clr%.w %0\;mov%.b %1,%0\"; } else if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) { if (REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM) return \"clr%.w %-\;mov%.b %1,%0\"; else return \"mov%.b %1,%0\;clr%.b %0\"; } else if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == POST_INC) return \"clr%.b %0\;mov%.b %1,%0\"; else { output_asm_insn (\"clr%.b %0\", operands); operands[0] = adj_offsettable_operand (operands[0], 1); return \"mov%.b %1,%0\"; } }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=do<>") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "dm")))] "" "* { if (DATA_REG_P (operands[0])) { if (GET_CODE (operands[1]) == REG && REGNO (operands[0]) == REGNO (operands[1])) return \"and%.l %#0xFF,%0\"; if (reg_mentioned_p (operands[0], operands[1])) return \"mov%.b %1,%0\;and%.l %#0xFF,%0\"; return \"clr%.l %0\;mov%.b %1,%0\"; } else if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) { operands[0] = XEXP (XEXP (operands[0], 0), 0); return \"clr%.l %0@-\;mov%.b %1,%0@(3)\"; } else if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == POST_INC) { operands[0] = XEXP (XEXP (operands[0], 0), 0); return \"clr%.l %0@+\;mov%.b %1,%0@(-1)\"; } else { output_asm_insn (\"clr%.l %0\", operands); operands[0] = adj_offsettable_operand (operands[0], 3); return \"mov%.b %1,%0\"; } }") ;; sign extension instructions (define_insn "extendhisi2" [(set (match_operand:SI 0 "general_operand" "=*d,a") (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,rmn")))] "" "@ ext%.l %0 mov%.w %1,%0") (define_insn "extendqihi2" [(set (match_operand:HI 0 "general_operand" "=d") (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))] "" "ext%.w %0") (define_insn "extendqisi2" [(set (match_operand:SI 0 "general_operand" "=d") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))] "TARGET_68020" "extb%.l %0") ;; Conversions between float and double. (define_insn "extendsfdf2" [(set (match_operand:DF 0 "general_operand" "=f,m") (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))] "TARGET_CE" "fmovesd %1,%0") (define_insn "truncdfsf2" [(set (match_operand:SF 0 "general_operand" "=f,m") (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))] "TARGET_CE" "fmoveds %1,%0") ;; Conversion between fixed point and floating point. ;; Note that among the fix-to-float insns ;; the ones that start with SImode come first. ;; That is so that an operand that is a CONST_INT ;; (and therefore lacks a specific machine mode). ;; will be recognized as SImode (which is always valid) ;; rather than as QImode or HImode. (define_insn "floatsisf2" [(set (match_operand:SF 0 "register_operand" "=f") (float:SF (match_operand:SI 1 "nonimmediate_operand" "dm")))] "TARGET_CE" "fmovels %1,%0") (define_insn "floatsidf2" [(set (match_operand:DF 0 "register_operand" "=f") (float:DF (match_operand:SI 1 "nonimmediate_operand" "dm")))] "TARGET_CE" "fmoveld %1,%0") (define_insn "floathisf2" [(set (match_operand:SF 0 "register_operand" "=f") (float:SF (match_operand:HI 1 "nonimmediate_operand" "dm")))] "TARGET_CE" "fmovews %1,%0") (define_insn "floathidf2" [(set (match_operand:DF 0 "register_operand" "=f") (float:DF (match_operand:HI 1 "nonimmediate_operand" "dm")))] "TARGET_CE" "fmovewd %1,%0") (define_insn "floatqisf2" [(set (match_operand:SF 0 "register_operand" "=f") (float:SF (match_operand:QI 1 "nonimmediate_operand" "dm")))] "TARGET_CE" "fmovebs %1,%0") (define_insn "floatqidf2" [(set (match_operand:DF 0 "register_operand" "=f") (float:DF (match_operand:QI 1 "nonimmediate_operand" "dm")))] "TARGET_CE" "fmovebd %1,%0") ;; Float-to-fix conversion insns. (define_insn "fix_truncsfqi2" [(set (match_operand:QI 0 "general_operand" "=dm") (fix:QI (fix:SF (match_operand:SF 1 "register_operand" "f"))))] "TARGET_CE" "fmovesb %1,%0") (define_insn "fix_truncsfhi2" [(set (match_operand:HI 0 "general_operand" "=dm") (fix:HI (fix:SF (match_operand:SF 1 "register_operand" "f"))))] "TARGET_CE" "fmovesw %1,%0") (define_insn "fix_truncsfsi2" [(set (match_operand:SI 0 "general_operand" "=dm") (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))] "TARGET_CE" "fmovesl %1,%0") (define_insn "fix_truncdfqi2" [(set (match_operand:QI 0 "general_operand" "=dm") (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))] "TARGET_CE" "fmovedb %1,%0") (define_insn "fix_truncdfhi2" [(set (match_operand:HI 0 "general_operand" "=dm") (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))] "TARGET_CE" "fmovedw %1,%0") (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "general_operand" "=dm") (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))] "TARGET_CE" "fmovedl %1,%0") ;; add instructions (define_insn "addsi3" [(set (match_operand:SI 0 "general_operand" "=m,r,!a,!a") (plus:SI (match_operand:SI 1 "general_operand" "%0,0,a,rJK") (match_operand:SI 2 "general_operand" "dIKLs,mrIKLs,rJK,a")))] "" "* { if (! operands_match_p (operands[0], operands[1])) { if (!ADDRESS_REG_P (operands[1])) { rtx tmp = operands[1]; operands[1] = operands[2]; operands[2] = tmp; } /* These insns can result from reloads to access stack slots over 64k from the frame pointer. */ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000) return \"mov%.l %2,%0\;add%.l %1,%0\"; if (GET_CODE (operands[2]) == REG) return \"lea %1@[%2:L:B],%0\"; else return \"lea %1@(%c2),%0\"; } if (GET_CODE (operands[2]) == CONST_INT) { if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 8) return (ADDRESS_REG_P (operands[0]) ? \"addq%.w %2,%0\" : \"addq%.l %2,%0\"); if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8) { operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2])); return (ADDRESS_REG_P (operands[0]) ? \"subq%.w %2,%0\" : \"subq%.l %2,%0\"); } if (ADDRESS_REG_P (operands[0]) && INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) < 0x8000) return \"add%.w %2,%0\"; } return \"add%.l %2,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=a") (plus:SI (match_operand:SI 1 "general_operand" "0") (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmn"))))] "" "add%.w %2,%0") (define_insn "addhi3" [(set (match_operand:HI 0 "general_operand" "=mr,mr,m,r") (plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0") (match_operand:HI 2 "general_operand" "I,L,dn,rmn")))] "" "@ addq%.w %2,%0 subq%.w #%n2,%0 add%.w %2,%0 add%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) (plus:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dn,rmn")))] "" "add%.w %1,%0") (define_insn "addqi3" [(set (match_operand:QI 0 "general_operand" "=md,mr,m,d") (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0") (match_operand:QI 2 "general_operand" "I,L,dn,dmn")))] "" "@ addq%.b %2,%0 subq%.b #%n2,%0 add%.b %2,%0 add%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) (plus:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dn,dmn")))] "" "add%.b %1,%0") (define_insn "adddf3" [(set (match_operand:DF 0 "register_operand" "=f") (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%f") (match_operand:DF 2 "nonimmediate_operand" "fm")))] "TARGET_CE" "fadd%.d %2,%1,%0") (define_insn "addsf3" [(set (match_operand:SF 0 "register_operand" "=f") (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%f") (match_operand:SF 2 "nonimmediate_operand" "fm")))] "TARGET_CE" "fadd%.s %2,%1,%0") ;; subtract instructions (define_insn "subsi3" [(set (match_operand:SI 0 "general_operand" "=m,r,!a,?d") (minus:SI (match_operand:SI 1 "general_operand" "0,0,a,mrIKs") (match_operand:SI 2 "general_operand" "dIKs,mrIKs,J,0")))] "" "* { if (! operands_match_p (operands[0], operands[1])) { if (operands_match_p (operands[0], operands[2])) { if (GET_CODE (operands[1]) == CONST_INT) { if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8) return \"subq%.l %1,%0\;neg%.l %0\"; } return \"sub%.l %1,%0\;neg%.l %0\"; } /* This case is matched by J, but negating -0x8000 in an lea would give an invalid displacement. So do this specially. */ if (INTVAL (operands[2]) == -0x8000) return \"mov%.l %1,%0\;sub%.l %2,%0\"; return \"lea %1@(%n2),%0\"; } if (GET_CODE (operands[2]) == CONST_INT) { if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 8) return \"subq%.l %2,%0\"; if (ADDRESS_REG_P (operands[0]) && INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) < 0x8000) return \"sub%.w %2,%0\"; } return \"sub%.l %2,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=a") (minus:SI (match_operand:SI 1 "general_operand" "0") (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmn"))))] "" "sub%.w %2,%0") (define_insn "subhi3" [(set (match_operand:HI 0 "general_operand" "=m,r") (minus:HI (match_operand:HI 1 "general_operand" "0,0") (match_operand:HI 2 "general_operand" "dn,rmn")))] "" "sub%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) (minus:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dn,rmn")))] "" "sub%.w %1,%0") (define_insn "subqi3" [(set (match_operand:QI 0 "general_operand" "=m,d") (minus:QI (match_operand:QI 1 "general_operand" "0,0") (match_operand:QI 2 "general_operand" "dn,dmn")))] "" "sub%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) (minus:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dn,dmn")))] "" "sub%.b %1,%0") (define_insn "subdf3" [(set (match_operand:DF 0 "register_operand" "=f,f,f") (minus:DF (match_operand:DF 1 "nonimmediate_operand" "f,f,m") (match_operand:DF 2 "nonimmediate_operand" "f,m,f")))] "TARGET_CE" "@ fsub%.d %2,%1,%0 fsub%.d %2,%1,%0 frsub%.d %1,%2,%0") (define_insn "subsf3" [(set (match_operand:SF 0 "register_operand" "=f,f,f") (minus:SF (match_operand:SF 1 "nonimmediate_operand" "f,f,m") (match_operand:SF 2 "nonimmediate_operand" "f,m,f")))] "TARGET_CE" "@ fsub%.s %2,%1,%0 fsub%.s %2,%1,%0 frsub%.s %1,%2,%0") ;; multiply instructions (define_insn "mulhi3" [(set (match_operand:HI 0 "general_operand" "=d") (mult:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "dmn")))] "" "muls %2,%0") (define_insn "mulhisi3" [(set (match_operand:SI 0 "general_operand" "=d") (mult:SI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%0")) (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm"))))] "" "muls %2,%0") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d") (mult:SI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%0")) (match_operand:SI 2 "const_int_operand" "n")))] "" "muls %2,%0") (define_insn "mulsi3" [(set (match_operand:SI 0 "general_operand" "=d") (mult:SI (match_operand:SI 1 "general_operand" "%0") (match_operand:SI 2 "general_operand" "dmsK")))] "TARGET_68020" "muls%.l %2,%0") (define_insn "umulhisi3" [(set (match_operand:SI 0 "general_operand" "=d") (mult:SI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%0")) (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm"))))] "" "mulu %2,%0") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d") (mult:SI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%0")) (match_operand:SI 2 "const_int_operand" "n")))] "" "mulu %2,%0") (define_insn "muldf3" [(set (match_operand:DF 0 "register_operand" "=f") (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%f") (match_operand:DF 2 "nonimmediate_operand" "fm")))] "TARGET_CE" "fmul%.d %2,%1,%0") (define_insn "mulsf3" [(set (match_operand:SF 0 "register_operand" "=f") (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%f") (match_operand:SF 2 "nonimmediate_operand" "fm")))] "TARGET_CE" "fmul%.s %2,%1,%0") ;; divide instructions (define_insn "divhi3" [(set (match_operand:HI 0 "general_operand" "=d") (div:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "dmn")))] "" "extl %0\;divs %2,%0") (define_insn "divhisi3" [(set (match_operand:HI 0 "general_operand" "=d") (truncate:HI (div:SI (match_operand:SI 1 "general_operand" "0") (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] "" "divs %2,%0") (define_insn "" [(set (match_operand:HI 0 "general_operand" "=d") (truncate:HI (div:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "const_int_operand" "n"))))] "" "divs %2,%0") (define_insn "divsi3" [(set (match_operand:SI 0 "general_operand" "=d") (div:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "dmsK")))] "TARGET_68020" "divs%.l %2,%0,%0") (define_insn "udivhi3" [(set (match_operand:HI 0 "general_operand" "=d") (udiv:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "dmn")))] "" "and%.l %#0xFFFF,%0\;divu %2,%0") (define_insn "udivhisi3" [(set (match_operand:HI 0 "general_operand" "=d") (truncate:HI (udiv:SI (match_operand:SI 1 "general_operand" "0") (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] "" "divu %2,%0") (define_insn "" [(set (match_operand:HI 0 "general_operand" "=d") (truncate:HI (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "0") (match_operand:HI 2 "const_int_operand" "n"))))] "" "divu %2,%0") (define_insn "udivsi3" [(set (match_operand:SI 0 "general_operand" "=d") (udiv:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "dmsK")))] "TARGET_68020" "divu%.l %2,%0,%0") (define_insn "divdf3" [(set (match_operand:DF 0 "register_operand" "=f,f,f") (div:DF (match_operand:DF 1 "nonimmediate_operand" "f,f,m") (match_operand:DF 2 "nonimmediate_operand" "f,m,f")))] "TARGET_CE" "@ fdiv%.d %2,%1,%0 fdiv%.d %2,%1,%0 frdiv%.d %1,%2,%0") (define_insn "divsf3" [(set (match_operand:SF 0 "register_operand" "=f,f,f") (div:SF (match_operand:SF 1 "nonimmediate_operand" "f,f,m") (match_operand:SF 2 "nonimmediate_operand" "f,m,f")))] "TARGET_CE" "@ fdiv%.s %2,%1,%0 fdiv%.s %2,%1,%0 frdiv%.s %1,%2,%0") ;; Remainder instructions. (define_insn "modhi3" [(set (match_operand:HI 0 "general_operand" "=d") (mod:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "dmn")))] "" "extl %0\;divs %2,%0\;swap %0") (define_insn "modhisi3" [(set (match_operand:HI 0 "general_operand" "=d") (truncate:HI (mod:SI (match_operand:SI 1 "general_operand" "0") (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] "" "divs %2,%0\;swap %0") (define_insn "" [(set (match_operand:HI 0 "general_operand" "=d") (truncate:HI (mod:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "const_int_operand" "n"))))] "" "divs %2,%0\;swap %0") (define_insn "umodhi3" [(set (match_operand:HI 0 "general_operand" "=d") (umod:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "dmn")))] "" "and%.l %#0xFFFF,%0\;divu %2,%0\;swap %0") (define_insn "umodhisi3" [(set (match_operand:HI 0 "general_operand" "=d") (truncate:HI (umod:SI (match_operand:SI 1 "general_operand" "0") (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] "" "divu %2,%0\;swap %0") (define_insn "" [(set (match_operand:HI 0 "general_operand" "=d") (truncate:HI (umod:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "const_int_operand" "n"))))] "" "divu %2,%0\;swap %0") (define_insn "divmodsi4" [(set (match_operand:SI 0 "general_operand" "=d") (div:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "dmsK"))) (set (match_operand:SI 3 "general_operand" "=d") (mod:SI (match_dup 1) (match_dup 2)))] "TARGET_68020" "divs%.l %2,%0,%3") (define_insn "udivmodsi4" [(set (match_operand:SI 0 "general_operand" "=d") (udiv:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "dmsK"))) (set (match_operand:SI 3 "general_operand" "=d") (umod:SI (match_dup 1) (match_dup 2)))] "TARGET_68020" "divu%.l %2,%0,%3") ;; logical-and instructions (define_insn "andsi3" [(set (match_operand:SI 0 "general_operand" "=m,d") (and:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_operand" "dKs,dmKs")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) | 0xffff) == 0xffffffff && (DATA_REG_P (operands[0]) || offsettable_memref_p (operands[0]))) { if (GET_CODE (operands[0]) != REG) operands[0] = adj_offsettable_operand (operands[0], 2); operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); /* Do not delete a following tstl %0 insn; that would be incorrect. */ CC_STATUS_INIT; if (operands[2] == const0_rtx) return \"clr%.w %0\"; return \"and%.w %2,%0\"; } return \"and%.l %2,%0\"; }") (define_insn "andhi3" [(set (match_operand:HI 0 "general_operand" "=m,d") (and:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_operand" "dn,dmn")))] "" "and%.w %2,%0") (define_insn "andqi3" [(set (match_operand:QI 0 "general_operand" "=m,d") (and:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_operand" "dn,dmn")))] "" "and%.b %2,%0") ;; inclusive-or instructions (define_insn "iorsi3" [(set (match_operand:SI 0 "general_operand" "=m,d") (ior:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_operand" "dKs,dmKs")))] "" "* { register int logval; if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >> 16 == 0 && (DATA_REG_P (operands[0]) || offsettable_memref_p (operands[0]))) { if (GET_CODE (operands[0]) != REG) operands[0] = adj_offsettable_operand (operands[0], 2); /* Do not delete a following tstl %0 insn; that would be incorrect. */ CC_STATUS_INIT; return \"or%.w %2,%0\"; } if (GET_CODE (operands[2]) == CONST_INT && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 && (DATA_REG_P (operands[0]) || offsettable_memref_p (operands[0]))) { if (DATA_REG_P (operands[0])) operands[1] = gen_rtx (CONST_INT, VOIDmode, logval); else { operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8)); operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8); } return \"bset %1,%0\"; } return \"or%.l %2,%0\"; }") (define_insn "iorhi3" [(set (match_operand:HI 0 "general_operand" "=m,d") (ior:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_operand" "dn,dmn")))] "" "or%.w %2,%0") (define_insn "iorqi3" [(set (match_operand:QI 0 "general_operand" "=m,d") (ior:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_operand" "dn,dmn")))] "" "or%.b %2,%0") ;; xor instructions (define_insn "xorsi3" [(set (match_operand:SI 0 "general_operand" "=do,m") (xor:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_operand" "di,dKs")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >> 16 == 0 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))) { if (! DATA_REG_P (operands[0])) operands[0] = adj_offsettable_operand (operands[0], 2); /* Do not delete a following tstl %0 insn; that would be incorrect. */ CC_STATUS_INIT; return \"eor%.w %2,%0\"; } return \"eor%.l %2,%0\"; }") (define_insn "xorhi3" [(set (match_operand:HI 0 "general_operand" "=dm") (xor:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "dn")))] "" "eor%.w %2,%0") (define_insn "xorqi3" [(set (match_operand:QI 0 "general_operand" "=dm") (xor:QI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "general_operand" "dn")))] "" "eor%.b %2,%0") ;; negation instructions (define_insn "negsi2" [(set (match_operand:SI 0 "general_operand" "=dm") (neg:SI (match_operand:SI 1 "general_operand" "0")))] "" "neg%.l %0") (define_insn "neghi2" [(set (match_operand:HI 0 "general_operand" "=dm") (neg:HI (match_operand:HI 1 "general_operand" "0")))] "" "neg%.w %0") (define_insn "negqi2" [(set (match_operand:QI 0 "general_operand" "=dm") (neg:QI (match_operand:QI 1 "general_operand" "0")))] "" "neg%.b %0") (define_insn "negsf2" [(set (match_operand:SF 0 "register_operand" "=f") (neg:SF (match_operand:SF 1 "nonimmediate_operand" "fm")))] "TARGET_CE" "fneg%.s %1,%0") (define_insn "negdf2" [(set (match_operand:DF 0 "register_operand" "=f") (neg:DF (match_operand:DF 1 "nonimmediate_operand" "fm")))] "TARGET_CE" "fneg%.d %1,%0") ;; Absolute value instructions (define_insn "abssf2" [(set (match_operand:SF 0 "register_operand" "=f") (abs:SF (match_operand:SF 1 "nonimmediate_operand" "fm")))] "TARGET_CE" "fabs%.s %1,%0") (define_insn "absdf2" [(set (match_operand:DF 0 "register_operand" "=f") (abs:DF (match_operand:DF 1 "nonimmediate_operand" "fm")))] "TARGET_CE" "fabs%.d %1,%0") ;; Square root instructions (define_insn "sqrtsf2" [(set (match_operand:SF 0 "register_operand" "=f") (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "fm")))] "TARGET_CE" "fsqrt%.s %1,%0") (define_insn "sqrtdf2" [(set (match_operand:DF 0 "register_operand" "=f") (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "fm")))] "TARGET_CE" "fsqrt%.d %1,%0") ;; one complement instructions (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "general_operand" "=dm") (not:SI (match_operand:SI 1 "general_operand" "0")))] "" "not%.l %0") (define_insn "one_cmplhi2" [(set (match_operand:HI 0 "general_operand" "=dm") (not:HI (match_operand:HI 1 "general_operand" "0")))] "" "not%.w %0") (define_insn "one_cmplqi2" [(set (match_operand:QI 0 "general_operand" "=dm") (not:QI (match_operand:QI 1 "general_operand" "0")))] "" "not%.b %0") ;; arithmetic shift instructions ;; We don't need the shift memory by 1 bit instruction (define_insn "ashlsi3" [(set (match_operand:SI 0 "general_operand" "=d") (ashift:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "dI")))] "" "asl%.l %2,%0") (define_insn "ashlhi3" [(set (match_operand:HI 0 "general_operand" "=d") (ashift:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] "" "asl%.w %2,%0") (define_insn "ashlqi3" [(set (match_operand:QI 0 "general_operand" "=d") (ashift:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] "" "asl%.b %2,%0") (define_insn "ashrsi3" [(set (match_operand:SI 0 "general_operand" "=d") (ashiftrt:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "dI")))] "" "asr%.l %2,%0") (define_insn "ashrhi3" [(set (match_operand:HI 0 "general_operand" "=d") (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] "" "asr%.w %2,%0") (define_insn "ashrqi3" [(set (match_operand:QI 0 "general_operand" "=d") (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] "" "asr%.b %2,%0") ;; logical shift instructions (define_insn "lshlsi3" [(set (match_operand:SI 0 "general_operand" "=d") (lshift:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "dI")))] "" "lsl%.l %2,%0") (define_insn "lshlhi3" [(set (match_operand:HI 0 "general_operand" "=d") (lshift:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] "" "lsl%.w %2,%0") (define_insn "lshlqi3" [(set (match_operand:QI 0 "general_operand" "=d") (lshift:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] "" "lsl%.b %2,%0") (define_insn "lshrsi3" [(set (match_operand:SI 0 "general_operand" "=d") (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "dI")))] "" "lsr%.l %2,%0") (define_insn "lshrhi3" [(set (match_operand:HI 0 "general_operand" "=d") (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] "" "lsr%.w %2,%0") (define_insn "lshrqi3" [(set (match_operand:QI 0 "general_operand" "=d") (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] "" "lsr%.b %2,%0") ;; rotate instructions (define_insn "rotlsi3" [(set (match_operand:SI 0 "general_operand" "=d") (rotate:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "dI")))] "" "rol%.l %2,%0") (define_insn "rotlhi3" [(set (match_operand:HI 0 "general_operand" "=d") (rotate:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] "" "rol%.w %2,%0") (define_insn "rotlqi3" [(set (match_operand:QI 0 "general_operand" "=d") (rotate:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] "" "rol%.b %2,%0") (define_insn "rotrsi3" [(set (match_operand:SI 0 "general_operand" "=d") (rotatert:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "dI")))] "" "ror%.l %2,%0") (define_insn "rotrhi3" [(set (match_operand:HI 0 "general_operand" "=d") (rotatert:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] "" "ror%.w %2,%0") (define_insn "rotrqi3" [(set (match_operand:QI 0 "general_operand" "=d") (rotatert:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] "" "ror%.b %2,%0") ;; Special cases of bit-field insns which we should ;; recognize in preference to the general case. ;; These handle aligned 8-bit and 16-bit fields, ;; which can usually be done with move instructions. (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do") (match_operand:SI 1 "const_int_operand" "i") (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 3 "general_operand" "d"))] "TARGET_68020 && TARGET_BITFIELD && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 && (GET_CODE (operands[0]) == REG || ! mode_dependent_address_p (XEXP (operands[0], 0)))" "* { if (REG_P (operands[0])) { if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32) return \"bfins %3,[%c2,%c1]%0\"; } else operands[0] = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8); if (GET_CODE (operands[3]) == MEM) operands[3] = adj_offsettable_operand (operands[3], (32 - INTVAL (operands[1])) / 8); if (INTVAL (operands[1]) == 8) return \"mov%.b %3,%0\"; return \"mov%.w %3,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=&d") (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do") (match_operand:SI 2 "const_int_operand" "i") (match_operand:SI 3 "const_int_operand" "i")))] "TARGET_68020 && TARGET_BITFIELD && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 && (GET_CODE (operands[1]) == REG || ! mode_dependent_address_p (XEXP (operands[1], 0)))" "* { if (REG_P (operands[1])) { if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) return \"bfextu [%c3,%c2]%1,%0\"; } else operands[1] = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); output_asm_insn (\"clrl %0\", operands); if (GET_CODE (operands[0]) == MEM) operands[0] = adj_offsettable_operand (operands[0], (32 - INTVAL (operands[1])) / 8); if (INTVAL (operands[2]) == 8) return \"mov%.b %1,%0\"; return \"mov%.w %1,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d") (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do") (match_operand:SI 2 "const_int_operand" "i") (match_operand:SI 3 "const_int_operand" "i")))] "TARGET_68020 && TARGET_BITFIELD && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 && (GET_CODE (operands[1]) == REG || ! mode_dependent_address_p (XEXP (operands[1], 0)))" "* { if (REG_P (operands[1])) { if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) return \"bfexts [%c3,%c2]%1,%0\"; } else operands[1] = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); if (INTVAL (operands[2]) == 8) return \"mov%.b %1,%0\;extb%.l %0\"; return \"mov%.w %1,%0\;ext%.l %0\"; }") ;; Bit field instructions, general cases. ;; "o,d" constraint causes a nonoffsettable memref to match the "o" ;; so that its address is reloaded. (define_insn "extv" [(set (match_operand:SI 0 "general_operand" "=d,d") (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d") (match_operand:SI 2 "general_operand" "di,di") (match_operand:SI 3 "general_operand" "di,di")))] "TARGET_68020 && TARGET_BITFIELD" "bfexts [%c3,%c2]%1,%0") (define_insn "extzv" [(set (match_operand:SI 0 "general_operand" "=d,d") (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d") (match_operand:SI 2 "general_operand" "di,di") (match_operand:SI 3 "general_operand" "di,di")))] "TARGET_68020 && TARGET_BITFIELD" "bfextu [%c3,%c2]%1,%0") (define_insn "" [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") (match_operand:SI 1 "general_operand" "di,di") (match_operand:SI 2 "general_operand" "di,di")) (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2)) (match_operand:SI 3 "const_int_operand" "i,i")))] "TARGET_68020 && TARGET_BITFIELD && (INTVAL (operands[3]) == -1 || (GET_CODE (operands[1]) == CONST_INT && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))" "* { CC_STATUS_INIT; return \"bfchg [%c2,%c1]%0\"; }") (define_insn "" [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") (match_operand:SI 1 "general_operand" "di,di") (match_operand:SI 2 "general_operand" "di,di")) (const_int 0))] "TARGET_68020 && TARGET_BITFIELD" "* { CC_STATUS_INIT; return \"bfclr [%c2,%c1]%0\"; }") (define_insn "" [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") (match_operand:SI 1 "general_operand" "di,di") (match_operand:SI 2 "general_operand" "di,di")) (const_int -1))] "TARGET_68020 && TARGET_BITFIELD" "* { CC_STATUS_INIT; return \"bfset [%c2,%c1]%0\"; }") (define_insn "insv" [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") (match_operand:SI 1 "general_operand" "di,di") (match_operand:SI 2 "general_operand" "di,di")) (match_operand:SI 3 "general_operand" "d,d"))] "TARGET_68020 && TARGET_BITFIELD" "bfins %3,[%c2,%c1]%0") ;; Now recognize bit field insns that operate on registers ;; (or at least were intended to do so). (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d") (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d") (match_operand:SI 2 "general_operand" "di") (match_operand:SI 3 "general_operand" "di")))] "TARGET_68020 && TARGET_BITFIELD" "bfexts [%c3,%c2]%1,%0") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d") (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d") (match_operand:SI 2 "general_operand" "di") (match_operand:SI 3 "general_operand" "di")))] "TARGET_68020 && TARGET_BITFIELD" "bfextu [%c3,%c2]%1,%0") (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d") (match_operand:SI 1 "general_operand" "di") (match_operand:SI 2 "general_operand" "di")) (const_int 0))] "TARGET_68020 && TARGET_BITFIELD" "* { CC_STATUS_INIT; return \"bfclr [%c2,%c1]%0\"; }") (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d") (match_operand:SI 1 "general_operand" "di") (match_operand:SI 2 "general_operand" "di")) (const_int -1))] "TARGET_68020 && TARGET_BITFIELD" "* { CC_STATUS_INIT; return \"bfset [%c2,%c1]%0\"; }") (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d") (match_operand:SI 1 "general_operand" "di") (match_operand:SI 2 "general_operand" "di")) (match_operand:SI 3 "general_operand" "d"))] "TARGET_68020 && TARGET_BITFIELD" "* { return \"bfins %3,[%c2,%c1]%0\"; }") ;; Special patterns for optimizing bit-field instructions. (define_insn "" [(set (cc0) (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") (match_operand:SI 1 "const_int_operand" "i") (match_operand:SI 2 "general_operand" "di")))] "TARGET_68020 && TARGET_BITFIELD" "* { if (operands[1] == const1_rtx && GET_CODE (operands[2]) == CONST_INT) { int width = GET_CODE (operands[0]) == REG ? 31 : 7; return output_btst (operands, gen_rtx (CONST_INT, VOIDmode, width - INTVAL (operands[2])), operands[0], insn, 1000); /* Pass 1000 as SIGNPOS argument so that btst will not think we are testing the sign bit for an `and' and assume that nonzero implies a negative result. */ } if (INTVAL (operands[1]) != 32) cc_status.flags = CC_NOT_NEGATIVE; return \"bftst [%c2,%c1]%0\"; }") ;;; now handle the register cases (define_insn "" [(set (cc0) (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d") (match_operand:SI 1 "const_int_operand" "i") (match_operand:SI 2 "general_operand" "di")))] "TARGET_68020 && TARGET_BITFIELD" "* { if (operands[1] == const1_rtx && GET_CODE (operands[2]) == CONST_INT) { int width = GET_CODE (operands[0]) == REG ? 31 : 7; return output_btst (operands, gen_rtx (CONST_INT, VOIDmode, width - INTVAL (operands[2])), operands[0], insn, 1000); /* Pass 1000 as SIGNPOS argument so that btst will not think we are testing the sign bit for an `and' and assume that nonzero implies a negative result. */ } if (INTVAL (operands[1]) != 32) cc_status.flags = CC_NOT_NEGATIVE; return \"bftst [%c2,%c1]%0\"; }") (define_insn "seq" [(set (match_operand:QI 0 "general_operand" "=d") (eq:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\"); ") (define_insn "sne" [(set (match_operand:QI 0 "general_operand" "=d") (ne:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"sne %0\", \"fsneq %0\", \"sne %0\"); ") (define_insn "sgt" [(set (match_operand:QI 0 "general_operand" "=d") (gt:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", \"and%.b %#0xc,%!\;sgt %0\"); ") (define_insn "sgtu" [(set (match_operand:QI 0 "general_operand" "=d") (gtu:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; return \"shi %0\"; ") (define_insn "slt" [(set (match_operand:QI 0 "general_operand" "=d") (lt:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ") (define_insn "sltu" [(set (match_operand:QI 0 "general_operand" "=d") (ltu:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; return \"scs %0\"; ") (define_insn "sge" [(set (match_operand:QI 0 "general_operand" "=d") (ge:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ") (define_insn "sgeu" [(set (match_operand:QI 0 "general_operand" "=d") (geu:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; return \"scc %0\"; ") (define_insn "sle" [(set (match_operand:QI 0 "general_operand" "=d") (le:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"sle %0\", \"fsle %0\", \"and%.b %#0xc,%!\;sle %0\"); ") (define_insn "sleu" [(set (match_operand:QI 0 "general_operand" "=d") (leu:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; return \"sls %0\"; ") ;; Basic conditional jump instructions. (define_insn "beq" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { OUTPUT_JUMP (\"jeq %l0\", \"fbeq %l0\", \"jeq %l0\"); }") (define_insn "bne" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { OUTPUT_JUMP (\"jne %l0\", \"fbneq %l0\", \"jne %l0\"); }") (define_insn "bgt" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* OUTPUT_JUMP (\"jgt %l0\", \"fbgt %l0\", \"and%.b %#0xc,%!\;jgt %l0\"); ") (define_insn "bgtu" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return \"jhi %l0\"; ") (define_insn "blt" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* OUTPUT_JUMP (\"jlt %l0\", \"fblt %l0\", \"jmi %l0\"); ") (define_insn "bltu" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return \"jcs %l0\"; ") (define_insn "bge" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* OUTPUT_JUMP (\"jge %l0\", \"fbge %l0\", \"jpl %l0\"); ") (define_insn "bgeu" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return \"jcc %l0\"; ") (define_insn "ble" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* OUTPUT_JUMP (\"jle %l0\", \"fble %l0\", \"and%.b %#0xc,%!\;jle %l0\"); ") (define_insn "bleu" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* return \"jls %l0\"; ") ;; Negated conditional jump instructions. (define_insn "" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { OUTPUT_JUMP (\"jne %l0\", \"fbneq %l0\", \"jne %l0\"); }") (define_insn "" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { OUTPUT_JUMP (\"jeq %l0\", \"fbeq %l0\", \"jeq %l0\"); }") (define_insn "" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* OUTPUT_JUMP (\"jle %l0\", \"fbngt %l0\", \"and%.b %#0xc,%!\;jle %l0\"); ") (define_insn "" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return \"jls %l0\"; ") (define_insn "" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* OUTPUT_JUMP (\"jge %l0\", \"fbnlt %l0\", \"jpl %l0\"); ") (define_insn "" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return \"jcc %l0\"; ") (define_insn "" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* OUTPUT_JUMP (\"jlt %l0\", \"fbnge %l0\", \"jmi %l0\"); ") (define_insn "" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return \"jcs %l0\"; ") (define_insn "" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* OUTPUT_JUMP (\"jgt %l0\", \"fbnle %l0\", \"and%.b %#0xc,%!\;jgt %l0\"); ") (define_insn "" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* return \"jhi %l0\"; ") ;; Subroutines of "casesi". (define_expand "casesi_1" [(set (match_operand:SI 3 "general_operand" "") (plus:SI (match_operand:SI 0 "general_operand" "") ;; Note operand 1 has been negated! (match_operand:SI 1 "immediate_operand" ""))) (set (cc0) (compare (match_operand:SI 2 "nonimmediate_operand" "") (match_dup 3))) (set (pc) (if_then_else (ltu (cc0) (const_int 0)) (label_ref (match_operand 4 "" "")) (pc)))] "" "") (define_expand "casesi_2" [(set (match_operand:SI 0 "" "") (mem:HI (match_operand:SI 1 "" ""))) ;; The USE here is so that at least one jump-insn will refer to the label, ;; to keep it alive in jump_optimize. (parallel [(set (pc) (plus:SI (pc) (match_dup 0))) (use (label_ref (match_operand 2 "" "")))])] "" "") ;; Operand 0 is index (in bytes); operand 1 is minimum, operand 2 the maximum; ;; operand 3 is CODE_LABEL for the table; ;; operand 4 is the CODE_LABEL to go to if index out of range. (define_expand "casesi" ;; We don't use these for generating the RTL, but we must describe ;; the operands here. [(match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "immediate_operand" "") (match_operand:SI 2 "general_operand" "") (match_operand 3 "" "") (match_operand 4 "" "")] "" " { rtx table_elt_addr; rtx index_diff; operands[1] = negate_rtx (SImode, operands[1]); index_diff = gen_reg_rtx (SImode); /* Emit the first few insns. */ emit_insn (gen_casesi_1 (operands[0], operands[1], operands[2], index_diff, operands[4])); /* Construct a memory address. This may emit some insns. */ table_elt_addr = memory_address_noforce (HImode, gen_rtx (PLUS, Pmode, gen_rtx (MULT, Pmode, index_diff, gen_rtx (CONST_INT, VOIDmode, 2)), gen_rtx (LABEL_REF, VOIDmode, operands[3]))); /* Emit the last few insns. */ emit_insn (gen_casesi_2 (gen_reg_rtx (HImode), table_elt_addr, operands[3])); DONE; }") ;; Recognize one of the insns resulting from casesi_2. (define_insn "" [(set (pc) (plus:SI (pc) (match_operand:HI 0 "general_operand" "r"))) (use (label_ref (match_operand 1 "" "")))] "" "* return \"jmp pc@(2:B)[%0:W:B]\"; ") ;; Unconditional and other jump instructions (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "* return \"jra %l0\"; ") (define_insn "" [(set (pc) (if_then_else (ne (match_operand:HI 0 "general_operand" "d,m,g") (const_int 0)) (label_ref (match_operand 1 "" "")) (pc))) (set (match_dup 0) (plus:HI (match_dup 0) (const_int -1)))] "" "@ dbra %0,%l1 subq%.w %#1,%0\;jcc %l1 subq%.w %#1,%0\;cmp%.w %#-1,%0\;jne %l1") (define_insn "" [(set (pc) (if_then_else (ne (match_operand:SI 0 "general_operand" "d,m,g") (const_int 0)) (label_ref (match_operand 1 "" "")) (pc))) (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))] "" "@ dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jcc %l1 subq%.l %#1,%0\;jcc %l1 subq%.l %#1,%0\;cmp%.l %#-1,%0\;jne %l1") ;; dbra patterns that use REG_NOTES info generated by strength_reduce. (define_insn "decrement_and_branch_until_zero" [(set (pc) (if_then_else (ge (match_operand:SI 0 "general_operand" "d,m,g") (const_int 1)) (label_ref (match_operand 1 "" "")) (pc))) (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))] "find_reg_note (insn, REG_NONNEG, 0)" "@ dbra %0,%l1\;clrw %0\;subql %#1,%0\;jcc %l1 subq%.l %#1,%0\;jcc %l1 subq%.l %#1,%0\;cmp%.l %#-1,%0\;jne %l1") ;; Call subroutine with no return value. (define_insn "call" [(call (match_operand:QI 0 "memory_operand" "o") (match_operand:SI 1 "general_operand" "g"))] "" "* { rtx xoperands[2]; int size = XINT(operands[1],0); if (size == 0) output_asm_insn (\"sub%.l a0,a0\;jbsr %0\", operands); else { xoperands[1] = gen_rtx (CONST_INT, VOIDmode, size/4); output_asm_insn (\"mov%.l sp,a0\;pea %a1\", xoperands); output_asm_insn (\"jbsr %0\", operands); size = size + 4; xoperands[1] = gen_rtx (CONST_INT, VOIDmode, size); if (size <= 8) output_asm_insn (\"addq%.l %1,sp\", xoperands); else if (size < 0x8000) output_asm_insn (\"add%.w %1,sp\", xoperands); else output_asm_insn (\"add%.l %1,sp\", xoperands); } return \"mov%.l a6@(-4),a0\"; }") ;; Call subroutine, returning value in operand 0 ;; (which must be a hard register). (define_insn "call_value" [(set (match_operand 0 "" "=rf") (call (match_operand:QI 1 "memory_operand" "o") (match_operand:SI 2 "general_operand" "g")))] "" "* { rtx xoperands[3]; int size = XINT(operands[2],0); if (size == 0) output_asm_insn(\"sub%.l a0,a0\;jbsr %1\", operands); else { xoperands[2] = gen_rtx (CONST_INT, VOIDmode, size/4); output_asm_insn (\"mov%.l sp,a0\;pea %a2\", xoperands); output_asm_insn (\"jbsr %1\", operands); size = size + 4; xoperands[2] = gen_rtx (CONST_INT, VOIDmode, size); if (size <= 8) output_asm_insn (\"addq%.l %2,sp\", xoperands); else if (size < 0x8000) output_asm_insn (\"add%.w %2,sp\", xoperands); else output_asm_insn (\"add%.l %2,sp\", xoperands); } return \"mov%.l a6@(-4),a0\"; }") ;; Call subroutine returning any type. (define_expand "untyped_call" [(parallel [(call (match_operand 0 "" "") (const_int 0)) (match_operand 1 "" "") (match_operand 2 "" "")])] "" " { int i; emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); for (i = 0; i < XVECLEN (operands[2], 0); i++) { rtx set = XVECEXP (operands[2], 0, i); emit_move_insn (SET_DEST (set), SET_SRC (set)); } /* The optimizer does not know that the call sets the function value registers we stored in the result block. We avoid problems by claiming that all hard registers are used and clobbered at this point. */ emit_insn (gen_blockage ()); DONE; }") ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and ;; all of memory. This blocks insns from being moved across this point. (define_insn "blockage" [(unspec_volatile [(const_int 0)] 0)] "" "") (define_insn "nop" [(const_int 0)] "" "nop") ;; This should not be used unless the add/sub insns can't be. (define_insn "" [(set (match_operand:SI 0 "general_operand" "=a") (match_operand:QI 1 "address_operand" "p"))] "" "lea %a1,%0") ;; This is the first machine-dependent peephole optimization. ;; It is useful when a floating value is returned from a function call ;; and then is moved into an FP register. ;; But it is mainly intended to test the support for these optimizations. ;Not applicable to Alliant -- floating results are returned in fp0 ;(define_peephole ; [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) ; (set (match_operand:DF 0 "register_operand" "f") ; (match_operand:DF 1 "register_operand" "ad"))] ; "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" ; "* ;{ ; rtx xoperands[2]; ; xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); ; output_asm_insn (\"mov%.l %1,%@\", xoperands); ; output_asm_insn (\"mov%.l %1,%-\", operands); ; return \"fmove%.d %+,%0\"; ;} ;") gcc-2.5.8/config/fx80/xm-fx80.h100444 22011 13 2433 5413066736 14411 0ustar kenneruser/* Configuration for GNU C-compiler for Alliant FX computers. Copyright (C) 1989, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* #defines that need visibility everywhere. */ #define FALSE 0 #define TRUE 1 /* This describes the machine the compiler is hosted on. */ #define HOST_BITS_PER_CHAR 8 #define HOST_BITS_PER_SHORT 16 #define HOST_BITS_PER_INT 32 #define HOST_BITS_PER_LONG 32 #define HOST_BITS_PER_LONGLONG 64 /* target machine dependencies. tm.h is a symbolic link to the actual target specific file. */ #include "tm.h" /* Arguments to use with `exit'. */ #define SUCCESS_EXIT_CODE 0 #define FATAL_EXIT_CODE 33 gcc-2.5.8/config/gmicro/ 40777 22011 13 0 5502602741 13422 5ustar kennerusergcc-2.5.8/config/gmicro/gmicro.c100444 22011 13 50372 5235132072 15162 0ustar kenneruser/* Subroutines for insn-output.c for the Gmicro. Ported by Masanobu Yuhara, Fujitsu Laboratories LTD. (yuhara@flab.fujitsu.co.jp) Copyright (C) 1990, 1991 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. Among other things, the copyright notice and this notice must be preserved on all copies. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include "config.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "output.h" #include "insn-attr.h" extern char *rtx_name[]; mypr (s, a1, a2, a3, a4, a5) char *s; int a1, a2, a3, a4, a5; { fprintf (stderr, s, a1, a2, a3, a4, a5); } myprcode (i) int i; { if (i < 0 || i > 90) fprintf (stderr, "code = %d\n", i); else fprintf (stderr, "code = %s\n", rtx_name[i]); } myabort (i) int i; { fprintf (stderr, "myabort"); myprcode (i); } /* This is how to output an ascii string. */ /* See ASM_OUTPUT_ASCII in gmicro.h. */ output_ascii (file, p, size) FILE *file; char *p; int size; { int i; int in_quote = 0; register int c; fprintf (file, "\t.sdata "); for (i = 0; i < size; i++) { c = p[i]; if (c >= ' ' && c < 0x7f) { if (!in_quote) { putc ('"', file); in_quote = 1; } putc (c, file); } else { if (in_quote) { putc ('"', file); in_quote = 0; } fprintf (file, "<%d>", c); } } if (in_quote) putc ('"', file); putc ('\n', file); } /* call this when GET_CODE (index) is MULT. */ print_scaled_index (file, index) FILE *file; register rtx index; { register rtx ireg; int scale; if (GET_CODE (XEXP (index, 0)) == REG) { ireg = XEXP (index, 0); scale = INTVAL (XEXP (index, 1)); } else { ireg = XEXP (index, 1); scale = INTVAL (XEXP (index, 0)); } if (scale == 1) fprintf (file, "%s", reg_names[REGNO (ireg)]); else fprintf (file, "%s*%d", reg_names[REGNO (ireg)], scale); } print_operand_address (file, addr) FILE *file; register rtx addr; { register rtx xtmp0, xtmp1, breg, ixreg; int scale; int needcomma = 0; rtx offset; fprintf (file, "@"); retry: switch (GET_CODE (addr)) { case MEM: fprintf (file, "@"); addr = XEXP (addr, 0); goto retry; case REG: fprintf (file, "%s", reg_names[REGNO (addr)]); break; case MULT: print_scaled_index (file, addr); break; case PRE_DEC: fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]); break; case POST_INC: fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]); break; case PLUS: xtmp0 = XEXP (addr, 0); xtmp1 = XEXP (addr, 1); ixreg = 0; breg = 0; offset = 0; if (CONSTANT_ADDRESS_P (xtmp0)) { offset = xtmp0; breg = xtmp1; } else if (CONSTANT_ADDRESS_P (xtmp1)) { offset = xtmp1; breg = xtmp0; } else { goto NOT_DISP; } if (REG_CODE_BASE_P (breg)) goto PRINT_MEM; if (GET_CODE (breg) == MULT) { if (REG_CODE_INDEX_P (XEXP (breg, 0))) { ixreg = XEXP (breg, 0); scale = INTVAL (XEXP (breg, 1)); breg = 0; } else { ixreg = XEXP (breg, 1); scale = INTVAL (XEXP (breg, 0)); breg = 0; } goto PRINT_MEM; } /* GET_CODE (breg) must be PLUS here. */ xtmp0 = XEXP (breg, 0); xtmp1 = XEXP (breg, 1); if (REG_CODE_BASE_P (xtmp0)) { breg = xtmp0; xtmp0 = xtmp1; } else { breg = xtmp1; /* xtmp0 = xtmp0; */ } if (GET_CODE (xtmp0) == MULT) { if (REG_CODE_INDEX_P (XEXP (xtmp0, 0))) { ixreg = XEXP (xtmp0, 0); scale = INTVAL (XEXP (xtmp0, 1)); } else { ixreg = XEXP (xtmp0, 1); scale = INTVAL (XEXP (xtmp0, 0)); } } else { ixreg = xtmp0; scale = 1; } goto PRINT_MEM; NOT_DISP: if (REG_CODE_BASE_P (xtmp0)) { breg = xtmp0; xtmp0 = xtmp1; } else if (REG_CODE_BASE_P (xtmp1)) { breg = xtmp1; /* xtmp0 = xtmp0; */ } else goto NOT_BASE; if (REG_CODE_INDEX_P (xtmp0)) { ixreg = xtmp0; scale = 1; goto PRINT_MEM; } else if (CONSTANT_ADDRESS_P (xtmp0)) { offset = xtmp0; goto PRINT_MEM; } else if (GET_CODE (xtmp0) == MULT) { if (REG_CODE_INDEX_P (XEXP (xtmp0, 0))) { ixreg = XEXP (xtmp0, 0); scale = INTVAL (XEXP (xtmp0, 1)); } else { ixreg = XEXP (xtmp0, 1); scale = INTVAL (XEXP (xtmp0, 0)); } goto PRINT_MEM; } /* GET_CODE (xtmp0) must be PLUS. */ xtmp1 = XEXP (xtmp0, 1); xtmp0 = XEXP (xtmp0, 0); if (CONSTANT_ADDRESS_P (xtmp0)) { offset = xtmp0; xtmp0 = xtmp1; } else { offset = xtmp1; /* xtmp0 = xtmp0; */ } if (REG_CODE_INDEX_P (xtmp0)) { ixreg = xtmp0; } else { /* GET_CODE (xtmp0) must be MULT. */ if (REG_CODE_INDEX_P (XEXP (xtmp0, 0))) { ixreg = XEXP (xtmp0, 0); scale = INTVAL (XEXP (xtmp0, 1)); } else { ixreg = XEXP (xtmp0, 1); scale = INTVAL (XEXP (xtmp0, 0)); } } goto PRINT_MEM; NOT_BASE: if (GET_CODE (xtmp0) == PLUS) { ixreg = xtmp1; /* xtmp0 = xtmp0; */ } else { ixreg = xtmp0; xtmp0 = xtmp1; } if (REG_CODE_INDEX_P (ixreg)) { scale = 1; } else if (REG_CODE_INDEX_P (XEXP (ixreg, 0))) { scale = INTVAL (XEXP (ixreg, 1)); ixreg = XEXP (ixreg, 0); } else { /* was else if with no condition. OK ??? */ scale = INTVAL (XEXP (ixreg, 0)); ixreg = XEXP (ixreg, 1); } if (REG_CODE_BASE_P (XEXP (xtmp0, 0))) { breg = XEXP (xtmp0, 0); offset = XEXP (xtmp0, 1); } else { breg = XEXP (xtmp0, 1); offset = XEXP (xtmp0, 0); } PRINT_MEM: if (breg == 0 && ixreg == 0) { output_address (offset); break; } else if (ixreg == 0 && offset == 0) { fprintf (file, "%s", reg_names[REGNO (breg)]); break; } else { fprintf (file, "("); if (offset != 0) { output_addr_const (file, offset); needcomma = 1; } if (breg != 0) { if (needcomma) fprintf (file, ","); fprintf (file, "%s", reg_names[REGNO (breg)]); needcomma = 1; } if (ixreg != 0) { if (needcomma) fprintf (file, ","); fprintf (file, "%s", reg_names[REGNO (ixreg)]); if (scale != 1) fprintf (file,"*%d", scale); } fprintf (file, ")"); break; } default: output_addr_const (file, addr); } } /* Return a REG that occurs in ADDR with coefficient 1. ADDR can be effectively incremented by incrementing REG. */ static rtx find_addr_reg (addr) rtx addr; { while (GET_CODE (addr) == PLUS) { if (GET_CODE (XEXP (addr, 0)) == REG) addr = XEXP (addr, 0); else if (GET_CODE (XEXP (addr, 1)) == REG) addr = XEXP (addr, 1); else if (GET_CODE (XEXP (addr, 0)) == PLUS) addr = XEXP (addr, 0); else if (GET_CODE (XEXP (addr, 1)) == PLUS) addr = XEXP (addr, 1); } if (GET_CODE (addr) == REG) return addr; return 0; } /* Return the best assembler insn template for moving operands[1] into operands[0] as a fullword. */ static char * singlemove_string (operands) rtx *operands; { if (FPU_REG_P (operands[0]) || FPU_REG_P (operands[1])) { if (GREG_P (operands[0]) || GREG_P (operands[1])) { myabort (101); /* Not Supported yet !! */ } else { return "fmov.s %1,%0"; } } return "mov.w %1,%0"; } /* Output assembler code to perform a doubleword move insn with operands OPERANDS. */ char * output_move_double (operands) rtx *operands; { enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1; rtx latehalf[2]; rtx addreg0 = 0, addreg1 = 0; /* First classify both operands. */ if (REG_P (operands[0])) optype0 = REGOP; else if (offsettable_memref_p (operands[0])) optype0 = OFFSOP; else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) optype0 = POPOP; else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) optype0 = PUSHOP; else if (GET_CODE (operands[0]) == MEM) optype0 = MEMOP; else optype0 = RNDOP; if (REG_P (operands[1])) optype1 = REGOP; else if (CONSTANT_P (operands[1])) optype1 = CNSTOP; else if (offsettable_memref_p (operands[1])) optype1 = OFFSOP; else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) optype1 = POPOP; else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) optype1 = PUSHOP; else if (GET_CODE (operands[1]) == MEM) optype1 = MEMOP; else optype1 = RNDOP; /* Check for the cases that the operand constraints are not supposed to allow to happen. Abort if we get one, because generating code for these cases is painful. */ if (optype0 == RNDOP || optype1 == RNDOP) myabort (102); /* If one operand is decrementing and one is incrementing decrement the former register explicitly and change that operand into ordinary indexing. */ if (optype0 == PUSHOP && optype1 == POPOP) { operands[0] = XEXP (XEXP (operands[0], 0), 0); output_asm_insn ("sub.w %#8,%0", operands); operands[0] = gen_rtx (MEM, DImode, operands[0]); optype0 = OFFSOP; } if (optype0 == POPOP && optype1 == PUSHOP) { operands[1] = XEXP (XEXP (operands[1], 0), 0); output_asm_insn ("sub.w %#8,%1", operands); operands[1] = gen_rtx (MEM, DImode, operands[1]); optype1 = OFFSOP; } /* If an operand is an unoffsettable memory ref, find a register we can increment temporarily to make it refer to the second word. */ if (optype0 == MEMOP) addreg0 = find_addr_reg (operands[0]); if (optype1 == MEMOP) addreg1 = find_addr_reg (operands[1]); /* Ok, we can do one word at a time. Normally we do the low-numbered word first, but if either operand is autodecrementing then we do the high-numbered word first. In either case, set up in LATEHALF the operands to use for the high-numbered word and in some cases alter the operands in OPERANDS to be suitable for the low-numbered word. */ if (optype0 == REGOP) latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); else if (optype0 == OFFSOP) latehalf[0] = adj_offsettable_operand (operands[0], 4); else latehalf[0] = operands[0]; if (optype1 == REGOP) latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); else if (optype1 == OFFSOP) latehalf[1] = adj_offsettable_operand (operands[1], 4); else if (optype1 == CNSTOP) { if (GET_CODE (operands[1]) == CONST_DOUBLE) split_double (operands[1], &operands[1], &latehalf[1]); else if (CONSTANT_P (operands[1])) latehalf[1] = const0_rtx; } else latehalf[1] = operands[1]; /* If insn is effectively movd N(sp),-(sp) then we will do the high word first. We should use the adjusted operand 1 (which is N+4(sp)) for the low word as well, to compensate for the first decrement of sp. */ if (optype0 == PUSHOP && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) operands[1] = latehalf[1]; /* If one or both operands autodecrementing, do the two words, high-numbered first. */ /* Likewise, the first move would clobber the source of the second one, do them in the other order. This happens only for registers; such overlap can't happen in memory unless the user explicitly sets it up, and that is an undefined circumstance. */ if (optype0 == PUSHOP || optype1 == PUSHOP || (optype0 == REGOP && optype1 == REGOP && REGNO (operands[0]) == REGNO (latehalf[1]))) { /* Make any unoffsettable addresses point at high-numbered word. */ if (addreg0) output_asm_insn ("add.w %#4,%0", &addreg0); if (addreg1) output_asm_insn ("add.w %#4,%0", &addreg1); /* Do that word. */ output_asm_insn (singlemove_string (latehalf), latehalf); /* Undo the adds we just did. */ if (addreg0) output_asm_insn ("sub.w %#4,%0", &addreg0); if (addreg1) output_asm_insn ("sub.w %#4,%0", &addreg1); /* Do low-numbered word. */ return singlemove_string (operands); } /* Normal case: do the two words, low-numbered first. */ output_asm_insn (singlemove_string (operands), operands); /* Make any unoffsettable addresses point at high-numbered word. */ if (addreg0) output_asm_insn ("add.w %#4,%0", &addreg0); if (addreg1) output_asm_insn ("add.w %#4,%0", &addreg1); /* Do that word. */ output_asm_insn (singlemove_string (latehalf), latehalf); /* Undo the adds we just did. */ if (addreg0) output_asm_insn ("sub.w %#4,%0", &addreg0); if (addreg1) output_asm_insn ("sub.w %#4,%0", &addreg1); return ""; } /* Move const_double to floating point register (DF) */ char * output_move_const_double (operands) rtx *operands; { int code = standard_fpu_constant_p (operands[1]); if (FPU_REG_P (operands[0])) { if (code != 0) { static char buf[40]; sprintf (buf, "fmvr from%d,%%0.d", code); return buf; } else { return "fmov %1,%0.d"; } } else if (GREG_P (operands[0])) { rtx xoperands[2]; xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); xoperands[1] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_HIGH (operands[1])); output_asm_insn ("mov.w %1,%0", xoperands); operands[1] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (operands[1])); return "mov.w %1,%0"; } else { return output_move_double (operands); /* ?????? */ } } char * output_move_const_single (operands) rtx *operands; { int code = standard_fpu_constant_p (operands[1]); static char buf[40]; if (FPU_REG_P (operands[0])) { if (code != 0) { sprintf (buf, "fmvr from%d,%%0.s", code); return buf; } return "fmov.s %f1,%0"; } else return "mov.w %f1,%0"; } /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get from the "fmvr" instruction of the Gmicro FPU. The value, anded with 0xff, gives the code to use in fmovecr to get the desired constant. */ u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x); d = u.d; if (d == 0.0) /* +0.0 */ return 0x0; /* Note: there are various other constants available but it is a nuisance to put in their values here. */ if (d == 1.0) /* +1.0 */ return 0x1; /* * Stuff that looks different if it's single or double */ if (GET_MODE (x) == SFmode) { if (d == S_PI) return 0x2; if (d == (S_PI / 2.0)) return 0x3; if (d == S_E) return 0x4; if (d == S_LOGEof2) return 0x5; if (d == S_LOGEof10) return 0x6; if (d == S_LOG10of2) return 0x7; if (d == S_LOG10ofE) return 0x8; if (d == S_LOG2ofE) return 0x9; } else { if (d == D_PI) return 0x2; if (d == (D_PI / 2.0)) return 0x3; if (d == D_E) return 0x4; if (d == D_LOGEof2) return 0x5; if (d == D_LOGEof10) return 0x6; if (d == D_LOG10of2) return 0x7; if (d == D_LOG10ofE) return 0x8; if (d == D_LOG2ofE) return 0x9; } return 0; } #undef S_PI #undef D_PI #undef S_E #undef D_E #undef S_LOGEof2 #undef D_LOGEof2 #undef S_LOGEof10 #undef D_LOGEof10 #undef S_LOG10of2 #undef D_LOG10of2 #undef S_LOG10ofE #undef D_LOG10ofE #undef S_LOG2ofE #undef D_LOG2ofE /* dest should be operand 0 */ /* imm should be operand 1 */ extern char *sub_imm_word (); char * add_imm_word (imm, dest, immp) int imm; rtx dest, *immp; { int is_reg, short_ok; if (imm < 0) { *immp = gen_rtx (CONST_INT, VOIDmode, -imm); return sub_imm_word (-imm, dest); } if (imm == 0) return "mov:l.w #0,%0"; short_ok = short_format_ok (dest); if (short_ok && imm <= 8) return "add:q %1,%0.w"; if (imm < 128) return "add:e %1,%0.w"; is_reg = (GET_CODE (dest) == REG); if (is_reg) return "add:l %1,%0.w"; if (short_ok) return "add:i %1,%0.w"; return "add %1,%0.w"; } char * sub_imm_word (imm, dest, immp) int imm; rtx dest, *immp; { int is_reg, short_ok; if (imm < 0 && imm != 0x80000000) { *immp = gen_rtx (CONST_INT, VOIDmode, -imm); return add_imm_word (-imm, dest); } if (imm == 0) return "mov:z.w #0,%0"; short_ok = short_format_ok (dest); if (short_ok && imm <= 8) return "sub:q %1,%0.w"; if (imm < 128) return "sub:e %1,%0.w"; is_reg = (GET_CODE (dest) == REG); if (is_reg) return "sub:l %1,%0.w"; if (short_ok) return "sub:i %1,%0.w"; return "sub %1,%0.w"; } int short_format_ok (x) rtx x; { rtx x0, x1; if (GET_CODE (x) == REG) return 1; if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PLUS) { x0 = XEXP (XEXP (x, 0), 0); x1 = XEXP (XEXP (x, 0), 1); return ((GET_CODE (x0) == REG && CONSTANT_P (x1) && ((unsigned) (INTVAL (x1) + 0x8000) < 0x10000)) || (GET_CODE (x1) == REG && CONSTANT_P (x0) && ((unsigned) (INTVAL (x0) + 0x8000) < 0x10000))); } return 0; } myoutput_sp_adjust (file, op, fsize) FILE *file; char *op; int fsize; { if (fsize == 0) ; else if (fsize < 8) fprintf (file, "\t%s:q #%d,sp.w\n", op, fsize); else if (fsize < 128) fprintf (file, "\t%s:e #%d,sp.w\n", op, fsize); else fprintf (file, "\t%s:l #%d,sp.w\n", op, fsize); } char * mov_imm_word (imm, dest) int imm; rtx dest; { int is_reg, short_ok; if (imm == 0) return "mov:z.w #0,%0"; short_ok = short_format_ok (dest); if (short_ok && imm > 0 && imm <= 8) return "mov:q %1,%0.w"; if (-128 <= imm && imm < 128) return "mov:e %1,%0.w"; is_reg = (GET_CODE (dest) == REG); if (is_reg) return "mov:l %1,%0.w"; if (short_ok) return "mov:i %1,%0.w"; return "mov %1,%0.w"; } char * cmp_imm_word (imm, dest) int imm; rtx dest; { int is_reg, short_ok; if (imm == 0) return "cmp:z.w #0,%0"; short_ok = short_format_ok (dest); if (short_ok && imm >0 && imm <= 8) return "cmp:q %1,%0.w"; if (-128 <= imm && imm < 128) return "cmp:e %1,%0.w"; is_reg = (GET_CODE (dest) == REG); if (is_reg) return "cmp:l %1,%0.w"; if (short_ok) return "cmp:i %1,%0.w"; return "cmp %1,%0.w"; } char * push_imm_word (imm) int imm; { if (imm == 0) return "mov:z.w #0,%-"; if (imm > 0 && imm <= 8) return "mov:q %1,%-.w"; if (-128 <= imm && imm < 128) return "mov:e %1,%-.w"; return "mov:g %1,%-.w"; /* In some cases, g-format may be better than I format.?? return "mov %1,%0.w"; */ } my_signed_comp (insn) rtx insn; { rtx my_insn; my_insn = NEXT_INSN (insn); if (GET_CODE (my_insn) != JUMP_INSN) { fprintf (stderr, "my_signed_comp: Not Jump_insn "); myabort (GET_CODE (my_insn)); } my_insn = PATTERN (my_insn); if (GET_CODE (my_insn) != SET) { fprintf (stderr, "my_signed_comp: Not Set "); myabort (GET_CODE (my_insn)); } my_insn = SET_SRC (my_insn); if (GET_CODE (my_insn) != IF_THEN_ELSE) { fprintf (stderr, "my_signed_comp: Not if_then_else "); myabort (GET_CODE (my_insn)); } switch (GET_CODE (XEXP (my_insn, 0))) { case NE: case EQ: case GE: case GT: case LE: case LT: return 1; case GEU: case GTU: case LEU: case LTU: return 0; } fprintf (stderr, "my_signed_comp: Not cccc "); myabort (GET_CODE (XEXP (my_insn, 0))); } gcc-2.5.8/config/gmicro/gmicro.h100444 22011 13 160200 5453234471 15207 0ustar kenneruser/* Definitions of target machine for GNU compiler. Gmicro (TRON) version. Ported by Masanobu Yuhara, Fujitsu Laboratories LTD. (yuhara@flab.fujitsu.co.jp) Copyright (C) 1987, 1988, 1989 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. Among other things, the copyright notice and this notice must be preserved on all copies. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Note that some other tm.h files include this one and then override many of the definitions that relate to assembler syntax. */ /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Dgmicro -Acpu(tron) -Amachine(tron)" /* #define CPP_SPEC ** currently not defined **/ /* #define CC1_SPEC ** currently not defined **/ /* Print subsidiary information on the compiler version in use. */ /* #define TARGET_VERSION fprintf (stderr, " (Gmicro syntax)"); */ /* Run-time compilation parameters selecting different hardware subsets. */ extern int target_flags; /* Macros used in the machine description to test the flags. */ /* Compile for a Gmicro/300. */ #define TARGET_G300 (target_flags & 1) /* Compile for a Gmicro/200. */ #define TARGET_G200 (target_flags & 2) /* Compile for a Gmicro/100. */ #define TARGET_G100 (target_flags & 4) /* Compile FPU insns for floating point (not library calls). */ #define TARGET_FPU (target_flags & 8) /* Pop up arguments by called function. */ #define TARGET_RTD (target_flags & 0x10) /* Compile passing first args in regs 0 and 1. This exists only to test compiler features that will be needed for RISC chips. It is not usable and is not intended to be usable on this cpu ;-< */ #define TARGET_REGPARM (target_flags & 0x20) #define TARGET_BITFIELD (target_flags & 0x40) #define TARGET_NEWRETURN (target_flags & 0x80) /* Do not expand __builtin_smov (strcpy) to multiple movs. Use the smov instruction. */ #define TARGET_FORCE_SMOV (target_flags & 0x100) /* default options are -m300, -mFPU, with bitfield instructions added because it won't always work otherwise. If there are versions of the gmicro that don't support bitfield instructions then it will take some thinking to figure out how to make them work. */ #define TARGET_DEFAULT 0x49 /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */ #define TARGET_SWITCHES \ { { "g300", 1}, \ { "g200", 2}, \ { "g100", 4}, \ { "fpu", 8}, \ { "soft-float", -8}, \ { "rtd", 0x10}, \ { "no-rtd", -0x10}, \ { "regparm", 0x20}, \ { "no-regparm", -0x20}, \ #if 0 /* Since we don't define PCC_BITFIELD_TYPE_MATTERS or use a large STRUCTURE_SIZE_BOUNDARY, we must have bitfield instructions. */ { "bitfield", 0x40}, \ { "no-bitfield", -0x40}, \ #endif { "newreturn", 0x80}, \ { "no-newreturn", -0x80}, \ { "force-smov", 0x100}, \ { "no-force-smov", -0x100}, \ { "", TARGET_DEFAULT}} /* Blow away G100 flag silently off TARGET_fpu (since we can't clear any bits in TARGET_SWITCHES above) */ #define OVERRIDE_OPTIONS \ { \ if (TARGET_G100) target_flags &= ~8; \ } /* target machine storage layout */ /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. This is true for Gmicro insns. We make it true always by avoiding using the single-bit insns except in special cases with constant bit numbers. */ #define BITS_BIG_ENDIAN 1 /* Define this if most significant byte of a word is the lowest numbered. */ /* That is true on the Gmicro. */ #define BYTES_BIG_ENDIAN 1 /* Define this if most significant word of a multiword number is the lowest numbered. */ /* For Gmicro we can decide arbitrarily since there are no machine instructions for them. ????? */ #define WORDS_BIG_ENDIAN 0 /* number of bits in an addressable storage unit */ #define BITS_PER_UNIT 8 /* Width in bits of a "word", which is the contents of a machine register. */ #define BITS_PER_WORD 32 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 4 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ #define POINTER_SIZE 32 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ #define PARM_BOUNDARY 32 /* Boundary (in *bits*) on which stack pointer should be aligned. */ #define STACK_BOUNDARY 32 /* Allocation boundary (in *bits*) for the code of a function. */ /* Instructions of the Gmicro should be on half-word boundary */ /* But word boundary gets better performance */ #define FUNCTION_BOUNDARY 32 /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 32 /* No data type wants to be aligned rounder than this. */ /* This is not necessarily 32 on the Gmicro */ #define BIGGEST_ALIGNMENT 32 /* Set this non-zero if move instructions will actually fail to work when given unaligned data. Unaligned data is allowed on Gmicro, though the access is slow. */ #define STRICT_ALIGNMENT 1 #define SLOW_UNALIGNED_ACCESS 1 /* Make strings word-aligned so strcpy from constants will be faster. */ #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ (TREE_CODE (EXP) == STRING_CST \ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) /* Make arrays of chars word-aligned for the same reasons. */ #define DATA_ALIGNMENT(TYPE, ALIGN) \ (TREE_CODE (TYPE) == ARRAY_TYPE \ && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) /* Define number of bits in most basic integer type. (If undefined, default is BITS_PER_WORD). */ #define INT_TYPE_SIZE 32 /* #define PCC_BITFIELD_TYPE_MATTERS 1 ????? */ /* #define CHECK_FLOAT_VALUE (MODE, VALUE) ????? */ /* Standard register usage. */ /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. For the Gmicro, we give the general registers numbers 0-15, and the FPU floating point registers numbers 16-31. */ #define FIRST_PSEUDO_REGISTER 32 /* 1 for registers that have pervasive standard uses and are not available for the register allocator. On the Gmicro, the stack pointer and the frame pointer are such registers. */ /* frame pointer is not indicated as fixed, because fp may be used freely when a frame is not built. */ #define FIXED_REGISTERS \ {0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 1, \ /* FPU registers. */ \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, } /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. */ #define CALL_USED_REGISTERS \ {1, 1, 1, 1, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 1, \ /* FPU registers. */ \ 1, 1, 1, 1, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, } /* Make sure everything's fine if we *don't* have a given processor. This assumes that putting a register in fixed_regs will keep the compilers mitt's completely off it. We don't bother to zero it out of register classes. If TARGET_FPU is not set, the compiler won't touch since no instructions that use these registers will be valid. */ /* This Macro is not defined now. #define CONDITIONAL_REGISTER_USAGE */ /* The Gmicro has no overlapping register */ /* #define OVERLAPPING_REGNO_P(REGNO) */ /* #define INSN_CLOBBERS_REGNO_P(INSN,REGNO) */ /* #define PRESERVE_DEATH_INFO_REGNO_P(REGNO) */ /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. On the Gmicro, ordinary registers hold 32 bits worth; for the Gmicro/FPU registers, a single register is always enough for anything that can be stored in them at all. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ ((REGNO) >= 16 ? 1 \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On the Gmicro, the cpu registers can hold any mode but the FPU registers can hold only SFmode or DFmode. And the FPU registers can't hold anything if FPU use is disabled. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ((REGNO) < 16 \ || ((REGNO) < 32 \ ? TARGET_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT || \ GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ : 0 )) /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. */ #define MODES_TIEABLE_P(MODE1, MODE2) \ (! TARGET_FPU \ || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ == ((MODE2) == SFmode || (MODE2) == DFmode))) /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ /* Gmicro pc isn't overloaded on a register. */ /* #define PC_REGNUM */ /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM 15 /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM 14 /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */ #define FRAME_POINTER_REQUIRED 0 /* Base register for access to arguments of the function. */ /* The Gmicro does not have hardware ap. Fp is treated as ap */ #define ARG_POINTER_REGNUM 14 /* Register in which static-chain is passed to a function. */ #define STATIC_CHAIN_REGNUM 0 /* Register in which address to store a structure value is passed to a function. */ #define STRUCT_VALUE_REGNUM 1 /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. One of the classes must always be named ALL_REGS and include all hard regs. If there is more than one class, another class must be named NO_REGS and contain no registers. The name GENERAL_REGS must be the name of a class (or an alias for another name such as ALL_REGS). This is the class of registers that is allowed by "g" or "r" in a register constraint. Also, registers outside this class are allocated only when instructions express preferences for them. The classes must be numbered in nondecreasing order; that is, a larger-numbered class must never be contained completely in a smaller-numbered class. For any two classes, it is very desirable that there be another class that represents their union. */ /* The Gmicro has two kinds of registers, so four classes would be a complete set. */ enum reg_class { NO_REGS, FPU_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ { "NO_REGS", "FPU_REGS", "GENERAL_REGS", "ALL_REGS" } /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS \ { \ 0, /* NO_REGS */ \ 0xffff0000, /* FPU_REGS */ \ 0x0000ffff, /* GENERAL_REGS */ \ 0xffffffff /* ALL_REGS */ \ } /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ extern enum reg_class regno_reg_class[]; #define REGNO_REG_CLASS(REGNO) ( (REGNO < 16) ? GENERAL_REGS : FPU_REGS ) /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS GENERAL_REGS #define BASE_REG_CLASS GENERAL_REGS /* Get reg_class from a letter such as appears in the machine description. We do a trick here to modify the effective constraints on the machine description; we zorch the constraint letters that aren't appropriate for a specific target. This allows us to guarantee that a specific kind of register will not be used for a given target without fiddling with the register classes above. */ #define REG_CLASS_FROM_LETTER(C) \ ((C) == 'r' ? GENERAL_REGS : \ ((C) == 'f' ? (TARGET_FPU ? FPU_REGS : NO_REGS) : \ NO_REGS)) /* The letters I, J, K, L and M in a register constraint string can be used to stand for particular ranges of immediate operands. This macro defines what the ranges are. C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. For the Gmicro, all immediate value optimizations are done by assembler, so no machine dependent definition is necessary ??? */ /* #define CONST_OK_FOR_LETTER_P(VALUE, C) ((C) == 'I') */ #define CONST_OK_FOR_LETTER_P(VALUE, C) 0 /* * The letters G defines all of the floating constants tha are *NOT* * Gmicro-FPU constant. */ #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'F' || \ (C) == 'G' && !(TARGET_FPU && standard_fpu_constant_p (VALUE))) /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. */ /* On the Gmicro series, there is no restriction on GENERAL_REGS, so CLASS is returned. I do not know whether I should treat FPU_REGS specially or not (at least, m68k does not). */ #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ /* On the Gmicro, this is the size of MODE in words, except in the FPU regs, where a single reg is always enough. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ ((CLASS) == FPU_REGS ? \ 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack makes the stack pointer a smaller address. */ #define STACK_GROWS_DOWNWARD /* Define this if the nominal address of the stack frame is at the high-address end of the local variables; that is, each additional local variable allocated goes at a more negative offset in the frame. */ #define FRAME_GROWS_DOWNWARD /* Offset within stack frame to start allocating local variables at. If FRAME_GROWS_DOWNWARD, this is the offset to the END of the first local allocated. Otherwise, it is the offset to the BEGINNING of the first local allocated. */ /* On the Gmicro, FP points to the old FP and the first local variables are at (FP - 4). */ #define STARTING_FRAME_OFFSET 0 /* If we generate an insn to push BYTES bytes, this says how many the stack pointer really advances by. */ /* On the Gmicro, sp is decremented by the exact size of the operand */ #define PUSH_ROUNDING(BYTES) (BYTES) /* Offset of first parameter from the argument pointer register value. */ /* On the Gmicro, the first argument is found at (ap + 8) where ap is fp. */ #define FIRST_PARM_OFFSET(FNDECL) 8 /* Value is the number of byte of arguments automatically popped when returning from a subroutine call. FUNTYPE is the data type of the function (as a tree), or for a library call it is an identifier node for the subroutine name. SIZE is the number of bytes of arguments passed on the stack. On the Gmicro, the EXITD insn may be used to pop them if the number of args is fixed, but if the number is variable then the caller must pop them all. The adjsp operand of the EXITD insn can't be used for library calls now because the library is compiled with the standard compiler. Use of adjsp operand is a selectable option, since it is incompatible with standard Unix calling sequences. If the option is not selected, the caller must always pop the args. On the m68k this is an RTD option, so I use the same name for the Gmicro. The option name may be changed in the future. */ #define RETURN_POPS_ARGS(FUNTYPE,SIZE) \ ((TARGET_RTD && TREE_CODE (FUNTYPE) != IDENTIFIER_NODE \ && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ = void_type_node))) \ ? (SIZE) : 0) /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */ /* On the Gmicro the floating return value is in fr0 not r0. */ #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE)) /* Define how to find the value returned by a library function assuming the value has mode MODE. */ #define LIBCALL_VALUE(MODE) \ (gen_rtx (REG, (MODE), \ ((TARGET_FPU && ((MODE) == SFmode || (MODE) == DFmode)) ? 16 : 0))) /* 1 if N is a possible register number for a function value. On the Gmicro, r0 and fp0 are the possible registers. */ #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 16) /* Define this if PCC uses the nonreentrant convention for returning structure and union values. */ #define PCC_STATIC_STRUCT_RETURN /* 1 if N is a possible register number for function argument passing. On the Gmicro, no registers are used in this way. */ /* Really? For the performance improvement, registers should be used !! */ #define FUNCTION_ARG_REGNO_P(N) 0 /* Define a data type for recording info about an argument list during the scan of that argument list. This data type should hold all necessary information about the function itself and about the args processed so far, enough to enable macros such as FUNCTION_ARG to determine where the next arg should go. On the Gmicro, this is a single integer, which is a number of bytes of arguments scanned so far. */ #define CUMULATIVE_ARGS int /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. On the Gmicro, the offset starts at 0. */ #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ ((CUM) = 0) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ ((CUM) += ((MODE) != BLKmode \ ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ : (int_size_in_bytes (TYPE) + 3) & ~3)) /* Define where to put the arguments to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. MODE is the argument's machine mode. TYPE is the data type of the argument (as a tree). This is null for libcalls where that information may not be available. CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called. NAMED is nonzero if this argument is a named parameter (otherwise it is an extra parameter matching an ellipsis). */ /* On the Gmicro all args are pushed, except if -mregparm is specified then the first two words of arguments are passed in d0, d1. *NOTE* -mregparm does not work. It exists only to test register calling conventions. */ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0) /* For an arg passed partly in registers and partly in memory, this is the number of registers used. For args passed entirely in registers or entirely in memory, zero. */ #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ ((TARGET_REGPARM && (CUM) < 8 \ && 8 < ((CUM) + ((MODE) == BLKmode \ ? int_size_in_bytes (TYPE) \ : GET_MODE_SIZE (MODE)))) \ ? 2 - (CUM) / 4 : 0) /* The following macro is defined to output register list. The LSB of Mask is the lowest number register. Regoff is MY_GREG_OFF or MY_FREG_OFF. Do NOT use in File, Mask, Regoff !! Should be changed from macros to functions. M.Yuhara */ #define MY_GREG_OFF 0 #define MY_FREG_OFF 16 #define MY_PRINT_MASK(File, Mask, Regoff) \ { \ int i, first = -1; \ if ((Mask) == 0) { \ fprintf(File, "#0"); \ } else { \ fprintf(File, "("); \ for (i = 0; i < 16; i++) { \ if ( (Mask) & (1 << i) ) { \ if (first < 0) { \ if (first == -2) { \ fprintf(File, ","); \ } \ first = i; \ fprintf(File, "%s", reg_names[Regoff + i]); \ } \ } else if (first >= 0) { \ if (i > first + 1) { \ fprintf(File, "-%s", reg_names[Regoff + i - 1]); \ } \ first = -2; \ } \ } \ if ( (first >= 0) && (first != 15) ) \ fprintf(File, "-%s", reg_names[Regoff + 15]);\ fprintf(File, ")"); \ } \ } #define MY_PRINT_ONEREG_L(FILE,MASK) \ { register int i; \ for (i = 0; i < 16; i++) \ if ( (1 << i) & (MASK)) { \ fprintf(FILE, "%s", reg_names[i]); \ (MASK) &= ~(1 << i); \ break; \ } \ } #define MY_PRINT_ONEREG_H(FILE,MASK) \ { register int i; \ for (i = 15; i >= 0; i--) \ if ( (1 << i) & (MASK)) { \ fprintf(FILE, "%s", reg_names[i]); \ (MASK) &= ~(1 << i); \ break; \ } \ } /* This macro generates the assembly code for function entry. FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. Refer to the array `regs_ever_live' to determine which registers to save; `regs_ever_live[I]' is nonzero if register number I is ever used in the function. This macro is responsible for knowing which registers should not be saved even if used. */ /* The next macro needs much optimization !! M.Yuhara */ #define FUNCTION_PROLOGUE(FILE, SIZE) \ { register int regno; \ register int mask = 0; \ register int nregs = 0; \ static char *reg_names[] = REGISTER_NAMES; \ extern char call_used_regs[]; \ int fsize = ((SIZE) + 3) & -4; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && !call_used_regs[regno]) { \ mask |= (1 << regno); \ nregs++; \ } \ if (frame_pointer_needed) { \ mask &= ~(1 << FRAME_POINTER_REGNUM); \ if (nregs > 4) { \ fprintf(FILE, "\tenter.w #%d,", fsize); \ MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \ fprintf(FILE,"\n"); \ } else { \ fprintf(FILE, "\tmov.w fp,@-sp\n"); \ fprintf(FILE, "\tmov.w sp,fp\n"); \ if (fsize > 0) \ myoutput_sp_adjust(FILE, "sub", fsize); \ while (nregs--) { \ fprintf(FILE, "\tmov.w "); \ MY_PRINT_ONEREG_H(FILE, mask); \ fprintf(FILE, ",@-sp\n"); \ } \ } \ } else { \ if (fsize > 0) \ myoutput_sp_adjust(FILE, "sub", fsize); \ if (mask != 0) { \ if (nregs > 4) { \ fprintf(FILE, "\tstm.w "); \ MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \ fprintf(FILE, ",@-sp\n"); \ } else { \ while (nregs--) { \ fprintf(FILE, "\tmov.w "); \ MY_PRINT_ONEREG_H(FILE, mask); \ fprintf(FILE, ",@-sp\n"); \ } \ } \ } \ } \ mask = 0; \ for (regno = 16; regno < 32; regno++) \ if (regs_ever_live[regno] && !call_used_regs[regno]) \ mask |= 1 << (regno - 16); \ if (mask != 0) { \ fprintf(FILE, "\tfstm.w "); \ MY_PRINT_MASK(FILE, mask, MY_FREG_OFF); \ fprintf(FILE, ",@-sp\n", mask); \ } \ } /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ /* ??? M.Yuhara */ #define FUNCTION_PROFILER(FILE, LABELNO) \ fprintf (FILE, "\tmova @LP%d,r0\n\tjsr mcount\n", (LABELNO)) /* Output assembler code to FILE to initialize this source file's basic block profiling info, if that has not already been done. */ #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ fprintf (FILE, "\tcmp #0,@LPBX0\n\tbne LPI%d\n\tpusha @LPBX0\n\tjsr ___bb_init_func\n\tadd #4,sp\nLPI%d:\n", \ LABELNO, LABELNO); /* Output assembler code to FILE to increment the entry-count for the BLOCKNO'th basic block in this source file. */ #define BLOCK_PROFILER(FILE, BLOCKNO) \ fprintf (FILE, "\tadd #1,@(LPBX2+%d)\n", 4 * BLOCKNO) /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, the stack pointer does not matter. The value is tested only in functions that have frame pointers. No definition is equivalent to always zero. */ #define EXIT_IGNORE_STACK 1 /* This macro generates the assembly code for function exit, on machines that need it. If FUNCTION_EPILOGUE is not defined then individual return instructions are generated for each return statement. Args are same as for FUNCTION_PROLOGUE. The function epilogue should not depend on the current stack pointer (when frame_pinter_needed) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ It should use the frame pointer only. This is mandatory because of alloca; we also take advantage of it to omit stack adjustments before returning. */ /* The Gmicro FPU seems to be unable to fldm/fstm double or single floating. It only allows extended !! */ /* Optimization is not enough, especially FREGs load !! M.Yuhara */ #define FUNCTION_EPILOGUE(FILE, SIZE) \ { register int regno; \ register int mask, fmask; \ register int nregs, nfregs; \ int offset, foffset; \ extern char call_used_regs[]; \ static char *reg_names[] = REGISTER_NAMES; \ int fsize = ((SIZE) + 3) & -4; \ FUNCTION_EXTRA_EPILOGUE (FILE, SIZE); \ nfregs = 0; fmask = 0; \ for (regno = 16; regno < 31; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ { nfregs++; fmask |= 1 << (regno - 16); } \ foffset = nfregs * 12; \ nregs = 0; mask = 0; \ if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ { nregs++; mask |= 1 << regno; } \ if (frame_pointer_needed) { \ offset = nregs * 4 + fsize; \ if (nfregs > 0) { \ fprintf(FILE, "\tfldm.x @(%d,fp),", -(foffset + offset));\ MY_PRINT_MASK(FILE, fmask, MY_FREG_OFF); \ fprintf(FILE, "\n"); \ } \ if (nregs > 4 \ || current_function_pops_args) { \ fprintf(FILE, "\tmova @(%d,fp),sp\n", -offset); \ fprintf(FILE, "\texitd "); \ MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \ fprintf(FILE, ",#%d\n", current_function_pops_args); \ } else { \ while (nregs--) { \ fprintf(FILE, "\tmov:l.w @(%d,fp),", -offset); \ MY_PRINT_ONEREG_L(FILE, mask); \ fprintf(FILE, "\n"); \ offset -= 4; \ } \ if (TARGET_NEWRETURN) { \ fprintf(FILE, "\tmova.w @(4,fp),sp\n"); \ fprintf(FILE, "\tmov:l.w @fp,fp\n"); \ } else { \ fprintf(FILE, "\tmov.w fp,sp\n"); \ fprintf(FILE, "\tmov.w @sp+,fp\n"); \ } \ fprintf(FILE, "\trts\n"); \ } \ } else { \ if (nfregs > 0) { \ fprintf(FILE, "\tfldm.w @sp+,"); \ MY_PRINT_MASK(FILE, fmask, MY_FREG_OFF); \ fprintf(FILE, "\n"); \ } \ if (nregs > 4) { \ fprintf(FILE, "\tldm.w @sp+,"); \ MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \ fprintf(FILE, "\n"); \ } else { \ while (nregs--) { \ fprintf(FILE, "\tmov.w @sp+,"); \ MY_PRINT_ONEREG_L(FILE,mask); \ fprintf(FILE, "\n"); \ } \ } \ if (current_function_pops_args) { \ myoutput_sp_adjust(FILE, "add", \ (fsize + 4 + current_function_pops_args)); \ fprintf(FILE, "\tjmp @(%d,sp)\n", current_function_pops_args);\ } else { \ if (fsize > 0) \ myoutput_sp_adjust(FILE, "add", fsize); \ fprintf(FILE, "\trts\n"); \ } \ } \ } /* This is a hook for other tm files to change. */ #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) /* If the memory address ADDR is relative to the frame pointer, correct it to be relative to the stack pointer instead. This is for when we don't use a frame pointer. ADDR should be a variable name. */ /* You have to change the next macro if you want to use more complex addressing modes (such as double indirection and more than one chain-addressing stages). */ #define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH) \ { int offset = -1; \ rtx regs = stack_pointer_rtx; \ if (ADDR == frame_pointer_rtx) \ offset = 0; \ else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \ && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \ offset = INTVAL (XEXP (ADDR, 1)); \ else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \ { rtx other_reg = XEXP (ADDR, 1); \ offset = 0; \ regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \ else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \ { rtx other_reg = XEXP (ADDR, 0); \ offset = 0; \ regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \ else if (GET_CODE (ADDR) == PLUS \ && GET_CODE (XEXP (ADDR, 0)) == PLUS \ && XEXP (XEXP (ADDR, 0), 0) == frame_pointer_rtx \ && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \ { rtx other_reg = XEXP (XEXP (ADDR, 0), 1); \ offset = INTVAL (XEXP (ADDR, 1)); \ regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \ else if (GET_CODE (ADDR) == PLUS \ && GET_CODE (XEXP (ADDR, 0)) == PLUS \ && XEXP (XEXP (ADDR, 0), 1) == frame_pointer_rtx \ && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \ { rtx other_reg = XEXP (XEXP (ADDR, 0), 0); \ offset = INTVAL (XEXP (ADDR, 1)); \ regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \ if (offset >= 0) \ { int regno; \ extern char call_used_regs[]; \ for (regno = 16; regno < 32; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ offset += 12; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ offset += 4; \ offset -= 4; \ ADDR = plus_constant (regs, offset + (DEPTH)); } } /* Addressing modes, and classification of registers for them. */ /* #define HAVE_POST_INCREMENT */ /* #define HAVE_POST_DECREMENT */ /* #define HAVE_PRE_DECREMENT */ /* #define HAVE_PRE_INCREMENT */ /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. */ /* Gmicro */ #define REGNO_OK_FOR_GREG_P(REGNO) \ ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) #define REGNO_OK_FOR_FPU_P(REGNO) \ (((REGNO) ^ 0x10) < 16 || (unsigned) (reg_renumber[REGNO] ^ 0x10) < 16) #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_GREG_P(REGNO) #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_GREG_P(REGNO) /* Now macros that check whether X is a register and also, strictly, whether it is in a specified class. These macros are specific to the Gmicro, and may be used only in code for printing assembler insns and in conditions for define_optimization. */ /* 1 if X is an fpu register. */ #define FPU_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPU_P (REGNO (X))) /* I used GREG_P in the gmicro.md file. */ #ifdef REG_OK_STRICT #define GREG_P(X) (REG_P (X) && REGNO_OK_FOR_GREG_P (REGNO(X))) #else #define GREG_P(X) (REG_P (X) && ((REGNO (X) & ~0xf) != 0x10)) #endif /* Maximum number of registers that can appear in a valid memory address. */ /* The Gmicro allows more registers in the chained addressing mode. But I do not know gcc supports such an architecture. */ #define MAX_REGS_PER_ADDRESS 2 /* Recognize any constant value that is a valid address. */ #define CONSTANT_ADDRESS_P(X) \ (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ || GET_CODE (X) == HIGH) /* Nonzero if the constant value X is a legitimate general operand. It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ #define LEGITIMATE_CONSTANT_P(X) 1 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. The usual definition accepts all pseudo regs; the other rejects them unless they have been allocated suitable hard regs. The symbol REG_OK_STRICT causes the latter definition to be used. Most source files want to accept pseudo regs in the hope that they will get allocated to the class that the insn wants them to be in. Source files for reload pass need to be strict. After reload, it makes no difference, since pseudo regs have been eliminated by then. */ #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) & ~0xf) != 0x10) /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~0xf) != 0x10) #else /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) #endif /* The gcc uses the following effective address of the Gmicro. (without using PC!!). {@} ( {Rbase} + {Disp} + {Rindex * [1,2,4,8]} ) where @: memory indirection. Rbase: Base Register = General Register. Disp: Displacement (up to 32bits) Rindex: Index Register = General Register. [1,2,4,8]: Scale of Index. 1 or 2 or 4 or 8. The inside of { } can be omitted. This restricts the chained addressing up to 1 stage. */ /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, except for CONSTANT_ADDRESS_P which is actually machine-independent. */ #define REG_CODE_BASE_P(X) \ (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) #define REG_CODE_INDEX_P(X) \ (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) /* GET_CODE(X) must be PLUS. This macro does not check for PLUS! */ #define BASE_PLUS_DISP_P(X) \ ( REG_CODE_BASE_P (XEXP (X, 0)) \ && CONSTANT_ADDRESS_P (XEXP (X, 1)) \ || \ REG_CODE_BASE_P (XEXP (X, 1)) \ && CONSTANT_ADDRESS_P (XEXP (X, 0)) ) /* 1 if X is {0,Rbase} + {0,disp}. */ #define BASED_ADDRESS_P(X) \ (CONSTANT_ADDRESS_P (X) \ || REG_CODE_BASE_P (X) \ || (GET_CODE (X) == PLUS) \ && BASE_PLUS_DISP_P (X)) /* 1 if X is 1 or 2 or 4 or 8. GET_CODE(X) must be CONST_INT. */ #define SCALE_OF_INDEX_P(X) \ ( INTVAL(X) == 4 \ || INTVAL(X) == 2 \ || INTVAL(X) == 8 \ || INTVAL(X) == 1 ) /* #define INDEX_TERM_P(X,MODE) */ #define INDEX_TERM_P(X) \ ( REG_CODE_INDEX_P(X) \ || (GET_CODE (X) == MULT \ && ( (xfoo0 = XEXP (X, 0)), (xfoo1 = XEXP(X, 1)), \ ( ( (GET_CODE (xfoo0) == CONST_INT) \ && SCALE_OF_INDEX_P (xfoo0) \ && REG_CODE_INDEX_P (xfoo1) ) \ || \ ( (GET_CODE (xfoo1) == CONST_INT) \ && SCALE_OF_INDEX_P (xfoo1) \ && REG_CODE_INDEX_P (xfoo0) ) )))) /* Assumes there are no cases such that X = (Ireg + Disp) + Disp */ #define BASE_DISP_INDEX_P(X) \ ( BASED_ADDRESS_P (X) \ || ( (GET_CODE (X) == PLUS) \ && ( ( (xboo0 = XEXP (X, 0)), (xboo1 = XEXP (X, 1)), \ (REG_CODE_BASE_P (xboo0) \ && (GET_CODE (xboo1) == PLUS) \ && ( ( CONSTANT_ADDRESS_P (XEXP (xboo1, 0)) \ && INDEX_TERM_P (XEXP (xboo1, 1)) ) \ || ( CONSTANT_ADDRESS_P (XEXP (xboo1, 1)) \ && INDEX_TERM_P (XEXP (xboo1, 0))) ))) \ || \ (CONSTANT_ADDRESS_P (xboo0) \ && (GET_CODE (xboo1) == PLUS) \ && ( ( REG_CODE_BASE_P (XEXP (xboo1, 0)) \ && INDEX_TERM_P (XEXP (xboo1, 1)) ) \ || ( REG_CODE_BASE_P (XEXP (xboo1, 1)) \ && INDEX_TERM_P (XEXP (xboo1, 0))) )) \ || \ (INDEX_TERM_P (xboo0) \ && ( ( (GET_CODE (xboo1) == PLUS) \ && ( ( REG_CODE_BASE_P (XEXP (xboo1, 0)) \ && CONSTANT_ADDRESS_P (XEXP (xboo1, 1)) ) \ || ( REG_CODE_BASE_P (XEXP (xboo1, 1)) \ && CONSTANT_ADDRESS_P (XEXP (xboo1, 0))) )) \ || \ (CONSTANT_ADDRESS_P (xboo1)) \ || \ (REG_CODE_BASE_P (xboo1)) ))))) /* If you want to allow double-indirection, you have to change the => conversion routine. M.Yuhara #ifdef REG_OK_STRICT #define DOUBLE_INDIRECTION(X,ADDR) {\ if (BASE_DISP_INDEX_P (XEXP (XEXP (X, 0), 0) )) goto ADDR; \ } #else #define DOUBLE_INDIRECTION(X,ADDR) { } #endif */ #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) {\ register rtx xboo0, xboo1, xfoo0, xfoo1; \ if (GET_CODE (X) == MEM) { \ /* \ if (GET_CODE (XEXP (X,0)) == MEM) { \ DOUBLE_INDIRECTION(X,ADDR); \ } else { \ if (BASE_DISP_INDEX_P (XEXP (X, 0))) goto ADDR; \ } \ */ \ } else { \ if (BASE_DISP_INDEX_P (X)) goto ADDR; \ if ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ && REG_P (XEXP (X, 0)) \ && (REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM)) \ goto ADDR; \ } \ } /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. OLDX is the address as it was before break_out_memory_refs was called. In some cases it is useful to look at this to decide what needs to be done. MODE and WIN are passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. It is always safe for this macro to do nothing. It exists to recognize opportunities to optimize the output. For the Gmicro, nothing is done now. */ #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {} /* Go to LABEL if ADDR (a legitimate address expression) has an effect that depends on the machine mode it is used for. On the VAX, the predecrement and postincrement address depend thus (the amount of decrement or increment being the length of the operand) and all indexed address depend thus (because the index scale factor is the length of the operand). The Gmicro mimics the VAX now. Since ADDE is legitimate, it cannot include auto-inc/dec. */ /* Unnecessary ??? */ #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) \ goto LABEL; } /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ /* #define CASE_VECTOR_MODE HImode */ #define CASE_VECTOR_MODE SImode /* Define this if the tablejump instruction expects the table to contain offsets from the address of the table. Do not define this if the table should contain absolute addresses. */ #define CASE_VECTOR_PC_RELATIVE /* Specify the tree operation to be used to convert reals to integers. */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR /* This is the kind of divide that is easiest to do in the general case. */ #define EASY_DIV_EXPR TRUNC_DIV_EXPR /* Define this as 1 if `char' should by default be signed; else as 0. */ #define DEFAULT_SIGNED_CHAR 1 /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ #define MOVE_MAX 4 /* Define this if zero-extension is slow (more than one real instruction). */ /* #define SLOW_ZERO_EXTEND */ /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS 0 /* Define if shifts truncate the shift count which implies one can omit a sign-extension or zero-extension of a shift count. */ /* #define SHIFT_COUNT_TRUNCATED */ /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 /* We assume that the store-condition-codes instructions store 0 for false and some other value for true. This is the value stored for true. */ /* #define STORE_FLAG_VALUE -1 */ /* When a prototype says `char' or `short', really pass an `int'. */ #define PROMOTE_PROTOTYPES /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ #define Pmode SImode /* A function address in a call instruction is a byte address (for indexing purposes) so give the MEM rtx a byte's mode. */ #define FUNCTION_MODE QImode /* Compute the cost of computing a constant rtl expression RTX whose rtx-code is CODE. The body of this macro is a portion of a switch statement. If the code is computed here, return it with a return statement. Otherwise, break from the switch. */ #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ if ((unsigned) INTVAL (RTX) < 8) return 0; \ if ((unsigned) (INTVAL (RTX) + 0x80) < 0x100) return 1; \ if ((unsigned) (INTVAL (RTX) + 0x8000) < 0x10000) return 2; \ case CONST: \ case LABEL_REF: \ case SYMBOL_REF: \ return 3; \ case CONST_DOUBLE: \ return 5; /* Define subroutines to call to handle multiply and divide. The `*' prevents an underscore from being prepended by the compiler. */ /* Use libgcc on Gmicro */ /* #define UDIVSI3_LIBCALL "*udiv" */ /* #define UMODSI3_LIBCALL "*urem" */ /* Tell final.c how to eliminate redundant test instructions. */ /* Here we define machine-dependent flags and fields in cc_status (see `conditions.h'). */ /* Set if the cc value is actually in the FPU, so a floating point conditional branch must be output. */ #define CC_IN_FPU 04000 /* Store in cc_status the expressions that the condition codes will describe after execution of an instruction whose pattern is EXP. Do not alter them if the instruction would not alter the cc's. */ /* Since Gmicro's compare instructions depend on the branch condition, all branch should be kept. More work must be done to optimize condition code !! M.Yuhara */ #define NOTICE_UPDATE_CC(EXP, INSN) {CC_STATUS_INIT;} /* The skeleton of the next macro is taken from "vax.h". FPU-reg manipulation is added. M.Yuhara */ /* Now comment out. #define NOTICE_UPDATE_CC(EXP, INSN) { \ if (GET_CODE (EXP) == SET) { \ if ( !FPU_REG_P (XEXP (EXP, 0)) \ && (XEXP (EXP, 0) != cc0_rtx) \ && (FPU_REG_P (XEXP (EXP, 1)) \ || GET_CODE (XEXP (EXP, 1)) == FIX \ || GET_CODE (XEXP (EXP, 1)) == FLOAT_TRUNCATE \ || GET_CODE (XEXP (EXP, 1)) == FLOAT_EXTEND)) { \ CC_STATUS_INIT; \ } else if (GET_CODE (SET_SRC (EXP)) == CALL) { \ CC_STATUS_INIT; \ } else if (GET_CODE (SET_DEST (EXP)) != PC) { \ cc_status.flags = 0; \ cc_status.value1 = SET_DEST (EXP); \ cc_status.value2 = SET_SRC (EXP); \ } \ } else if (GET_CODE (EXP) == PARALLEL \ && GET_CODE (XVECEXP (EXP, 0, 0)) == SET \ && GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) != PC) {\ cc_status.flags = 0; \ cc_status.value1 = SET_DEST (XVECEXP (EXP, 0, 0)); \ cc_status.value2 = SET_SRC (XVECEXP (EXP, 0, 0)); \ /* PARALLELs whose first element sets the PC are aob, sob VAX insns. \ They do change the cc's. So drop through and forget the cc's. * / \ } else CC_STATUS_INIT; \ if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \ && cc_status.value2 \ && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \ cc_status.value2 = 0; \ if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM \ && cc_status.value2 \ && GET_CODE (cc_status.value2) == MEM) \ cc_status.value2 = 0; \ if ( (cc_status.value1 && FPU_REG_P (cc_status.value1)) \ || (cc_status.value2 && FPU_REG_P (cc_status.value2))) \ cc_status.flags = CC_IN_FPU; \ } */ #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ { if (cc_prev_status.flags & CC_IN_FPU) \ return FLOAT; \ if (cc_prev_status.flags & CC_NO_OVERFLOW) \ return NO_OV; \ return NORMAL; } /* Control the assembler format that we output. */ /* Output before read-only data. */ #define TEXT_SECTION_ASM_OP ".section text,code,align=4" /* Output before writable data. */ #define DATA_SECTION_ASM_OP ".section data,data,align=4" /* Output before uninitialized data. */ #define BSS_SECTION_ASM_OP ".section bss,data,align=4" #define EXTRA_SECTIONS in_bss #define EXTRA_SECTION_FUNCTIONS \ void \ bss_section () \ { \ if (in_section != in_bss) { \ fprintf (asm_out_file, "%s\n", BSS_SECTION_ASM_OP); \ in_section = in_bss; \ } \ } /* Output at beginning of assembler file. It is not appropriate for this to print a list of the options used, since that's not the convention that we use. */ #define ASM_FILE_START(FILE) /* Output at the end of assembler file. */ #define ASM_FILE_END(FILE) fprintf (FILE, "\t.end\n"); /* Don't try to define `gcc_compiled.' since the assembler do not accept symbols with periods and GDB doesn't run on this machine anyway. */ #define ASM_IDENTIFY_GCC(FILE) /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ #define ASM_APP_ON "" /* #define ASM_APP_ON "#APP\n" */ /* Output to assembler file text saying following lines no longer contain unusual constructs. */ #define ASM_APP_OFF "" /* #define ASM_APP_OFF ";#NO_APP\n" */ /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ #define REGISTER_NAMES \ {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ "r8", "r9", "r10", "r11", "r12", "r13", "fp", "sp", \ "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \ "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15"} /* How to renumber registers for dbx and gdb. */ #define DBX_REGISTER_NUMBER(REGNO) (REGNO) /* Define this if gcc should produce debugging output for dbx in response to the -g flag. This does not work for the Gmicro now */ #define DBX_DEBUGGING_INFO /* This is how to output the definition of a user-level label named NAME, such as the label on a static function or variable NAME. */ #define ASM_OUTPUT_LABEL(FILE,NAME) { \ assemble_name (FILE, NAME); \ fputs (":\n", FILE); \ } /* This is how to output a command to make the user-level label named NAME defined for reference from other files. */ #define ASM_GLOBALIZE_LABEL(FILE,NAME) {\ fputs ("\t.global ", FILE); \ assemble_name (FILE, NAME); \ fputs ("\n", FILE); \ } /* This is how to output a command to make the external label named NAME which are not defined in the file to be referable */ /* ".import" does not work ??? */ #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) { \ fputs ("\t.global ", FILE); \ assemble_name (FILE, NAME); \ fputs ("\n", FILE); \ } /* This is how to output a reference to a user-level label named NAME. `assemble_name' uses this. */ #define ASM_OUTPUT_LABELREF(FILE,NAME) \ fprintf (FILE, "_%s", NAME) /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, "%s%d:\n", PREFIX, NUM) /* This is how to store into the string LABEL the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ sprintf (LABEL, "*%s%d", PREFIX, NUM) /* This is how to output an assembler line defining a `double' constant. */ /* do {...} while(0) is necessary, because these macros are used as if (xxx) MACRO; else .... ^ */ #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { union { double d; long l[2];} tem; \ tem.d = (VALUE); \ fprintf (FILE, "\t.fdata.d h'%x%08x.d\n", tem.l[0], tem.l[1]); \ } while(0) /* This is how to output an assembler line defining a `float' constant. */ #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { union { float f; long l;} tem; \ tem.f = (VALUE); \ fprintf (FILE, "\t.fdata.s h'%x.s\n", tem.l); \ } while(0) /* This is how to output an assembler line defining an `int' constant. */ #define ASM_OUTPUT_INT(FILE,VALUE) \ ( fprintf (FILE, "\t.data.w "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* Likewise for `char' and `short' constants. */ #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "\t.data.h "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ( fprintf (FILE, "\t.data.b "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* This is how to output an assembler line for a numeric constant byte. */ #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf (FILE, "\t.data.b h'%x\n", (VALUE)) #define ASM_OUTPUT_ASCII(FILE,P,SIZE) \ output_ascii ((FILE), (P), (SIZE)) /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tmov %s,@-sp\n", reg_names[REGNO]) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tmov @sp+,%s\n", reg_names[REGNO]) /* This is how to output an element of a case-vector that is absolute. (The Gmicro does not use such vectors, but we must define this macro anyway.) */ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "\t.data.w L%d\n", VALUE) /* This is how to output an element of a case-vector that is relative. */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\t.data.w L%d-L%d\n", VALUE, REL) /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #define ASM_OUTPUT_ALIGN(FILE,LOG) \ fprintf (FILE, "\t.align %d\n", (1 << (LOG))); #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t.res.b %d\n", (SIZE)) /* This says how to output an assembler line to define a global common symbol. */ #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( bss_section (), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ":\t.res.b %d\n", (ROUNDED)),\ fprintf ((FILE), "\t.export "), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), "\n") ) /* This says how to output an assembler line to define a local common symbol. */ #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( bss_section (), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ":\t.res.b %d\n", (ROUNDED))) /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ /* $__ is unique ????? M.Yuhara */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12), \ sprintf ((OUTPUT), "$__%s%d", (NAME), (LABELNO))) /* Define the parentheses used to group arithmetic operations in assembler code. */ #define ASM_OPEN_PAREN "(" #define ASM_CLOSE_PAREN ")" /* Define results of standard character escape sequences. */ #define TARGET_BELL 007 #define TARGET_BS 010 #define TARGET_TAB 011 #define TARGET_NEWLINE 012 #define TARGET_VT 013 #define TARGET_FF 014 #define TARGET_CR 015 /* Output a float value (represented as a C double) as an immediate operand. This macro is a Gmicro/68k-specific macro. */ #define ASM_OUTPUT_FLOAT_OPERAND(FILE,VALUE) \ do { union { float f; long l;} tem; \ tem.f = (VALUE); \ fprintf (FILE, "#h'%x.s", tem.l); \ } while(0) /* Output a double value (represented as a C double) as an immediate operand. This macro is a 68k-specific macro. */ #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ do { union { double d; long l[2];} tem; \ tem.d = (VALUE); \ fprintf (FILE, "#h'%x%08x.d", tem.l[0], tem.l[1]); \ } while(0) /* Print operand X (an rtx) in assembler syntax to file FILE. CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. For `%' followed by punctuation, CODE is the punctuation and X is null. On the Gmicro, we use several CODE characters: 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 'b' for branch target label. '-' for an operand pushing on the stack. '+' for an operand pushing on the stack. '#' for an immediate operand prefix */ #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ ( (CODE) == '#' || (CODE) == '-' \ || (CODE) == '+' || (CODE) == '@' || (CODE) == '!') #define PRINT_OPERAND(FILE, X, CODE) \ { int i; \ static char *reg_name[] = REGISTER_NAMES; \ /* fprintf (stderr, "PRINT_OPERAND CODE=%c(0x%x), ", CODE, CODE);\ myprcode(GET_CODE(X)); */ \ if (CODE == '#') fprintf (FILE, "#"); \ else if (CODE == '-') fprintf (FILE, "@-sp"); \ else if (CODE == '+') fprintf (FILE, "@sp+"); \ else if (CODE == 's') fprintf (stderr, "err: PRINT_OPERAND \n"); \ else if (CODE == '!') fprintf (stderr, "err: PRINT_OPERAND \n"); \ else if (CODE == '.') fprintf (stderr, "err: PRINT_OPERAND <.>\n"); \ else if (CODE == 'b') { \ if (GET_CODE (X) == MEM) \ output_addr_const (FILE, XEXP (X, 0)); /* for bsr */ \ else \ output_addr_const (FILE, X); /* for bcc */ \ } \ else if (CODE == 'p') \ print_operand_address (FILE, X); \ else if (GET_CODE (X) == REG) \ fprintf (FILE, "%s", reg_name[REGNO (X)]); \ else if (GET_CODE (X) == MEM) \ output_address (XEXP (X, 0)); \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \ { union { double d; int i[2]; } u; \ union { float f; int i; } u1; \ u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \ u1.f = u.d; \ if (CODE == 'f') \ ASM_OUTPUT_FLOAT_OPERAND (FILE, u1.f); \ else \ fprintf (FILE, "#h'%x", u1.i); } \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != DImode) \ { union { double d; int i[2]; } u; \ u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \ ASM_OUTPUT_DOUBLE_OPERAND (FILE, u.d); } \ else { putc ('#', FILE); \ output_addr_const (FILE, X); }} /* Note that this contains a kludge that knows that the only reason we have an address (plus (label_ref...) (reg...)) is in the insn before a tablejump, and we know that m68k.md generates a label LInnn: on such an insn. */ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ { print_operand_address (FILE, ADDR); } /* Local variables: version-control: t End: */ gcc-2.5.8/config/gmicro/gmicro.md100444 22011 13 205605 5353602312 15361 0ustar kenneruser;;- Machine description for GNU compiler ;;- Fujitsu Gmicro Version ;;- Ported by M.Yuhara, Fujitsu Laboratories LTD. ;; ;; Copyright (C) 1990 Free Software Foundation, Inc. ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; Among other things, the copyright ;; notice and this notice must be preserved on all copies. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ;;- instruction definitions ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ;;- When naming insn's (operand 0 of define_insn) be careful about using ;;- names from other targets machine descriptions. ;;- cpp macro #define NOTICE_UPDATE_CC is essentially a no-op for the ;;- gmicro; no compares are eliminated. ;;- The original structure of this file is m68k.md. ;; ??? Work to be done: ;; Add patterns for ACB and SCB instructions. ;; Add define_insn patterns to recognize the insns that extend a byte ;; to a word and add it into a word, etc. ;;- Some of these insn's are composites of several Gmicro op codes. ;;- The assembler (or final @@??) insures that the appropriate one is ;;- selected. (define_insn "" [(set (match_operand:DF 0 "push_operand" "=m") (match_operand:DF 1 "general_operand" "rmfF"))] "" "* { if (FPU_REG_P (operands[1])) return \"fmov.d %f1,%0\"; return output_move_double (operands); }") (define_insn "" [(set (match_operand:DI 0 "push_operand" "=m") (match_operand:DF 1 "general_operand" "rmF"))] "" "* { return output_move_double (operands); }") ;; We don't want to allow a constant operand for test insns because ;; (set (cc0) (const_int foo)) has no mode information. Such insns will ;; be folded while optimizing anyway. (define_insn "tstsi" [(set (cc0) (match_operand:SI 0 "nonimmediate_operand" "rm"))] "" "cmp:z.w #0,%0") (define_insn "tsthi" [(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "rm"))] "" "cmp:z.h #0,%0") (define_insn "tstqi" [(set (cc0) (match_operand:QI 0 "nonimmediate_operand" "rm"))] "" "cmp:z.b #0,%0") (define_insn "tstsf" [(set (cc0) (match_operand:SF 0 "general_operand" "fmF"))] "TARGET_FPU" "* { cc_status.flags = CC_IN_FPU; return \"ftst.s %0\"; }") (define_insn "tstdf" [(set (cc0) (match_operand:DF 0 "general_operand" "fmF"))] "TARGET_FPU" "* { cc_status.flags = CC_IN_FPU; return \"ftst.d %0\"; }") ;; compare instructions. ;; (operand0 - operand1) (define_insn "cmpsi" [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "ri,rm") (match_operand:SI 1 "general_operand" "rm,rmi")))] "" "* { int signed_flag = my_signed_comp (insn); if (which_alternative == 0) { cc_status.flags |= CC_REVERSED; if (signed_flag && GET_CODE (operands[0]) == CONST_INT) { register rtx xfoo; xfoo = operands[1]; operands[0] = operands[1]; operands[1] = xfoo; return cmp_imm_word (INTVAL (operands[1]), operands[0]); } if (signed_flag) return \"cmp.w %0,%1\"; return \"cmpu.w %0,%1\"; } if (signed_flag) { if (GET_CODE (operands[1]) == CONST_INT) return cmp_imm_word (INTVAL (operands[1]), operands[0]); return \"cmp.w %1,%0\"; } else return \"cmpu.w %1,%0\"; }") (define_insn "cmphi" [(set (cc0) (compare (match_operand:HI 0 "nonimmediate_operand" "ri,rm") (match_operand:HI 1 "general_operand" "rm,rmi")))] "" "* { int signed_flag = my_signed_comp (insn); if (which_alternative == 0) { cc_status.flags |= CC_REVERSED; if (signed_flag) return \"cmp.h %0,%1\"; return \"cmpu.h %0,%1\"; } if (signed_flag) return \"cmp.h %1,%0\"; return \"cmpu.h %1,%0\"; }") (define_insn "cmpqi" [(set (cc0) (compare (match_operand:QI 0 "nonimmediate_operand" "ri,rm") (match_operand:QI 1 "general_operand" "rm,rmi")))] "" "* { int signed_flag = my_signed_comp (insn); if (which_alternative == 0) { cc_status.flags |= CC_REVERSED; if (signed_flag) return \"cmp.b %0,%1\"; return \"cmpu.b %0,%1\"; } if (signed_flag) return \"cmp.b %1,%0\"; return \"cmpu.b %1,%0\"; }") (define_insn "cmpdf" [(set (cc0) (compare (match_operand:DF 0 "general_operand" "f,mG") (match_operand:DF 1 "general_operand" "fmG,f")))] "TARGET_FPU" "* { cc_status.flags = CC_IN_FPU; if (FPU_REG_P (operands[0])) return \"fcmp.d %f1,%f0\"; cc_status.flags |= CC_REVERSED; return \"fcmp.d %f0,%f1\"; }") (define_insn "cmpsf" [(set (cc0) (compare (match_operand:SF 0 "general_operand" "f,mG") (match_operand:SF 1 "general_operand" "fmG,f")))] "TARGET_FPU" "* { cc_status.flags = CC_IN_FPU; if (FPU_REG_P (operands[0])) return \"fcmp.s %f1,%0\"; cc_status.flags |= CC_REVERSED; return \"fcmp.s %f0,%1\"; }") ;; Recognizers for btst instructions. (define_insn "" [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "rm") (const_int 1) (match_operand:SI 1 "general_operand" "rmi")))] "" "btst %1.w,%0.b") (define_insn "" [(set (cc0) (zero_extract (match_operand:HI 0 "nonimmediate_operand" "rm") (const_int 1) (match_operand:SI 1 "general_operand" "rmi")))] "" "btst %1.w,%0.h") (define_insn "" [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "rm") (const_int 1) (match_operand:SI 1 "general_operand" "rmi")))] "" "btst %1.w,%0.w") ;; The following two patterns are like the previous two ;; except that they use the fact that bit-number operands (offset) ;; are automatically masked to 3 or 5 bits when the base is a register. (define_insn "" [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "r") (const_int 1) (and:SI (match_operand:SI 1 "general_operand" "rmi") (const_int 7))))] "" "btst %1.w,%0.b") (define_insn "" [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "r") (const_int 1) (and:SI (match_operand:SI 1 "general_operand" "rmi") (const_int 31))))] "" "btst %1.w,%0.w") ; More various size-patterns are allowed for btst, but not ; included yet. M.Yuhara (define_insn "" [(set (cc0) (and:SI (sign_extend:SI (sign_extend:HI (match_operand:QI 0 "nonimmediate_operand" "rm"))) (match_operand:SI 1 "general_operand" "i")))] "(GET_CODE (operands[1]) == CONST_INT && (unsigned) INTVAL (operands[1]) < 0x100 && exact_log2 (INTVAL (operands[1])) >= 0)" "* { register int log = exact_log2 (INTVAL (operands[1])); operands[1] = gen_rtx (CONST_INT, VOIDmode, log); return \"btst %1,%0.b\"; }") ; I can add more patterns like above. But not yet. M.Yuhara ; mtst is supported only by G/300. (define_insn "" [(set (cc0) (and:SI (match_operand:SI 0 "general_operand" "%rmi") (match_operand:SI 1 "general_operand" "rm")))] "TARGET_G300" "* { if (GET_CODE (operands[0]) == CONST_INT) return \"mtst.w %0,%1\"; return \"mtst.w %1,%0\"; }") (define_insn "" [(set (cc0) (and:HI (match_operand:HI 0 "general_operand" "%rmi") (match_operand:HI 1 "general_operand" "rm")))] "TARGET_G300" "* { if (GET_CODE (operands[0]) == CONST_INT) return \"mtst.h %0,%1\"; return \"mtst.h %1,%0\"; }") (define_insn "" [(set (cc0) (and:QI (match_operand:QI 0 "general_operand" "%rmi") (match_operand:QI 1 "general_operand" "rm")))] "TARGET_G300" "* { if (GET_CODE (operands[0]) == CONST_INT) return \"mtst.b %0,%1\"; return \"mtst.b %1,%0\"; }") ;; move instructions /* added by M.Yuhara */ ;; 1.35.04 89.08.28 modification start ;; register_operand -> general_operand ;; ashift -> mult (define_insn "" [(set (mem:SI (plus:SI (match_operand:SI 0 "general_operand" "r") (ashift:SI (match_operand:SI 1 "general_operand" "r") (const_int 2)))) (match_operand:SI 2 "general_operand" "rmi"))] "" "* { return \"mov.w %2,@(%0:b,%1*4)\"; }") (define_insn "" [(set (mem:SI (plus:SI (ashift:SI (match_operand:SI 0 "general_operand" "r") (const_int 2)) (match_operand:SI 1 "general_operand" "r"))) (match_operand:SI 2 "general_operand" "rmi"))] "" "* { return \"mov.w %2,@(%1:b,%0*4)\"; }") (define_insn "" [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r") (mult:SI (match_operand:SI 1 "register_operand" "r") (const_int 4)))) (match_operand:SI 2 "general_operand" "rmi"))] "" "* { return \"mov.w %2,@(%0:b,%1*4)\"; }") (define_insn "" [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "r") (const_int 4)) (match_operand:SI 1 "register_operand" "r"))) (match_operand:SI 2 "general_operand" "rmi"))] "" "* { return \"mov.w %2,@(%1:b,%0*4)\"; }") (define_insn "" [(set (mem:SI (plus:SI (match_operand:SI 0 "general_operand" "r") (plus:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "register_operand" "i")))) (match_operand:SI 3 "general_operand" "rmi"))] "" "* { return \"mov.w %3,@(%c2,%0,%1)\"; }") (define_insn "" [(set (mem:SI (plus:SI (plus:SI (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "register_operand" "r")) (match_operand:SI 2 "general_operand" "i"))) (match_operand:SI 3 "general_operand" "rmi"))] "" "* { return \"mov.w %3,@(%c2,%0,%1)\"; }") (define_insn "" [(set (mem:SI (plus:SI (match_operand:SI 0 "general_operand" "i") (plus:SI (match_operand:SI 1 "register_operand" "r") (mult:SI (match_operand:SI 2 "register_operand" "r") (const_int 4))))) (match_operand:SI 3 "general_operand" "rmi"))] "" "* { return \"mov.w %3,@(%1:b,%0,%2*4)\"; }") ;; 89.08.28 1.35.04 modification end ;; Should add "!" to op2 ?? ;; General move-address-to-operand should handle these. ;; If that does not work, please figure out why. ;(define_insn "" ; [(set (match_operand:SI 0 "push_operand" "=m") ; (plus:SI ; (match_operand:SI 1 "immediate_operand" "i") ; (match_operand:SI 2 "general_operand" "r")))] ; "" ; "mova.w @(%c1,%2),%-") ;(define_insn "" ; [(set (match_operand:SI 0 "push_operand" "=m") ; (plus:SI ; (match_operand:SI 1 "general_operand" "r") ; (match_operand:SI 2 "immediate_operand" "i")))] ; "" ; "mova.w @(%c2,%1),%-") (define_insn "" [(set (match_operand:SI 0 "push_operand" "=m") (minus:SI (match_operand:SI 1 "general_operand" "r") (match_operand:SI 2 "immediate_operand" "i")))] "" "mova.w @(%n2,%1),%-") ;; General case of fullword move. (define_insn "movsi" [(set (match_operand:SI 0 "general_operand" "=rm") (match_operand:SI 1 "general_operand" "rmi"))] "" "* { if (GET_CODE (operands[1]) == CONST_INT) return mov_imm_word (INTVAL (operands[1]), operands[0]); /* if (address_operand (operands[1], SImode)) return \"mova.w %1,%0\"; */ if (push_operand (operands[0], SImode)) return \"mov.w %1,%-\"; return \"mov.w %1,%0\"; }") /* pushsi 89.08.10 for test M.Yuhara */ /* (define_insn "" [(set (match_operand:SI 0 "push_operand" "=m") (match_operand:SI 1 "general_operand" "rmi"))] "" "* { if (GET_CODE (operands[1]) == CONST_INT) return mov_imm_word (INTVAL (operands[1]), operands[0]); if (push_operand (operands[0], SImode)) return \"mov.w %1,%-\"; return \"mov.w %1,%0\"; }") */ (define_insn "movhi" [(set (match_operand:HI 0 "general_operand" "=rm") (match_operand:HI 1 "general_operand" "rmi"))] "" "* { if (push_operand (operands[0], SImode)) return \"mov.h %1,%-\"; return \"mov.h %1,%0\"; }") ;; Is the operand constraint "+" necessary ???? ;; Should I check push_operand ???? (define_insn "movstricthi" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm")) (match_operand:HI 1 "general_operand" "rmi"))] "" "mov.h %1,%0"); (define_insn "movqi" [(set (match_operand:QI 0 "general_operand" "=rm") (match_operand:QI 1 "general_operand" "rmi"))] "" "* { if (GREG_P (operands[0])) { if (CONSTANT_P (operands[1])) return \"mov:l %1,%0.w\"; else return \"mov:l %1.b,%0.w\"; } if (GREG_P (operands[1])) return \"mov:s %1.w,%0.b\"; return \"mov.b %1,%0\"; }") (define_insn "movstrictqi" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm")) (match_operand:QI 1 "general_operand" "rmi"))] "" "mov.b %1,%0") (define_insn "movsf" [(set (match_operand:SF 0 "general_operand" "=f,mf,rm,fr") (match_operand:SF 1 "general_operand" "mfF,f,rmF,fr"))] "" "* { switch (which_alternative) { case 0: if (GET_CODE (operands[1]) == CONST_DOUBLE) return output_move_const_single (operands); return \"fmov.s %1,%0\"; case 1: return \"fmov.s %1,%0\"; case 2: if (GET_CODE (operands[1]) == CONST_DOUBLE) return output_move_const_single (operands); return \"mov.w %1,%0\"; case 3: if (FPU_REG_P (operands[0])) return \"mov.w %1,%-\\n\\tfmov.s %+,%0\"; return \"fmov.s %1,%-\\n\\tmov.w %+,%0\"; } }") (define_insn "movdf" [(set (match_operand:DF 0 "general_operand" "=f,mf,rm,fr") (match_operand:DF 1 "general_operand" "mfF,f,rmF,fr"))] "" "* { switch (which_alternative) { case 0: if (GET_CODE (operands[1]) == CONST_DOUBLE) return output_move_const_double (operands); return \"fmov.d %1,%0\"; case 1: return \"fmov.d %1,%0\"; case 2: if (GET_CODE (operands[1]) == CONST_DOUBLE) return output_move_const_double (operands); return output_move_double (operands); case 3: if (FPU_REG_P (operands[0])) { rtx xoperands[2]; xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); output_asm_insn (\"mov.w %1,%-\", xoperands); output_asm_insn (\"mov.w %1,%-\", operands); return \"fmov.d %+,%0\"; } else { output_asm_insn (\"fmov.d %f1,%-\", operands); output_asm_insn (\"mov.w %+,%0\", operands); operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); return \"mov.w %+,%0\"; } } }") ;; movdi can apply to fp regs in some cases ;; Must check again. you can use fsti/fldi, etc. ;; FPU reg should be included ?? ;; 89.12.13 for test (define_insn "movdi" ;; Let's see if it really still needs to handle fp regs, and, if so, why. [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro") (match_operand:DI 1 "general_operand" "rF,m,roiF"))] "" "* { if (FPU_REG_P (operands[0])) { if (FPU_REG_P (operands[1])) return \"fmov.d %1,%0\"; if (REG_P (operands[1])) { rtx xoperands[2]; xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); output_asm_insn (\"mov.w %1,%-\", xoperands); output_asm_insn (\"mov.w %1,%-\", operands); return \"fmov.d %+,%0\"; } if (GET_CODE (operands[1]) == CONST_DOUBLE) return output_move_const_double (operands); return \"fmov.d %f1,%0\"; } else if (FPU_REG_P (operands[1])) { if (REG_P (operands[0])) { output_asm_insn (\"fmov.d %f1,%-\;mov.w %+,%0\", operands); operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); return \"mov.w %+,%0\"; } else return \"fmov.d %f1,%0\"; } return output_move_double (operands); } ") ;; The definition of this insn does not really explain what it does, ;; but it should suffice ;; that anything generated as this insn will be recognized as one ;; and that it won't successfully combine with anything. ;; This is dangerous when %0 and %1 overlapped !!!!! ;; Ugly code... (define_insn "movstrhi" [(set (match_operand:BLK 0 "general_operand" "=m") (match_operand:BLK 1 "general_operand" "m")) (use (match_operand:HI 2 "general_operand" "rmi")) (clobber (reg:SI 0)) (clobber (reg:SI 1)) (clobber (reg:SI 2))] "" "* { int op2const; rtx tmpx; if (CONSTANT_P (operands[1])) { fprintf (stderr, \"smov 1 const err \"); abort (); } else if (GET_CODE (operands[1]) == REG) { fprintf (stderr, \"smov 1 reg err \"); abort (); } else if (GET_CODE (operands[1]) == MEM) { tmpx = XEXP (operands[1], 0); if (CONSTANT_ADDRESS_P (tmpx) || GREG_P (tmpx)) { operands[1] = tmpx; output_asm_insn (\"mov.w %1,r0\", operands); } else { output_asm_insn (\"mova %1,r0\", operands); } } else { fprintf (stderr, \"smov 1 else err \"); abort (); output_asm_insn (\"mova.w %p1,r0\", operands); } if (CONSTANT_P (operands[0])) { fprintf (stderr, \"smov 0 const err \"); abort (); } else if (GET_CODE (operands[0]) == REG) { fprintf (stderr, \"smov 0 reg err \"); abort (); } else if (GET_CODE (operands[0]) == MEM) { tmpx = XEXP (operands[0], 0); if (CONSTANT_ADDRESS_P (tmpx) || GREG_P (tmpx)) { operands[0] = tmpx; output_asm_insn (\"mov.w %0,r1\", operands); } else { output_asm_insn (\"mova %0,r1\", operands); } } else { fprintf (stderr, \"smov 0 else err \"); abort (); } if (GET_CODE (operands[2]) == CONST_INT) { op2const = INTVAL (operands[2]); if (op2const % 4 != 0) { output_asm_insn (\"mov.w %2,r2\", operands); return \"smov/n/f.b\"; } op2const = op2const / 4; if (op2const <= 4) { if (op2const == 0) abort (0); if (op2const == 1) return \"mov.w @r0,@r1\"; output_asm_insn (\"mov.w @r0,@r1\", operands); if (op2const == 2) return \"mov.w @(4,r0),@(4,r1)\"; output_asm_insn (\"mov.w @(4,r0),@(4,r1)\", operands); if (op2const == 3) return \"mov.w @(8,r0),@(8,r1)\"; output_asm_insn (\"mov.w @(8,r0),@(8,r1)\", operands); return \"mov.w @(12,r0),@(12,r1)\"; } operands[2] = gen_rtx (CONST_INT, VOIDmode, op2const); output_asm_insn (\"mov.w %2,r2\", operands); return \"smov/n/f.w\"; } else { fprintf (stderr, \"smov 0 else err \"); abort (); output_asm_insn (\"mov %2.h,r2.w\", operands); return \"smov/n/f.b\"; } }") ;; M.Yuhara 89.08.24 ;; experiment on the built-in strcpy (__builtin_smov) ;; ;; len = 0 means unknown string length. ;; ;; mem:SI is dummy. Necessary so as not to be deleted by optimization. ;; Use of BLKmode would be better... ;; ;; (define_insn "smovsi" [(set (mem:SI (match_operand:SI 0 "general_operand" "=rm")) (mem:SI (match_operand:SI 1 "general_operand" "rm"))) (use (match_operand:SI 2 "general_operand" "i")) (clobber (reg:SI 0)) (clobber (reg:SI 1)) (clobber (reg:SI 2)) (clobber (reg:SI 3))] "" "* { int len, wlen, blen, offset; char tmpstr[128]; rtx xoperands[1]; len = INTVAL (operands[2]); output_asm_insn (\"mov.w %1,r0\\t; begin built-in strcpy\", operands); output_asm_insn (\"mov.w %0,r1\", operands); if (len == 0) { output_asm_insn (\"mov:z.w #0,r2\", operands); output_asm_insn (\"mov:z.w #0,r3\", operands); return \"smov/eq/f.b\\t; end built-in strcpy\"; } wlen = len / 4; blen = len - wlen * 4; if (wlen > 0) { if (len <= 40 && !TARGET_FORCE_SMOV) { output_asm_insn (\"mov.w @r0,@r1\", operands); offset = 4; while ( (blen = len - offset) > 0) { if (blen >= 4) { sprintf (tmpstr, \"mov.w @(%d,r0),@(%d,r1)\", offset, offset); output_asm_insn (tmpstr, operands); offset += 4; } else if (blen >= 2) { sprintf (tmpstr, \"mov.h @(%d,r0),@(%d,r1)\", offset, offset); output_asm_insn (tmpstr, operands); offset += 2; } else { sprintf (tmpstr, \"mov.b @(%d,r0),@(%d,r1)\", offset, offset); output_asm_insn (tmpstr, operands); offset++; } } return \"\\t\\t; end built-in strcpy\"; } else { xoperands[0] = gen_rtx (CONST_INT, VOIDmode, wlen); output_asm_insn (\"mov.w %0,r2\", xoperands); output_asm_insn (\"smov/n/f.w\", operands); } } if (blen >= 2) { output_asm_insn (\"mov.h @r0,@r1\", operands); if (blen == 3) output_asm_insn (\"mov.b @(2,r0),@(2,r1)\", operands); } else if (blen == 1) { output_asm_insn (\"mov.b @r0,@r1\", operands); } return \"\\t\\t; end built-in strcpy\"; }") ;; truncation instructions (define_insn "truncsiqi2" [(set (match_operand:QI 0 "general_operand" "=rm") (truncate:QI (match_operand:SI 1 "general_operand" "rmi")))] "" "mov %1.w,%0.b") ; "* ;{ ; if (GET_CODE (operands[0]) == REG) ; return \"mov.w %1,%0\"; ; if (GET_CODE (operands[1]) == MEM) ; operands[1] = adj_offsettable_operand (operands[1], 3); ; return \"mov.b %1,%0\"; ;}") (define_insn "trunchiqi2" [(set (match_operand:QI 0 "general_operand" "=rm") (truncate:QI (match_operand:HI 1 "general_operand" "rmi")))] "" "mov %1.h,%0.b") ; "* ;{ ; if (GET_CODE (operands[0]) == REG) ; return \"mov.h %1,%0\"; ; if (GET_CODE (operands[1]) == MEM) ; operands[1] = adj_offsettable_operand (operands[1], 1); ; return \"mov.b %1,%0\"; ;}") (define_insn "truncsihi2" [(set (match_operand:HI 0 "general_operand" "=rm") (truncate:HI (match_operand:SI 1 "general_operand" "rmi")))] "" "mov %1.w,%0.h") ; "* ;{ ; if (GET_CODE (operands[0]) == REG) ; return \"mov.w %1,%0\"; ; if (GET_CODE (operands[1]) == MEM) ; operands[1] = adj_offsettable_operand (operands[1], 2); ; return \"mov.h %1,%0\"; ;}") ;; zero extension instructions ;; define_expand (68k) -> define_insn (Gmicro) (define_insn "zero_extendhisi2" [(set (match_operand:SI 0 "general_operand" "=rm") (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] "" "movu %1.h,%0.w") (define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "general_operand" "=rm") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))] "" "movu %1.b,%0.h") (define_insn "zero_extendqisi2" [(set (match_operand:SI 0 "general_operand" "=rm") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] "" "movu %1.b,%0.w") ;; sign extension instructions (define_insn "extendhisi2" [(set (match_operand:SI 0 "general_operand" "=rm") (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] "" "mov %1.h,%0.w") (define_insn "extendqihi2" [(set (match_operand:HI 0 "general_operand" "=rm") (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))] "" "mov %1.b,%0.h") (define_insn "extendqisi2" [(set (match_operand:SI 0 "general_operand" "=rm") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] "" "mov %1.b,%0.w") ;; Conversions between float and double. (define_insn "extendsfdf2" [(set (match_operand:DF 0 "general_operand" "=*frm,f") (float_extend:DF (match_operand:SF 1 "general_operand" "f,rmF")))] "TARGET_FPU" "* { if (FPU_REG_P (operands[0])) { if (GET_CODE (operands[1]) == CONST_DOUBLE) return output_move_const_double (operands); if (GREG_P (operands[1])) { output_asm_insn (\"mov.w %1,%-\", operands); return \"fmov %+.s,%0.d\"; } return \"fmov %1.s,%0.d\"; } else { if (GREG_P (operands[0])) { output_asm_insn (\"fmov %1.s,%-.d\", operands); output_asm_insn (\"mov.w %+,%0\", operands); operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); return \"mov.w %+,%0\"; } return \"fmov %1.s,%0.d\"; } }") (define_insn "truncdfsf2" [(set (match_operand:SF 0 "general_operand" "=rfm") (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] "TARGET_FPU" "* { if (GREG_P (operands[0])) { output_asm_insn (\"fmov %1.d,%-.s\", operands); return \"mov.w %+,%0\"; } return \"fmov %1.d,%0.s\"; }") ;; Conversion between fixed point and floating point. ;; Note that among the fix-to-float insns ;; the ones that start with SImode come first. ;; That is so that an operand that is a CONST_INT ;; (and therefore lacks a specific machine mode). ;; will be recognized as SImode (which is always valid) ;; rather than as QImode or HImode. (define_insn "floatsisf2" [(set (match_operand:SF 0 "general_operand" "=f") (float:SF (match_operand:SI 1 "general_operand" "rmi")))] "TARGET_FPU" "fldi %1.w,%0.s") (define_insn "floatsidf2" [(set (match_operand:DF 0 "general_operand" "=f") (float:DF (match_operand:SI 1 "general_operand" "rmi")))] "TARGET_FPU" "fldi %1.w,%0.d") (define_insn "floathisf2" [(set (match_operand:SF 0 "general_operand" "=f") (float:SF (match_operand:HI 1 "general_operand" "rmi")))] "TARGET_FPU" "fldi %1.h,%0.s") (define_insn "floathidf2" [(set (match_operand:DF 0 "general_operand" "=f") (float:DF (match_operand:HI 1 "general_operand" "rmi")))] "TARGET_FPU" "fldi %1.h,%0.d") (define_insn "floatqisf2" [(set (match_operand:SF 0 "general_operand" "=f") (float:SF (match_operand:QI 1 "general_operand" "rmi")))] "TARGET_FPU" "fldi %1.b,%0.s") (define_insn "floatqidf2" [(set (match_operand:DF 0 "general_operand" "=f") (float:DF (match_operand:QI 1 "general_operand" "rmi")))] "TARGET_FPU" "fldi %1.b,%0.d") ;;; Convert a float to a float whose value is an integer. ;;; This is the first stage of converting it to an integer type. ; ;(define_insn "ftruncdf2" ; [(set (match_operand:DF 0 "general_operand" "=f") ; (fix:DF (match_operand:DF 1 "general_operand" "fFm")))] ; "TARGET_FPU" ; "* ;{ ; return \"fintrz.d %f1,%0\"; ;}") ; ;(define_insn "ftruncsf2" ; [(set (match_operand:SF 0 "general_operand" "=f") ; (fix:SF (match_operand:SF 1 "general_operand" "fFm")))] ; "TARGET_FPU" ; "* ;{ ; return \"fintrz.s %f1,%0\"; ;}") ;; Convert a float to an integer. (define_insn "fix_truncsfqi2" [(set (match_operand:QI 0 "general_operand" "=rm") (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "f"))))] "TARGET_FPU" "fsti %1.s,%0.b") (define_insn "fix_truncsfhi2" [(set (match_operand:HI 0 "general_operand" "=rm") (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "f"))))] "TARGET_FPU" "fsti %1.s,%0.h") (define_insn "fix_truncsfsi2" [(set (match_operand:SI 0 "general_operand" "=rm") (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "f"))))] "TARGET_FPU" "fsti %1.s,%0.w") (define_insn "fix_truncdfqi2" [(set (match_operand:QI 0 "general_operand" "=rm") (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "f"))))] "TARGET_FPU" "fsti %1.d,%0.b") (define_insn "fix_truncdfhi2" [(set (match_operand:HI 0 "general_operand" "=rm") (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "f"))))] "TARGET_FPU" "fsti %1.d,%0.h") (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "general_operand" "=rm") (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "f"))))] "TARGET_FPU" "fsti %1.d,%0.w") ;;; Special add patterns ;;; 89.09.28 ;; This should be redundant; please find out why regular addsi3 ;; fails to match this case. ;(define_insn "" ; [(set (mem:SI (plus:SI ; (plus:SI (match_operand 0 "general_operand" "r") ; (match_operand 1 "general_operand" "r")) ; (match_operand 2 "general_operand" "i"))) ; (plus:SI ; (mem:SI (plus:SI ; (plus:SI (match_dup 0) ; (match_dup 1)) ; (match_dup 2))) ; (match_operand 3 "general_operand" "rmi")))] ; "" ; "add.w %3,@(%c2,%0,%1)") ;; add instructions ;; Note that the last two alternatives are near-duplicates ;; in order to handle insns generated by reload. ;; This is needed since they are not themselves reloaded, ;; so commutativity won't apply to them. (define_insn "addsi3" [(set (match_operand:SI 0 "general_operand" "=rm,!r,!r") (plus:SI (match_operand:SI 1 "general_operand" "%0,r,ri") (match_operand:SI 2 "general_operand" "rmi,ri,r")))] "" "* { if (which_alternative == 0) { if (GET_CODE (operands[2]) == CONST_INT) { operands[1] = operands[2]; return add_imm_word (INTVAL (operands[1]), operands[0], &operands[1]); } else return \"add.w %2,%0\"; } else { if (GET_CODE (operands[1]) == REG && REGNO (operands[0]) == REGNO (operands[1])) return \"add.w %2,%0\"; if (GET_CODE (operands[2]) == REG && REGNO (operands[0]) == REGNO (operands[2])) return \"add.w %1,%0\"; if (GET_CODE (operands[1]) == REG) { if (GET_CODE (operands[2]) == REG) return \"mova.w @(%1,%2),%0\"; else return \"mova.w @(%c2,%1),%0\"; } else return \"mova.w @(%c1,%2),%0\"; } }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=rm") (plus:SI (match_operand:SI 1 "general_operand" "0") (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmi"))))] "" "* { if (CONSTANT_P (operands[2])) { operands[1] = operands[2]; return add_imm_word (INTVAL (operands[1]), operands[0], &operands[1]); } else return \"add %2.h,%0.w\"; }") (define_insn "addhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (plus:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "rmi")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) return \"sub.h #%n2,%0\"; if (GREG_P (operands[0])) { if (CONSTANT_P (operands[2])) return \"add:l %2,%0.w\"; else return \"add:l %2.h,%0.w\"; } return \"add.h %2,%0\"; }") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm")) (plus:HI (match_dup 0) (match_operand:HI 1 "general_operand" "rmi")))] "" "add.h %1,%0") (define_insn "addqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (plus:QI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "general_operand" "rmi")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) return \"sub.b #%n2,%0\"; if (GREG_P (operands[0])) { if (CONSTANT_P (operands[2])) return \"add:l %2,%0.w\"; else return \"add:l %2.b,%0.w\"; } return \"add.b %2,%0\"; }") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm")) (plus:QI (match_dup 0) (match_operand:QI 1 "general_operand" "rmi")))] "" "add.b %1,%0") (define_insn "adddf3" [(set (match_operand:DF 0 "general_operand" "=f") (plus:DF (match_operand:DF 1 "general_operand" "%0") (match_operand:DF 2 "general_operand" "fmG")))] "TARGET_FPU" "fadd.d %f2,%0") (define_insn "addsf3" [(set (match_operand:SF 0 "general_operand" "=f") (plus:SF (match_operand:SF 1 "general_operand" "%0") (match_operand:SF 2 "general_operand" "fmG")))] "TARGET_FPU" "fadd.s %f2,%0") ;; subtract instructions (define_insn "subsi3" [(set (match_operand:SI 0 "general_operand" "=rm,!r") (minus:SI (match_operand:SI 1 "general_operand" "0,r") (match_operand:SI 2 "general_operand" "rmi,i")))] "" "* { if (which_alternative == 0 || (GET_CODE (operands[1]) == REG && REGNO (operands[0]) == REGNO (operands[1]))) { if (GET_CODE (operands[2]) == CONST_INT) { operands[1] = operands[2]; return sub_imm_word (INTVAL (operands[1]), operands[0], &operands[1]); } else return \"sub.w %2,%0\"; } else return \"mova.w @(%n2,%1),%0\"; }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=rm") (minus:SI (match_operand:SI 1 "general_operand" "0") (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmi"))))] "" "sub %2.h,%0.w") (define_insn "subhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (minus:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "rmi")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0 && INTVAL (operands[2]) != 0x8000) return \"add.h #%n2,%0\"; return \"sub.h %2,%0\"; }") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm")) (minus:HI (match_dup 0) (match_operand:HI 1 "general_operand" "rmi")))] "" "sub.h %1,%0") (define_insn "subqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (minus:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "rmi")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0 && INTVAL (operands[2]) != 0x80) return \"add.b #%n2,%0\"; return \"sub.b %2,%0\"; }") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm")) (minus:QI (match_dup 0) (match_operand:QI 1 "general_operand" "rmi")))] "" "sub.b %1,%0") (define_insn "subdf3" [(set (match_operand:DF 0 "general_operand" "=f") (minus:DF (match_operand:DF 1 "general_operand" "0") (match_operand:DF 2 "general_operand" "fmG")))] "TARGET_FPU" "fsub.d %f2,%0") (define_insn "subsf3" [(set (match_operand:SF 0 "general_operand" "=f") (minus:SF (match_operand:SF 1 "general_operand" "0") (match_operand:SF 2 "general_operand" "fmG")))] "TARGET_FPU" "fsub.s %f2,%0") ;; multiply instructions (define_insn "mulqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (mult:QI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "general_operand" "rmi")))] "" "mul.b %2,%0") (define_insn "mulhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (mult:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "rmi")))] "" "mul.h %2,%0") ;; define_insn "mulhisi3" (define_insn "mulsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (mult:SI (match_operand:SI 1 "general_operand" "%0") (match_operand:SI 2 "general_operand" "rmi")))] "" "mul.w %2,%0") (define_insn "muldf3" [(set (match_operand:DF 0 "general_operand" "=f") (mult:DF (match_operand:DF 1 "general_operand" "%0") (match_operand:DF 2 "general_operand" "fmG")))] "TARGET_FPU" "fmul.d %f2,%0") (define_insn "mulsf3" [(set (match_operand:SF 0 "general_operand" "=f") (mult:SF (match_operand:SF 1 "general_operand" "%0") (match_operand:SF 2 "general_operand" "fmG")))] "TARGET_FPU" "fmul.s %f2,%0") ;; divide instructions (define_insn "divqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (div:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "rmi")))] "" "div.b %2,%0") (define_insn "divhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (div:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "rmi")))] "" "div.h %2,%0") (define_insn "divhisi3" [(set (match_operand:HI 0 "general_operand" "=r") (div:HI (match_operand:SI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "rmi")))] "" "div %2.h,%0.w") (define_insn "divsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (div:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "rmi")))] "" "div.w %2,%0") (define_insn "udivqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (udiv:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "rmi")))] "" "divu.b %2,%0") (define_insn "udivhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (udiv:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "rmi")))] "" "divu.h %2,%0") (define_insn "udivhisi3" [(set (match_operand:HI 0 "general_operand" "=r") (udiv:HI (match_operand:SI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "rmi")))] "" "divu %2.h,%0.w") (define_insn "udivsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (udiv:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "rmi")))] "" "divu.w %2,%0") (define_insn "divdf3" [(set (match_operand:DF 0 "general_operand" "=f") (div:DF (match_operand:DF 1 "general_operand" "0") (match_operand:DF 2 "general_operand" "fmG")))] "TARGET_FPU" "fdiv.d %f2,%0") (define_insn "divsf3" [(set (match_operand:SF 0 "general_operand" "=f") (div:SF (match_operand:SF 1 "general_operand" "0") (match_operand:SF 2 "general_operand" "fmG")))] "TARGET_FPU" "fdiv.s %f2,%0") ;; Remainder instructions. (define_insn "modqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (mod:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "rmi")))] "" "rem.b %2,%0") (define_insn "modhisi3" [(set (match_operand:HI 0 "general_operand" "=r") (mod:HI (match_operand:SI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "rmi")))] "" "rem.h %2,%0") (define_insn "umodqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (umod:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "rmi")))] "" "remu.b %2,%0") (define_insn "umodhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (umod:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "rmi")))] "" "remu.h %2,%0") (define_insn "umodhisi3" [(set (match_operand:HI 0 "general_operand" "=r") (umod:HI (match_operand:SI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "rmi")))] "" "remu %2.h,%0.w") ;; define_insn "divmodsi4" (define_insn "udivmodsi4" [(set (match_operand:SI 0 "general_operand" "=rm") (udiv:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "rmi"))) (set (match_operand:SI 3 "general_operand" "=r") (umod:SI (match_dup 1) (match_dup 2)))] "" "mov.w #0,%3;divx.w %2,%0,%3") ;; logical-and instructions (define_insn "andsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (and:SI (match_operand:SI 1 "general_operand" "%0") (match_operand:SI 2 "general_operand" "rmi")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) | 0xffff) == 0xffffffff && (GREG_P (operands[0]) || offsettable_memref_p (operands[0]))) { if (GET_CODE (operands[0]) != REG) operands[0] = adj_offsettable_operand (operands[0], 2); operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); /* Do not delete a following tstl %0 insn; that would be incorrect. */ CC_STATUS_INIT; return \"and.h %2,%0\"; } return \"and.w %2,%0\"; }") (define_insn "andhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (and:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "rmi")))] "" "and.h %2,%0") (define_insn "andqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (and:QI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "general_operand" "rmi")))] "" "and.b %2,%0") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=r") (and:SI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")) (match_operand:SI 2 "general_operand" "0")))] "" "* { if (GET_CODE (operands[1]) == CONST_INT) return \"and %1,%0.w\"; return \"and %1.h,%0.w\"; }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=r") (and:SI (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")) (match_operand:SI 2 "general_operand" "0")))] "" "* { if (GET_CODE (operands[1]) == CONST_INT) return \"and %1,%0.w\"; return \"and %1.b,%0.w\"; }") ;; inclusive-or instructions (define_insn "iorsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (ior:SI (match_operand:SI 1 "general_operand" "%0") (match_operand:SI 2 "general_operand" "rmi")))] "" "* { register int logval; if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >> 16 == 0 && (GREG_P (operands[0]) || offsettable_memref_p (operands[0]))) { if (GET_CODE (operands[0]) != REG) operands[0] = adj_offsettable_operand (operands[0], 2); /* Do not delete a following tstl %0 insn; that would be incorrect. */ CC_STATUS_INIT; return \"or.h %2,%0\"; } if (GET_CODE (operands[2]) == CONST_INT && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 && (GREG_P (operands[0]) || offsettable_memref_p (operands[0]))) { if (GREG_P (operands[0])) { if (logval < 7) { operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - logval); return \"bset.b %1,%0\"; } operands[1] = gen_rtx (CONST_INT, VOIDmode, 31 - logval); return \"bset.w %1,%0\"; } else { operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8)); operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - (logval % 8)); } return \"bset.b %1,%0\"; } return \"or.w %2,%0\"; }") (define_insn "iorhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (ior:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "rmi")))] "" "or.h %2,%0") (define_insn "iorqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (ior:QI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "general_operand" "rmi")))] "" "or.b %2,%0") ;; xor instructions (define_insn "xorsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (xor:SI (match_operand:SI 1 "general_operand" "%0") (match_operand:SI 2 "general_operand" "rmi")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >> 16 == 0 && (offsettable_memref_p (operands[0]) || GREG_P (operands[0]))) { if (! GREG_P (operands[0])) operands[0] = adj_offsettable_operand (operands[0], 2); /* Do not delete a following tstl %0 insn; that would be incorrect. */ CC_STATUS_INIT; return \"xor.h %2,%0\"; } return \"xor.w %2,%0\"; }") (define_insn "xorhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (xor:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "rmi")))] "" "xor.h %2,%0") (define_insn "xorqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (xor:QI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "general_operand" "rmi")))] "" "xor.b %2,%0") ;; negation instructions (define_insn "negsi2" [(set (match_operand:SI 0 "general_operand" "=rm") (neg:SI (match_operand:SI 1 "general_operand" "0")))] "" "neg.w %0") (define_insn "neghi2" [(set (match_operand:HI 0 "general_operand" "=rm") (neg:HI (match_operand:HI 1 "general_operand" "0")))] "" "neg.h %0") (define_insn "negqi2" [(set (match_operand:QI 0 "general_operand" "=rm") (neg:QI (match_operand:QI 1 "general_operand" "0")))] "" "neg.b %0") (define_insn "negsf2" [(set (match_operand:SF 0 "general_operand" "=f") (neg:SF (match_operand:SF 1 "general_operand" "fmF")))] "TARGET_FPU" "fneg.s %f1,%0") (define_insn "negdf2" [(set (match_operand:DF 0 "general_operand" "=f") (neg:DF (match_operand:DF 1 "general_operand" "fmF")))] "TARGET_FPU" "fneg.d %f1,%0") ;; Absolute value instructions (define_insn "abssf2" [(set (match_operand:SF 0 "general_operand" "=f") (abs:SF (match_operand:SF 1 "general_operand" "fmF")))] "TARGET_FPU" "fabs.s %f1,%0") (define_insn "absdf2" [(set (match_operand:DF 0 "general_operand" "=f") (abs:DF (match_operand:DF 1 "general_operand" "fmF")))] "TARGET_FPU" "fabs.d %f1,%0") ;; one complement instructions (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "general_operand" "=rm") (not:SI (match_operand:SI 1 "general_operand" "0")))] "" "not.w %0") (define_insn "one_cmplhi2" [(set (match_operand:HI 0 "general_operand" "=rm") (not:HI (match_operand:HI 1 "general_operand" "0")))] "" "not.h %0") (define_insn "one_cmplqi2" [(set (match_operand:QI 0 "general_operand" "=rm") (not:QI (match_operand:QI 1 "general_operand" "0")))] "" "not.b %0") ;; Optimized special case of shifting. ;; Must precede the general case. (define_insn "" [(set (match_operand:SI 0 "general_operand" "=r") (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m") (const_int 24)))] "GET_CODE (XEXP (operands[1], 0)) != POST_INC && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC" "mov:l %1.b,%0.w") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=r") (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") (const_int 24)))] "GET_CODE (XEXP (operands[1], 0)) != POST_INC && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC" "movu %1.b,%0.w") (define_insn "" [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i") (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") (const_int 24))))] "(GET_CODE (operands[0]) == CONST_INT && (INTVAL (operands[0]) & ~0xff) == 0)" "* { cc_status.flags |= CC_REVERSED; if (my_signed_comp (insn)) return \"cmp.b %0,%1\"; return \"cmpu.b %0,%1\"; }") (define_insn "" [(set (cc0) (compare (lshiftrt:SI (match_operand:SI 0 "memory_operand" "m") (const_int 24)) (match_operand:QI 1 "general_operand" "i")))] "(GET_CODE (operands[1]) == CONST_INT && (INTVAL (operands[1]) & ~0xff) == 0)" "* if (my_signed_comp (insn)) return \"cmp.b %1,%0\"; return \"cmpu.b %1,%0\"; ") (define_insn "" [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i") (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m") (const_int 24))))] "(GET_CODE (operands[0]) == CONST_INT && ((INTVAL (operands[0]) + 0x80) & ~0xff) == 0)" "* cc_status.flags |= CC_REVERSED; if (my_signed_comp (insn)) return \"cmp.b %0,%1\"; return \"cmpu.b %0,%1\"; ") (define_insn "" [(set (cc0) (compare (ashiftrt:SI (match_operand:SI 0 "memory_operand" "m") (const_int 24)) (match_operand:QI 1 "general_operand" "i")))] "(GET_CODE (operands[1]) == CONST_INT && ((INTVAL (operands[1]) + 0x80) & ~0xff) == 0)" "* if (my_signed_comp (insn)) return \"cmp.b %1,%0\"; return \"cmpu.b %1,%0\"; ") ;; arithmetic shift instructions ;; We don't need the shift memory by 1 bit instruction (define_insn "ashlsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (ashift:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "rmi")))] "" "sha.w %2,%0") (define_insn "ashlhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (ashift:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "rmi")))] "" "sha.h %2,%0") (define_insn "ashlqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (ashift:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "rmi")))] "" "sha.b %2,%0") ;; Arithmetic right shift on the Gmicro works by negating the shift count ;; ashiftrt -> ashift (define_expand "ashrsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (ashift:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "rmi")))] "" "{ operands[2] = negate_rtx (SImode, operands[2]); }") ;; ashiftrt -> ashift (define_expand "ashrhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (ashift:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "rmi")))] "" " { operands[2] = negate_rtx (HImode, operands[2]); }") ;; ashiftrt -> ashift (define_expand "ashrqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (ashift:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "rmi")))] "" " { operands[2] = negate_rtx (QImode, operands[2]); }") ;; logical shift instructions (define_insn "lshlsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (lshift:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "rmi")))] "" "shl.w %2,%0") (define_insn "lshlhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (lshift:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "rmi")))] "" "shl.h %2,%0") (define_insn "lshlqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (lshift:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "rmi")))] "" "shl.b %2,%0") ;; lshiftrt -> lshift (define_expand "lshrsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (lshift:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "rmi")))] "" " { operands[2] = negate_rtx (SImode, operands[2]); }") ;; lshiftrt -> lshift (define_expand "lshrhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (lshift:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "rmi")))] "" " { operands[2] = negate_rtx (HImode, operands[2]); }") ;; lshiftrt -> lshift (define_expand "lshrqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (lshift:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "rmi")))] "" " { operands[2] = negate_rtx (QImode, operands[2]); }") ;; rotate instructions (define_insn "rotlsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (rotate:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "rmi")))] "" "rol.w %2,%0") (define_insn "rotlhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (rotate:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "rmi")))] "" "rol.h %2,%0") (define_insn "rotlqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (rotate:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "rmi")))] "" "rol.b %2,%0") (define_expand "rotrsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (rotatert:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "rmi")))] "" " { operands[2] = negate_rtx (SImode, operands[2]); }") (define_expand "rotrhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (rotatert:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "rmi")))] "" " { operands[2] = negate_rtx (HImode, operands[2]); }") (define_expand "rotrqi3" [(set (match_operand:QI 0 "general_operand" "=rm") (rotatert:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "rmi")))] "" " { operands[2] = negate_rtx (QImode, operands[2]); }") ;; Special cases of bit-field insns which we should ;; recognize in preference to the general case. ;; These handle aligned 8-bit and 16-bit fields, ;; which can usually be done with move instructions. ;; Should I add mode_dependent_address_p ???? (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm") (match_operand:SI 1 "immediate_operand" "i") (match_operand:SI 2 "immediate_operand" "i")) (match_operand:SI 3 "general_operand" "rm"))] "TARGET_BITFIELD && GET_CODE (operands[1]) == CONST_INT && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 && (GET_CODE (operands[0]) != REG || ( INTVAL (operands[1]) + INTVAL (operands[2]) == 32))" "* { if (GET_CODE (operands[3]) == MEM) operands[3] = adj_offsettable_operand (operands[3], (32 - INTVAL (operands[1])) / 8); if (GET_CODE (operands[0]) == REG) { if (INTVAL (operands[1]) == 8) return \"movu %3.b,%0.w\"; return \"movu %3.h,%0.w\"; } else { operands[0] = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8); if (INTVAL (operands[1]) == 8) return \"mov.b %3,%0\"; return \"mov.h %3,%0\"; } }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=&r") (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "rm") (match_operand:SI 2 "immediate_operand" "i") (match_operand:SI 3 "immediate_operand" "i")))] "TARGET_BITFIELD && GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) && GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) % INTVAL (operands[2]) == 0" "* { if (!REG_P (operands[1])) operands[1] = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); if (REG_P (operands[0])) { if (REG_P (operands[1])) { if (INTVAL (operands[2]) == 8) { /* width == 8 */ switch (INTVAL (operands[3])) { case 0: return \"mov.w %1,%0;shl.w #-24,%0\"; break; case 8: return \"mov.w %1,%0;shl.w #8,%0;shl.w #-24,%0\"; break; case 16: return \"mov.w %1,%0;shl.w #16,%0;shl.w #-24,%0\"; break; case 24: return \"movu %1.b,%0.w\"; break; default: myabort (2); } } else { switch (INTVAL (operands[3])) { case 0: return \"mov.w %1,%0;shl.w #-16,%0\"; break; case 16: return \"movu %1.h,%0.w\"; break; default: myabort (3); } } } else { if (INTVAL (operands[2]) == 8) return \"movu %1.h,%0.w\"; else return \"movu %1.b,%0.w\"; } } else { /* op[0] == MEM */ if (INTVAL (operands[2]) == 8) return \"movu %1.b,%0.w\"; return \"movu %1.h,%0.w\"; } }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=r") (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") (match_operand:SI 2 "immediate_operand" "i") (match_operand:SI 3 "immediate_operand" "i")))] "TARGET_BITFIELD && GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) && GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) % INTVAL (operands[2]) == 0" "* { if (!REG_P (operands[1])) operands[1] = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); if (REG_P (operands[0])) { if (REG_P (operands[1])) { if (INTVAL (operands[2]) == 8) { /* width == 8 */ switch (INTVAL (operands[3])) { case 0: return \"mov.w %1,%0;sha.w #-24,%0\"; break; case 8: return \"mov.w %1,%0;shl.w #8,%0;sha.w #-24,%0\"; break; case 16: return \"mov.w %1,%0;shl.w #16,%0;sha.w #-24,%0\"; break; case 24: return \"mov %1.b,%0.w\"; break; default: myabort (4); } } else { switch (INTVAL (operands[3])) { case 0: return \"mov.w %1,%0;sha.w #-16,%0\"; break; case 16: return \"mov %1.h,%0.w\"; break; default: myabort (5); } } } else { if (INTVAL (operands[2]) == 8) return \"mov %1.h,%0.w\"; else return \"mov %1.b,%0.w\"; } } else { /* op[0] == MEM */ if (INTVAL (operands[2]) == 8) return \"mov %1.b,%0.w\"; return \"mov %1.h,%0.w\"; } }") ;; Bit field instructions, general cases. ;; "o,d" constraint causes a nonoffsettable memref to match the "o" ;; so that its address is reloaded. ;; extv dest:SI src(:QI/:SI) width:SI pos:SI ;; r.w m r.w/# rmi ;; %0 %1 %2 %3 (define_insn "extv" [(set (match_operand:SI 0 "general_operand" "=r") (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "m") (match_operand:SI 2 "general_operand" "ri") (match_operand:SI 3 "general_operand" "rmi")))] "TARGET_BITFIELD" "bfext %3,%2,%1,%0") (define_insn "extzv" [(set (match_operand:SI 0 "general_operand" "=r") (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "m") (match_operand:SI 2 "general_operand" "ri") (match_operand:SI 3 "general_operand" "rmi")))] "TARGET_BITFIELD" "bfextu %3,%2,%1,%0") ;; There is no insn on the Gmicro to NOT/SET/CLR bitfield. ;; insv dest(BF):QI/SI width:SI pos:SI src:SI ;; m r.w rmi r.w/i ;; 0 1 2 3 (define_insn "insv" [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+m,m") (match_operand:SI 1 "general_operand" "r,i") (match_operand:SI 2 "general_operand" "rmi,i")) (match_operand:SI 3 "general_operand" "ri,ri"))] "TARGET_BITFIELD" "bfinsu %3,%2,%1,%0") ;;; bfins/bfinsu ???????? ;; == == == == == == == == == == == == == ;; Now recognize bit field insns that operate on registers ;; (or at least were intended to do so). ;; On the Gmicro/300, ;; bitfield instructions are not applicable to registers ;-< ;; But I write the register cases, because without them the gcc ;; seems to use "and" instruction with some other instructions ;; instead of using a shift instruction. ;; It is because on many processors shift instructions are slower. ;; On the Gmicro/300 which has a barrel shifter, ;; it is faster to use a shift instruction. ;; ;; Restricts width and offset to be immediates. ;; (define_insn "" [(set (match_operand:SI 0 "general_operand" "=r") (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "r") (match_operand:SI 2 "immediate_operand" "i") (match_operand:SI 3 "immediate_operand" "i")))] "TARGET_BITFIELD" "* { if (REGNO (operands[0]) != REGNO (operands[1])) output_asm_insn (\"mov.w %1,%0\", operands); if (INTVAL (operands[3]) != 0) output_asm_insn (\"shl.w %3,%0\", operands); operands[2] = gen_rtx (CONST_INT, VOIDmode, -(32 - INTVAL (operands[2]))); return \"sha.w %3,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=r") (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "r") (match_operand:SI 2 "immediate_operand" "i") (match_operand:SI 3 "immediate_operand" "i")))] "TARGET_BITFIELD" "* { if (REGNO (operands[0]) != REGNO (operands[1])) output_asm_insn (\"mov.w %1,%0\", operands); if (INTVAL (operands[3]) != 0) output_asm_insn (\"shl.w %3,%0\", operands); operands[2] = gen_rtx (CONST_INT, VOIDmode, -(32 - INTVAL (operands[2]))); return \"shl.w %3,%0\"; }") ;; There are more descriptions for m68k, but not yet for the Gmicro. ;; ;; Basic conditional jump instructions. (define_insn "beq" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { OUTPUT_JUMP (\"beq %b0\", \"fbeq %b0\", \"beq %b0\"); }") (define_insn "bne" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { OUTPUT_JUMP (\"bne %b0\", \"fbne %b0\", \"bne %b0\"); }") (define_insn "bgt" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* OUTPUT_JUMP (\"bgt %b0\", \"fbgt %b0\", 0); ") (define_insn "bgtu" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "bgt %b0") (define_insn "blt" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* OUTPUT_JUMP (\"blt %b0\", \"fblt %b0\", \"bms %b0\"); ") ;; bms ????? ;; (define_insn "bltu" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "blt %b0") (define_insn "bge" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* OUTPUT_JUMP (\"bge %b0\", \"fbge %b0\", \"bmc %b0\"); ") ;; bmc ?? (define_insn "bgeu" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "bge %b0") (define_insn "ble" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "ble %b0") (define_insn "bleu" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "ble %b0") ;; Negated conditional jump instructions. (define_insn "" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { OUTPUT_JUMP (\"bne %b0\", \"fbne %b0\", \"bne %b0\"); }") (define_insn "" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { OUTPUT_JUMP (\"beq %b0\", \"fbeq %b0\", \"beq %b0\"); }") (define_insn "" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* OUTPUT_JUMP (\"ble %b0\", \"fbngt %b0\", 0); ") ;; fbngt ??? (define_insn "" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "ble %b0") (define_insn "" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* OUTPUT_JUMP (\"bge %b0\", \"fbnlt %b0\", \"jbmc %b0\"); ") (define_insn "" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "blt %b0") (define_insn "" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* OUTPUT_JUMP (\"blt %b0\", \"fbnge %b0\", \"jbms %b0\"); ") (define_insn "" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "blt %b0") ;; ???? (define_insn "" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* OUTPUT_JUMP (\"bgt %b0\", \"fbnle %b0\", 0); ") (define_insn "" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "bgt %b0") ;; Unconditional and other jump instructions (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "bra %b0") (define_insn "tablejump" [(set (pc) (plus:SI (pc) (match_operand:SI 0 "general_operand" "r"))) (use (label_ref (match_operand 1 "" "")))] "" "jmp @(pc:b,4:4,%0)") ;; ;; Should Add code for "ACB", "SCB". !!! ???? ;; See m68k.h (dbra) ;; ;; Call subroutine with no return value. (define_insn "call" [(call (match_operand:QI 0 "general_operand" "m") (match_operand:SI 1 "general_operand" "rmi"))] ;; Operand 1 not really used on the Gmicro. "" "* { if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0],0)) == SYMBOL_REF) return \"bsr %b0\"; return \"jsr %0\"; }") ;; Call subroutine, returning value in operand 0 ;; (which must be a hard register). (define_insn "call_value" [(set (match_operand 0 "" "=rf") (call (match_operand:QI 1 "general_operand" "m") (match_operand:SI 2 "general_operand" "rmi")))] ;; Operand 2 not really used on the Gmicro. "" "* { if (GET_CODE (operands[1]) == MEM && GET_CODE (XEXP (operands[1],0)) == SYMBOL_REF) return \"bsr %b1\"; return \"jsr %1\"; }") ;; Call subroutine returning any type. (define_expand "untyped_call" [(parallel [(call (match_operand 0 "" "") (const_int 0)) (match_operand 1 "" "") (match_operand 2 "" "")])] "" " { int i; emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); for (i = 0; i < XVECLEN (operands[2], 0); i++) { rtx set = XVECEXP (operands[2], 0, i); emit_move_insn (SET_DEST (set), SET_SRC (set)); } /* The optimizer does not know that the call sets the function value registers we stored in the result block. We avoid problems by claiming that all hard registers are used and clobbered at this point. */ emit_insn (gen_blockage ()); DONE; }") ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and ;; all of memory. This blocks insns from being moved across this point. (define_insn "blockage" [(unspec_volatile [(const_int 0)] 0)] "" "") (define_insn "nop" [(const_int 0)] "" "nop") ;; Turned off because the general move-an-address pattern handles it. ;; ;; Thus goes after the move instructions ;; because the move instructions are better (require no spilling) ;; when they can apply. ;; After add/sub now !! ;(define_insn "pushasi" ; [(set (match_operand:SI 0 "push_operand" "=m") ; (match_operand:SI 1 "address_operand" "p"))] ; "" ; "* ;{ ; if (GET_CODE (operands[1]) == CONST_INT) ; return push_imm_word (INTVAL (operands[1]), operands[0]); ; if (CONSTANT_P (operands[1])) ; return \"mov.w %1,%-\"; ; if (GET_CODE (operands[1]) == REG) ; return \"mov.w %1,%-\"; ; else if (GET_CODE (operands[1]) == MEM) ; { ; return \"mov.w %1,%-\"; ; } ; else ; return \"mova.w %p1,%-\"; ;}") ;; This should not be used unless the add/sub insns can't be. /* mova.[whq] 89.08.11 for test M.Yuhara */ ;(define_insn "" ; [(set (match_operand:SI 0 "general_operand" "=rm") ; (address (match_operand:SI 1 "address_operand" "p")))] ; "" ; "* ;{ ; if (GET_CODE (operands[1]) == CONST_INT) ; return mov_imm_word (INTVAL (operands[1]), operands[0]); ; if (CONSTANT_P (operands[1])) ; return \"mov.w %1,%0\"; ; if (GET_CODE (operands[1]) == REG) ; return \"mov.w %1,%0\"; ; else if (GET_CODE (operands[1]) == MEM) { ; operands[1] = XEXP (operands[1],0); ; return \"mov.w %1,%0\"; ; } ; else ; return \"mova.w %p1,%0\"; ;}") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=rm") (address (match_operand:HI 1 "address_operand" "")))] "" "* { if (GET_CODE (operands[1]) == CONST_INT) return mov_imm_word (INTVAL (operands[1]), operands[0]); if (CONSTANT_P (operands[1])) return \"mov.w %1,%0\"; if (GET_CODE (operands[1]) == REG) return \"mov.w %1,%0\"; else if (GET_CODE (operands[1]) == MEM) { operands[1] = XEXP (operands[1],0); return \"mov.w %1,%0\"; /* OK ? */ } else return \"mova.w %p1,%0\"; }") ;(define_insn "" ; [(set (match_operand:SI 0 "general_operand" "=rm") ; (match_operand:QI 1 "address_operand" "p"))] ; "" ; "* ;{ ; if (push_operand (operands[0], SImode)) ; return \"mova %1,%-\"; ; return \"mova %1,%0\"; ;}") ;(define_insn "" ; [(set (match_operand:SI 0 "general_operand" "=rm") ; (match_operand:QI 1 "address_operand" "p"))] ; "" ; "* ;{ ; if (CONSTANT_P (operands[1])) ; return \"mov.w %1,%0\"; ; else if (GET_CODE (operands[1]) == REG) ; return \"mov.w %1,%0\"; ; else if (GET_CODE (operands[1]) == MEM) ; { ; operands[1] = XEXP (operands[1],0); ; return \"mov.w %1,%0 ; OK?\"; ; } ; else if (GET_CODE (operands[0]) == REG ; && GET_CODE (operands[1]) == PLUS) ; { ; rtx xreg, xdisp; ; ; if (GET_CODE (XEXP (operands[1], 0)) == REG ; && REGNO (XEXP (operands[1], 0)) == REGNO (operands[0])) ; { ; xreg = XEXP (operands[1], 0); ; xdisp = XEXP (operands[1],1); ; } ; else ; { ; xreg = XEXP (operands[1], 1); ; xdisp = XEXP (operands[1],0); ; } ; ; if (GET_CODE (xreg) == REG ; && REGNO (xreg) == REGNO (operands[0]) ; && (CONSTANT_P (xdisp) || GET_CODE (xdisp) == REG)) ; { ; operands[1] = xdisp; ; if (CONSTANT_P (xdisp)) ; return add_imm_word (INTVAL (xdisp), xreg, &operands[1]); ; else ; return \"add.w %1,%0\"; ; } ; } ; return \"mova.w %p1,%0\"; ;}") ;; This is the first machine-dependent peephole optimization. ;; It is useful when a floating value is returned from a function call ;; and then is moved into an FP register. ;; But it is mainly intended to test the support for these optimizations. (define_peephole [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) (set (match_operand:DF 0 "register_operand" "=f") (match_operand:DF 1 "register_operand" "r"))] "FPU_REG_P (operands[0]) && ! FPU_REG_P (operands[1])" "* { rtx xoperands[2]; xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); output_asm_insn (\"mov.w %1,@sp\", xoperands); output_asm_insn (\"mov.w %1,%-\", operands); return \"fmov.d %+,%0\"; } ") gcc-2.5.8/config/h8300/ 40777 22011 13 0 5502602743 12706 5ustar kennerusergcc-2.5.8/config/h8300/h8300.c100444 22011 13 47236 5433346666 13753 0ustar kenneruser/* Subroutines for insn-output.c for Hitachi H8/300. Copyright (C) 1992,1993 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com) and Jim Wilson (wilson@cygnus.com). This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include "config.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "output.h" #include "insn-attr.h" #include "flags.h" #include "recog.h" #include "expr.h" #include "tree.h" /* Forward declarations. */ void print_operand_address (); char *index (); /* True if a #pragma interrupt has been seen for the current function. */ int pragma_interrupt; /* True if a #pragma saveall has been seen for the current function. */ int pragma_saveall; char *names_big[] = {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7"}; char * byte_reg (x, b) rtx x; int b; { static char *names_small[] = {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h", "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7lBAD", "r7hBAD"}; return names_small[REGNO (x) * 2 + b]; } /* REGNO must be saved/restored across calls if this macro is true. */ static int word_reg_used (regno) int regno; { if (regno < 7 && (pragma_interrupt || pragma_saveall || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) || (regs_ever_live[regno] & ! call_used_regs[regno]))) return 1; return 0; } /* Output assembly language to FILE for the operation OP with operand size SIZE. */ static void dosize (file, op, size, fped) FILE *file; char *op; unsigned int size; int fped; { switch (size) { case 4: case 3: fprintf (file, "\t%ss\t#%d,sp\n", op, 2); size -= 2; /* Fall through... */ case 2: case 1: fprintf (file, "\t%ss\t#%d,sp\n", op, size); size = 0; break; case 0: break; default: fprintf (file, "\tmov.w\t#%d,r5\n\t%s.w\tr5,sp\n", size, op); size = 0; break; } } /* Output assembly language code for the function prologue. */ static int push_order[FIRST_PSEUDO_REGISTER] = {6, 5, 4, 3, 2, 1, 0, -1, -1}; static int pop_order[FIRST_PSEUDO_REGISTER] = {0, 1, 2, 3, 4, 5, 6, -1, -1}; /* This is what the stack looks like after the prolog of a function with a frame has been set up: return pc fp-> old fp sp-> This is what the stack looks like after the prolog of a function which doesn't have a frame: return pc sp-> */ void function_prologue (file, size) FILE *file; int size; { register int mask = 0; int fsize = (size + 1) & -2; int idx; if (frame_pointer_needed) { /* Push the fp. */ fprintf (file, "\tpush\t%s\n", names_big[FRAME_POINTER_REGNUM]); fprintf (file, "\tmov.w\tr7,r6\n"); /* Leave room for the locals. */ dosize (file, "sub", fsize, 1); /* Push the rest of the registers. */ for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) { int regno = push_order[idx]; if (regno >= 0 && word_reg_used (regno) && regno != FRAME_POINTER_REGNUM) fprintf (file, "\tpush\t%s\n", names_big[regno]); } } else { dosize (file, "sub", fsize, 0); for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) { int regno = push_order[idx]; if (regno >= 0 && word_reg_used (regno)) fprintf (file, "\tpush\t%s\n", names_big[regno]); } } } /* Output assembly language code for the function epilogue. */ void function_epilogue (file, size) FILE *file; int size; { register int regno; register int mask = 0; int fsize = (size + 1) & -2; int nregs; int offset; int idx; rtx insn = get_last_insn (); /* If the last insn was a BARRIER, we don't have to write any code. */ if (GET_CODE (insn) == NOTE) insn = prev_nonnote_insn (insn); if (insn && GET_CODE (insn) == BARRIER) return; nregs = 0; if (frame_pointer_needed) { /* Pop saved registers. */ for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) { regno = pop_order[idx]; if (regno >= 0 && regno != FRAME_POINTER_REGNUM && word_reg_used (regno)) fprintf (file, "\tpop\t%s\n", names_big[regno]); } /* Deallocate locals. */ dosize (file, "add", fsize, 1); /* Pop frame pointer. */ fprintf (file, "\tpop\t%s\n", names_big[FRAME_POINTER_REGNUM]); } else { /* Deallocate locals and pop saved registers. */ for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) { regno = pop_order[idx]; if (regno >= 0 && word_reg_used (regno)) fprintf (file, "\tpop\t%s\n", names_big[regno]); } dosize (file, "add", fsize, 0); } if (pragma_interrupt) fprintf (file, "\trte\n"); else fprintf (file, "\trts\n"); pragma_interrupt = 0; pragma_saveall = 0; } /* Return true if VALUE is a valid constant for constraint 'P'. */ int potl8 (value) { switch (value) { case 1: case 2: case 4: case 8: case 16: case 32: case 64: case 128: return 1; } return 0; } /* Return true if VALUE is a valid constant for constraint 'O'. */ int potg8 (value) int value; { switch (value) { case 256: case 512: case 1024: case 2048: case 4096: case 8192: case 16384: case 32768: return 1; } return 0; } /* Return true is OP is a valid source operand for an integer move instruction. */ int general_operand_src (op, mode) rtx op; enum machine_mode mode; { /* We can't have a pre-dec as a source. */ if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC) return 0; return general_operand (op, mode); } /* Return true if OP is a valid destination operand for an integer move instruction. */ int general_operand_dst (op, mode) rtx op; enum machine_mode mode; { /* We can't have a post-inc as a dest. */ if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC) return 0; return general_operand (op, mode); } /* Handle machine specific pragmas for compatibility with existing compilers for the H8/300 pragma saveall generates prolog/epilog code which saves and restores all the registers on function entry. pragma interrupt saves and restores all registers, and exits with an rte instruction rather than an rts. A pointer to a function with this attribute may be safely used in an interrupt vector. */ int handle_pragma (file) FILE *file; { int c; char pbuf[20]; int psize; c = getc (file); while (c == ' ' || c == '\t') c = getc (file); if (c == '\n' || c == EOF) return c; for (psize = 0; psize < sizeof (pbuf) - 1 && isalpha (c); psize++) { pbuf[psize] = c; c = getc (file); } pbuf[psize] = 0; if (strcmp (pbuf, "interrupt") == 0) pragma_interrupt = 1; if (strcmp (pbuf, "saveall") == 0) pragma_saveall = 1; return c; } /* If the next arg with MODE and TYPE is to be passed in a register, return the rtx to represent where it is passed. CUM represents the state after the last argument. NAMED is not used. */ rtx function_arg (cum, mode, type, named) CUMULATIVE_ARGS *cum; enum machine_mode mode; tree type; int named; { rtx result = 0; int libcall = 0; /* Right now reload has a problem with reg passing with small reg classes. */ if (cum->libcall || (named && TARGET_QUICKCALL)) libcall = 1; if (TARGET_NOQUICK) libcall = 0; if (mode != VOIDmode && libcall && mode != DFmode && mode != SFmode) { switch (cum->nbytes) { case 0: result = gen_rtx (REG, mode, 0); break; case 2: result = gen_rtx (REG, mode, 1); break; case 4: result = gen_rtx (REG, mode, 4); break; case 6: result = gen_rtx (REG, mode, 5); break; default: return 0; } } return result; } /* Documentation for the machine specific operand escapes: 'C' print (operand - 2). 'E' low byte of reg or -ve lsb of constant 'F' high byte of reg of -ve msb of constant 'G' negate constant 'L' fake label, changed after used twice. 'M' turn a 'M' constant into its negative mod 2. 'T' print operand as a word 'V' print log2 of constant - used for bset instructions 'X' 8 bit register or other operand 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8. 'Z' print int & 7 'e' first word of 32 bit value 'f' second word of 32 bit value 'j' print operand as condition code. 'k' print operand as reverse condition code. 's' low byte of 16 bit value 't' high byte of 16 bit value 'w' 1st byte of 32 bit value zzzzzzzz yyyyyyyy xxxxxxxx wwwwwwww 'x' 2nd byte of 32 bit value 'y' 3rd byte of 32 bit value 'z' 4th byte of 32 bit value */ /* Return assembly language string which identifies a comparison type. */ char * cond_string (code) enum rtx_code code; { switch (code) { case NE: return "ne"; case EQ: return "eq"; case GE: return "ge"; case GT: return "gt"; case LE: return "le"; case LT: return "lt"; case GEU: return "hs"; case GTU: return "hi"; case LEU: return "ls"; case LTU: return "lo"; default: abort (); } } /* Print operand X using operand code CODE to assembly language output file FILE. */ void print_operand (file, x, code) FILE *file; rtx x; int code; { /* This is used to general unique labels for the 'L' code. */ static int lab = 1000; /* This is used for communication between the 'P' and 'U' codes. */ static char *last_p; /* This is used for communication between the 'Z' and 'Y' codes. */ static int bitint; switch (code) { case 'L': /* 'L' must always be used twice in a single pattern. It generates the same lable twice, and then will generate a unique label the next time it is used. */ asm_fprintf (file, "tl%d", (lab++) / 2); break; case 'X': if (GET_CODE (x) == REG) fprintf (file, "%s", byte_reg (x, 0)); else goto def; break; case 'G': if (GET_CODE (x) != CONST_INT) abort (); fprintf (file, "#%d", 0xff & (-INTVAL (x))); break; case 'T': if (GET_CODE (x) == REG) fprintf (file, "%s", names_big[REGNO (x)]); else goto def; break; case 'w': if (GET_CODE (x) == CONST_INT) fprintf (file, "#%d", INTVAL (x) & 0xff); else fprintf (file, "%s", byte_reg (x, 2)); break; case 'x': if (GET_CODE (x) == CONST_INT) fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff); else fprintf (file, "%s", byte_reg (x, 3)); break; case 'y': if (GET_CODE (x) == CONST_INT) fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff); else fprintf (file, "%s", byte_reg (x, 0)); break; case 'z': if (GET_CODE (x) == CONST_INT) fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff); else fprintf (file, "%s", byte_reg (x, 1)); break; /* FOR 16 bits. */ case 't': if (GET_CODE (x) == CONST_INT) fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff); else fprintf (file, "%s", byte_reg (x, 1)); break; case 's': if (GET_CODE (x) == CONST_INT) fprintf (file, "#%d", (INTVAL (x)) & 0xff); else fprintf (file, "%s", byte_reg (x, 0)); break; case 'u': if (GET_CODE (x) != CONST_INT) abort (); fprintf (file, "%d", INTVAL (x)); break; case 'Z': bitint = INTVAL (x); fprintf (file, "#%d", bitint & 7); break; case 'Y': fprintf (file, "%c", bitint > 7 ? 'h' : 'l'); break; case 'O': bitint = exact_log2 ((~INTVAL (x)) & 0xff); if (bitint == -1) abort (); fprintf (file, "#%d", bitint & 7); break; case 'V': bitint = exact_log2 (INTVAL (x)); if (bitint == -1) abort (); fprintf (file, "#%d", bitint & 7); break; case 'P': if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM) { last_p = ""; fprintf (file, ".w"); } else { last_p = "l"; fprintf (file, ".b"); } break; case 'U': fprintf (file, "%s%s", names_big[REGNO (x)], last_p); break; case 'M': /* For -4 and -2, the other 2 is handled separately. */ switch (INTVAL (x)) { case -2: case -4: fprintf (file, "#2"); break; case -1: case -3: fprintf (file, "#1"); break; default: abort (); } break; case 'e': switch (GET_CODE (x)) { case REG: fprintf (file, "%s", names_big[REGNO (x)]); break; case MEM: x = adj_offsettable_operand (x, 0); print_operand (file, x, 0); break; case CONST_INT: fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff)); break; default: abort (); break; } break; case 'f': switch (GET_CODE (x)) { case REG: fprintf (file, "%s", names_big[REGNO (x) + 1]); break; case MEM: x = adj_offsettable_operand (x, 2); print_operand (file, x, 0); break; case CONST_INT: fprintf (file, "#%d", INTVAL (x) & 0xffff); break; default: abort (); } break; case 'C': fprintf (file, "#%d", INTVAL (x) - 2); break; case 'E': switch (GET_CODE (x)) { case REG: fprintf (file, "%sl", names_big[REGNO (x)]); break; case CONST_INT: fprintf (file, "#%d", (-INTVAL (x)) & 0xff); break; default: abort (); } break; case 'F': switch (GET_CODE (x)) { case REG: fprintf (file, "%sh", names_big[REGNO (x)]); break; case CONST_INT: fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8); break; default: abort (); } break; case 'j': asm_fprintf (file, cond_string (GET_CODE (x))); break; case 'k': asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x)))); break; def: ; default: switch (GET_CODE (x)) { case REG: fprintf (file, "%s", names_big[REGNO (x)]); break; case MEM: fprintf (file, "@"); output_address (XEXP (x, 0)); break; case CONST_INT: case SYMBOL_REF: case CONST: case LABEL_REF: fprintf (file, "#"); print_operand_address (file, x); break; } } } /* Output assembly language output for the address ADDR to FILE. */ void print_operand_address (file, addr) FILE *file; rtx addr; { switch (GET_CODE (addr)) { case REG: fprintf (file, "%s", names_big[REGNO (addr)]); break; case PRE_DEC: fprintf (file, "-%s", names_big[REGNO (XEXP (addr, 0))]); break; case POST_INC: fprintf (file, "%s+", names_big[REGNO (XEXP (addr, 0))]); break; case PLUS: fprintf (file, "("); if (GET_CODE (XEXP (addr, 0)) == REG) { /* reg,foo */ print_operand_address (file, XEXP (addr, 1)); fprintf (file, ","); print_operand_address (file, XEXP (addr, 0)); } else { /* foo+k */ print_operand_address (file, XEXP (addr, 0)); fprintf (file, "+"); print_operand_address (file, XEXP (addr, 1)); } fprintf (file, ")"); break; case CONST_INT: if (INTVAL (addr) < 0) { int v = -INTVAL (addr); fprintf (file, "-%d", v); } else fprintf (file, "%d", INTVAL (addr)); break; default: output_addr_const (file, addr); break; } } /* Output to FILE a reference to the user-level label NAME. Strip off the section name if any. It is separated from the label name by a space. */ void asm_output_labelref (file, name) FILE *file; char *name; { char *p; fputc ('_', file); for (p = name; *p; p++) { if (*p == ' ') { /* If we found a space in the name, then we've skipped over the section encoding. */ fputs (p + 1, file); return; } } /* No space, so no section. */ fputs (name, file); } /* Output all insn addresses and their sizes into the assembly language output file. This is helpful for debugging whether the length attributes in the md file are correct. This is not meant to be a user selectable option. */ void final_prescan_insn (insn, operand, num_operands) rtx insn, *operand; int num_operands; { /* This holds the last insn address. */ static int last_insn_address = 0; int uid = INSN_UID (insn); if (TARGET_ADDRESSES) { fprintf (asm_out_file, "; %d %d\n", insn_addresses[uid], insn_addresses[uid] - last_insn_address); last_insn_address = insn_addresses[uid]; } } static void shift_n_bits (lval, operand, f, notzero) rtx lval; rtx operand; rtx (*f) (); int notzero; { rtx label = gen_label_rtx (); rtx bot = gen_label_rtx (); if (! notzero) { /* Have to put a zero test at the top. */ emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, lval)); emit_jump_insn (gen_beq (bot)); } emit_label (label); f (operand); emit_insn (gen_rtx (SET, QImode, lval, gen_rtx (MINUS, QImode, lval, const1_rtx))); emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, lval)); emit_jump_insn (gen_bne (label)); emit_label (bot); /* We can't end an expand with a label. */ emit_move_insn (operand, operand); } int can_shift (code, operands, f, limit, fby_eight) int code; rtx operands[]; rtx (*f) (); int limit; rtx (*fby_eight) (); { extern int rtx_equal_function_value_matters; emit_move_insn (operands[0], operands[1]); if (GET_CODE (operands[2]) != CONST_INT) { rtx lval; /* Can't define expand a loop after rtl generation. */ if (! rtx_equal_function_value_matters) return 0; lval = gen_reg_rtx (QImode); convert_move (lval, operands[2], 1); shift_n_bits (lval, operands[0], f, 0); } else { int i; i = INTVAL (operands[2]); if (i >= 8 && fby_eight) { fby_eight (operands[0]); i -= 8; } if (i > limit) { rtx lval; /* Can't define expand a loop after rtl generation. */ if (! rtx_equal_function_value_matters) return 0; lval = gen_reg_rtx (QImode); emit_move_insn (lval, gen_rtx (CONST_INT, VOIDmode, i)); shift_n_bits (lval, operands[0], f, 1); } else { while (i--) f (operands[0]); } } return 1; } int domovsi (operands) rtx operands[]; { rtx src = operands[1]; rtx dst = operands[0]; if (push_operand (dst, GET_MODE (dst))) { /* Source must be a reg. */ if (! REG_P (src)) { rtx tmp = gen_reg_rtx (GET_MODE (dst)); emit_move_insn (tmp, src); operands[1] = tmp; } } return 0; } int io (FROM, TO) { int OFFSET = 0; if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) (OFFSET) = 2 + frame_pointer_needed * 2; else { int regno; int offset = 0; for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) if ((regs_ever_live[regno] && (! call_used_regs[regno] || regno == FRAME_POINTER_REGNUM))) offset += 2; (OFFSET) = offset + get_frame_size (); if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) (OFFSET) += 2; /* Skip saved PC. */ } return OFFSET; } gcc-2.5.8/config/h8300/h8300.h100444 22011 13 116632 5453234476 13772 0ustar kenneruser/* Definitions of target machine for GNU compiler. Hitachi H8/300 version generating coff Copyright (C) 1992, 1993 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-D__H8300__ -D_DOUBLE_IS_32BITS -Acpu(h8300) -Amachine(h8300)" #define LIB_SPEC "%{mrelax:-relax} %{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} " /* Print subsidiary information on the compiler version in use. */ #define TARGET_VERSION fprintf (stderr, " (Hitachi H8/300)"); /* Run-time compilation parameters selecting different hardware subsets. */ int target_flags; /* Macros used in the machine description to test the flags. */ /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */ #define TARGET_SWITCHES \ { {"int32",8}, \ {"long16",16}, \ {"double64",32}, \ {"addresses",64 }, \ {"quickcall",128}, \ {"slowbyte",256}, \ {"noquick",512}, \ {"relax",1024}, \ { "", TARGET_DEFAULT}} #define OPTIMIZATION_OPTIONS(OPTIMIZE) \ { \ obey_regdecls = 0; \ flag_omit_frame_pointer = (OPTIMIZE > 1); \ } #define OVERRIDE_OPTIONS \ { \ flag_no_function_cse = 1; \ } #define TARGET_INT32 (target_flags & 8) #define TARGET_LONG16 (target_flags & 16) #define TARGET_DOUBLE32 (!(target_flags & 32)) #define TARGET_ADDRESSES (target_flags & 64) #define TARGET_QUICKCALL (target_flags & 128) #define TARGET_SLOWBYTE (target_flags & 256) #define TARGET_NOQUICK (target_flags & 512) /* Default target_flags if no switches specified. */ #ifndef TARGET_DEFAULT #define TARGET_DEFAULT 0 #endif #define TARGET_NO_IMPORT (target_flags & MASK_NO_IMPORT) /* Target machine storage layout. */ /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. This is not true on the H8/300. */ #define BITS_BIG_ENDIAN 0 /* Define this if most significant byte of a word is the lowest numbered. */ /* That is true on the H8/300. */ #define BYTES_BIG_ENDIAN 1 /* Define this if most significant word of a multiword number is lowest numbered. This is true on an H8/300 (actually we can make it up, but we choose to be consistent. */ #define WORDS_BIG_ENDIAN 1 /* Number of bits in an addressable storage unit */ #define BITS_PER_UNIT 8 #define UNITS_PER_PTR 2 /* Width in bits of a "word", which is the contents of a machine register. Note that this is not necessarily the width of data type `int'; if using 16-bit ints on a 68000, this would still be 32. But on a machine with 16-bit registers, this would be 16. */ #define BITS_PER_WORD 16 #define MAX_BITS_PER_WORD 16 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 2 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ #define POINTER_SIZE 16 #define SHORT_TYPE_SIZE 16 #define INT_TYPE_SIZE (TARGET_INT32 ? 32 : 16) #define LONG_TYPE_SIZE 32 #define LONG_LONG_TYPE_SIZE 32 #define DOUBLE_TYPE_SIZE (TARGET_DOUBLE32 ? 32 : 64) #define FLOAT_TYPE_SIZE 32 #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE #define MAX_FIXED_MODE_SIZE 32 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ #define PARM_BOUNDARY 16 /* Allocation boundary (in *bits*) for the code of a function. */ #define FUNCTION_BOUNDARY 16 /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY (16) /* Every structure's size must be a multiple of this. */ #define STRUCTURE_SIZE_BOUNDARY 16 /* A bitfield declared as `int' forces `int' alignment for the struct. */ #define PCC_BITFIELD_TYPE_MATTERS 0 /* No data type wants to be aligned rounder than this. */ #define BIGGEST_ALIGNMENT 16 /* No structure field wants to be aligned rounder than this. */ #define BIGGEST_FIELD_ALIGNMENT 16 /* The stack goes in 16 bit lumps. */ #define STACK_BOUNDARY 16 /* Define this if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 1 /* Standard register usage. */ /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. Reg 8 does not correspond to any hardware register, but instead appears in the RTL as an argument pointer prior to reload, and is eliminated during reloading in favor of either the stack or frame pointer. */ #define FIRST_PSEUDO_REGISTER 9 /* 1 for registers that have pervasive standard uses and are not available for the register allocator. r7 is the stack pointer, r8 is the arg pointer. */ #define FIXED_REGISTERS \ { 0,0,0,0, 0,0,0,1, 1 } /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. The H8/300 destroys r0, r1, r4 and r5. */ #define CALL_USED_REGISTERS \ {1,1,0,0, 1,1,0,1, 1 } /* This is the order in which to allocate registers normally. */ #define REG_ALLOC_ORDER { 0, 1, 4, 5, 2, 3, 6, 7, 8 } /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. If an even reg, then anything goes. Otherwise the mode must be QI or HI. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ((((REGNO) & 1) == 0) || (MODE == HImode) || (MODE == QImode)) /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. */ #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2)) /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ /* H8/300 pc is not overloaded on a register. */ /*#define PC_REGNUM 15*/ /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM 7 /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM 6 /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */ #define FRAME_POINTER_REQUIRED 0 /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM 8 /* Register in which static-chain is passed to a function. */ #define STATIC_CHAIN_REGNUM 0 /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. One of the classes must always be named ALL_REGS and include all hard regs. If there is more than one class, another class must be named NO_REGS and contain no registers. The name GENERAL_REGS must be the name of a class (or an alias for another name such as ALL_REGS). This is the class of registers that is allowed by "g" or "r" in a register constraint. Also, registers outside this class are allocated only when instructions express preferences for them. The classes must be numbered in nondecreasing order; that is, a larger-numbered class must never be contained completely in a smaller-numbered class. For any two classes, it is very desirable that there be another class that represents their union. */ /* The H8/300 has only one kind of register, but we mustn't do byte by byte operations on the sp, so we keep it as a different class. */ enum reg_class { NO_REGS, LONG_REGS, GENERAL_REGS, SP_REG, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ {"NO_REGS", "LONG_REGS", "GENERAL_REGS", "SP_REG", "ALL_REGS", "LIM_REGS"} /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS \ { 0, /* No regs */ \ 0x7f, /* LONG_REGS */ \ 0x7f, /* GENERAL_REGS */ \ 0x80, /* SP_REG */ \ 0xff, /* ALL_REGS */ \ } /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ #define REGNO_REG_CLASS(REGNO) \ ((REGNO) >= STACK_POINTER_REGNUM \ ? ((REGNO) >= FRAME_POINTER_REGNUM \ ? SP_REG \ : GENERAL_REGS) \ : LONG_REGS) /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS NO_REGS #define BASE_REG_CLASS GENERAL_REGS /* Get reg_class from a letter such as appears in the machine description. */ #define REG_CLASS_FROM_LETTER(C) \ ((C) == 'a' ? SP_REG : (((C) == 'l') ? LONG_REGS : NO_REGS)) /* The letters I, J, K, L, M, N, O, P in a register constraint string can be used to stand for particular ranges of immediate operands. This macro defines what the ranges are. C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. */ #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? (VALUE) == 0 : \ (C) == 'J' ? (((VALUE) & 0xff00) == 0) : \ (C) == 'K' ? ((VALUE) == 1 || (VALUE) == 2) : \ (C) == 'L' ? ((VALUE) == -1 || (VALUE) == -2) : \ (C) == 'M' ? ((VALUE) == 3 || (VALUE) == 4) : \ (C) == 'N' ? ((VALUE) == -3 || (VALUE) == -4) : \ (C) == 'O' ? (potg8 (VALUE)) : \ (C) == 'P' ? (potl8 (VALUE)) : \ 0) /* Similar, but for floating constants, and defining letters G and H. Here VALUE is the CONST_DOUBLE rtx itself. `G' is a floating-point zero. */ #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'G' ? ((VALUE) == CONST0_RTX (DFmode) \ || (VALUE) == CONST0_RTX (DFmode)) \ : 0) /* Extra constraints - 'U' if for an operand valid for a bset destination; i.e. a register or register indirect target. */ #define EXTRA_CONSTRAINT(OP, C) \ (((C) == 'U') \ ? ((GET_CODE (OP) == REG) \ || ((GET_CODE (OP) == MEM) \ && GET_CODE (XEXP (OP, 0)) == REG)) \ : 0) /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. */ #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ /* On the H8, this is the size of MODE in words, except in the FP regs, where a single reg is always enough. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* Any SI register to register move may need to be reloaded, so define REGISTER_MOVE_COST to be > 2 so that reload never shortcuts. */ #define REGISTER_MOVE_COST(CLASS1, CLASS2) 3 /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack makes the stack pointer a smaller address. */ #define STACK_GROWS_DOWNWARD /* Define this if the nominal address of the stack frame is at the high-address end of the local variables; that is, each additional local variable allocated goes at a more negative offset in the frame. */ #define FRAME_GROWS_DOWNWARD /* Offset within stack frame to start allocating local variables at. If FRAME_GROWS_DOWNWARD, this is the offset to the END of the first local allocated. Otherwise, it is the offset to the BEGINNING of the first local allocated. */ #define STARTING_FRAME_OFFSET 0 /* If we generate an insn to push BYTES bytes, this says how many the stack pointer really advances by. On the H8/300, @-sp really pushes a byte if you ask it to - but that's dangerous, so we claim that it always pushes a word, then we catch the mov.b rx,@-sp and turn it into a mov.w rx,@-sp on output. */ #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1) /* Offset of first parameter from the argument pointer register value. */ /* Is equal to the size of the saved fp + pc, even if an fp isn't saved since the value is used before we know. */ #define FIRST_PARM_OFFSET(FNDECL) 0 /* Value is the number of bytes of arguments automatically popped when returning from a subroutine call. FUNTYPE is the data type of the function (as a tree), or for a library call it is an identifier node for the subroutine name. SIZE is the number of bytes of arguments passed on the stack. On the H8/300 the return does not pop anything. */ #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0 /* Definitions for register eliminations. This is an array of structures. Each structure initializes one pair of eliminable registers. The "from" register number is given first, followed by "to". Eliminations of the same "from" register are listed in order of preference. We have two registers that can be eliminated on the i386. First, the frame pointer register can often be eliminated in favor of the stack pointer register. Secondly, the argument pointer register can always be eliminated; it is replaced with either the stack or frame pointer. */ #define ELIMINABLE_REGS \ {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} #define CAN_ELIMINATE(FROM, TO) \ ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ ? ! frame_pointer_needed \ : 1) /* Define the offset between two registers, one to be eliminated, and the other its replacement, at the start of a routine. */ #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) OFFSET = io (FROM,TO) /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. On the H8/300 the return value is in R0/R1. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ gen_rtx (REG, TYPE_MODE (VALTYPE), 0) /* Define how to find the value returned by a library function assuming the value has mode MODE. */ /* On the H8/300 the return value is in R0/R1. */ #define LIBCALL_VALUE(MODE) \ gen_rtx (REG, MODE, 0) /* 1 if N is a possible register number for a function value. On the H8/300, R0 is the only register thus used. */ #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) /* Define this if PCC uses the nonreentrant convention for returning structure and union values. */ #define PCC_STATIC_STRUCT_RETURN /* 1 if N is a possible register number for function argument passing. On the H8/300, no registers are used in this way. */ #define FUNCTION_ARG_REGNO_P(N) 0 /* Register in which address to store a structure value is passed to a function. */ #define STRUCT_VALUE 0 #define STRUCT_VALUE_REGNUM 0 #define STRUCT_VALUE_INCOMING 0 /* Return true if X should be returned in memory. */ #define RETURN_IN_MEMORY(X) \ (TYPE_MODE (X) == BLKmode || GET_MODE_SIZE (TYPE_MODE (X)) > 4) /* Don't default to pcc-struct-return, because we have already specified exactly how to return structures in the RETURN_IN_MEMORY macro. */ #define DEFAULT_PCC_STRUCT_RETURN 0 /* When defined, the compiler allows registers explicitly used in the rtl to be used as spill registers but prevents the compiler from extending the lifetime of these registers. */ #define SMALL_REGISTER_CLASSES /* Define a data type for recording info about an argument list during the scan of that argument list. This data type should Hold all necessary information about the function itself and about the args processed so far, enough to enable macros such as FUNCTION_ARG to determine where the next arg should go. On the H8/300, this is a two item struct, the first is the number of bytes scanned so far, the second the name of any libcall. */ #define CUMULATIVE_ARGS struct cum_arg struct cum_arg { int nbytes; struct rtx_def* libcall; }; /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. On the H8/300, the offset starts at 0. */ #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ ((CUM).nbytes = 0, (CUM).libcall = LIBNAME) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. All sizes rounded up to even bytes. */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ ((CUM).nbytes += ((MODE) != BLKmode \ ? (GET_MODE_SIZE (MODE) + 1) & ~1 \ : (int_size_in_bytes (TYPE) + 1) & ~1)) /* Define where to put the arguments to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. MODE is the argument's machine mode. TYPE is the data type of the argument (as a tree). This is null for libcalls where that information may not be available. CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called. NAMED is nonzero if this argument is a named parameter (otherwise it is an extra parameter matching an ellipsis). */ /* On the H8/300 all normal args are pushed, we pass args to named functions in registers. */ extern struct rtx_def *function_arg(); #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ function_arg (&CUM, MODE, TYPE, NAMED) /* This macro generates the assembly code for function entry. FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. Refer to the array `regs_ever_live' to determine which registers to save; `regs_ever_live[I]' is nonzero if register number I is ever used in the function. This macro is responsible for knowing which registers should not be saved even if used. */ #define FUNCTION_PROLOGUE(FILE, SIZE) \ function_prologue (FILE, SIZE) /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ #define FUNCTION_PROFILER(FILE, LABELNO) \ fprintf (FILE, "\t; not implemented\n", (LABELNO)); /* Output assembler code to FILE to initialize this source file's basic block profiling info, if that has not already been done. */ #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ fprintf (FILE, "\t; not implemented \n", LABELNO, LABELNO); /* Output assembler code to FILE to increment the entry-count for the BLOCKNO'th basic block in this source file. */ #define BLOCK_PROFILER(FILE, BLOCKNO) \ fprintf (FILE, "\t; not implemented\n"); /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, the stack pointer does not matter. The value is tested only in functions that have frame pointers. No definition is equivalent to always zero. */ #define EXIT_IGNORE_STACK 0 /* This macro generates the assembly code for function exit, on machines that need it. If FUNCTION_EPILOGUE is not defined then individual return instructions are generated for each return statement. Args are same as for FUNCTION_PROLOGUE. */ #define FUNCTION_EPILOGUE(FILE, SIZE) \ function_epilogue (FILE, SIZE) /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. */ #define TRAMPOLINE_TEMPLATE(FILE) \ fprintf (FILE, " trampolines not implemented\n"); /* Length in units of the trampoline for entering a nested function. */ #define TRAMPOLINE_SIZE 15 /* Emit RTL insns to initialize the variable parts of a trampoline. FNADDR is an RTX for the address of the function's pure code. CXT is an RTX for the static chain value for the function. */ /* We copy the register-mask from the function's pure code to the start of the trampoline. */ #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ emit_move_insn (gen_rtx (MEM, HImode, TRAMP), \ gen_rtx (MEM, HImode, FNADDR)); \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), CXT);\ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 11)), \ plus_constant (FNADDR, 2)); \ } /* Addressing modes, and classification of registers for them. Although the H8/300 has pre decrement destinations and post increment sources on moves, they are not general enough to be much use to gcc */ /*#define HAVE_POST_INCREMENT*/ /*#define HAVE_POST_DECREMENT */ /*#define HAVE_PRE_DECREMENT*/ /*#define HAVE_PRE_INCREMENT */ /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. */ #define REGNO_OK_FOR_INDEX_P(regno) 0 #define REGNO_OK_FOR_BASE_P(regno) \ ((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0) /* Maximum number of registers that can appear in a valid memory address. */ #define MAX_REGS_PER_ADDRESS 1 /* 1 if X is an rtx for a constant that is a valid address. */ #define CONSTANT_ADDRESS_P(X) \ (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ || GET_CODE (X) == HIGH) /* Nonzero if the constant value X is a legitimate general operand. It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ #define LEGITIMATE_CONSTANT_P(X) (GET_CODE (X) != CONST_DOUBLE) /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. The usual definition accepts all pseudo regs; the other rejects them unless they have been allocated suitable hard regs. The symbol REG_OK_STRICT causes the latter definition to be used. Most source files want to accept pseudo regs in the hope that they will get allocated to the class that the insn wants them to be in. Source files for reload pass need to be strict. After reload, it makes no difference, since pseudo regs have been eliminated by then. */ #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ #define REG_OK_FOR_INDEX_P(X) 0 /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ #define REG_OK_FOR_BASE_P(X) 1 #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X)) #else /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) #endif /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, except for CONSTANT_ADDRESS_P which is actually machine-independent. On the H8/300, a legitimate address has the form REG, REG+CONSTANT_ADDRESS or CONSTANT_ADDRESS. */ /* Accept either REG or SUBREG where a register is valid. */ #define RTX_OK_FOR_BASE_P(X) \ ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \ || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X)) \ && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ if (RTX_OK_FOR_BASE_P (X)) goto ADDR; \ if (CONSTANT_ADDRESS_P (X)) goto ADDR; \ if (GET_CODE (X) == PLUS \ && CONSTANT_ADDRESS_P (XEXP (X, 1)) \ && RTX_OK_FOR_BASE_P (XEXP (X, 0))) goto ADDR; /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. OLDX is the address as it was before break_out_memory_refs was called. In some cases it is useful to look at this to decide what needs to be done. MODE and WIN are passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. It is always safe for this macro to do nothing. It exists to recognize opportunities to optimize the output. For the H8/300, don't do anything. */ #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {} /* Go to LABEL if ADDR (a legitimate address expression) has an effect that depends on the machine mode it is used for. On the H8/300, the predecrement and postincrement address depend thus (the amount of decrement or increment being the length of the operand) and all indexed address depend thus (because the index scale factor is the length of the operand). */ #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL; /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE HImode /* Define this if the case instruction expects the table to contain offsets from the address of the table. Do not define this if the table should contain absolute addresses. */ /*#define CASE_VECTOR_PC_RELATIVE*/ /* Define this if the case instruction drops through after the table when the index is out of range. Don't define it if the case insn jumps to the default label instead. */ #define CASE_DROPS_THROUGH /* Specify the tree operation to be used to convert reals to integers. */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR /* This is the kind of divide that is easiest to do in the general case. */ #define EASY_DIV_EXPR TRUNC_DIV_EXPR /* Define this as 1 if `char' should by default be signed; else as 0. On the H8/300, sign extension is expensive, so we'll say that chars are unsigned. */ #define DEFAULT_SIGNED_CHAR 0 /* This flag, if defined, says the same insns that convert to a signed fixnum also convert validly to an unsigned one. */ #define FIXUNS_TRUNC_LIKE_FIX_TRUNC /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ #define MOVE_MAX 2 /* Define this if zero-extension is slow (more than one real instruction). */ /* #define SLOW_ZERO_EXTEND */ /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS TARGET_SLOWBYTE /* Define if shifts truncate the shift count which implies one can omit a sign-extension or zero-extension of a shift count. */ /* #define SHIFT_COUNT_TRUNCATED */ /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ #define Pmode HImode #define SIZE_TYPE "unsigned int" #define PTRDIFF_TYPE "int" /* A function address in a call instruction is a byte address (for indexing purposes) so give the MEM rtx a byte's mode. */ #define FUNCTION_MODE QImode /* Compute the cost of computing a constant rtl expression RTX whose rtx-code is CODE. The body of this macro is a portion of a switch statement. If the code is computed here, return it with a return statement. Otherwise, break from the switch. */ #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ switch (INTVAL (RTX)) \ { \ case 0: \ case 1: \ case 2: \ case -1: \ case -2: \ return 0; \ default: \ return 1; \ } \ case CONST: \ case LABEL_REF: \ case SYMBOL_REF: \ return 3; \ case CONST_DOUBLE: \ return 20; #define BRANCH_COST 2 /* Provide the costs of a rtl expression. This is in the body of a switch on CODE. */ #define RTX_COSTS(RTX,CODE,OUTER_CODE) \ case MOD: \ case DIV: \ return 60; \ case MULT: \ return 20; \ case LSHIFT: \ case ASHIFT: \ case ASHIFTRT: \ case LSHIFTRT: \ case ROTATE: \ case ROTATERT: \ if (GET_MODE (RTX) == HImode) \ return 2; \ return 10; \ /* Tell final.c how to eliminate redundant test instructions. */ /* Store in cc_status the expressions that the condition codes will describe after execution of an instruction whose pattern is EXP. Do not alter them if the instruction would not alter the cc's. */ #define NOTICE_UPDATE_CC(EXP, INSN) \ switch (get_attr_cc (INSN)) \ { \ case CC_NONE: \ /* Insn does not affect the CC at all. */ \ break; \ case CC_NONE_0HIT: \ /* Insn does not change the CC, but the 0'th operand has been \ changed. */ \ if (cc_status.value1 != 0 \ && reg_overlap_mentioned_p (recog_operand[0], cc_status.value1))\ cc_status.value1 = 0; \ \ if (cc_status.value2 != 0 \ && reg_overlap_mentioned_p (recog_operand[0], cc_status.value2))\ cc_status.value2 = 0; \ break; \ case CC_SET: \ /* Insn sets CC to recog_operand[0], but overflow is impossible. */\ CC_STATUS_INIT; \ cc_status.flags |= CC_NO_OVERFLOW; \ cc_status.value1 = recog_operand[0]; \ break; \ case CC_COMPARE: \ /* The insn is a compare instruction. */ \ CC_STATUS_INIT; \ cc_status.value1 = recog_operand[0]; \ cc_status.value1 = recog_operand[1]; \ break; \ case CC_WHOOPS: \ case CC_CLOBBER: \ /* Insn clobbers CC. */ \ CC_STATUS_INIT; \ break; \ } \ #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ { \ if (cc_status.flags & CC_NO_OVERFLOW) \ return NO_OV; \ return NORMAL; \ } /* Control the assembler format that we output. */ #define ASM_IDENTIFY_GCC /* nothing */ /* Output at beginning of assembler file. */ #define ASM_FILE_START(FILE) \ { \ fprintf (FILE, ";\tGCC For the Hitachi H8/300\n"); \ if (optimize) \ fprintf (FILE, "; -O%d\n", optimize); \ fprintf (FILE, "\n\n"); \ output_file_directive (FILE, main_input_filename); \ } #define ASM_FILE_END(FILE) \ fprintf (FILE, "\t.end\n"); /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ #define ASM_APP_ON "; #APP\n" /* Output to assembler file text saying following lines no longer contain unusual constructs. */ #define ASM_APP_OFF "; #NO_APP\n" #define FILE_ASM_OP "\t.file\n" #define IDENT_ASM_OP "\t.ident\n" /* Output before read-only data. */ #define TEXT_SECTION_ASM_OP "\t.section .text" #define DATA_SECTION_ASM_OP "\t.section .data" #define BSS_SECTION_ASM_OP "\t.section .bss" #define EXTRA_SECTIONS in_user #define EXTRA_SECTION_FUNCTIONS \ void \ user_section (name) \ char *name; \ { \ fprintf (asm_out_file, "\t.section\t%s\n", name); \ in_section = in_user; \ } #define MAX_TEXT_ALIGN 16 /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ #define REGISTER_NAMES \ { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "ap"} /* How to renumber registers for dbx and gdb. H8/300 needs no change in the numeration. */ #define DBX_REGISTER_NUMBER(REGNO) (REGNO) /* This is how to output the definition of a user-level label named NAME, such as the label on a static function or variable NAME. */ #define SDB_DEBUGGING_INFO #define SDB_DELIM "\n" #define ASM_OUTPUT_LABEL(FILE,NAME) \ do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) /*#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) */ /* This is how to output a command to make the user-level label named NAME defined for reference from other files. */ #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) /*#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ ASM_OUTPUT_LABEL(FILE, NAME); */ /* This is how to output a reference to a user-level label named NAME. */ #define ASM_OUTPUT_LABELREF(FILE, NAME) \ asm_output_labelref (FILE, NAME) /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM) \ fprintf (FILE, ".%s%d:\n", PREFIX, NUM) /* This is how to store into the string LABEL the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ sprintf (LABEL, "*.%s%d", PREFIX, NUM) /* This is how to output an assembler line defining a `double' constant. It is .dfloat or .gfloat, depending. */ /*#define ASM_OUTPUT_DOUBLE(FILE, VALUE) \ fprintf (FILE, "\t.double %.20e\n", (VALUE))*/ /* This is how to output an assembler line defining a `float' constant. */ #define ASM_OUTPUT_FLOAT(FILE, VALUE) \ fprintf (FILE, "\t.float %.20e\n", \ ((VALUE) > 1e30 ? 1e30 \ : ((VALUE) < -1e30) ? -1e30 : (double) ((float) VALUE))); /* This is how to output an assembler line defining an `int' constant. */ #define ASM_OUTPUT_INT(FILE, VALUE) \ ( fprintf (FILE, "\t.long "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* Likewise for `char' and `short' constants. */ #define ASM_OUTPUT_CHAR(FILE, VALUE) \ ( fprintf (FILE, "\t.byte "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #define ASM_OUTPUT_SHORT(FILE, VALUE) \ ( fprintf (FILE, "\t.word "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* This is how to output an assembler line for a numeric constant byte. */ #define ASM_OUTPUT_BYTE(FILE, VALUE) \ fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ fprintf (FILE, "\tpush %s\n", reg_names[REGNO]) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO]) /* This is how to output an element of a case-vector that is absolute. */ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ asm_fprintf (FILE, "\t.word .L%d\n", VALUE) /* This is how to output an element of a case-vector that is relative. */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\t.word.w .L%d-.L%d\n", VALUE, REL) /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #define ASM_OUTPUT_ALIGN(FILE, LOG) \ if ((LOG) != 0) \ fprintf (FILE, "\t.align %d\n", 1 << (LOG)) /* This is how to output an assembler line that says to advance the location counter by SIZE bytes. */ #define ASM_OUTPUT_IDENT(FILE, NAME) \ fprintf (FILE, "%s\t \"%s\"\n", IDENT_ASM_OP, NAME) #define ASM_OUTPUT_SKIP(FILE, SIZE) \ fprintf (FILE, "\t.space %d\n", (SIZE)) /* This says how to output an assembler line to define a global common symbol. */ #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fputs ("\t.comm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%d\n", (SIZE))) /* This says how to output an assembler line to define a local common symbol. */ #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \ ( fputs ("\t.lcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%d\n", (SIZE))) /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO))) /* Define the parentheses used to group arithmetic operations in assembler code. */ #define ASM_OPEN_PAREN "(" #define ASM_CLOSE_PAREN ")" /* Define results of standard character escape sequences. */ #define TARGET_BELL 007 #define TARGET_BS 010 #define TARGET_TAB 011 #define TARGET_NEWLINE 012 #define TARGET_VT 013 #define TARGET_FF 014 #define TARGET_CR 015 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ ((CODE) == '#') #define PRINT_OPERAND(FILE, X, CODE) \ print_operand (FILE, X, CODE) /* Print a memory operand whose address is X, on file FILE. This uses a function in h8300.c. */ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ print_operand_address (FILE, ADDR) #define HANDLE_PRAGMA(FILE) handle_pragma (FILE) #define FINAL_PRESCAN_INSN(insn, operand, nop) \ final_prescan_insn (insn, operand, nop) /* Define this macro if GNU CC should generate calls to the System V (and ANSI C) library functions `memcpy' and `memset' rather than the BSD functions `bcopy' and `bzero'. */ #define TARGET_MEM_FUNCTIONS 1 /* Define subroutines to call to handle various operations not supported in the hardware */ #define DIVHI3_LIBCALL "__divhi3" #define UDIVHI3_LIBCALL "__udivhi3" #define MULHI3_LIBCALL "__mulhi3" #define MODHI3_LIBCALL "__modhi3" #define UMODHI3_LIBCALL "__umodhi3" #define ADDSI3_LIBCALL "__addsi3" #define SUBSI3_LIBCALL "__subsi3" #define MOVE_RATIO 3 #if 0 /* This stuff doesn't work currently. */ #undef SELECT_SECTION #define SELECT_SECTION(DECL,RELOC) select_section(DECL, RELOC) #define SELECT_FUNCTION_SECTION(a,b) SELECT_SECTION(a,b) #endif gcc-2.5.8/config/h8300/h8300.md100444 22011 13 106640 5433345560 14134 0ustar kenneruser;;- Machine description for the Hitachi H8/300 for the GNU C compiler ;; Copyright (C) 1992, 1993 Free Software Foundation, Inc. ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ;; The original PO technology requires these to be ordered by speed, ;; so that assigner will pick the fastest. ;; See file "rtl.def" for documentation on define_insn, match_*, et. al. (define_attr "type" "branch,return,call,arith,move,float,multi" (const_string "arith")) ;; The size of instructions in bytes. (define_attr "length" "" (cond [(eq_attr "type" "branch") (if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -128)) (le (minus (pc) (match_dup 0)) (const_int 128))) (const_int 2) (const_int 6)) (eq_attr "type" "move") (const_int 4) (eq_attr "type" "return") (const_int 2) (eq_attr "type" "float") (const_int 12) (eq_attr "type" "call") (const_int 4)] (const_int 200))) (define_attr "cc" "none,clobber,none_0hit,set,compare,whoops" (const_string "whoops")) ;; ---------------------------------------------------------------------- ;; move instructions ;; ---------------------------------------------------------------------- ;; movhi (define_insn "" [(set (match_operand:HI 0 "push_operand" "=<") (match_operand:HI 1 "register_operand" "ra"))] "" "mov.w %T1,%T0" [(set_attr "type" "move") (set_attr "length" "2") (set_attr "cc" "set")]) (define_insn "movstricthi" [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "=r,r,r,o,<")) (match_operand:HI 1 "general_operand_src" "I,r,io,r,r"))] "" "@ sub.w %T0,%T0 mov.w %T1,%T0 mov.w %T1,%T0 mov.w %T1,%T0 mov.w %T1,%T0" [(set_attr "type" "move") (set_attr "length" "2,2,4,4,2") (set_attr "cc" "set")]) (define_insn "" [(set (match_operand:HI 0 "general_operand_dst" "=ra,ra,ra,o,<") (match_operand:HI 1 "general_operand_src" "I,ra,ion,ra,ra"))] "" "@ sub.w %T0,%T0 mov.w %T1,%T0 mov.w %T1,%T0 mov.w %T1,%T0 mov.w %T1,%T0" [(set_attr "type" "move") (set_attr "length" "2,2,4,4,2") (set_attr "cc" "set")]) (define_expand "movhi" [(set (match_operand:HI 0 "general_operand_dst" "") (match_operand:HI 1 "general_operand_src" ""))] "" " { /* One of the ops has to be in a register. */ if (! register_operand (operand1, HImode) && ! register_operand (operand0, HImode)) operands[1] = copy_to_mode_reg (HImode, operand1); }") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=&ra") (plus:HI (match_operand:HI 1 "general_operand_src" "g") (match_operand:HI 2 "register_operand" "ra")))] "" "mov.w %T1,%T0\;add.w %T2,%T0" [(set_attr "type" "arith") (set_attr "length" "6") (set_attr "cc" "set")]) ;; movqi (define_insn "" [(set (match_operand:QI 0 "push_operand" "=<") (match_operand:QI 1 "register_operand" "r"))] "" "mov.w %T1,%T0" [(set_attr "type" "move") (set_attr "length" "2") (set_attr "cc" "set")]) (define_insn "movstrictqi" [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "=r,r,r,o,<")) (match_operand:QI 1 "general_operand_src" "I,r,io,r,r"))] "" "@ sub.b %X0,%X0 mov.b %X1,%X0 mov.b %X1,%X0 mov.b %X1,%X0 mov.b %X1,%X0" [(set_attr "type" "move") (set_attr "length" "2,2,4,4,2") (set_attr "cc" "set")]) (define_insn "" [(set (match_operand:QI 0 "general_operand_dst" "=r,r,r,o,<") (match_operand:QI 1 "general_operand_src" "I,r,io,r,r"))] "" "@ sub.b %X0,%X0 mov.b %X1,%X0 mov.b %X1,%X0 mov.b %X1,%X0 mov.b %X1,%X0" [(set_attr "type" "move") (set_attr "length" "2,2,4,4,2") (set_attr "cc" "set")]) (define_expand "movqi" [(set (match_operand:QI 0 "general_operand_dst" "") (match_operand:QI 1 "general_operand_src" ""))] "" " { /* One of the ops has to be in a register. */ if (! register_operand (operand0, QImode) && ! register_operand (operand1, QImode)) operands[1] = copy_to_mode_reg (QImode, operand1); }") ;; movsi (define_insn "" [(set (match_operand:SI 0 "general_operand_dst" "=l,l,l,o,<") (match_operand:SI 1 "general_operand_src" "I,l,ion,l,l"))] "" "* { int rn = -1; switch (which_alternative) { case 0: return \"sub.w %e0,%e0\;sub.w %f0,%f0\"; case 1: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; case 2: /* Make sure we don't trample the register we index with. */ if (GET_CODE (operands[1]) == MEM) { rtx inside = XEXP (operands[1], 0); if (REG_P (inside)) rn = REGNO (inside); else if (GET_CODE (inside) == PLUS) { rtx lhs = XEXP (inside, 0); rtx rhs = XEXP (inside, 1); if (REG_P (lhs)) rn = REGNO (lhs); if (REG_P (rhs)) rn = REGNO (rhs); } } if (rn == REGNO (operands[0])) /* Move the second word first. */ return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; else return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; case 3: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; case 4: return \"mov.w %f1,%T0\;mov.w %e1,%T0\"; } }" [(set_attr "type" "move") (set_attr "length" "4,4,8,8,4") (set_attr "cc" "clobber")]) (define_insn "" [(set (match_operand:SI 0 "push_operand" "=<") (match_operand:SI 1 "register_operand" "l"))] "" "mov.w %f1,%T0\;mov.w %e1,%T0" [(set_attr "type" "move") (set_attr "length" "4") (set_attr "cc" "clobber")]) (define_expand "movsi" [(set (match_operand:SI 0 "general_operand_dst" "") (match_operand:SI 1 "general_operand_src" ""))] "" "if (domovsi (operands)) DONE;") (define_insn "" [(set (match_operand:SF 0 "general_operand_dst" "=l,l,l,o,<") (match_operand:SF 1 "general_operand_src" "I,l,ion,l,l"))] "" "* { /* This is a copy of the movsi stuff. */ int rn = -1; switch (which_alternative) { case 0: return \"sub.w %e0,%e0\;sub.w %f0,%f0\"; case 1: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; case 2: /* Make sure we don't trample the register we index with. */ if (GET_CODE (operands[1]) == MEM) { rtx inside = XEXP (operands[1], 0); if (REG_P (inside)) rn = REGNO (inside); else if (GET_CODE (inside) == PLUS) { rtx lhs = XEXP (inside, 0); rtx rhs = XEXP (inside, 1); if (REG_P (lhs)) rn = REGNO (lhs); if (REG_P (rhs)) rn = REGNO (rhs); } } if (rn == REGNO (operands[0])) /* Move the second word first. */ return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; else return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; case 3: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; case 4: return \"mov.w %f1,%T0\;mov.w %e1,%T0\"; } }" [(set_attr "type" "move") (set_attr "length" "4,4,8,8,4") (set_attr "cc" "clobber")]) (define_insn "" [(set (match_operand:SF 0 "push_operand" "=<") (match_operand:SF 1 "register_operand" "l"))] "" "mov.w %f1,%T0\;mov.w %e1,%T0" [(set_attr "type" "move") (set_attr "length" "4") (set_attr "cc" "clobber")]) (define_expand "movsf" [(set (match_operand:SF 0 "general_operand_dst" "") (match_operand:SF 1 "general_operand_src" ""))] "" "if (domovsi (operands)) DONE;") ;; Block move (define_expand "movstrhi" [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" "")) (mem:BLK (match_operand:BLK 1 "general_operand" ""))) (use (match_operand:HI 2 "general_operand" "")) (use (match_operand:HI 3 "immediate_operand" "")) (clobber (match_dup 3)) ])] "" " { rtx src_ptr = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); rtx dst_ptr = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); enum machine_mode mode = INTVAL (operands[3]) >=2 ? HImode : QImode; rtx tmpreg = gen_reg_rtx (mode); rtx increment = mode == QImode ? const1_rtx : const2_rtx; rtx length = operands[2]; rtx label = gen_label_rtx (); rtx end_src_ptr = gen_reg_rtx (Pmode); emit_insn (gen_rtx (SET, VOIDmode, end_src_ptr, gen_rtx (PLUS, Pmode, src_ptr, length))); emit_label (label); emit_move_insn (tmpreg, gen_rtx (MEM, mode, src_ptr)); emit_move_insn (gen_rtx (MEM, mode, dst_ptr), tmpreg); emit_insn (gen_rtx (SET, VOIDmode, src_ptr, gen_rtx (PLUS, Pmode, src_ptr, increment))); emit_insn (gen_rtx (SET, VOIDmode, dst_ptr, gen_rtx (PLUS, Pmode, dst_ptr, increment))); emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, HImode, src_ptr, end_src_ptr))); emit_jump_insn (gen_bne (label)); DONE; } ") ;; ---------------------------------------------------------------------- ;; Test instructions ;; ---------------------------------------------------------------------- (define_insn "tstqi" [(set (cc0) (match_operand:QI 0 "register_operand" "ra"))] "" "cmp.b #0,%X0" [(set_attr "type" "arith") (set_attr "length" "2") (set_attr "cc" "set")]) (define_insn "tsthi" [(set (cc0) (match_operand:HI 0 "register_operand" "ra"))] "" "mov.w %T0,%T0" [(set_attr "type" "arith") (set_attr "length" "2") (set_attr "cc" "set")]) (define_insn "cmphi" [(set (cc0) (compare:HI (match_operand:HI 0 "register_operand" "ra") (match_operand:HI 1 "register_operand" "ra")))] "" "cmp.w %T1,%T0" [(set_attr "type" "arith") (set_attr "length" "2") (set_attr "cc" "compare")]) (define_insn "cmpqi" [(set (cc0) (compare:QI (match_operand:QI 0 "register_operand" "ra") (match_operand:QI 1 "nonmemory_operand" "rai")))] "" "cmp.b %X1,%X0" [(set_attr "type" "arith") (set_attr "length" "2") (set_attr "cc" "compare")]) ;; ---------------------------------------------------------------------- ;; Add instructions ;; ---------------------------------------------------------------------- (define_insn "" [(set (match_operand:HI 0 "register_operand" "=ra,ra,ra,ra,r,ra") (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0") (match_operand:HI 2 "nonmemory_operand" "K,M,L,N,n,ra")))] "" "@ adds %T2,%T0 adds #2,%T0\;adds %C2,%T0 subs %M2,%T0 subs #2,%T0\;subs %M2,%T0 add.b %s2,%s0\;addx %t2,%t0 add.w %T2,%T0" [(set_attr "type" "multi,multi,multi,multi,multi,arith") (set_attr "length" "2,4,2,4,4,2") (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,clobber,set")]) (define_expand "addhi3" [(set (match_operand:HI 0 "register_operand" "") (plus:HI (match_operand:HI 1 "register_operand" "") (match_operand:HI 2 "nonmemory_operand" "")))] "" " { if (operands[0] != operands[1]) emit_move_insn (operands[0], operands[1]); }") (define_insn "addqi3" [(set (match_operand:QI 0 "register_operand" "=r") (plus:QI (match_operand:QI 1 "register_operand" "%0") (match_operand:QI 2 "nonmemory_operand" "ri")))] "" "add.b %X2,%X0" [(set_attr "type" "arith") (set_attr "length" "2") (set_attr "cc" "set")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=l,l") (plus:SI (match_operand:SI 1 "register_operand" "%0,0") (match_operand:SI 2 "nonmemory_operand" "l,n"))) (clobber (match_operand:HI 3 "register_operand" "=&l,l"))] "" "@ add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0" [(set_attr "type" "multi") (set_attr "length" "8,6") (set_attr "cc" "clobber")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=l,l") (plus:SI (match_operand:SI 1 "register_operand" "%0,0") (match_operand:SI 2 "nonmemory_operand" "n,r")))] "" "@ add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0" [(set_attr "type" "arith") (set_attr "length" "8,6") (set_attr "cc" "clobber")]) (define_expand "addsi3" [(set (match_dup 3) (match_operand:SI 1 "register_operand" "")) (set (match_dup 3) (plus:SI (match_dup 3) (match_operand:SI 2 "nonmemory_operand" ""))) (set (match_operand:SI 0 "register_operand" "") (match_dup 3))] "" " { operands[3] = gen_rtx (REG, SImode, 0); }") ;; ----------------------------------------------------------------------; ;; Subtract instructions ;; ---------------------------------------------------------------------- (define_insn "" [(set (match_operand:HI 0 "register_operand" "=ra,ra,ra,r") (minus:HI (match_operand:HI 1 "general_operand" "0,0,0,0") (match_operand:HI 2 "nonmemory_operand" "K,M,ra,n")))] "" "@ subs %T2,%T0 subs #2,%T0\;subs %E2,%T0 sub.w %T2,%T0 add.b %E2,%s0\;addx %F2,%t0 ; -%0" [(set_attr "type" "multi") (set_attr "length" "2,4,2,4") (set_attr "cc" "none_0hit,none_0hit,set,clobber")]) (define_insn "subqi3" [(set (match_operand:QI 0 "register_operand" "=r,r") (minus:QI (match_operand:QI 1 "register_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "r,i")))] "" "@ sub.b %X2,%X0 add.b %G2,%X0" [(set_attr "type" "arith") (set_attr "length" "2") (set_attr "cc" "set")]) (define_expand "subhi3" [(set (match_operand:HI 0 "register_operand" "") (minus:HI (match_operand:HI 1 "register_operand" "") (match_operand:HI 2 "nonmemory_operand" "")))] "" " { if (operands[0] != operands[1]) emit_move_insn (operands[0], operands[1]); }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=l") (minus:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "register_operand" "l")))] "" "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0" [(set_attr "type" "arith") (set_attr "length" "6") (set_attr "cc" "clobber")]) (define_expand "subsi3" [(set (match_dup 3) (match_operand:SI 1 "register_operand" "")) (set (match_dup 3) (minus:SI (match_dup 3) (match_operand:SI 2 "nonmemory_operand" ""))) (set (match_operand:SI 0 "register_operand" "") (match_dup 3))] "" "operands[3] = gen_rtx (REG, SImode, 0);") ;; ---------------------------------------------------------------------- ;; Multiply instruction ;; ---------------------------------------------------------------------- (define_insn "umulqihi3" [(set (match_operand:HI 0 "register_operand" "=r") (mult:HI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "register_operand" "r")))] "" "mulxu %X2,%T0" [(set_attr "type" "multi") (set_attr "length" "2") (set_attr "cc" "none_0hit")]) ;; ---------------------------------------------------------------------- ;; Divide instructions ;; ---------------------------------------------------------------------- (define_insn "udivqi3" [(set (match_operand:QI 0 "register_operand" "=r") (udiv:QI (match_operand:HI 1 "general_operand" "0") (match_operand:QI 2 "register_operand" "r")))] "" "divxu %X2,%T0" [(set_attr "type" "multi") (set_attr "length" "2") (set_attr "cc" "clobber")]) (define_insn "divqi3" [(set (match_operand:QI 0 "register_operand" "=r") (div:QI (match_operand:HI 1 "general_operand" "0") (match_operand:QI 2 "register_operand" "r")))] "" "divxu %X2,%T0" [(set_attr "type" "multi") (set_attr "length" "2") (set_attr "cc" "clobber")]) ;; ---------------------------------------------------------------------- ;; And instructions ;; ---------------------------------------------------------------------- (define_insn "andqi3" [(set (match_operand:QI 0 "general_operand" "=r") (and:QI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "general_operand" "rn")))] "" "and %X2,%X0" [(set_attr "type" "arith") (set_attr "length" "2") (set_attr "cc" "set")]) (define_insn "andhi3" [(set (match_operand:HI 0 "register_operand" "=r") (and:HI (match_operand:HI 1 "register_operand" "%0") (match_operand:HI 2 "general_operand" "ri")))] "" "and %s2,%s0\;and %t2,%t0" [(set_attr "type" "multi") (set_attr "length" "4") (set_attr "cc" "clobber")]) ;; ---------------------------------------------------------------------- ;; Or instructions ;; ---------------------------------------------------------------------- (define_insn "iorqi3" [(set (match_operand:QI 0 "general_operand" "=r,U") (ior:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_operand" "rn,P")))] "" "@ or %X2,%X0 bset %V2,%X0" [(set_attr "type" "arith") (set_attr "length" "2,4") (set_attr "cc" "set,none_0hit")]) (define_insn "iorhi3" [(set (match_operand:HI 0 "general_operand" "=r,r") (ior:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_operand" "J,ri")))] "" "@ or %s2,%s0 or %s2,%s0\;or %t2,%t0" [(set_attr "type" "multi") (set_attr "length" "2,4") (set_attr "cc" "clobber,clobber")]) ;; ---------------------------------------------------------------------- ;; Xor instructions ;; ---------------------------------------------------------------------- (define_insn "xorqi3" [(set (match_operand:QI 0 "general_operand" "=r") (xor:QI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "nonmemory_operand" "ri")))] "" "xor %X2,%X0" [(set_attr "type" "arith") (set_attr "length" "2") (set_attr "cc" "set")]) (define_insn "xorhi3" [(set (match_operand:HI 0 "general_operand" "=r") (xor:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "nonmemory_operand" "ri")))] "" "xor %s2,%s0\;xor %t2,%t0" [(set_attr "type" "multi") (set_attr "length" "4") (set_attr "cc" "clobber")]) ;; ---------------------------------------------------------------------- ;; Negation instructions ;; ---------------------------------------------------------------------- (define_insn "negqi2" [(set (match_operand:QI 0 "register_operand" "=r") (neg:QI (match_operand:QI 1 "general_operand" "0")))] "" "neg %X0" [(set_attr "type" "arith") (set_attr "length" "2") (set_attr "cc" "set")]) (define_expand "neghi2" [(set (match_dup 2) (not:HI (match_operand:HI 1 "register_operand" "r"))) (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1))) (set (match_operand:HI 0 "register_operand" "=r") (match_dup 2))] "" "operands[2] = gen_reg_rtx (HImode);") (define_expand "negsi2" [(set (match_dup 2) (not:SI (match_operand:SI 1 "register_operand" "r"))) (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1))) (set (match_operand:SI 0 "register_operand" "=r") (match_dup 2))] "" "operands[2] = gen_reg_rtx (SImode);") ;; ---------------------------------------------------------------------- ;; Not instructions ;; ---------------------------------------------------------------------- (define_insn "one_cmplqi2" [(set (match_operand:QI 0 "register_operand" "=r") (not:QI (match_operand:QI 1 "general_operand" "0")))] "" "not %X0" [(set_attr "type" "arith") (set_attr "length" "2") (set_attr "cc" "set")]) (define_insn "one_cmplhi2" [(set (match_operand:HI 0 "register_operand" "=r") (not:HI (match_operand:HI 1 "general_operand" "0")))] "" "not %s0\;not %t0" [(set_attr "type" "arith") (set_attr "length" "4") (set_attr "cc" "clobber")]) (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "=r") (not:SI (match_operand:SI 1 "general_operand" "0")))] "" "not %w0\;not %x0\;not %y0\;not %z0" [(set_attr "type" "arith") (set_attr "length" "8") (set_attr "cc" "clobber")]) ;; ---------------------------------------------------------------------- ;; Conditional branches ;; ---------------------------------------------------------------------- (define_expand "ble" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "") (define_expand "bleu" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "") (define_expand "bge" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "") (define_expand "bgeu" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "") (define_expand "blt" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "") (define_expand "bltu" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "") (define_expand "bgt" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "") (define_expand "bgtu" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "") (define_expand "beq" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "") (define_expand "bne" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "") (define_insn "" [(set (pc) (if_then_else (match_operator 1 "comparison_operator" [(cc0) (const_int 0)]) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { if (get_attr_length (insn) == 2) return \"b%j1 %l0\"; else return \"b%k1 %L0\;jmp @%l0\;%L0:\"; }" [(set_attr "type" "branch") (set_attr "cc" "none")]) (define_insn "" [(set (pc) (if_then_else (match_operator 1 "comparison_operator" [(cc0) (const_int 0)]) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { if (get_attr_length (insn) == 2) return \"b%k1 %l0\"; else return \"b%j1 %L0\;jmp @%l0\;%L0:\"; }" [(set_attr "type" "branch") (set_attr "cc" "none")]) ;; ---------------------------------------------------------------------- ;; Unconditional branches ;; ---------------------------------------------------------------------- (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "* { if (get_attr_length (insn) == 2) return \"bra %l0\"; else return \"jmp @%l0\"; }" [(set_attr "type" "branch") (set_attr "cc" "none")]) (define_insn "tablejump" [(set (pc) (match_operand:HI 0 "register_operand" "")) (use (label_ref (match_operand 1 "" "")))] "" "jmp @%0" [(set_attr "type" "branch") (set_attr "cc" "none") (set_attr "length" "2")]) ;; Call subroutine with no return value. (define_insn "call" [(call (match_operand:QI 0 "memory_operand" "o") (match_operand:HI 1 "general_operand" "g"))] "" "jsr %0" [(set_attr "type" "call") (set_attr "cc" "clobber") (set_attr "length" "4")]) ;; Call subroutine, returning value in operand 0 ;; (which must be a hard register). (define_insn "call_value" [(set (match_operand 0 "" "=r") (call (match_operand:QI 1 "memory_operand" "o") (match_operand:HI 2 "general_operand" "g")))] "" "jsr %1" [(set_attr "type" "call") (set_attr "cc" "clobber") (set_attr "length" "4")]) (define_insn "nop" [(const_int 0)] "" "nop" [(set_attr "type" "multi") (set_attr "cc" "none") (set_attr "length" "2")]) (define_insn "indirect_jump" [(set (pc) (match_operand:HI 0 "register_operand" "r"))] "" "jmp @%0" [(set_attr "type" "branch") (set_attr "cc" "none") (set_attr "length" "2")]) ;; ----------------------------------------------------------------- ;; Shifts ;; ----------------------------------------------------------------- ;; All H8 shifts go one bit at a time, here they are defined with names ;; so can use them in the expands.. ;; QI BIT SHIFTS (define_insn "ashlqi3_one" [(set (match_operand:QI 0 "register_operand" "=r") (ashift:QI (match_operand:QI 1 "register_operand" "0") (const_int 1)))] "" "shal %X0" [(set_attr "type" "arith") (set_attr "length" "2") (set_attr "cc" "set")]) (define_insn "ashrqi3_one" [(set (match_operand:QI 0 "register_operand" "=r") (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") (const_int 1)))] "" "shar %X0" [(set_attr "type" "arith") (set_attr "length" "2") (set_attr "cc" "set")]) (define_insn "lshrqi3_one" [(set (match_operand:QI 0 "register_operand" "=r") (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") (const_int 1)))] "" "shlr %X0" [(set_attr "type" "arith") (set_attr "length" "2") (set_attr "cc" "set")]) (define_expand "ashlqi3" [(set (match_operand:QI 0 "register_operand" "=r") (ashift:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "rn")))] "" " { if (can_shift (ASHIFT, operands, gen_ashlqi3_one, 4, 0)) DONE; else FAIL; }") (define_expand "ashrqi3" [(set (match_operand:QI 0 "register_operand" "=r") (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "rn")))] "" " { if (can_shift (ASHIFTRT, operands, gen_ashrqi3_one, 4, 0)) DONE; else FAIL; }") (define_expand "lshrqi3" [(set (match_operand:QI 0 "register_operand" "=r") (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "rn")))] "" " { if (can_shift (LSHIFTRT, operands, gen_lshrqi3_one, 4, 0)) DONE; else FAIL; }") ;; HI BIT SHIFTS (define_insn "ashlhi3_one" [(set (match_operand:HI 0 "register_operand" "=r") (ashift:HI (match_operand:HI 1 "register_operand" "0") (const_int 1)))] "" "add.w %T1,%T0" [(set_attr "type" "multi") (set_attr "length" "4") (set_attr "cc" "set")]) (define_insn "ashlhi3_eight" [(set (match_operand:HI 0 "register_operand" "=r") (ashift:HI (match_operand:HI 1 "register_operand" "0") (const_int 8)))] "" "mov.b %s1,%t0\;mov.b #0,%s0" [(set_attr "type" "multi") (set_attr "length" "4") (set_attr "cc" "clobber")]) (define_expand "ashlhi3" [(set (match_operand:HI 0 "register_operand" "") (ashift:HI (match_operand:HI 1 "general_operand_src" "") (match_operand:HI 2 "nonmemory_operand" "")))] "" " { if (can_shift (ASHIFT, operands, gen_ashlhi3_one, 4, gen_ashlhi3_eight)) DONE; else FAIL; }") (define_insn "lshrhi3_one" [(set (match_operand:HI 0 "register_operand" "=r") (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") (const_int 1)))] "" "shlr %t0\;rotxr %s0" [(set_attr "type" "multi") (set_attr "length" "4") (set_attr "cc" "clobber")]) (define_insn "lshlhi3_eight" [(set (match_operand:HI 0 "register_operand" "=r") (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") (const_int 8)))] "" "mov.b %t1,%s0\;mov.b #0,%t0" [(set_attr "type" "multi") (set_attr "length" "4") (set_attr "cc" "clobber")]) (define_expand "lshrhi3" [(set (match_operand:HI 0 "register_operand" "") (lshiftrt:HI (match_operand:HI 1 "general_operand_src" "") (match_operand:HI 2 "nonmemory_operand" "")))] "" " { if (can_shift (LSHIFTRT, operands, gen_lshrhi3_one, 4, gen_lshlhi3_eight)) DONE; else FAIL; }") (define_insn "ashrhi3_one" [(set (match_operand:HI 0 "register_operand" "=r") (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") (const_int 1)))] "" "shar %t0\;rotxr %s0" [(set_attr "type" "multi") (set_attr "length" "4") (set_attr "cc" "clobber")]) ; signed shift right by 8 bits ; fetch the carry bit from the top, copy the byte right, subtract the ; top byte from itself - carry. (define_insn "ashrhi3_eight" [(set (match_operand:HI 0 "register_operand" "=r") (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") (const_int 8)))] "" "bld #7,%t0\;mov.b %t0,%s0\;subx %t0,%t0" [(set_attr "type" "multi") (set_attr "length" "6") (set_attr "cc" "clobber")]) (define_expand "ashrhi3" [(set (match_operand:HI 0 "register_operand" "") (ashiftrt:HI (match_operand:HI 1 "general_operand_src" "") (match_operand:HI 2 "nonmemory_operand" "")))] "" " { if (can_shift (ASHIFTRT, operands, gen_ashrhi3_one, 4, gen_ashrhi3_eight)) DONE; else FAIL; }") ;; SI BIT SHIFTS (define_insn "ashlsi3_one" [(set (match_operand:SI 0 "register_operand" "=r") (ashift:SI (match_operand:SI 1 "register_operand" "0") (const_int 1)))] "" "add.w %f1,%f0\;addx %y1,%y0\;addx %z1,%z0" [(set_attr "type" "multi") (set_attr "length" "6") (set_attr "cc" "clobber")]) (define_expand "ashlsi3" [(set (match_operand:SI 0 "register_operand" "") (ashift:SI (match_operand:SI 1 "general_operand_src" "") (match_operand:SI 2 "nonmemory_operand" "")))] "" " { if (can_shift (ASHIFT, operands, gen_ashlsi3_one, 1, 0)) DONE; else FAIL; }") (define_insn "lshrsi3_one" [(set (match_operand:SI 0 "register_operand" "=r") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") (const_int 1)))] "" "shlr %z0\;rotxr %y0\;rotxr %x0\;rotxr %w0" [(set_attr "type" "multi") (set_attr "length" "8") (set_attr "cc" "clobber")]) (define_expand "lshrsi3" [(set (match_operand:SI 0 "register_operand" "") (lshiftrt:SI (match_operand:SI 1 "general_operand_src" "") (match_operand:SI 2 "nonmemory_operand" "")))] "" " { if (can_shift (LSHIFTRT, operands, gen_lshrsi3_one, 1, 0)) DONE; else FAIL; }") (define_insn "ashrsi3_one" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") (const_int 1)))] "" "shar %z0\;rotxr %y0\;rotxr %x0\;rotxr %w0" [(set_attr "type" "multi") (set_attr "length" "16") (set_attr "cc" "clobber")]) (define_expand "ashrsi3" [(set (match_operand:SI 0 "register_operand" "") (ashiftrt:SI (match_operand:SI 1 "general_operand_src" "") (match_operand:SI 2 "nonmemory_operand" "")))] "" " { if (can_shift (ASHIFTRT, operands, gen_ashrsi3_one, 1, 0)) DONE; else FAIL; }") ;; ---------------------------------------------------------------------- ;; BIT FIELDS ;; ---------------------------------------------------------------------- (define_insn "" [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r") (const_int 1) (match_operand:HI 2 "general_operand" "g")) (match_operand:HI 3 "general_operand" "r"))] "" "bld #0,%3l\;bst %Z2,%0%Y1" [(set_attr "type" "multi") (set_attr "length" "4") (set_attr "cc" "clobber")]) (define_expand "insv" [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r") (match_operand:HI 1 "general_operand" "g") (match_operand:HI 2 "general_operand" "g")) (match_operand:HI 3 "general_operand" "r"))] "" "if (INTVAL (operands[1]) != 1) FAIL;") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=&r") (zero_extract:HI (match_operand:HI 1 "register_operand" "r") (const_int 1) (match_operand:HI 3 "general_operand" "g")))] "" "sub.w %T0,%T0\;bld %Z3,%T1%Y1\;rotxl %T0l" [(set_attr "type" "multi") (set_attr "length" "6") (set_attr "cc" "clobber")]) (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (sign_extract:HI (match_operand:HI 1 "register_operand" "r") (const_int 1) (match_operand:HI 3 "general_operand" "g")))] "" "bld %Z3,%1%Y1\;sub.x %0l,%0l\;mov.b %0l,%0h" [(set_attr "type" "multi") (set_attr "length" "6") (set_attr "cc" "clobber")]) (define_expand "extzv" [(set (match_operand:HI 0 "register_operand" "") (zero_extract:HI (match_operand:HI 1 "register_operand" "") (match_operand:HI 2 "general_operand" "") (match_operand:HI 3 "general_operand" "")))] "" "if (INTVAL (operands[2]) != 1) FAIL;") (define_expand "extv" [(set (match_operand:HI 0 "register_operand" "") (sign_extract:HI (match_operand:HI 1 "register_operand" "") (match_operand:HI 2 "general_operand" "") (match_operand:HI 3 "immediate_operand" "")))] "" "if (INTVAL (operands[2]) != 1) FAIL;") ;; ---------------------------------------------------------------------- ;; Conversions ;; ---------------------------------------------------------------------- (define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "=r") (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))] "" "mov.b %X1,%s0\;mov.b #0,%t0" [(set_attr "type" "multi") (set_attr "length" "4") (set_attr "cc" "clobber")]) (define_insn "extendqihi2" [(set (match_operand:HI 0 "register_operand" "=r") (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))] "" "* { if (REGNO (operands[1]) != REGNO (operands[0])) return \"mov.b %X1,%s0\;bld #7,%s0\;subx %t0,%t0\"; else return \"bld #7,%s0\;subx %t0,%t0\"; }" [(set_attr "type" "multi") (set_attr "length" "6") (set_attr "cc" "clobber")]) (define_insn "extendhisi2_one" [(set (match_operand:SI 0 "register_operand" "=l") (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))] "" "mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0" [(set_attr "length" "10") (set_attr "cc" "clobber")]) (define_expand "extendhisi2" [(set (reg:HI 1) (match_operand:HI 1 "general_operand" "")) (set (reg:SI 0) (sign_extend:SI (reg:HI 1))) (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))] "" "") ;; ---------------------------------------------------------------------- ;; peepholes ;; ---------------------------------------------------------------------- ;; notice a move which could be predecremented (define_peephole [(set (match_operand:HI 1 "register_operand" "") (plus:HI (match_dup 1) (const_int -1))) (set (mem:HI (match_dup 1)) (match_operand:HI 0 "register_operand" ""))] "REGNO (operands[1]) != REGNO (operands[0])" "mov.w %T0,@-%T1" [(set_attr "length" "2") (set_attr "cc" "set")]) (define_peephole [(set (match_operand:HI 1 "register_operand" "") (plus:HI (match_dup 1) (const_int -1))) (set (mem:QI (match_dup 1)) (match_operand:QI 0 "register_operand" ""))] "REGNO (operands[1]) != REGNO (operands[0])" "mov.b %X0,@-%T1" [(set_attr "length" "2") (set_attr "cc" "set")]) ;; notice a move which could be post incremented (define_peephole [(set (match_operand:HI 0 "register_operand" "") (mem:HI (match_operand:HI 1 "register_operand" ""))) (set (match_dup 1) (plus:HI (match_dup 1) (const_int 2)))] "REGNO (operands[1]) != REGNO (operands[0])" "mov.w @%T1+,%T0" [(set_attr "length" "2") (set_attr "cc" "set")]) (define_peephole [(set (match_operand:QI 0 "register_operand" "") (mem:QI (match_operand:HI 1 "register_operand" ""))) (set (match_dup 1) (plus:HI (match_dup 1) (const_int 1)))] "REGNO (operands[1]) != REGNO (operands[0])" "mov.b @%T1+,%X0" [(set_attr "length" "2") (set_attr "cc" "set")]) ;; notice when two byte moves in a row could be a word move (define_peephole [(set (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "ra") (match_operand:HI 2 "immediate_operand" "n"))) (match_operand:QI 0 "register_operand" "r")) (set (mem:QI (plus:HI (match_dup 1) (match_operand:HI 4 "immediate_operand" "n"))) (match_operand:QI 3 "register_operand" "r"))] "(INTVAL (operands[2]) == INTVAL (operands[4]) + 1) && (REGNO (operands[0]) + 1 == REGNO (operands[3]))" "mov.w %T0,@(%u4,%T1)" [(set_attr "length" "6") (set_attr "cc" "set")]) (define_peephole [(set (match_operand:QI 0 "register_operand" "=r") (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "ra") (match_operand:HI 2 "immediate_operand" "n")))) (set (match_operand:QI 3 "register_operand" "=r") (mem:QI (plus:HI (match_dup 1) (match_operand:HI 4 "immediate_operand" "n"))))] "(INTVAL (operands[2]) == INTVAL (operands[4]) + 1) && (REGNO (operands[0]) + 1 == REGNO (operands[3]))" "mov.w @(%u4,%T1),%T0" [(set_attr "length" "6") (set_attr "cc" "set")]) gcc-2.5.8/config/h8300/t-h8300100444 22011 13 355 5443705744 13717 0ustar kenneruserLIBGCC1 = libgcc1.null CROSS_LIBGCC1 = libgcc1.null T_CFLAGS = -DDONT_HAVE_STDIO -DDONT_HAVE_SETJMP # we do not have DF or DI types, so fake out the libgcc2 compilation LIBGCC2_CFLAGS=-O -DDF=SF -DDI=SI $(GCC_CFLAGS) LIB2FUNCS_EXTRA = gcc-2.5.8/config/h8300/xm-h8300.h100444 22011 13 2620 5433345737 14344 0ustar kenneruser/* Configuration for GNU C-compiler for H8/300. Copyright (C) 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* #defines that need visibility everywhere. */ #define FALSE 0 #define TRUE 1 /* This describes the machine the compiler is hosted on. */ #define HOST_BITS_PER_CHAR 8 #define HOST_BITS_PER_SHORT 16 #define HOST_BITS_PER_INT 16 #define HOST_BITS_PER_LONG 32 #define HOST_BITS_PER_LONGLONG 64 /* Arguments to use with `exit'. */ #define SUCCESS_EXIT_CODE 0 #define FATAL_EXIT_CODE 33 /* If compiled with GNU C, use the built-in alloca */ #ifdef __GNUC__ #define alloca __builtin_alloca #else #define USE_C_ALLOCA #endif /* target machine dependencies. tm.h is a symbolic link to the actual target specific file. */ #include "tm.h" gcc-2.5.8/config/i370/ 40777 22011 13 0 5502602745 12630 5ustar kennerusergcc-2.5.8/config/i370/i370.md100444 22011 13 267230 5453625346 14004 0ustar kenneruser;;- Machine description for GNU compiler -- System/370 version. ;; Copyright (C) 1989, 1993 Free Software Foundation, Inc. ;; Contributed by Jan Stein (jan@cd.chalmers.se). ;; Modifed for MVS C/370 by Dave Pitts (pitts@mcdata.com) ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code ;;- updates for most instructions. ;; ;; Special constraints for 370 machine description: ;; ;; a -- Any address register from 1 to 15. ;; d -- Any register from 0 to 15. ;; I -- An 8-bit constant (0..255). ;; J -- A 12-bit constant (0..4095). ;; K -- A 16-bit constant (-32768..32767). ;; ;; Special formats used for outputting 370 instructions. ;; ;; %B -- Print a constant byte integer. ;; %H -- Print a signed 16-bit constant. ;; %L -- Print least significant word of a CONST_DOUBLE. ;; %M -- Print most significant word of a CONST_DOUBLE. ;; %N -- Print next register (second word of a DImode reg). ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)). ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)). ;; %X -- Print a constant byte integer in hex. ;; ;; We have a special contraint for pattern matching. ;; ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. ;; ;; r_or_s_operand -- Matches a register or a valid S operand in a RS, SI ;; or SS type instruction or a register ;; ;; For MVS C/370 we use the following stack locations for: ;; ;; 136 - internal function result buffer ;; 140 - numeric conversion buffer ;; 144 - pointer to internal function result buffer ;; 148 - start of automatic variables and function arguments ;; ;; To support programs larger than a page, 4096 bytes, PAGE_REGISTER points ;; to a page origin table, all internal labels are generated to reload the ;; BASE_REGISTER knowing what page it is on and all branch instructions go ;; directly to the target if it is known that the target is on the current ;; page (essentially backward references). All forward references and off ;; page references are handled by loading the address of target into a ;; register and branching indirectly. ;; ;; Some *di patterns have been commented out per advice from RMS, as gcc ;; will generate the right things to do. ;; ;; ;;- Test instructions. ;; ; ; tstdi instruction pattern(s). ; (define_insn "tstdi" [(set (cc0) (match_operand:DI 0 "register_operand" "d"))] "" "* { check_label_emit (); mvs_check_page (0, 4, 0); return \"SRDA %0,0\"; }") ; ; tstsi instruction pattern(s). ; (define_insn "tstsi" [(set (cc0) (match_operand:SI 0 "register_operand" "d"))] "" "* { check_label_emit (); mvs_check_page (0, 2, 0); return \"LTR %0,%0\"; }") ; ; tsthi instruction pattern(s). ; (define_insn "tsthi" [(set (cc0) (match_operand:HI 0 "register_operand" "d"))] "" "* { check_label_emit (); mvs_check_page (0, 4, 2); return \"CH %0,=H'0'\"; }") ; ; tstqi instruction pattern(s). ; (define_insn "" [(set (cc0) (match_operand:QI 0 "r_or_s_operand" "dm"))] "unsigned_jump_follows_p (insn)" "* { check_label_emit (); if (REG_P (operands[0])) { mvs_check_page (0, 4, 4); return \"N %0,=X'000000FF'\"; } mvs_check_page (0, 4, 0); return \"CLI %0,0\"; }") (define_insn "tstqi" [(set (cc0) (match_operand:QI 0 "register_operand" "d"))] "" "* { check_label_emit (); if (unsigned_jump_follows_p (insn)) { mvs_check_page (0, 4, 4); return \"N %0,=X'000000FF'\"; } mvs_check_page (0, 8, 0); return \"SLL %0,24\;SRA %0,24\"; }") ; ; tstdf instruction pattern(s). ; (define_insn "tstdf" [(set (cc0) (match_operand:DF 0 "general_operand" "f"))] "" "* { check_label_emit (); mvs_check_page (0, 2, 0); return \"LTDR %0,%0\"; }") ; ; tstsf instruction pattern(s). ; (define_insn "tstsf" [(set (cc0) (match_operand:SF 0 "general_operand" "f"))] "" "* { check_label_emit (); mvs_check_page (0, 2, 0); return \"LTER %0,%0\"; }") ;; ;;- Compare instructions. ;; ; ; cmpdi instruction pattern(s). ; ;(define_insn "cmpdi" ; [(set (cc0) ; (compare (match_operand:DI 0 "register_operand" "d") ; (match_operand:DI 1 "general_operand" "")))] ; "" ; "* ;{ ; check_label_emit (); ; if (REG_P (operands[1])) ; { ; mvs_check_page (0, 8, 0); ; if (unsigned_jump_follows_p (insn)) ; return \"CLR %0,%1\;BNE *+6\;CLR %N0,%N1\"; ; return \"CR %0,%1\;BNE *+6\;CLR %N0,%N1\"; ; } ; mvs_check_page (0, 12, 0); ; if (unsigned_jump_follows_p (insn)) ; return \"CL %0,%M1\;BNE *+8\;CL %N0,%L1\"; ; return \"C %0,%M1\;BNE *+8\;CL %N0,%L1\"; ;}") ; ; cmpsi instruction pattern(s). ; (define_insn "cmpsi" [(set (cc0) (compare (match_operand:SI 0 "register_operand" "d") (match_operand:SI 1 "general_operand" "")))] "" "* { check_label_emit (); if (REG_P (operands[1])) { mvs_check_page (0, 2, 0); if (unsigned_jump_follows_p (insn)) return \"CLR %0,%1\"; return \"CR %0,%1\"; } if (GET_CODE (operands[1]) == CONST_INT) { mvs_check_page (0, 4, 4); if (unsigned_jump_follows_p (insn)) return \"CL %0,=F'%c1'\"; return \"C %0,=F'%c1'\"; } mvs_check_page (0, 4, 0); if (unsigned_jump_follows_p (insn)) return \"CL %0,%1\"; return \"C %0,%1\"; }") ; ; cmphi instruction pattern(s). ; (define_insn "cmphi" [(set (cc0) (compare (match_operand:HI 0 "register_operand" "d") (match_operand:HI 1 "general_operand" "")))] "" "* { check_label_emit (); if (REG_P (operands[1])) { mvs_check_page (0, 8, 0); if (unsigned_jump_follows_p (insn)) return \"STH %1,140(,13)\;CLM %0,3,140(13)\"; return \"STH %1,140(,13)\;CH %0,140(,13)\"; } if (GET_CODE (operands[1]) == CONST_INT) { mvs_check_page (0, 4, 2); return \"CH %0,=H'%h1'\"; } mvs_check_page (0, 4, 0); return \"CH %0,%1\"; }") ; ; cmpqi instruction pattern(s). ; (define_insn "" [(set (cc0) (compare (match_operand:QI 0 "r_or_s_operand" "g") (match_operand:QI 1 "r_or_s_operand" "g")))] "unsigned_jump_follows_p (insn)" "* { check_label_emit (); if (REG_P (operands[0])) { if (REG_P (operands[1])) { mvs_check_page (0, 8, 0); return \"STC %1,140(,13)\;CLM %0,1,140(13)\"; } if (GET_CODE (operands[1]) == CONST_INT) { mvs_check_page (0, 4, 1); return \"CLM %0,1,=X'%X1'\"; } mvs_check_page (0, 4, 0); return \"CLM %0,1,%1\"; } else if (GET_CODE (operands[0]) == CONST_INT) { cc_status.flags |= CC_REVERSED; if (REG_P (operands[1])) { mvs_check_page (0, 4, 1); return \"CLM %1,1,=X'%X0'\"; } mvs_check_page (0, 4, 0); return \"CLI %1,%B0\"; } if (GET_CODE (operands[1]) == CONST_INT) { mvs_check_page (0, 4, 0); return \"CLI %0,%B1\"; } if (GET_CODE (operands[1]) == MEM) { mvs_check_page (0, 6, 0); return \"CLC %O0(1,%R0),%1\"; } cc_status.flags |= CC_REVERSED; mvs_check_page (0, 4, 0); return \"CLM %1,1,%0\"; }") (define_insn "cmpqi" [(set (cc0) (compare (match_operand:QI 0 "register_operand" "d") (match_operand:QI 1 "general_operand" "di")))] "" "* { check_label_emit (); if (unsigned_jump_follows_p (insn)) { if (REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"CLM %0,1,%1\"; } if (GET_CODE (operands[1]) == CONST_INT) { mvs_check_page (0, 4, 1); return \"CLM %0,1,=X'%X1'\"; } mvs_check_page (0, 8, 0); return \"STC %1,140(,13)\;CLM %0,1,140(13)\"; } if (REG_P (operands[1])) { mvs_check_page (0, 18, 0); return \"SLL %0,24\;SRA %0,24\;SLL %1,24\;SRA %1,24\;CR %0,%1\"; } mvs_check_page (0, 12, 0); return \"SLL %0,24\;SRA %0,24\;C %0,%1\"; }") ; ; cmpdf instruction pattern(s). ; (define_insn "cmpdf" [(set (cc0) (compare (match_operand:DF 0 "general_operand" "f,mF") (match_operand:DF 1 "general_operand" "fmF,f")))] "" "* { check_label_emit (); if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) { mvs_check_page (0, 2, 0); return \"CDR %0,%1\"; } mvs_check_page (0, 4, 0); return \"CD %0,%1\"; } cc_status.flags |= CC_REVERSED; mvs_check_page (0, 4, 0); return \"CD %1,%0\"; }") ; ; cmpsf instruction pattern(s). ; (define_insn "cmpsf" [(set (cc0) (compare (match_operand:SF 0 "general_operand" "f,mF") (match_operand:SF 1 "general_operand" "fmF,f")))] "" "* { check_label_emit (); if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) { mvs_check_page (0, 2, 0); return \"CER %0,%1\"; } mvs_check_page (0, 4, 0); return \"CE %0,%1\"; } cc_status.flags |= CC_REVERSED; mvs_check_page (0, 4, 0); return \"CE %1,%0\"; }") ; ; cmpstrsi instruction pattern(s). ; (define_expand "cmpstrsi" [(set (match_operand:SI 0 "general_operand" "") (compare (match_operand:BLK 1 "general_operand" "") (match_operand:BLK 2 "general_operand" ""))) (use (match_operand:SI 3 "general_operand" "")) (use (match_operand:SI 4 "" ""))] "" " { rtx op1, op2; op1 = XEXP (operands[1], 0); if (GET_CODE (op1) == REG || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1, 0)) == REG && GET_CODE (XEXP (op1, 1)) == CONST_INT && (unsigned) INTVAL (XEXP (op1, 1)) < 4096)) { op1 = operands[1]; } else { op1 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op1)); } op2 = XEXP (operands[2], 0); if (GET_CODE (op2) == REG || (GET_CODE (op2) == PLUS && GET_CODE (XEXP (op2, 0)) == REG && GET_CODE (XEXP (op2, 1)) == CONST_INT && (unsigned) INTVAL (XEXP (op2, 1)) < 4096)) { op2 = operands[2]; } else { op2 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op2)); } if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256) { emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, gen_rtx (SET, VOIDmode, operands[0], gen_rtx (COMPARE, VOIDmode, op1, op2)), gen_rtx (USE, VOIDmode, operands[3])))); } else { rtx reg1 = gen_reg_rtx (DImode); rtx reg2 = gen_reg_rtx (DImode); rtx subreg = gen_rtx (SUBREG, SImode, reg1, 1); emit_insn (gen_rtx (SET, VOIDmode, subreg, operands[3])); emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, reg2, 1), subreg)); emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5, gen_rtx (SET, VOIDmode, operands[0], gen_rtx (COMPARE, VOIDmode, op1, op2)), gen_rtx (USE, VOIDmode, reg1), gen_rtx (USE, VOIDmode, reg2), gen_rtx (CLOBBER, VOIDmode, reg1), gen_rtx (CLOBBER, VOIDmode, reg2)))); } DONE; }") ; Compare a block that is less than 256 bytes in length. (define_insn "" [(set (match_operand:SI 0 "register_operand" "d") (compare (match_operand:BLK 1 "s_operand" "m") (match_operand:BLK 2 "s_operand" "m"))) (use (match_operand:QI 3 "immediate_operand" "I"))] "((unsigned) INTVAL (operands[3]) < 256)" "* { check_label_emit (); mvs_check_page (0, 22, 0); return \"LA %0,1\;CLC %O1(%c3,%R1),%2\;BH *+12\;BL *+6\;SLR %0,%0\;LNR %0,%0\"; }") ; Compare a block that is larger than 255 bytes in length. (define_insn "" [(set (match_operand:SI 0 "register_operand" "d") (compare (match_operand:BLK 1 "general_operand" "m") (match_operand:BLK 2 "general_operand" "m"))) (use (match_operand:DI 3 "register_operand" "d")) (use (match_operand:DI 4 "register_operand" "d")) (clobber (match_dup 3)) (clobber (match_dup 4))] "" "* { check_label_emit (); mvs_check_page (0, 26, 0); return \"LA %3,%1\;LA %4,%2\;LA %0,1\;CLCL %3,%4\;BH *+12\;BL *+6\;SLR %0,%0\;LNR %0,%0\"; }") ;; ;;- Move instructions. ;; ; ; movdi instruction pattern(s). ; (define_insn "" [(set (match_operand:DI 0 "r_or_s_operand" "=dm") (match_operand:DI 1 "r_or_s_operand" "dim*fF"))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); if (REG_P (operands[0])) { if (FP_REG_P (operands[1])) { mvs_check_page (0, 8, 0); return \"STD %1,140(,13)\;LM %0,%N0,140(13)\"; } if (REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"LR %0,%1\;LR %N0,%N1\"; } if (operands[1] == const0_rtx) { CC_STATUS_INIT; mvs_check_page (0, 4, 0); return \"SLR %0,%0\;SLR %N0,%N0\"; } if (GET_CODE (operands[1]) == CONST_INT && (unsigned) INTVAL (operands[1]) < 4096) { CC_STATUS_INIT; mvs_check_page (0, 6, 0); return \"SLR %0,%0\;LA %N0,%c1\"; } if (GET_CODE (operands[1]) == CONST_INT) { CC_STATUS_SET (operands[0], operands[1]); mvs_check_page (0, 8, 0); return \"L %0,%1\;SRDA %0,32\"; } mvs_check_page (0, 4, 0); return \"LM %0,%N0,%1\"; } else if (FP_REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"STD %1,%0\"; } else if (REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"STM %1,%N1,%0\"; } mvs_check_page (0, 6, 0); return \"MVC %O0(8,%R0),%1\"; }") (define_insn "movdi" [(set (match_operand:DI 0 "general_operand" "=dm") (match_operand:DI 1 "general_operand" "dim*fF"))] "" "* { check_label_emit (); if (REG_P (operands[0])) { if (FP_REG_P (operands[1])) { mvs_check_page (0, 8, 0); return \"STD %1,140(,13)\;LM %0,%N0,140(13)\"; } if (REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"LR %0,%1\;LR %N0,%N1\"; } if (operands[1] == const0_rtx) { CC_STATUS_INIT; mvs_check_page (0, 4, 0); return \"SLR %0,%0\;SLR %N0,%N0\"; } if (GET_CODE (operands[1]) == CONST_INT && (unsigned) INTVAL (operands[1]) < 4096) { CC_STATUS_INIT; mvs_check_page (0, 6, 0); return \"SLR %0,%0\;LA %N0,%c1\"; } if (GET_CODE (operands[1]) == CONST_INT) { CC_STATUS_SET (operands[0], operands[1]); mvs_check_page (0, 8, 0); return \"L %0,%1\;SRDA %0,32\"; } mvs_check_page (0, 4, 0); return \"LM %0,%N0,%1\"; } else if (FP_REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"STD %1,%0\"; } mvs_check_page (0, 4, 0); return \"STM %1,%N1,%0\"; }") ; ; movsi instruction pattern(s). ; (define_insn "" [(set (match_operand:SI 0 "r_or_s_operand" "=dm,dm") (match_operand:SI 1 "r_or_s_operand" "dim,*fF"))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); if (REG_P (operands[0])) { if (FP_REG_P (operands[1])) { mvs_check_page (0, 8, 0); return \"STE %1,140(,13)\;L %0,140(,13)\"; } if (REG_P (operands[1])) { mvs_check_page (0, 2, 0); return \"LR %0,%1\"; } if (operands[1] == const0_rtx) { CC_STATUS_INIT; mvs_check_page (0, 2, 0); return \"SLR %0,%0\"; } if (GET_CODE (operands[1]) == CONST_INT && (unsigned) INTVAL (operands[1]) < 4096) { mvs_check_page (0, 4, 0); return \"LA %0,%c1\"; } mvs_check_page (0, 4, 0); return \"L %0,%1\"; } else if (FP_REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"STE %1,%0\"; } else if (REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"ST %1,%0\"; } mvs_check_page (0, 6, 0); return \"MVC %O0(4,%R0),%1\"; }") (define_insn "movsi" [(set (match_operand:SI 0 "general_operand" "=d,dm") (match_operand:SI 1 "general_operand" "dimF,*fd"))] "" "* { check_label_emit (); if (REG_P (operands[0])) { if (FP_REG_P (operands[1])) { mvs_check_page (0, 8, 0); return \"STE %1,140(,13)\;L %0,140(,13)\"; } if (REG_P (operands[1])) { mvs_check_page (0, 2, 0); return \"LR %0,%1\"; } if (operands[1] == const0_rtx) { CC_STATUS_INIT; mvs_check_page (0, 2, 0); return \"SLR %0,%0\"; } if (GET_CODE (operands[1]) == CONST_INT && (unsigned) INTVAL (operands[1]) < 4096) { mvs_check_page (0, 4, 0); return \"LA %0,%c1\"; } mvs_check_page (0, 4, 0); return \"L %0,%1\"; } else if (FP_REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"STE %1,%0\"; } mvs_check_page (0, 4, 0); return \"ST %1,%0\"; }") ;(define_expand "movsi" ; [(set (match_operand:SI 0 "general_operand" "=d,dm") ; (match_operand:SI 1 "general_operand" "dimF,*fd"))] ; "" ; " ;{ ; rtx op0, op1; ; ; op0 = operands[0]; ; if (GET_CODE (op0) == CONST ; && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SYMBOL_REF ; && SYMBOL_REF_FLAG (XEXP (XEXP (op0, 0), 0))) ; { ; op0 = gen_rtx (MEM, SImode, copy_to_mode_reg (SImode, XEXP (op0, 0))); ; } ; ; op1 = operands[1]; ; if (GET_CODE (op1) == CONST ; && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF ; && SYMBOL_REF_FLAG (XEXP (XEXP (op1, 0), 0))) ; { ; op1 = gen_rtx (MEM, SImode, copy_to_mode_reg (SImode, XEXP (op1, 0))); ; } ; ; emit_insn (gen_rtx (SET, VOIDmode, op0, op1)); ; DONE; ;}") ; ; movhi instruction pattern(s). ; (define_insn "" [(set (match_operand:HI 0 "r_or_s_operand" "=g") (match_operand:HI 1 "r_or_s_operand" "g"))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); if (REG_P (operands[0])) { if (REG_P (operands[1])) { mvs_check_page (0, 2, 0); return \"LR %0,%1\"; } if (operands[1] == const0_rtx) { CC_STATUS_INIT; mvs_check_page (0, 2, 0); return \"SLR %0,%0\"; } if (GET_CODE (operands[1]) == CONST_INT && (unsigned) INTVAL (operands[1]) < 4096) { mvs_check_page (0, 4, 0); return \"LA %0,%c1\"; } if (GET_CODE (operands[1]) == CONST_INT) { mvs_check_page (0, 4, 2); return \"LH %0,=H'%h1'\"; } mvs_check_page (0, 4, 0); return \"LH %0,%1\"; } else if (REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"STH %1,%0\"; } if (GET_CODE (operands[1]) == CONST_INT) { mvs_check_page (0, 6, 0); return \"MVC %O0(2,%R0),=H'%h1'\"; } mvs_check_page (0, 6, 0); return \"MVC %O0(2,%R0),%1\"; }") (define_insn "movhi" [(set (match_operand:HI 0 "general_operand" "=d,m") (match_operand:HI 1 "general_operand" "g,d"))] "" "* { check_label_emit (); if (REG_P (operands[0])) { if (REG_P (operands[1])) { mvs_check_page (0, 2, 0); return \"LR %0,%1\"; } if (operands[1] == const0_rtx) { CC_STATUS_INIT; mvs_check_page (0, 2, 0); return \"SLR %0,%0\"; } if (GET_CODE (operands[1]) == CONST_INT && (unsigned) INTVAL (operands[1]) < 4096) { mvs_check_page (0, 4, 0); return \"LA %0,%c1\"; } if (GET_CODE (operands[1]) == CONST_INT) { mvs_check_page (0, 4, 2); return \"LH %0,=H'%h1'\"; } mvs_check_page (0, 4, 0); return \"LH %0,%1\"; } mvs_check_page (0, 4, 0); return \"STH %1,%0\"; }") ; ; movqi instruction pattern(s). ; (define_insn "" [(set (match_operand:QI 0 "r_or_s_operand" "=g") (match_operand:QI 1 "r_or_s_operand" "g"))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); if (REG_P (operands[0])) { if (REG_P (operands[1])) { mvs_check_page (0, 2, 0); return \"LR %0,%1\"; } if (operands[1] == const0_rtx) { CC_STATUS_INIT; mvs_check_page (0, 2, 0); return \"SLR %0,%0\"; } if (GET_CODE (operands[1]) == CONST_INT) { if (INTVAL (operands[1]) >= 0) { mvs_check_page (0, 4, 0); return \"LA %0,%c1\"; } mvs_check_page (0, 4, 0); return \"L %0,=F'%c1'\"; } mvs_check_page (0, 4, 0); return \"IC %0,%1\"; } else if (REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"STC %1,%0\"; } else if (GET_CODE (operands[1]) == CONST_INT) { mvs_check_page (0, 4, 0); return \"MVI %0,%B1\"; } mvs_check_page (0, 6, 0); return \"MVC %O0(1,%R0),%1\"; }") (define_insn "movqi" [(set (match_operand:QI 0 "general_operand" "=d,m") (match_operand:QI 1 "general_operand" "g,d"))] "" "* { check_label_emit (); if (REG_P (operands[0])) { if (REG_P (operands[1])) { mvs_check_page (0, 2, 0); return \"LR %0,%1\"; } if (operands[1] == const0_rtx) { CC_STATUS_INIT; mvs_check_page (0, 2, 0); return \"SLR %0,%0\"; } if (GET_CODE (operands[1]) == CONST_INT) { if (INTVAL (operands[1]) >= 0) { mvs_check_page (0, 4, 0); return \"LA %0,%c1\"; } mvs_check_page (0, 4, 0); return \"L %0,=F'%c1'\"; } mvs_check_page (0, 4, 0); return \"IC %0,%1\"; } mvs_check_page (0, 4, 0); return \"STC %1,%0\"; }") ; ; movestrictqi instruction pattern(s). ; (define_insn "movestrictqi" [(set (strict_low_part (match_operand:QI 0 "general_operand" "=d")) (match_operand:QI 1 "general_operand" "g"))] "" "* { check_label_emit (); if (REG_P (operands[1])) { mvs_check_page (0, 8, 0); return \"STC %1,140(,13)\;IC %0,140(,13)\"; } mvs_check_page (0, 4, 0); return \"IC %0,%1\"; }") ; ; movstricthi instruction pattern(s). ; (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "=d")) (match_operand:HI 1 "r_or_s_operand" "g"))] "" "* { check_label_emit (); if (REG_P (operands[1])) { mvs_check_page (0, 8, 0); return \"STH %1,140(,13)\;ICM %0,3,140(13)\"; } else if (GET_CODE (operands[1]) == CONST_INT) { mvs_check_page (0, 4, 2); return \"ICM %0,3,=H'%h1'\"; } mvs_check_page (0, 4, 0); return \"ICM %0,3,%1\"; }") (define_insn "movestricthi" [(set (strict_low_part (match_operand:HI 0 "general_operand" "=dm")) (match_operand:HI 1 "general_operand" "d"))] "" "* { check_label_emit (); if (REG_P (operands[0])) { mvs_check_page (0, 8, 0); return \"STH %1,140(,13)\;ICM %0,3,140(13)\"; } mvs_check_page (0, 4, 0); return \"STH %1,%0\"; }") ; ; movdf instruction pattern(s). ; (define_insn "" [(set (match_operand:DF 0 "r_or_s_operand" "=fm,fm,*dm") (match_operand:DF 1 "r_or_s_operand" "fmF,*dm,fmF"))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) { mvs_check_page (0, 2, 0); return \"LDR %0,%1\"; } if (REG_P (operands[1])) { mvs_check_page (0, 8, 0); return \"STM %1,%N1,140(13)\;LD %0,140(,13)\"; } if (operands[1] == const0_rtx) { CC_STATUS_SET (operands[0], operands[1]); mvs_check_page (0, 2, 0); return \"SDR %0,%0\"; } mvs_check_page (0, 4, 0); return \"LD %0,%1\"; } if (REG_P (operands[0])) { if (FP_REG_P (operands[1])) { mvs_check_page (0, 12, 0); return \"STD %1,140(,13)\;LM %0,%N0,140(13)\"; } mvs_check_page (0, 4, 0); return \"LM %0,%N0,%1\"; } else if (FP_REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"STD %1,%0\"; } else if (REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"STM %1,%N1,%0\"; } mvs_check_page (0, 6, 0); return \"MVC %O0(8,%R0),%1\"; }") (define_insn "movdf" [(set (match_operand:DF 0 "general_operand" "=f,fm,m,*d") (match_operand:DF 1 "general_operand" "fmF,*d,f,fmF"))] "" "* { check_label_emit (); if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) { mvs_check_page (0, 2, 0); return \"LDR %0,%1\"; } if (REG_P (operands[1])) { mvs_check_page (0, 8, 0); return \"STM %1,%N1,140(13)\;LD %0,140(,13)\"; } if (operands[1] == const0_rtx) { CC_STATUS_SET (operands[0], operands[1]); mvs_check_page (0, 2, 0); return \"SDR %0,%0\"; } mvs_check_page (0, 4, 0); return \"LD %0,%1\"; } else if (REG_P (operands[0])) { if (FP_REG_P (operands[1])) { mvs_check_page (0, 12, 0); return \"STD %1,140(,13)\;LM %0,%N0,140(13)\"; } mvs_check_page (0, 4, 0); return \"LM %0,%N0,%1\"; } else if (FP_REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"STD %1,%0\"; } mvs_check_page (0, 4, 0); return \"STM %1,%N1,%0\"; }") ; ; movsf instruction pattern(s). ; (define_insn "" [(set (match_operand:SF 0 "r_or_s_operand" "=fm,fm,*dm") (match_operand:SF 1 "r_or_s_operand" "fmF,*dm,fmF"))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) { mvs_check_page (0, 2, 0); return \"LER %0,%1\"; } if (REG_P (operands[1])) { mvs_check_page (0, 8, 0); return \"ST %1,140(,13)\;LE %0,140(,13)\"; } if (operands[1] == const0_rtx) { CC_STATUS_SET (operands[0], operands[1]); mvs_check_page (0, 2, 0); return \"SER %0,%0\"; } mvs_check_page (0, 4, 0); return \"LE %0,%1\"; } else if (REG_P (operands[0])) { if (FP_REG_P (operands[1])) { mvs_check_page (0, 8, 0); return \"STE %1,140(,13)\;L %0,140(,13)\"; } mvs_check_page (0, 4, 0); return \"L %0,%1\"; } else if (FP_REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"STE %1,%0\"; } else if (REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"ST %1,%0\"; } mvs_check_page (0, 6, 0); return \"MVC %O0(4,%R0),%1\"; }") (define_insn "movsf" [(set (match_operand:SF 0 "general_operand" "=f,fm,m,*d") (match_operand:SF 1 "general_operand" "fmF,*d,f,fmF"))] "" "* { check_label_emit (); if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) { mvs_check_page (0, 2, 0); return \"LER %0,%1\"; } if (REG_P (operands[1])) { mvs_check_page (0, 8, 0); return \"ST %1,140(,13)\;LE %0,140(,13)\"; } if (operands[1] == const0_rtx) { CC_STATUS_SET (operands[0], operands[1]); mvs_check_page (0, 2, 0); return \"SER %0,%0\"; } mvs_check_page (0, 4, 0); return \"LE %0,%1\"; } else if (REG_P (operands[0])) { if (FP_REG_P (operands[1])) { mvs_check_page (0, 8, 0); return \"STE %1,140(,13)\;L %0,140(,13)\"; } mvs_check_page (0, 4, 0); return \"L %0,%1\"; } else if (FP_REG_P (operands[1])) { mvs_check_page (0, 4, 0); return \"STE %1,%0\"; } mvs_check_page (0, 4, 0); return \"ST %1,%0\"; }") ; ; movstrsi instruction pattern(s). ; (define_expand "movstrsi" [(set (match_operand:BLK 0 "general_operand" "") (match_operand:BLK 1 "general_operand" "")) (use (match_operand:SI 2 "general_operand" "")) (match_operand 3 "" "")] "" " { rtx op0, op1; op0 = XEXP (operands[0], 0); if (GET_CODE (op0) == REG || (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 0)) == REG && GET_CODE (XEXP (op0, 1)) == CONST_INT && (unsigned) INTVAL (XEXP (op0, 1)) < 4096)) { op0 = operands[0]; } else { op0 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op0)); } op1 = XEXP (operands[1], 0); if (GET_CODE (op1) == REG || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1, 0)) == REG && GET_CODE (XEXP (op1, 1)) == CONST_INT && (unsigned) INTVAL (XEXP (op1, 1)) < 4096)) { op1 = operands[1]; } else { op1 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op1)); } if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 256) { emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, gen_rtx (SET, VOIDmode, op0, op1), gen_rtx (USE, VOIDmode, operands[2])))); } else { rtx reg1 = gen_reg_rtx (DImode); rtx reg2 = gen_reg_rtx (DImode); rtx subreg = gen_rtx (SUBREG, SImode, reg1, 1); emit_insn (gen_rtx (SET, VOIDmode, subreg, operands[2])); emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, reg2, 1), subreg)); emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5, gen_rtx (SET, VOIDmode, op0, op1), gen_rtx (USE, VOIDmode, reg1), gen_rtx (USE, VOIDmode, reg2), gen_rtx (CLOBBER, VOIDmode, reg1), gen_rtx (CLOBBER, VOIDmode, reg2)))); } DONE; }") ; Move a block that is less than 256 bytes in length. (define_insn "" [(set (match_operand:BLK 0 "s_operand" "=m") (match_operand:BLK 1 "s_operand" "m")) (use (match_operand 2 "immediate_operand" "I"))] "((unsigned) INTVAL (operands[2]) < 256)" "* { check_label_emit (); mvs_check_page (0, 6, 0); return \"MVC %O0(%c2,%R0),%1\"; }") ; Move a block that is larger than 255 bytes in length. (define_insn "" [(set (match_operand:BLK 0 "general_operand" "=m") (match_operand:BLK 1 "general_operand" "m")) (use (match_operand:DI 2 "register_operand" "d")) (use (match_operand:DI 3 "register_operand" "d")) (clobber (match_dup 2)) (clobber (match_dup 3))] "" "* { check_label_emit (); mvs_check_page (0, 10, 0); return \"LA %2,%0\;LA %3,%1\;MVCL %2,%3\"; }") ;; ;;- Conversion instructions. ;; ; ; extendsidi2 instruction pattern(s). ; (define_expand "extendsidi2" [(set (match_operand:DI 0 "general_operand" "") (sign_extend:DI (match_operand:SI 1 "general_operand" "")))] "" " { if (GET_CODE (operands[1]) != CONST_INT) { emit_insn (gen_rtx (SET, VOIDmode, operand_subword (operands[0], 0, 1, DImode), operands[1])); emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (ASHIFTRT, DImode, operands[0], gen_rtx (CONST_INT, SImode, 32)))); } else { if (INTVAL (operands[1]) < 0) { emit_insn (gen_rtx (SET, VOIDmode, operand_subword (operands[0], 0, 1, DImode), gen_rtx (CONST_INT, SImode, -1))); } else { emit_insn (gen_rtx (SET, VOIDmode, operand_subword (operands[0], 0, 1, DImode), gen_rtx (CONST_INT, SImode, 0))); } emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (SImode, operands[0]), operands[1])); } DONE; }") ; ; extendhisi2 instruction pattern(s). ; (define_insn "extendhisi2" [(set (match_operand:SI 0 "general_operand" "=d,m") (sign_extend:SI (match_operand:HI 1 "general_operand" "g,d")))] "" "* { check_label_emit (); if (REG_P (operands[0])) { if (REG_P (operands[1])) if (REGNO (operands[0]) != REGNO (operands[1])) { mvs_check_page (0, 2, 0); return \"LR %0,%1\;SLL %0,16\;SRA %0,16\"; } else return \"\"; /* Should be empty. 16-bits regs are always 32-bits. */ if (operands[1] == const0_rtx) { CC_STATUS_INIT; mvs_check_page (0, 2, 0); return \"SLR %0,%0\"; } if (GET_CODE (operands[1]) == CONST_INT && (unsigned) INTVAL (operands[1]) < 4096) { mvs_check_page (0, 4, 0); return \"LA %0,%c1\"; } if (GET_CODE (operands[1]) == CONST_INT) { mvs_check_page (0, 4, 2); return \"LH %0,=H'%h1'\"; } mvs_check_page (0, 4, 0); return \"LH %0,%1\"; } mvs_check_page (0, 4, 0); return \"SLL %0,16\;SRA %0,16\;ST %1,%0\"; }") ; ; extendqisi2 instruction pattern(s). ; (define_insn "extendqisi2" [(set (match_operand:SI 0 "general_operand" "=d") (sign_extend:SI (match_operand:QI 1 "general_operand" "0mi")))] "" "* { check_label_emit (); CC_STATUS_SET (operands[0], operands[1]); if (REG_P (operands[1])) { mvs_check_page (0, 8, 0); return \"SLL %0,24\;SRA %0,24\"; } if (s_operand (operands[1])) { mvs_check_page (0, 8, 0); return \"ICM %0,8,%1\;SRA %0,24\"; } mvs_check_page (0, 12, 0); return \"IC %0,%1\;SLL %0,24\;SRA %0,24\"; }") ; ; extendqihi2 instruction pattern(s). ; (define_insn "extendqihi2" [(set (match_operand:HI 0 "general_operand" "=d") (sign_extend:HI (match_operand:QI 1 "general_operand" "0m")))] "" "* { check_label_emit (); CC_STATUS_SET (operands[0], operands[1]); if (REG_P (operands[1])) { mvs_check_page (0, 8, 0); return \"SLL %0,24\;SRA %0,24\"; } if (s_operand (operands[1])) { mvs_check_page (0, 8, 0); return \"ICM %0,8,%1\;SRA %0,24\"; } mvs_check_page (0, 12, 0); return \"IC %0,%1\;SLL %0,24\;SRA %0,24\"; }") ; ; zero_extendsidi2 instruction pattern(s). ; (define_expand "zero_extendsidi2" [(set (match_operand:DI 0 "general_operand" "") (zero_extend:DI (match_operand:SI 1 "general_operand" "")))] "" " { emit_insn (gen_rtx (SET, VOIDmode, operand_subword (operands[0], 0, 1, DImode), operands[1])); emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (LSHIFTRT, DImode, operands[0], gen_rtx (CONST_INT, SImode, 32)))); DONE; }") ; ; zero_extendhisi2 instruction pattern(s). ; (define_insn "zero_extendhisi2" [(set (match_operand:SI 0 "general_operand" "=d") (zero_extend:SI (match_operand:HI 1 "general_operand" "0")))] "" "* { check_label_emit (); CC_STATUS_SET (operands[0], operands[1]); mvs_check_page (0, 4, 4); return \"N %1,=X'0000FFFF'\"; }") ; ; zero_extendqisi2 instruction pattern(s). ; (define_insn "zero_extendqisi2" [(set (match_operand:SI 0 "general_operand" "=d,&d") (zero_extend:SI (match_operand:QI 1 "general_operand" "0i,m")))] "" "* { check_label_emit (); if (REG_P (operands[1])) { CC_STATUS_SET (operands[0], operands[1]); mvs_check_page (0, 4, 4); return \"N %0,=X'000000FF'\"; } if (GET_CODE (operands[1]) == CONST_INT) { mvs_check_page (0, 4, 0); return \"LA %0,%c1\"; } CC_STATUS_INIT; mvs_check_page (0, 8, 0); return \"SLR %0,%0\;IC %0,%1\"; }") ; ; zero_extendqihi2 instruction pattern(s). ; (define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "general_operand" "=d,&d") (zero_extend:HI (match_operand:QI 1 "general_operand" "0i,m")))] "" "* { check_label_emit (); if (REG_P (operands[1])) { CC_STATUS_SET (operands[0], operands[1]); mvs_check_page (0, 4, 4); return \"N %0,=X'000000FF'\"; } if (GET_CODE (operands[1]) == CONST_INT) { mvs_check_page (0, 4, 0); return \"LA %0,%c1\"; } CC_STATUS_INIT; mvs_check_page (0, 8, 0); return \"SLR %0,%0\;IC %0,%1\"; }") ; ; truncsihi2 instruction pattern(s). ; (define_insn "truncsihi2" [(set (match_operand:HI 0 "general_operand" "=d,m") (truncate:HI (match_operand:SI 1 "general_operand" "0,d")))] "" "* { check_label_emit (); if (REG_P (operands[0])) { CC_STATUS_SET (operands[0], operands[1]); mvs_check_page (0, 8, 0); return \"SLL %0,16\;SRA %0,16\"; } mvs_check_page (0, 4, 0); return \"STH %1,%0\"; }") ; ; fix_truncdfsi2 instruction pattern(s). ; (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "general_operand" "=d") (fix:SI (truncate:DF (match_operand:DF 1 "general_operand" "f")))) (clobber (reg:DF 16))] "" "* { check_label_emit (); CC_STATUS_INIT; if (REGNO (operands[1]) == 16) { mvs_check_page (0, 12, 8); return \"AD 0,=XL8'4F08000000000000'\;STD 0,140(,13)\;L %0,144(,13)\"; } mvs_check_page (0, 14, 8); return \"LDR 0,%1\;AD 0,=XL8'4F08000000000000'\;STD 0,140(,13)\;L %0,144(,13)\"; }") ; ; floatsidf2 instruction pattern(s). ; ; Uses the float field of the TCA. ; (define_insn "floatsidf2" [(set (match_operand:DF 0 "general_operand" "=f") (float:DF (match_operand:SI 1 "general_operand" "d")))] "" "* { check_label_emit (); CC_STATUS_INIT; mvs_check_page (0, 16, 8); return \"ST %1,508(,12)\;XI 508(12),128\;LD %0,504(,12)\;SD %0,=XL8'4E00000080000000'\"; }") ; ; truncdfsf2 instruction pattern(s). ; (define_insn "truncdfsf2" [(set (match_operand:SF 0 "general_operand" "=f") (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] "" "* { check_label_emit (); mvs_check_page (0, 2, 0); return \"LRER %0,%1\"; }") ; ; extendsfdf2 instruction pattern(s). ; (define_insn "extendsfdf2" [(set (match_operand:DF 0 "general_operand" "=f") (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))] "" "* { check_label_emit (); CC_STATUS_SET (0, const0_rtx); if (FP_REG_P (operands[1])) { if (REGNO (operands[0]) == REGNO (operands[1])) { mvs_check_page (0, 10, 0); return \"STE %1,140(,13)\;SDR %0,%0\;LE %0,140(,13)\"; } mvs_check_page (0, 4, 0); return \"SDR %0,%0\;LER %0,%1\"; } mvs_check_page (0, 6, 0); return \"SDR %0,%0\;LE %0,%1\"; }") ;; ;;- Add instructions. ;; ; ; adddi3 instruction pattern(s). ; (define_expand "adddi3" [(set (match_operand:DI 0 "general_operand" "") (plus:DI (match_operand:DI 1 "general_operand" "") (match_operand:DI 2 "general_operand" "")))] "" " { rtx label = gen_label_rtx (); rtx op0_high = operand_subword (operands[0], 0, 1, DImode); rtx op0_low = gen_lowpart (SImode, operands[0]); emit_insn (gen_rtx (SET, VOIDmode, op0_high, gen_rtx (PLUS, SImode, operand_subword (operands[1], 0, 1, DImode), operand_subword (operands[2], 0, 1, DImode)))); emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, gen_rtx (SET, VOIDmode, op0_low, gen_rtx (PLUS, SImode, gen_lowpart (SImode, operands[1]), gen_lowpart (SImode, operands[2]))), gen_rtx (USE, VOIDmode, gen_rtx (LABEL_REF, VOIDmode, label))))); emit_insn (gen_rtx (SET, VOIDmode, op0_high, gen_rtx (PLUS, SImode, op0_high, gen_rtx (CONST_INT, SImode, 1)))); emit_label (label); DONE; }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d") (plus:SI (match_operand:SI 1 "general_operand" "%0") (match_operand:SI 2 "general_operand" "g"))) (use (label_ref (match_operand 3 "" "")))] "" "* { int onpage; check_label_emit (); onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[3])); if (REG_P (operands[2])) { if (!onpage) { mvs_check_page (0, 8, 4); return \"ALR %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; } if (mvs_check_page (0, 6, 0)) { mvs_check_page (0, 2, 4); return \"ALR %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; } return \"ALR %0,%2\;BC 12,%l3\"; } if (!onpage) { mvs_check_page (0, 10, 4); return \"AL %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; } if (mvs_check_page (0, 8 ,0)) { mvs_check_page (0, 2, 4); return \"AL %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; } return \"AL %0,%2\;BC 12,%l3\"; }") ; ; addsi3 instruction pattern(s). ; ; The following insn is used when it is known that operand one is an address, ; frame, stack or argument pointer, and operand two is a constant that is ; small enough to fit in the displacement field. ; Notice that we can't allow the frame pointer to used as a normal register ; because of this insn. ; (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (plus:SI (match_operand:SI 1 "general_operand" "%a") (match_operand:SI 2 "immediate_operand" "J")))] "((REGNO (operands[1]) == FRAME_POINTER_REGNUM || REGNO (operands[1]) == ARG_POINTER_REGNUM || REGNO (operands[1]) == STACK_POINTER_REGNUM) && (unsigned) INTVAL (operands[2]) < 4096)" "* { check_label_emit (); CC_STATUS_INIT; mvs_check_page (0, 4, 0); return \"LA %0,%c2(,%1)\"; }") ; This insn handles additions that are relative to the frame pointer. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (plus:SI (match_operand:SI 1 "register_operand" "%a") (match_operand:SI 2 "immediate_operand" "i")))] "REGNO (operands[1]) == FRAME_POINTER_REGNUM" "* { check_label_emit (); if ((unsigned) INTVAL (operands[2]) < 4096) { mvs_check_page (0, 4, 0); return \"LA %0,%c2(,%1)\"; } if (REGNO (operands[1]) == REGNO (operands[0])) { mvs_check_page (0, 4, 0); return \"A %0,%2\"; } mvs_check_page (0, 6, 0); return \"L %0,%2\;AR %0,%1\"; }") (define_insn "addsi3" [(set (match_operand:SI 0 "general_operand" "=d") (plus:SI (match_operand:SI 1 "general_operand" "%0") (match_operand:SI 2 "general_operand" "g")))] "" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"AR %0,%2\"; } if (GET_CODE (operands[2]) == CONST_INT) { if (INTVAL (operands[2]) == -1) { CC_STATUS_INIT; mvs_check_page (0, 2, 0); return \"BCTR %0,0\"; } } mvs_check_page (0, 4, 0); return \"A %0,%2\"; }") ; ; addhi3 instruction pattern(s). ; (define_insn "addhi3" [(set (match_operand:HI 0 "general_operand" "=d") (plus:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "dmi")))] "" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"STH %2,140(,13)\;AH %0,140(,13)\"; } if (GET_CODE (operands[2]) == CONST_INT) { if (INTVAL (operands[2]) == -1) { CC_STATUS_INIT; mvs_check_page (0, 2, 0); return \"BCTR %0,0\"; } mvs_check_page (0, 4, 2); return \"AH %0,=H'%h2'\"; } mvs_check_page (0, 4, 0); return \"AH %0,%2\"; }") ; ; addqi3 instruction pattern(s). ; (define_insn "addqi3" [(set (match_operand:QI 0 "general_operand" "=d") (plus:QI (match_operand:QI 1 "general_operand" "%a") (match_operand:QI 2 "general_operand" "ai")))] "" "* { check_label_emit (); CC_STATUS_INIT; mvs_check_page (0, 4, 0); if (REG_P (operands[2])) return \"LA %0,0(%1,%2)\"; return \"LA %0,%B2(,%1)\"; }") ; ; adddf3 instruction pattern(s). ; (define_insn "adddf3" [(set (match_operand:DF 0 "general_operand" "=f") (plus:DF (match_operand:DF 1 "general_operand" "%0") (match_operand:DF 2 "general_operand" "fmF")))] "" "* { check_label_emit (); if (FP_REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"ADR %0,%2\"; } mvs_check_page (0, 4, 0); return \"AD %0,%2\"; }") ; ; addsf3 instruction pattern(s). ; (define_insn "addsf3" [(set (match_operand:SF 0 "general_operand" "=f") (plus:SF (match_operand:SF 1 "general_operand" "%0") (match_operand:SF 2 "general_operand" "fmF")))] "" "* { check_label_emit (); if (FP_REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"AER %0,%2\"; } mvs_check_page (0, 4, 0); return \"AE %0,%2\"; }") ;; ;;- Subtract instructions. ;; ; ; subdi3 instruction pattern(s). ; (define_expand "subdi3" [(set (match_operand:DI 0 "general_operand" "") (minus:DI (match_operand:DI 1 "general_operand" "") (match_operand:DI 2 "general_operand" "")))] "" " { rtx label = gen_label_rtx (); rtx op0_high = operand_subword (operands[0], 0, 1, DImode); rtx op0_low = gen_lowpart (SImode, operands[0]); emit_insn (gen_rtx (SET, VOIDmode, op0_high, gen_rtx (MINUS, SImode, operand_subword (operands[1], 0, 1, DImode), operand_subword (operands[2], 0, 1, DImode)))); emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, gen_rtx (SET, VOIDmode, op0_low, gen_rtx (MINUS, SImode, gen_lowpart (SImode, operands[1]), gen_lowpart (SImode, operands[2]))), gen_rtx (USE, VOIDmode, gen_rtx (LABEL_REF, VOIDmode, label))))); emit_insn (gen_rtx (SET, VOIDmode, op0_high, gen_rtx (MINUS, SImode, op0_high, gen_rtx (CONST_INT, SImode, 1)))); emit_label (label); DONE; }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d") (minus:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "g"))) (use (label_ref (match_operand 3 "" "")))] "" "* { int onpage; check_label_emit (); CC_STATUS_INIT; onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[3])); if (REG_P (operands[2])) { if (!onpage) { mvs_check_page (0, 8, 4); return \"SLR %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; } if (mvs_check_page (0, 6, 0)) { mvs_check_page (0, 2, 4); return \"SLR %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; } return \"SLR %0,%2\;BC 12,%l3\"; } if (!onpage) { mvs_check_page (0, 10, 4); return \"SL %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; } if (mvs_check_page (0, 8, 0)) { mvs_check_page (0, 2, 4); return \"SL %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; } return \"SL %0,%2\;BC 12,%l3\"; }") ; ; subsi3 instruction pattern(s). ; (define_insn "subsi3" [(set (match_operand:SI 0 "general_operand" "=d") (minus:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "g")))] "" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"SR %0,%2\"; } if (operands[2] == const1_rtx) { CC_STATUS_INIT; mvs_check_page (0, 2, 0); return \"BCTR %0,0\"; } mvs_check_page (0, 4, 0); return \"S %0,%2\"; }") ; ; subhi3 instruction pattern(s). ; (define_insn "subhi3" [(set (match_operand:HI 0 "general_operand" "=d") (minus:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "g")))] "" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"STH %2,140(,13)\;SH %0,140(,13)\"; } if (operands[2] == const1_rtx) { CC_STATUS_INIT; mvs_check_page (0, 2, 0); return \"BCTR %0,0\"; } if (GET_CODE (operands[2]) == CONST_INT) { mvs_check_page (0, 4, 2); return \"SH %0,=H'%h2'\"; } mvs_check_page (0, 4, 0); return \"SH %0,%2\"; }") ; ; subqi3 instruction pattern(s). ; (define_expand "subqi3" [(set (match_operand:QI 0 "general_operand" "=d") (minus:QI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "general_operand" "di")))] "" " { if (REG_P (operands[2])) { emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (MINUS, QImode, operands[1], operands[2]))); } else { emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (PLUS, QImode, operands[1], negate_rtx (QImode, operands[2])))); } DONE; }") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=d") (minus:QI (match_operand:QI 1 "register_operand" "%0") (match_operand:QI 2 "register_operand" "d")))] "" "* { check_label_emit (); CC_STATUS_INIT; mvs_check_page (0, 2, 0); return \"SR %0,%2\"; }") ; ; subdf3 instruction pattern(s). ; (define_insn "subdf3" [(set (match_operand:DF 0 "general_operand" "=f") (minus:DF (match_operand:DF 1 "general_operand" "0") (match_operand:DF 2 "general_operand" "fmF")))] "" "* { check_label_emit (); if (FP_REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"SDR %0,%2\"; } mvs_check_page (0, 4, 0); return \"SD %0,%2\"; }") ; ; subsf3 instruction pattern(s). ; (define_insn "subsf3" [(set (match_operand:SF 0 "general_operand" "=f") (minus:SF (match_operand:SF 1 "general_operand" "0") (match_operand:SF 2 "general_operand" "fmF")))] "" "* { check_label_emit (); if (FP_REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"SER %0,%2\"; } mvs_check_page (0, 4, 0); return \"SE %0,%2\"; }") ;; ;;- Multiply instructions. ;; ; ; mulsi3 instruction pattern(s). ; (define_expand "mulsi3" [(set (match_operand:SI 0 "general_operand" "") (mult:SI (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" "")))] "" " { if (GET_CODE (operands[1]) == CONST_INT && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')) { emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (MULT, SImode, operands[2], operands[1]))); } else if (GET_CODE (operands[2]) == CONST_INT && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')) { emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (MULT, SImode, operands[1], operands[2]))); } else { rtx r = gen_reg_rtx (DImode); emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, r, 1), operands[1])); emit_insn (gen_rtx (SET, VOIDmode, r, gen_rtx (MULT, SImode, r, operands[2]))); emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (SUBREG, SImode, r, 1))); } DONE; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (mult:SI (match_operand:SI 1 "general_operand" "%0") (match_operand:SI 2 "immediate_operand" "K")))] "" "* { check_label_emit (); mvs_check_page (0, 4, 0); return \"MH %0,%2\"; }") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (mult:SI (match_operand:DI 1 "general_operand" "%0") (match_operand:SI 2 "general_operand" "g")))] "" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"MR %0,%2\"; } mvs_check_page (0, 4, 0); return \"M %0,%2\"; }") ; ; muldf3 instruction pattern(s). ; (define_insn "muldf3" [(set (match_operand:DF 0 "general_operand" "=f") (mult:DF (match_operand:DF 1 "general_operand" "%0") (match_operand:DF 2 "general_operand" "fmF")))] "" "* { check_label_emit (); if (FP_REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"MDR %0,%2\"; } mvs_check_page (0, 4, 0); return \"MD %0,%2\"; }") ; ; mulsf3 instruction pattern(s). ; (define_insn "mulsf3" [(set (match_operand:SF 0 "general_operand" "=f") (mult:SF (match_operand:SF 1 "general_operand" "%0") (match_operand:SF 2 "general_operand" "fmF")))] "" "* { check_label_emit (); if (FP_REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"MER %0,%2\"; } mvs_check_page (0, 4, 0); return \"ME %0,%2\"; }") ;; ;;- Divide instructions. ;; ; ; divsi3 instruction pattern(s). ; (define_expand "divsi3" [(set (match_operand:SI 0 "general_operand" "") (div:SI (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" "")))] "" " { rtx r = gen_reg_rtx (DImode); emit_insn (gen_extendsidi2 (r, operands[1])); emit_insn (gen_rtx (SET, VOIDmode, r, gen_rtx (DIV, SImode, r, operands[2]))); emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (SUBREG, SImode, r, 1))); DONE; }") ; ; udivsi3 instruction pattern(s). ; (define_expand "udivsi3" [(set (match_operand:SI 0 "general_operand" "") (udiv:SI (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" "")))] "" " { rtx dr = gen_reg_rtx (DImode); rtx dr_0 = gen_rtx (SUBREG, SImode, dr, 0); rtx dr_1 = gen_rtx (SUBREG, SImode, dr, 1); if (GET_CODE (operands[2]) == CONST_INT) { if (INTVAL (operands[2]) > 0) { emit_insn (gen_zero_extendsidi2 (dr, operands[1])); emit_insn (gen_rtx (SET, VOIDmode, dr, gen_rtx (DIV, SImode, dr, operands[2]))); } else { rtx label1 = gen_label_rtx (); emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1])); emit_insn (gen_rtx (SET, VOIDmode, dr_1, const0_rtx)); emit_insn (gen_cmpsi (dr_0, operands[2])); emit_jump_insn (gen_bltu (label1)); emit_insn (gen_rtx (SET, VOIDmode, dr_1, const1_rtx)); emit_label (label1); } } else { rtx label1 = gen_label_rtx (); rtx label2 = gen_label_rtx (); rtx label3 = gen_label_rtx (); rtx sr = gen_reg_rtx (SImode); emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1])); emit_insn (gen_rtx (SET, VOIDmode, sr, operands[2])); emit_insn (gen_rtx (SET, VOIDmode, dr_1, const0_rtx)); emit_insn (gen_cmpsi (sr, dr_0)); emit_jump_insn (gen_bgtu (label3)); emit_insn (gen_cmpsi (sr, const1_rtx)); emit_jump_insn (gen_blt (label2)); emit_jump_insn (gen_beq (label1)); emit_insn (gen_rtx (SET, VOIDmode, dr, gen_rtx (LSHIFTRT, DImode, dr, gen_rtx (CONST_INT, SImode, 32)))); emit_insn (gen_rtx (SET, VOIDmode, dr, gen_rtx (DIV, SImode, dr, sr))); emit_jump_insn (gen_jump (label3)); emit_label (label1); emit_insn (gen_rtx (SET, VOIDmode, dr_1, dr_0)); emit_jump_insn (gen_jump (label3)); emit_label (label2); emit_insn (gen_rtx (SET, VOIDmode, dr_1, const1_rtx)); emit_label (label3); } emit_insn (gen_rtx (SET, VOIDmode, operands[0], dr_1)); DONE; }") ; This is used by divsi3 & udivsi3. (define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (div:SI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "general_operand" "")))] "" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"DR %0,%2\"; } mvs_check_page (0, 4, 0); return \"D %0,%2\"; }") ; ; divdf3 instruction pattern(s). ; (define_insn "divdf3" [(set (match_operand:DF 0 "general_operand" "=f") (div:DF (match_operand:DF 1 "general_operand" "0") (match_operand:DF 2 "general_operand" "fmF")))] "" "* { check_label_emit (); if (FP_REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"DDR %0,%2\"; } mvs_check_page (0, 4, 0); return \"DD %0,%2\"; }") ; ; divsf3 instruction pattern(s). ; (define_insn "divsf3" [(set (match_operand:SF 0 "general_operand" "=f") (div:SF (match_operand:SF 1 "general_operand" "0") (match_operand:SF 2 "general_operand" "fmF")))] "" "* { check_label_emit (); if (FP_REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"DER %0,%2\"; } mvs_check_page (0, 4, 0); return \"DE %0,%2\"; }") ;; ;;- Modulo instructions. ;; ; ; modsi3 instruction pattern(s). ; (define_expand "modsi3" [(set (match_operand:SI 0 "general_operand" "") (mod:SI (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" "")))] "" " { rtx r = gen_reg_rtx (DImode); emit_insn (gen_extendsidi2 (r, operands[1])); emit_insn (gen_rtx (SET, VOIDmode, r, gen_rtx (MOD, SImode, r, operands[2]))); emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (SUBREG, SImode, r, 0))); DONE; }") ; ; umodsi3 instruction pattern(s). ; (define_expand "umodsi3" [(set (match_operand:SI 0 "general_operand" "") (umod:SI (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" "")))] "" " { rtx dr = gen_reg_rtx (DImode); rtx dr_0 = gen_rtx (SUBREG, SImode, dr, 0); rtx dr_1 = gen_rtx (SUBREG, SImode, dr, 1); emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1])); if (GET_CODE (operands[2]) == CONST_INT) { if (INTVAL (operands[2]) > 0) { emit_insn (gen_rtx (SET, VOIDmode, dr, gen_rtx (LSHIFTRT, DImode, dr, gen_rtx (CONST_INT, SImode, 32)))); emit_insn (gen_rtx (SET, VOIDmode, dr, gen_rtx (MOD, SImode, dr, operands[2]))); } else { rtx label1 = gen_label_rtx (); rtx sr = gen_reg_rtx (SImode); emit_insn (gen_rtx (SET, VOIDmode, sr, operands[2])); emit_insn (gen_cmpsi (dr_0, sr)); emit_jump_insn (gen_bltu (label1)); emit_insn (gen_rtx (SET, VOIDmode, sr, gen_rtx (ABS, SImode, sr))); emit_insn (gen_rtx (SET, VOIDmode, dr_0, gen_rtx (PLUS, SImode, dr_0, sr))); emit_label (label1); } } else { rtx label1 = gen_label_rtx (); rtx label2 = gen_label_rtx (); rtx label3 = gen_label_rtx (); rtx sr = gen_reg_rtx (SImode); emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1])); emit_insn (gen_rtx (SET, VOIDmode, sr, operands[2])); emit_insn (gen_cmpsi (sr, dr_0)); emit_jump_insn (gen_bgtu (label3)); emit_insn (gen_cmpsi (sr, const1_rtx)); emit_jump_insn (gen_blt (label2)); emit_jump_insn (gen_beq (label1)); emit_insn (gen_rtx (SET, VOIDmode, dr, gen_rtx (LSHIFTRT, DImode, dr, gen_rtx (CONST_INT, SImode, 32)))); emit_insn (gen_rtx (SET, VOIDmode, dr, gen_rtx (MOD, SImode, dr, sr))); emit_jump_insn (gen_jump (label3)); emit_label (label1); emit_insn (gen_rtx (SET, VOIDmode, dr_0, const0_rtx)); emit_jump_insn (gen_jump (label3)); emit_label (label2); emit_insn (gen_rtx (SET, VOIDmode, dr_0, gen_rtx (MINUS, SImode, dr_0, sr))); emit_label (label3); } emit_insn (gen_rtx (SET, VOIDmode, operands[0], dr_0)); DONE; }") ; This is used by modsi3 & umodsi3. (define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (mod:SI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "general_operand" "")))] "" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"DR %0,%2\"; } mvs_check_page (0, 4, 0); return \"D %0,%2\"; }") ;; ;;- And instructions. ;; ; ; anddi3 instruction pattern(s). ; ;(define_expand "anddi3" ; [(set (match_operand:DI 0 "general_operand" "") ; (and:DI (match_operand:DI 1 "general_operand" "") ; (match_operand:DI 2 "general_operand" "")))] ; "" ; " ;{ ; rtx gen_andsi3(); ; ; emit_insn (gen_andsi3 (operand_subword (operands[0], 0, 1, DImode), ; operand_subword (operands[1], 0, 1, DImode), ; operand_subword (operands[2], 0, 1, DImode))); ; emit_insn (gen_andsi3 (gen_lowpart (SImode, operands[0]), ; gen_lowpart (SImode, operands[1]), ; gen_lowpart (SImode, operands[2]))); ; DONE; ;}") ; ; andsi3 instruction pattern(s). ; (define_insn "" [(set (match_operand:SI 0 "r_or_s_operand" "=d,m") (and:SI (match_operand:SI 1 "r_or_s_operand" "%0,0") (match_operand:SI 2 "r_or_s_operand" "g,mi")))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"NR %0,%2\"; } if (REG_P (operands[0])) { mvs_check_page (0, 4, 0); return \"N %0,%2\"; } CC_STATUS_INIT; mvs_check_page (0, 6, 0); return \"NC %O0(4,%R0),%2\"; }") (define_insn "andsi3" [(set (match_operand:SI 0 "general_operand" "=d") (and:SI (match_operand:SI 1 "general_operand" "%0") (match_operand:SI 2 "general_operand" "g")))] "" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"NR %0,%2\"; } mvs_check_page (0, 4, 0); return \"N %0,%2\"; }") ; ; andhi3 instruction pattern(s). ; (define_insn "" [(set (match_operand:HI 0 "r_or_s_operand" "=d,m") (and:HI (match_operand:HI 1 "r_or_s_operand" "%0,0") (match_operand:HI 2 "r_or_s_operand" "di,mi")))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"NR %0,%2\"; } if (REG_P (operands[0])) { mvs_check_page (0, 4, 0); return \"N %0,%H2\"; } CC_STATUS_INIT; if (GET_CODE (operands[2]) == CONST_INT) { mvs_check_page (0, 6, 2); return \"NC %O0(2,%R0),=H'%h2'\"; } mvs_check_page (0, 6, 0); return \"NC %O0(2,%R0),%2\"; }") (define_insn "andhi3" [(set (match_operand:HI 0 "general_operand" "=d") (and:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "di")))] "" "* { check_label_emit (); if (GET_CODE (operands[2]) == CONST_INT) { mvs_check_page (0, 4, 0); return \"N %0,%H2\"; } mvs_check_page (0, 2, 0); return \"NR %0,%2\"; }") ; ; andqi3 instruction pattern(s). ; (define_insn "" [(set (match_operand:QI 0 "r_or_s_operand" "=d,m") (and:QI (match_operand:QI 1 "r_or_s_operand" "%0,0") (match_operand:QI 2 "r_or_s_operand" "di,mi")))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); CC_STATUS_INIT; if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"NR %0,%2\"; } if (REG_P (operands[0])) { mvs_check_page (0, 4, 0); return \"N %0,%2\"; } if (GET_CODE (operands[2]) == CONST_INT) { mvs_check_page (0, 4, 0); return \"NI %0,%B2\"; } mvs_check_page (0, 6, 0); return \"NC %O0(1,%R0),%2\"; }") (define_insn "andqi3" [(set (match_operand:QI 0 "general_operand" "=d") (and:QI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "general_operand" "di")))] "" "* { check_label_emit (); CC_STATUS_INIT; if (GET_CODE (operands[2]) == CONST_INT) { mvs_check_page (0, 4, 0); return \"N %0,%2\"; } mvs_check_page (0, 2, 0); return \"NR %0,%2\"; }") ;; ;;- Bit set (inclusive or) instructions. ;; ; ; iordi3 instruction pattern(s). ; ;(define_expand "iordi3" ; [(set (match_operand:DI 0 "general_operand" "") ; (ior:DI (match_operand:DI 1 "general_operand" "") ; (match_operand:DI 2 "general_operand" "")))] ; "" ; " ;{ ; rtx gen_iorsi3(); ; ; emit_insn (gen_iorsi3 (operand_subword (operands[0], 0, 1, DImode), ; operand_subword (operands[1], 0, 1, DImode), ; operand_subword (operands[2], 0, 1, DImode))); ; emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), ; gen_lowpart (SImode, operands[1]), ; gen_lowpart (SImode, operands[2]))); ; DONE; ;}") ; ; iorsi3 instruction pattern(s). ; (define_insn "" [(set (match_operand:SI 0 "r_or_s_operand" "=d,m") (ior:SI (match_operand:SI 1 "r_or_s_operand" "%0,0") (match_operand:SI 2 "r_or_s_operand" "g,mi")))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"OR %0,%2\"; } if (REG_P (operands[0])) { mvs_check_page (0, 4, 0); return \"O %0,%2\"; } CC_STATUS_INIT; mvs_check_page (0, 6, 0); return \"OC %O0(4,%R0),%2\"; }") (define_insn "iorsi3" [(set (match_operand:SI 0 "general_operand" "=d") (ior:SI (match_operand:SI 1 "general_operand" "%0") (match_operand:SI 2 "general_operand" "g")))] "" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"OR %0,%2\"; } mvs_check_page (0, 4, 0); return \"O %0,%2\"; }") ; ; iorhi3 instruction pattern(s). ; (define_insn "" [(set (match_operand:HI 0 "r_or_s_operand" "=d,m") (ior:HI (match_operand:HI 1 "r_or_s_operand" "%0,0") (match_operand:HI 2 "r_or_s_operand" "di,mi")))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"OR %0,%2\"; } if (REG_P (operands[0])) { mvs_check_page (0, 4, 0); return \"O %0,%H2\"; } CC_STATUS_INIT; if (GET_CODE (operands[2]) == CONST_INT) { mvs_check_page (0, 6, 2); return \"OC %O0(2,%R0),=H'%h2'\"; } mvs_check_page (0, 6, 0); return \"OC %O0(2,%R0),%2\"; }") (define_insn "iorhi3" [(set (match_operand:HI 0 "general_operand" "=d") (ior:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "di")))] "" "* { check_label_emit (); if (GET_CODE (operands[2]) == CONST_INT) { mvs_check_page (0, 4, 0); return \"O %0,%H2\"; } mvs_check_page (0, 2, 0); return \"OR %0,%2\"; }") ; ; iorqi3 instruction pattern(s). ; (define_insn "" [(set (match_operand:QI 0 "r_or_s_operand" "=d,m") (ior:QI (match_operand:QI 1 "r_or_s_operand" "%0,0") (match_operand:QI 2 "r_or_s_operand" "di,mi")))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); CC_STATUS_INIT; if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"OR %0,%2\"; } if (REG_P (operands[0])) { mvs_check_page (0, 4, 0); return \"O %0,%2\"; } CC_STATUS_INIT; if (GET_CODE (operands[2]) == CONST_INT) { mvs_check_page (0, 4, 0); return \"OI %0,%B2\"; } mvs_check_page (0, 6, 0); return \"OC %O0(1,%R0),%2\"; }") (define_insn "iorqi3" [(set (match_operand:QI 0 "general_operand" "=d") (ior:QI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "general_operand" "di")))] "" "* { check_label_emit (); CC_STATUS_INIT; if (GET_CODE (operands[2]) == CONST_INT) { mvs_check_page (0, 4, 0); return \"O %0,%2\"; } mvs_check_page (0, 2, 0); return \"OR %0,%2\"; }") ;; ;;- Xor instructions. ;; ; ; xordi3 instruction pattern(s). ; ;(define_expand "xordi3" ; [(set (match_operand:DI 0 "general_operand" "") ; (xor:DI (match_operand:DI 1 "general_operand" "") ; (match_operand:DI 2 "general_operand" "")))] ; "" ; " ;{ ; rtx gen_xorsi3(); ; ; emit_insn (gen_xorsi3 (operand_subword (operands[0], 0, 1, DImode), ; operand_subword (operands[1], 0, 1, DImode), ; operand_subword (operands[2], 0, 1, DImode))); ; emit_insn (gen_xorsi3 (gen_lowpart (SImode, operands[0]), ; gen_lowpart (SImode, operands[1]), ; gen_lowpart (SImode, operands[2]))); ; DONE; ;}") ; ; xorsi3 instruction pattern(s). ; (define_insn "" [(set (match_operand:SI 0 "r_or_s_operand" "=d,m") (xor:SI (match_operand:SI 1 "r_or_s_operand" "%0,0") (match_operand:SI 2 "r_or_s_operand" "g,mi")))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"XR %0,%2\"; } if (REG_P (operands[0])) { mvs_check_page (0, 4, 0); return \"X %0,%2\"; } CC_STATUS_INIT; mvs_check_page (0, 6, 0); return \"XC %O0(4,%R0),%2\"; }") (define_insn "xorsi3" [(set (match_operand:SI 0 "general_operand" "=d") (xor:SI (match_operand:SI 1 "general_operand" "%0") (match_operand:SI 2 "general_operand" "g")))] "" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"XR %0,%2\"; } mvs_check_page (0, 4, 0); return \"X %0,%2\"; }") ; ; xorhi3 instruction pattern(s). ; (define_insn "" [(set (match_operand:HI 0 "r_or_s_operand" "=d,m") (xor:HI (match_operand:HI 1 "r_or_s_operand" "%0,0") (match_operand:HI 2 "r_or_s_operand" "di,mi")))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"XR %0,%2\"; } if (REG_P (operands[0])) { mvs_check_page (0, 4, 0); return \"X %0,%H2\"; } CC_STATUS_INIT; if (GET_CODE (operands[2]) == CONST_INT) { mvs_check_page (0, 6, 2); return \"XC %O0(2,%R0),=H'%h2'\"; } mvs_check_page (0, 6, 0); return \"XC %O0(2,%R0),%2\"; }") (define_insn "xorhi3" [(set (match_operand:HI 0 "general_operand" "=d") (xor:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "di")))] "" "* { check_label_emit (); if (GET_CODE (operands[2]) == CONST_INT) { mvs_check_page (0, 4, 0); return \"X %0,%2\"; } mvs_check_page (0, 2, 0); return \"XR %0,%2\"; }") ; ; xorqi3 instruction pattern(s). ; (define_insn "" [(set (match_operand:QI 0 "r_or_s_operand" "=d,m") (xor:QI (match_operand:QI 1 "r_or_s_operand" "%0,0") (match_operand:QI 2 "r_or_s_operand" "di,mi")))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); CC_STATUS_INIT; if (REG_P (operands[2])) { mvs_check_page (0, 2, 0); return \"XR %0,%2\"; } if (REG_P (operands[0])) { mvs_check_page (0, 4, 0); return \"X %0,%2\"; } if (GET_CODE (operands[2]) == CONST_INT) { mvs_check_page (0, 4, 0); return \"XI %0,%B2\"; } mvs_check_page (0, 6, 0); return \"XC %O0(1,%R0),%2\"; }") (define_insn "xorqi3" [(set (match_operand:QI 0 "general_operand" "=d") (xor:QI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "general_operand" "di")))] "" "* { check_label_emit (); CC_STATUS_INIT; if (GET_CODE (operands[2]) == CONST_INT) { mvs_check_page (0, 4, 0); return \"X %0,%2\"; } mvs_check_page (0, 2, 0); return \"XR %0,%2\"; }") ;; ;;- Negate instructions. ;; ; ; negsi2 instruction pattern(s). ; (define_insn "negsi2" [(set (match_operand:SI 0 "general_operand" "=d") (neg:SI (match_operand:SI 1 "general_operand" "d")))] "" "* { check_label_emit (); mvs_check_page (0, 2, 0); return \"LCR %0,%1\"; }") ; ; neghi2 instruction pattern(s). ; (define_insn "neghi2" [(set (match_operand:HI 0 "general_operand" "=d") (neg:HI (match_operand:HI 1 "general_operand" "d")))] "" "* { check_label_emit (); mvs_check_page (0, 10, 0); return \"SLL %1,16\;SRA %1,16\;LCR %0,%1\"; }") ; ; negdf2 instruction pattern(s). ; (define_insn "negdf2" [(set (match_operand:DF 0 "general_operand" "=f") (neg:DF (match_operand:DF 1 "general_operand" "f")))] "" "* { check_label_emit (); mvs_check_page (0, 2, 0); return \"LCDR %0,%1\"; }") ; ; negsf2 instruction pattern(s). ; (define_insn "negsf2" [(set (match_operand:SF 0 "general_operand" "=f") (neg:SF (match_operand:SF 1 "general_operand" "f")))] "" "* { check_label_emit (); mvs_check_page (0, 2, 0); return \"LCER %0,%1\"; }") ;; ;;- Absolute value instructions. ;; ; ; abssi2 instruction pattern(s). ; (define_insn "abssi2" [(set (match_operand:SI 0 "general_operand" "=d") (abs:SI (match_operand:SI 1 "general_operand" "d")))] "" "* { check_label_emit (); mvs_check_page (0, 2, 0); return \"LPR %0,%1\"; }") ; ; abshi2 instruction pattern(s). ; (define_insn "abshi2" [(set (match_operand:HI 0 "general_operand" "=d") (abs:HI (match_operand:HI 1 "general_operand" "d")))] "" "* { check_label_emit (); mvs_check_page (0, 10, 0); return \"SLL %1,16\;SRA %1,16\;LPR %0,%1\"; }") ; ; absdf2 instruction pattern(s). ; (define_insn "absdf2" [(set (match_operand:DF 0 "general_operand" "=f") (abs:DF (match_operand:DF 1 "general_operand" "f")))] "" "* { check_label_emit (); mvs_check_page (0, 2, 0); return \"LPDR %0,%1\"; }") ; ; abssf2 instruction pattern(s). ; (define_insn "abssf2" [(set (match_operand:SF 0 "general_operand" "=f") (abs:SF (match_operand:SF 1 "general_operand" "f")))] "" "* { check_label_emit (); mvs_check_page (0, 2, 0); return \"LPER %0,%1\"; }") ;; ;;- One complement instructions. ;; ; ; one_cmpldi2 instruction pattern(s). ; ;(define_expand "one_cmpldi2" ; [(set (match_operand:DI 0 "general_operand" "") ; (not:DI (match_operand:DI 1 "general_operand" "")))] ; "" ; " ;{ ; rtx gen_one_cmplsi2(); ; ; emit_insn (gen_one_cmplsi2 (operand_subword (operands[0], 0, 1, DImode), ; operand_subword (operands[1], 0, 1, DImode))); ; emit_insn (gen_one_cmplsi2 (gen_lowpart (SImode, operands[0]), ; gen_lowpart (SImode, operands[1]))); ; DONE; ;}") ; ; one_cmplsi2 instruction pattern(s). ; (define_insn "" [(set (match_operand:SI 0 "r_or_s_operand" "=dm") (not:SI (match_operand:SI 1 "r_or_s_operand" "0")))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); if (REG_P (operands[0])) { mvs_check_page (0, 4, 4); return \"X %0,=F'-1'\"; } CC_STATUS_INIT; mvs_check_page (0, 6, 4); return \"XC %O0(4,%R0),=F'-1'\"; }") (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "general_operand" "=d") (not:SI (match_operand:SI 1 "general_operand" "0")))] "" "* { check_label_emit (); mvs_check_page (0, 4, 4); return \"X %0,=F'-1'\"; }") ; ; one_cmplhi2 instruction pattern(s). ; (define_insn "" [(set (match_operand:HI 0 "r_or_s_operand" "=dm") (not:HI (match_operand:HI 1 "r_or_s_operand" "0")))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); if (REG_P (operands[0])) { mvs_check_page (0, 4, 4); return \"X %0,=F'-1'\"; } CC_STATUS_INIT; mvs_check_page (0, 6, 4); return \"XC %O0(2,%R0),=X'FFFF'\"; }") (define_insn "one_cmplhi2" [(set (match_operand:HI 0 "general_operand" "=d") (not:HI (match_operand:HI 1 "general_operand" "0")))] "" "* { check_label_emit (); mvs_check_page (0, 4, 4); return \"X %0,=F'-1'\"; }") ; ; one_cmplqi2 instruction pattern(s). ; (define_insn "" [(set (match_operand:QI 0 "r_or_s_operand" "=dm") (not:QI (match_operand:QI 1 "r_or_s_operand" "0")))] "TARGET_CHAR_INSTRUCTIONS" "* { check_label_emit (); CC_STATUS_INIT; if (REG_P (operands[0])) { mvs_check_page (0, 4, 4); return \"X %0,=F'-1'\"; } mvs_check_page (0, 4, 0); return \"XI %0,255\"; }") (define_insn "one_cmplqi2" [(set (match_operand:QI 0 "general_operand" "=d") (not:QI (match_operand:QI 1 "general_operand" "0")))] "" "* { check_label_emit (); CC_STATUS_INIT; mvs_check_page (0, 4, 4); return \"X %0,=F'-1'\"; }") ;; ;;- Arithmetic shift instructions. ;; ; ; ashldi3 instruction pattern(s). ; (define_insn "ashldi3" [(set (match_operand:DI 0 "general_operand" "=d") (ashift:DI (match_operand:DI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); CC_STATUS_INIT; mvs_check_page (0, 4, 0); if (REG_P (operands[2])) return \"SLDA %0,0(%2)\"; return \"SLDA %0,%c2\"; }") ; ; ashrdi3 instruction pattern(s). ; (define_insn "ashrdi3" [(set (match_operand:DI 0 "register_operand" "=d") (ashiftrt:DI (match_operand:DI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); mvs_check_page (0, 4, 0); if (REG_P (operands[2])) return \"SRDA %0,0(%2)\"; return \"SRDA %0,%c2\"; }") ; ; ashlsi3 instruction pattern(s). ; (define_insn "ashlsi3" [(set (match_operand:SI 0 "general_operand" "=d") (ashift:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); CC_STATUS_INIT; mvs_check_page (0, 4, 0); if (REG_P (operands[2])) return \"SLL %0,0(%2)\"; return \"SLL %0,%c2\"; }") ; ; ashrsi3 instruction pattern(s). ; (define_insn "ashrsi3" [(set (match_operand:SI 0 "general_operand" "=d") (ashiftrt:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); mvs_check_page (0, 4, 0); if (REG_P (operands[2])) return \"SRA %0,0(%2)\"; return \"SRA %0,%c2\"; }") ; ; ashlhi3 instruction pattern(s). ; (define_insn "ashlhi3" [(set (match_operand:HI 0 "general_operand" "=d") (ashift:HI (match_operand:HI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); mvs_check_page (0, 8, 0); if (REG_P (operands[2])) return \"SLL %0,16(%2)\;SRA %0,16\"; return \"SLL %0,16+%c2\;SRA %0,16\"; }") ; ; ashrhi3 instruction pattern(s). ; (define_insn "ashrhi3" [(set (match_operand:HI 0 "general_operand" "=d") (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); mvs_check_page (0, 4, 0); if (REG_P (operands[2])) return \"SLL %0,16\;SRA %0,16(%2)\"; return \"SLL %0,16\;SRA %0,16+%c2\"; }") ; ; ashlqi3 instruction pattern(s). ; (define_insn "ashlqi3" [(set (match_operand:QI 0 "general_operand" "=d") (ashift:QI (match_operand:QI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); CC_STATUS_INIT; mvs_check_page (0, 4, 0); if (REG_P (operands[2])) return \"SLL %0,0(%2)\"; return \"SLL %0,%c2\"; }") ; ; ashrqi3 instruction pattern(s). ; (define_insn "ashrqi3" [(set (match_operand:QI 0 "general_operand" "=d") (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); mvs_check_page (0, 8, 0); if (REG_P (operands[2])) return \"SLL %0,24\;SRA %0,24(%2)\"; return \"SLL %0,24\;SRA %0,24+%c2\"; }") ;; ;;- Logical shift instructions. ;; ; ; lshldi3 instruction pattern(s). ; (define_insn "lshldi3" [(set (match_operand:DI 0 "general_operand" "=d") (lshift:DI (match_operand:DI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); mvs_check_page (0, 4, 0); if (REG_P (operands[2])) return \"SLDL %0,0(%2)\"; return \"SLDL %0,%c2\"; }") ; ; lshrdi3 instruction pattern(s). ; (define_insn "lshrdi3" [(set (match_operand:DI 0 "general_operand" "=d") (lshiftrt:DI (match_operand:DI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); mvs_check_page (0, 4, 0); if (REG_P (operands[2])) return \"SRDL %0,0(%2)\"; return \"SRDL %0,%c2\"; }") ; ; lshlsi3 instruction pattern(s). ; (define_insn "lshlsi3" [(set (match_operand:SI 0 "general_operand" "=d") (lshift:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); mvs_check_page (0, 4, 0); if (REG_P (operands[2])) return \"SLL %0,0(%2)\"; return \"SLL %0,%c2\"; }") ; ; lshrsi3 instruction pattern(s). ; (define_insn "lshrsi3" [(set (match_operand:SI 0 "general_operand" "=d") (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); mvs_check_page (0, 4, 0); if (REG_P (operands[2])) return \"SRL %0,0(%2)\"; return \"SRL %0,%c2\"; }") ; ; lshlhi3 instruction pattern(s). ; (define_insn "lshlhi3" [(set (match_operand:HI 0 "general_operand" "=d") (lshift:HI (match_operand:HI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); CC_STATUS_INIT; mvs_check_page (0, 4, 0); if (REG_P (operands[2])) return \"SLL %0,0(%2)\"; return \"SLL %0,%c2\"; }") ; ; lshrhi3 instruction pattern(s). ; (define_insn "lshrhi3" [(set (match_operand:HI 0 "general_operand" "=d") (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); CC_STATUS_INIT; if (REG_P (operands[2])) { mvs_check_page (0, 8, 4); return \"N %0,=X'0000FFFF'\;SRL %0,0(%2)\"; } mvs_check_page (0, 8, 4); return \"N %0,=X'0000FFFF'\;SRL %0,%c2\"; }") ; ; lshlqi3 instruction pattern(s). ; (define_insn "lshlqi3" [(set (match_operand:QI 0 "general_operand" "=d") (lshift:QI (match_operand:QI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); mvs_check_page (0, 4, 0); if (REG_P (operands[2])) return \"SLL %0,0(%2)\"; return \"SLL %0,%c2\"; }") ; ; lshrqi3 instruction pattern(s). ; (define_insn "lshrqi3" [(set (match_operand:QI 0 "general_operand" "=d") (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "Ja")))] "" "* { check_label_emit (); CC_STATUS_INIT; mvs_check_page (0, 8, 4); if (REG_P (operands[2])) return \"N %0,=X'000000FF'\;SRL %0,0(%2)\"; return \"N %0,=X'000000FF'\;SRL %0,%c2\"; }") ;; ;;- Conditional jump instructions. ;; ; ; beq instruction pattern(s). ; (define_insn "beq" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BER 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BER 14\"; } return \"BE %l0\"; }") ; ; bne instruction pattern(s). ; (define_insn "bne" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BNER 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BNER 14\"; } return \"BNE %l0\"; }") ; ; bgt instruction pattern(s). ; (define_insn "bgt" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BHR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BHR 14\"; } return \"BH %l0\"; }") ; ; bgtu instruction pattern(s). ; (define_insn "bgtu" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BHR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BHR 14\"; } return \"BH %l0\"; }") ; ; blt instruction pattern(s). ; (define_insn "blt" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BLR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BLR 14\"; } return \"BL %l0\"; }") ; ; bltu instruction pattern(s). ; (define_insn "bltu" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BLR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BLR 14\"; } return \"BL %l0\"; }") ; ; bge instruction pattern(s). ; (define_insn "bge" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BNLR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BNLR 14\"; } return \"BNL %l0\"; }") ; ; bgeu instruction pattern(s). ; (define_insn "bgeu" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BNLR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BNLR 14\"; } return \"BNL %l0\"; }") ; ; ble instruction pattern(s). ; (define_insn "ble" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BNHR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BNHR 14\"; } return \"BNH %l0\"; }") ; ; bleu instruction pattern(s). ; (define_insn "bleu" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BNHR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BNHR 14\"; } return \"BNH %l0\"; }") ;; ;;- Negated conditional jump instructions. ;; (define_insn "" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BNER 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BNER 14\"; } return \"BNE %l0\"; }") (define_insn "" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BER 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BER 14\"; } return \"BE %l0\"; }") (define_insn "" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BNHR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BNHR 14\"; } return \"BNH %l0\"; }") (define_insn "" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BNHR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BNHR 14\"; } return \"BNH %l0\"; }") (define_insn "" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BNLR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BNLR 14\"; } return \"BNL %l0\"; }") (define_insn "" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BNLR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BNLR 14\"; } return \"BNL %l0\"; }") (define_insn "" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BLR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BLR 14\"; } return \"BL %l0\"; }") (define_insn "" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BLR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BLR 14\"; } return \"BL %l0\"; }") (define_insn "" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BHR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BHR 14\"; } return \"BH %l0\"; }") (define_insn "" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BHR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BHR 14\"; } return \"BH %l0\"; }") ;; ;;- Subtract one and jump if not zero. ;; (define_insn "" [(set (pc) (if_then_else (ne (plus:SI (match_operand:SI 0 "register_operand" "+d") (const_int -1)) (const_int 0)) (label_ref (match_operand 1 "" "")) (pc))) (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[1]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l1)\;BCTR %0,14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l1)\;BCTR %0,14\"; } return \"BCT %0,%l1\"; }") (define_insn "" [(set (pc) (if_then_else (eq (plus:SI (match_operand:SI 0 "register_operand" "+d") (const_int -1)) (const_int 0)) (pc) (label_ref (match_operand 1 "" "")))) (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[1]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l1)\;BCTR %0,14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l1)\;BCTR %0,14\"; } return \"BCT %0,%l1\"; }") ;; ;;- Unconditional jump instructions. ;; ; ; jump instruction pattern(s). ; (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "* { check_label_emit (); if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) { mvs_check_page (0, 6, 4); return \"L 14,=A(%l0)\;BR 14\"; } if (mvs_check_page (0, 4, 0)) { mvs_check_page (0, 2, 4); return \"L 14,=A(%l0)\;BR 14\"; } return \"B %l0\"; }") ; ; indirect-jump instruction pattern(s). ; (define_insn "indirect_jump" [(set (pc) (match_operand:SI 0 "general_operand" "r"))] "(GET_CODE (operands[0]) != MEM )" "* { check_label_emit (); mvs_check_page (0, 2, 0); return \"BR %0\"; }") ; ; tablejump instruction pattern(s). ; (define_insn "tablejump" [(set (pc) (match_operand:SI 0 "general_operand" "am")) (use (label_ref (match_operand 1 "" "")))] "" "* { check_label_emit (); if (REG_P (operands[0])) { mvs_check_page (0, 6, 0); return \"BR %0\;DS 0F\"; } mvs_check_page (0, 10, 0); return \"L 14,%0\;BR 14\;DS 0F\"; }") ;; ;;- Jump to subroutine. ;; ;; For the C/370 environment the internal functions, ie. sqrt, are called with ;; a non-standard form. So, we must fix it here. There's no BM like IBM. ;; ; ; call instruction pattern(s). ; (define_insn "call" [(call (match_operand:QI 0 "memory_operand" "m") (match_operand:SI 1 "immediate_operand" "i"))] "" "* { static char temp[128]; int i = STACK_POINTER_OFFSET; check_label_emit (); if (mvs_function_check (XSTR (operands[0], 0))) { mvs_check_page (0, 22, 4); sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\;LD 0,136(,13)\", i - 4, i - 4 ); } else { mvs_check_page (0, 10, 4); sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\", i ); } return temp; }") ; ; call_value instruction pattern(s). ; (define_insn "call_value" [(set (match_operand 0 "" "rf") (call (match_operand:QI 1 "memory_operand" "m") (match_operand:SI 2 "general_operand" "i")))] "" "* { static char temp[128]; int i = STACK_POINTER_OFFSET; check_label_emit (); if (mvs_function_check (XSTR (operands[1], 0))) { mvs_check_page (0, 22, 4); sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\;LD 0,136(,13)\", i - 4, i - 4 ); } else { mvs_check_page (0, 10, 4); sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\", i ); } return temp; }") (define_insn "" [(call (mem:QI (match_operand:SI 0 "" "i")) (match_operand:SI 1 "general_operand" "g"))] "GET_CODE (operands[0]) == SYMBOL_REF" "* { static char temp[128]; int i = STACK_POINTER_OFFSET; check_label_emit (); if (mvs_function_check (XSTR (operands[0], 0))) { mvs_check_page (0, 22, 4); sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\;LD 0,136(,13)\", i - 4, i - 4 ); } else { mvs_check_page (0, 10, 4); sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\", i ); } return temp; }") (define_insn "" [(set (match_operand 0 "" "rf") (call (mem:QI (match_operand:SI 1 "" "i")) (match_operand:SI 2 "general_operand" "g")))] "GET_CODE (operands[1]) == SYMBOL_REF" "* { static char temp[128]; int i = STACK_POINTER_OFFSET; check_label_emit (); if (mvs_function_check (XSTR (operands[1], 0))) { mvs_check_page (0, 22, 4); sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\;LD 0,136(,13)\", i - 4, i - 4 ); } else { mvs_check_page (0, 10, 4); sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\", i ); } return temp; }") ;; ;;- Miscellaneous instructions. ;; ; ; nop instruction pattern(s). ; (define_insn "nop" [(const_int 0)] "" "* { check_label_emit (); mvs_check_page (0, 2, 0); return \"LR 0,0\"; }") gcc-2.5.8/config/i370/mvs.h100444 22011 13 140207 5453625425 13746 0ustar kenneruser/* Definitions of target machine for GNU compiler. System/370 version. Copyright (C) 1989, 1993 Free Software Foundation, Inc. Contributed by Jan Stein (jan@cd.chalmers.se). Modified for C/370 MVS by Dave Pitts (pitts@mcdata.com) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifdef sun #include #include #endif #include #define TARGET_VERSION printf (" (370/MVS)"); /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-DGCC -Dgcc -DMVS -Dmvs -Asystem(mvs) -Acpu(i370) -Amachine(i370)" /* Run-time compilation parameters selecting different hardware subsets. */ extern int target_flags; /* The sizes of the code and literals on the current page. */ extern int mvs_page_code, mvs_page_lit; /* The current page number and the base page number for the function. */ extern int mvs_page_num, function_base_page; /* True if a label has been emitted. */ extern int mvs_label_emited; /* The name of the current function. */ extern char *mvs_function_name; /* The length of the function name malloc'd area. */ extern int mvs_function_name_length; /* The amount of space used for outgoing arguments. */ extern int current_function_outgoing_args_size; /* Compile using char instructins (mvc, nc, oc, xc). On 4341 use this since these are more than twice as fast as load-op-store. On 3090 don't use this since load-op-store is much faster. */ #define TARGET_CHAR_INSTRUCTIONS (target_flags & 1) /* Default target switches */ #define TARGET_DEFAULT 1 /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */ #define TARGET_SWITCHES \ { { "char-instructions", 1}, \ { "no-char-instructions", -1}, \ { "", TARGET_DEFAULT} } /* Target machine storage layout */ /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. */ #define BITS_BIG_ENDIAN 1 /* Define this if most significant byte of a word is the lowest numbered. */ #define BYTES_BIG_ENDIAN 1 /* Define this if MS word of a multiword is the lowest numbered. */ #define WORDS_BIG_ENDIAN 1 /* Number of bits in an addressible storage unit. */ #define BITS_PER_UNIT 8 /* Width in bits of a "word", which is the contents of a machine register. */ #define BITS_PER_WORD 32 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 4 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ #define POINTER_SIZE 32 /* Allocation boundary (in *bits*) for storing pointers in memory. */ #define POINTER_BOUNDARY 32 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ #define PARM_BOUNDARY 32 /* Boundary (in *bits*) on which stack pointer should be aligned. */ #define STACK_BOUNDARY 32 /* Allocation boundary (in *bits*) for the code of a function. */ #define FUNCTION_BOUNDARY 32 /* There is no point aligning anything to a rounder boundary than this. */ #define BIGGEST_ALIGNMENT 64 /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 32 /* Define this if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 0 /* Define target floating point format. */ #define TARGET_FLOAT_FORMAT IBM_FLOAT_FORMAT /* Define character mapping for cross-compiling. */ #define TARGET_EBCDIC 1 #ifdef HOST_EBCDIC #define MAP_CHARACTER(c) ((char)(c)) #else #define MAP_CHARACTER(c) ((char)mvs_map_char (c)) #endif /* Define maximum length of page minus page escape overhead. */ #define MAX_MVS_PAGE_LENGTH 4080 /* Define if special allocation order desired. */ #define REG_ALLOC_ORDER \ { 0, 1, 2, 3, 14, 15, 12, 10, 9, 8, 7, 6, 5, 4, 16, 17, 18, 19, 11, 13 } /* Standard register usage. */ /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. For the 370, we give the data registers numbers 0-15, and the floating point registers numbers 16-19. */ #define FIRST_PSEUDO_REGISTER 20 /* Define base and page registers. */ #define BASE_REGISTER 3 #define PAGE_REGISTER 4 /* 1 for registers that have pervasive standard uses and are not available for the register allocator. On the 370 under C/370, R13 is stack (DSA) pointer, R12 is the TCA pointer, R3 is the base register, R4 is the page origin table pointer and R11 is the arg pointer. */ #define FIXED_REGISTERS \ { 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0 } /*0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19*/ /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. NOTE: all floating registers are undefined across calls. */ #define CALL_USED_REGISTERS \ { 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 } /*0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19*/ /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ ((REGNO) > 15 ? 1 : (GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1) / UNITS_PER_WORD) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On the 370, the cpu registers can hold QI, HI, SI, SF and DF. The even registers can hold DI. The floating point registers can hold either SF or DF. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ((REGNO) < 16 ? ((REGNO) & 1) == 0 || (MODE) != DImode \ : (MODE) == SFmode || (MODE) == DFmode) /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. */ #define MODES_TIEABLE_P(MODE1, MODE2) \ (((MODE1) == SFmode || (MODE1) == DFmode) \ == ((MODE2) == SFmode || (MODE2) == DFmode)) /* Mark external references. */ #define ENCODE_SECTION_INFO(decl) \ if (DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)) \ SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1; /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ /* 370 PC isn't overloaded on a register. */ /* #define PC_REGNUM */ /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM 13 /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM 13 /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */ #define FRAME_POINTER_REQUIRED 1 /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM 11 /* Register in which static-chain is passed to a function. */ #define STATIC_CHAIN_REGNUM 10 /* Register in which address to store a structure value is passed to a function. */ #define STRUCT_VALUE_REGNUM 1 /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. One of the classes must always be named ALL_REGS and include all hard regs. If there is more than one class, another class must be named NO_REGS and contain no registers. The name GENERAL_REGS must be the name of a class (or an alias for another name such as ALL_REGS). This is the class of registers that is allowed by "g" or "r" in a register constraint. Also, registers outside this class are allocated only when instructions express preferences for them. The classes must be numbered in nondecreasing order; that is, a larger-numbered class must never be contained completely in a smaller-numbered class. For any two classes, it is very desirable that there be another class that represents their union. */ enum reg_class { NO_REGS, ADDR_REGS, DATA_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES }; #define GENERAL_REGS DATA_REGS #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ { "NO_REGS", "ADDR_REGS", "DATA_REGS", "FP_REGS", "ALL_REGS" } /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS {0, 0x0fffe, 0x0ffff, 0xf0000, 0xfffff} /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ #define REGNO_REG_CLASS(REGNO) \ ((REGNO) >= 16 ? FP_REGS : (REGNO) != 0 ? ADDR_REGS : DATA_REGS) /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS ADDR_REGS #define BASE_REG_CLASS ADDR_REGS /* Get reg_class from a letter such as appears in the machine description. */ #define REG_CLASS_FROM_LETTER(C) \ ((C) == 'a' ? ADDR_REGS : \ ((C) == 'd' ? DATA_REGS : \ ((C) == 'f' ? FP_REGS : NO_REGS))) /* The letters I, J, K, L and M in a register constraint string can be used to stand for particular ranges of immediate operands. This macro defines what the ranges are. C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. */ #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? (unsigned) (VALUE) < 256 : \ (C) == 'J' ? (unsigned) (VALUE) < 4096 : \ (C) == 'K' ? (VALUE) >= -32768 && (VALUE) < 32768 : 0) /* Similar, but for floating constants, and defining letters G and H. Here VALUE is the CONST_DOUBLE rtx itself. */ #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1 /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. */ #define PREFERRED_RELOAD_CLASS(X, CLASS) \ (GET_CODE(X) == CONST_DOUBLE ? FP_REGS : \ GET_CODE(X) == CONST_INT ? DATA_REGS : \ GET_CODE(X) == LABEL_REF || \ GET_CODE(X) == SYMBOL_REF || \ GET_CODE(X) == CONST ? ADDR_REGS : (CLASS)) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ ((CLASS) == FP_REGS ? 1 : \ (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack makes the stack pointer a smaller address. */ /* #define STACK_GROWS_DOWNWARD */ /* Define this if the nominal address of the stack frame is at the high-address end of the local variables; that is, each additional local variable allocated goes at a more negative offset in the frame. */ /* #define FRAME_GROWS_DOWNWARD */ /* Offset within stack frame to start allocating local variables at. If FRAME_GROWS_DOWNWARD, this is the offset to the END of the first local allocated. Otherwise, it is the offset to the BEGINNING of the first local allocated. */ #define STARTING_FRAME_OFFSET \ (STACK_POINTER_OFFSET + current_function_outgoing_args_size) #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = STARTING_FRAME_OFFSET /* If we generate an insn to push BYTES bytes, this says how many the stack pointer really advances by. On the 370, we have no push instruction. */ /* #define PUSH_ROUNDING(BYTES) */ /* Accumulate the outgoing argument count so we can request the right DSA size and determine stack offset. */ #define ACCUMULATE_OUTGOING_ARGS /* Define offset from stack pointer, to location where a parm can be pushed. */ #define STACK_POINTER_OFFSET 148 /* Offset of first parameter from the argument pointer register value. */ #define FIRST_PARM_OFFSET(FNDECL) 0 /* 1 if N is a possible register number for function argument passing. On the 370, no registers are used in this way. */ #define FUNCTION_ARG_REGNO_P(N) 0 /* Define a data type for recording info about an argument list during the scan of that argument list. This data type should hold all necessary information about the function itself and about the args processed so far, enough to enable macros such as FUNCTION_ARG to determine where the next arg should go. */ #define CUMULATIVE_ARGS int /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) ((CUM) = 0) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ ((CUM) += ((MODE) == DFmode || (MODE) == SFmode \ ? 256 \ : (MODE) != BLKmode \ ? (GET_MODE_SIZE (MODE) + 3) / 4 \ : (int_size_in_bytes (TYPE) + 3) / 4)) /* Define where to put the arguments to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. */ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0 /* For an arg passed partly in registers and partly in memory, this is the number of registers used. For args passed entirely in registers or entirely in memory, zero. */ #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 /* Define if returning from a function call automatically pops the arguments described by the number-of-args field in the call. */ #define RETURN_POPS_ARGS(FUNTYPE, STACKSIZE) 0 /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 15. */ #define RET_REG(MODE) ((MODE) == DFmode || (MODE) == SFmode ? 16 : 15) /* On the 370 the return value is in R15 or R16. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ gen_rtx(REG, TYPE_MODE (VALTYPE), RET_REG(TYPE_MODE(VALTYPE))) /* Define how to find the value returned by a library function assuming the value has mode MODE. */ #define LIBCALL_VALUE(MODE) gen_rtx(REG, MODE, RET_REG(MODE)) /* 1 if N is a possible register number for a function value. On the 370 under C/370, R15 and R16 are thus used. */ #define FUNCTION_VALUE_REGNO_P(N) ((N) == 15 || (N) == 16) /* This macro definition sets up a default value for `main' to return. */ #define DEFAULT_MAIN_RETURN c_expand_return (integer_zero_node) /* This macro generates the assembly code for function entry. All of the C/370 environment is preserved. */ #define FUNCTION_PROLOGUE(FILE, LSIZE) \ { \ static int function_label_index = 1; \ static int function_first = 0; \ static int function_year, function_month, function_day; \ static int function_hour, function_minute, function_second; \ int i; \ if (!function_first) \ { \ struct tm *function_time; \ time_t lcltime; \ time (&lcltime); \ function_time = localtime (&lcltime); \ function_year = function_time->tm_year + 1900; \ function_month = function_time->tm_mon + 1; \ function_day = function_time->tm_mday; \ function_hour = function_time->tm_hour; \ function_minute = function_time->tm_min; \ function_second = function_time->tm_sec; \ } \ fprintf (FILE, "\tUSING\t*,15\n"); \ fprintf (FILE, "\tB\tFPL%03d\n", function_label_index); \ fprintf (FILE, "\tDC\tAL1(FPL%03d+4-*)\n", function_label_index + 1); \ fprintf (FILE, "\tDC\tX'CE',X'A0',X'10'\n"); \ fprintf (FILE, "\tDC\tA($PPA2)\n"); \ fprintf (FILE, "\tDC\tF'%d'\n", 0); \ fprintf (FILE, "\tDC\tF'%d'\n", STACK_POINTER_OFFSET + LSIZE \ + current_function_outgoing_args_size); \ fprintf (FILE, "FPL%03d\tEQU\t*\n", function_label_index + 1); \ fprintf (FILE, "\tDC\tAL2(%d),C'%s'\n", strlen (mvs_function_name), \ mvs_function_name); \ fprintf (FILE, "\tDS\t0F\n"); \ if (!function_first) \ { \ fprintf (FILE, "$PPA2\tEQU\t*\n"); \ fprintf (FILE, "\tDC\tX'03',X'00',X'33',X'00'\n"); \ fprintf (FILE, "\tDC\tV(CEESTART),A(0)\n"); \ fprintf (FILE, "\tDC\tA($TIMES)\n"); \ fprintf (FILE, "\tDS\t0F\n"); \ fprintf (FILE, "$TIMES\tEQU\t*\n"); \ fprintf (FILE, "\tDC\tCL4'%d',CL4'%02d%02d',CL6'%02d%02d00'\n", \ function_year, function_month, function_day, \ function_hour, function_minute, function_second); \ fprintf (FILE, "\tDC\tCL2'01',CL4'0100'\n"); \ } \ fprintf (FILE, "\tDS\t0H\n"); \ fprintf (FILE, "FPL%03d\tEQU\t*\n", function_label_index); \ fprintf (FILE, "\tSTM\t14,12,12(13)\n"); \ fprintf (FILE, "\tL\t2,76(,13)\n"); \ fprintf (FILE, "\tL\t0,16(,15)\n"); \ fprintf (FILE, "\tALR\t0,2\n"); \ fprintf (FILE, "\tCL\t0,12(,12)\n"); \ fprintf (FILE, "\tBNH\t*+10\n"); \ fprintf (FILE, "\tL\t15,116(,12)\n"); \ fprintf (FILE, "\tBALR\t14,15\n"); \ fprintf (FILE, "\tL\t15,72(,13)\n"); \ fprintf (FILE, "\tSTM\t15,0,72(2)\n"); \ fprintf (FILE, "\tMVI\t0(2),X'10'\n"); \ fprintf (FILE, "\tST\t13,4(,2)\n "); \ fprintf (FILE, "\tLR\t13,2\n"); \ fprintf (FILE, "\tLR\t11,1\n"); \ fprintf (FILE, "\tDROP\t15\n"); \ fprintf (FILE, "\tBALR\t%d,0\n", BASE_REGISTER); \ fprintf (FILE, "PG%d\tEQU\t*\n", mvs_page_num ); \ fprintf (FILE, "\tUSING\t*,%d\n", BASE_REGISTER); \ fprintf (FILE, "\tL\t%d,=A(PGT%d)\n", PAGE_REGISTER, mvs_page_num); \ mvs_page_code = 4; \ mvs_page_lit = 4; \ mvs_check_page (FILE, 0, 0); \ function_base_page = mvs_page_num; \ function_first = 1; \ function_label_index += 2; \ } #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ { \ if (strlen (NAME) * 2 > mvs_function_name_length) \ { \ if (mvs_function_name) \ free (mvs_function_name); \ mvs_function_name = 0; \ } \ if (!mvs_function_name) \ { \ mvs_function_name_length = strlen (NAME) * 2; \ mvs_function_name = (char *) malloc (mvs_function_name_length); \ if (mvs_function_name == 0) \ { \ fatal ("virtual memory exceeded"); \ abort (); \ } \ } \ if (!strcmp (NAME, "main")) \ strcpy (mvs_function_name, "gccmain"); \ else \ strcpy (mvs_function_name, NAME); \ fprintf (FILE, "\tDS\t0H\n"); \ assemble_name (FILE, mvs_function_name); \ fputs ("\tCSECT\n", FILE); \ } /* This macro generates the assembly code for function exit, on machines that need it. If FUNCTION_EPILOGUE is not defined then individual return instructions are generated for each return statement. Args are same as for FUNCTION_PROLOGUE. The function epilogue should not depend on the current stack pointer! It should use the frame pointer only. This is mandatory because of alloca; we also take advantage of it to omit stack adjustments before returning. */ #define FUNCTION_EPILOGUE(FILE, LSIZE) \ { \ int i; \ check_label_emit(); \ mvs_check_page (FILE,14,0); \ fprintf (FILE, "\tL\t13,4(,13)\n"); \ fprintf (FILE, "\tL\t14,12(,13)\n"); \ fprintf (FILE, "\tLM\t2,12,28(13)\n"); \ fprintf (FILE, "\tBALR\t1,14\n"); \ fprintf (FILE, "\tDC\tA("); \ mvs_page_num++; \ assemble_name (FILE, mvs_function_name); \ fprintf (FILE, ")\n" ); \ fprintf (FILE, "\tDS\t0F\n" ); \ fprintf (FILE, "\tLTORG\n"); \ fprintf (FILE, "\tDS\t0F\n"); \ fprintf (FILE, "PGT%d\tEQU\t*\n", function_base_page); \ mvs_free_label(); \ for ( i = function_base_page; i < mvs_page_num; i++ ) \ fprintf (FILE, "\tDC\tA(PG%d)\n", i); \ } /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. On the 370, the trampoline contains these instructions: BALR 14,0 USING *,14 L STATIC_CHAIN_REGISTER,X L 15,Y BR 15 X DS 0F Y DS 0F */ #define TRAMPOLINE_TEMPLATE(FILE) \ { \ ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x05E0)); \ ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x5800 | \ STATIC_CHAIN_REGNUM << 4)); \ ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xE00A)); \ ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x58F0)); \ ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xE00E)); \ ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x07FF)); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ } /* Length in units of the trampoline for entering a nested function. */ #define TRAMPOLINE_SIZE 20 /* Emit RTL insns to initialize the variable parts of a trampoline. */ #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), CXT); \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), FNADDR); \ } /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ #define FUNCTION_PROFILER(FILE, LABELNO) \ fprintf (FILE, "Error: No profiling availble.\n") /* Define EXIT_IGNORE_STACK if, when returning from a function, the stack pointer does not matter (provided there is a frame pointer). */ #define EXIT_IGNORE_STACK 1 /* Addressing modes, and classification of registers for them. */ /* #define HAVE_POST_INCREMENT */ /* #define HAVE_POST_DECREMENT */ /* #define HAVE_PRE_DECREMENT */ /* #define HAVE_PRE_INCREMENT */ /* These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. These definitions are NOT overridden anywhere. */ #define REGNO_OK_FOR_INDEX_P(REGNO) \ (((REGNO) > 0 && (REGNO) < 16) \ || (reg_renumber[REGNO] > 0 && reg_renumber[REGNO] < 16)) #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P(REGNO) #define REGNO_OK_FOR_DATA_P(REGNO) \ ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) #define REGNO_OK_FOR_FP_P(REGNO) \ ((unsigned) ((REGNO) - 16) < 4 || (unsigned) (reg_renumber[REGNO] - 16) < 4) /* Now macros that check whether X is a register and also, strictly, whether it is in a specified class. */ /* 1 if X is a data register. */ #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) /* 1 if X is an fp register. */ #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) /* 1 if X is an address register. */ #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) /* Maximum number of registers that can appear in a valid memory address. */ #define MAX_REGS_PER_ADDRESS 2 /* Recognize any constant value that is a valid address. */ #define CONSTANT_ADDRESS_P(X) \ (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE \ || (GET_CODE (X) == CONST \ && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF) \ || (GET_CODE (X) == CONST \ && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \ && !SYMBOL_REF_FLAG (XEXP (XEXP (X, 0), 0)))) /* Nonzero if the constant value X is a legitimate general operand. It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ #define LEGITIMATE_CONSTANT_P(X) 1 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. The usual definition accepts all pseudo regs; the other rejects them all. The symbol REG_OK_STRICT causes the latter definition to be used. Most source files want to accept pseudo regs in the hope that they will get allocated to the class that the insn wants them to be in. Some source files that are used after register allocation need to be strict. */ #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ #define REG_OK_FOR_INDEX_P(X) \ ((REGNO(X) > 0 && REGNO(X) < 16) || REGNO(X) >= 20) /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P(X) #else /* REG_OK_STRICT */ /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P(REGNO(X)) /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P(REGNO(X)) #endif /* REG_OK_STRICT */ /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, except for CONSTANT_ADDRESS_P which is actually machine-independent. */ #define COUNT_REGS(X, REGS, FAIL) \ if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \ REGS += 1; \ else if (GET_CODE (X) != CONST_INT || (unsigned) INTVAL (X) >= 4096) \ goto FAIL; #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { \ if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \ goto ADDR; \ if (GET_CODE (X) == PLUS) \ { \ int regs = 0; \ rtx x0 = XEXP (X, 0); \ rtx x1 = XEXP (X, 1); \ if (GET_CODE (x0) == PLUS) \ { \ COUNT_REGS (XEXP (x0, 0), regs, FAIL); \ COUNT_REGS (XEXP (x0, 1), regs, FAIL); \ COUNT_REGS (x1, regs, FAIL); \ if (regs == 2) \ goto ADDR; \ } \ else if (GET_CODE (x1) == PLUS) \ { \ COUNT_REGS (x0, regs, FAIL); \ COUNT_REGS (XEXP (x1, 0), regs, FAIL); \ COUNT_REGS (XEXP (x1, 1), regs, FAIL); \ if (regs == 2) \ goto ADDR; \ } \ else \ { \ COUNT_REGS (x0, regs, FAIL); \ COUNT_REGS (x1, regs, FAIL); \ if (regs != 0) \ goto ADDR; \ } \ } \ FAIL: ; \ } /* The 370 has no mode dependent addresses. */ #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. */ #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ { \ if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \ copy_to_mode_reg (SImode, XEXP (X, 1))); \ if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \ copy_to_mode_reg (SImode, XEXP (X, 0))); \ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \ force_operand (XEXP (X, 0), 0)); \ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \ force_operand (XEXP (X, 1), 0)); \ if (memory_address_p (MODE, X)) \ goto WIN; \ } /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE SImode /* Define this if the tablejump instruction expects the table to contain offsets from the address of the table. Do not define this if the table should contain absolute addresses. */ /* #define CASE_VECTOR_PC_RELATIVE */ /* Specify the tree operation to be used to convert reals to integers. */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR /* Define this if fixuns_trunc is the same as fix_trunc. */ #define FIXUNS_TRUNC_LIKE_FIX_TRUNC /* We use "unsigned char" as default. */ #define DEFAULT_SIGNED_CHAR 0 /* This is the kind of divide that is easiest to do in the general case. */ #define EASY_DIV_EXPR TRUNC_DIV_EXPR /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ #define MOVE_MAX 256 /* Define this if zero-extension is slow (more than one real instruction). */ #define SLOW_ZERO_EXTEND /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS 1 /* Define if shifts truncate the shift count which implies one can omit a sign-extension or zero-extension of a shift count. */ /* #define SHIFT_COUNT_TRUNCATED */ /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) (OUTPREC != 16) /* We assume that the store-condition-codes instructions store 0 for false and some other value for true. This is the value stored for true. */ /* #define STORE_FLAG_VALUE -1 */ /* When a prototype says `char' or `short', really pass an `int'. */ #define PROMOTE_PROTOTYPES /* Don't perform CSE on function addresses. */ #define NO_FUNCTION_CSE /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ #define Pmode SImode /* A function address in a call instruction is a byte address (for indexing purposes) so give the MEM rtx a byte's mode. */ #define FUNCTION_MODE QImode /* Compute the cost of computing a constant rtl expression RTX whose rtx-code is CODE. The body of this macro is a portion of a switch statement. If the code is computed here, return it with a return statement. Otherwise, break from the switch. */ #define CONST_COSTS(RTX, CODE, OUTERCODE) \ case CONST_INT: \ if ((unsigned) INTVAL (RTX) < 0xfff) return 1; \ case CONST: \ case LABEL_REF: \ case SYMBOL_REF: \ return 2; \ case CONST_DOUBLE: \ return 4; /* Tell final.c how to eliminate redundant test instructions. */ /* Here we define machine-dependent flags and fields in cc_status (see `conditions.h'). */ /* Store in cc_status the expressions that the condition codes will describe after execution of an instruction whose pattern is EXP. Do not alter them if the instruction would not alter the cc's. On the 370, load insns do not alter the cc's. However, in some cases these instructions can make it possibly invalid to use the saved cc's. In those cases we clear out some or all of the saved cc's so they won't be used. */ #define NOTICE_UPDATE_CC(EXP, INSN) \ { \ rtx exp = (EXP); \ if (GET_CODE (exp) == PARALLEL) /* Check this */ \ exp = XVECEXP (exp, 0, 0); \ if (GET_CODE (exp) != SET) \ CC_STATUS_INIT; \ else \ { \ if (XEXP (exp, 0) == cc0_rtx) \ { \ cc_status.value1 = XEXP (exp, 0); \ cc_status.value2 = XEXP (exp, 1); \ cc_status.flags = 0; \ } \ else \ { \ if (cc_status.value1 \ && reg_mentioned_p (XEXP (exp, 0), cc_status.value1)) \ cc_status.value1 = 0; \ if (cc_status.value2 \ && reg_mentioned_p (XEXP (exp, 0), cc_status.value2)) \ cc_status.value2 = 0; \ switch (GET_CODE (XEXP (exp, 1))) \ { \ case PLUS: case MINUS: case MULT: /* case UMULT: */ \ case DIV: case UDIV: case NEG: case ASHIFT: \ case ASHIFTRT: case AND: case IOR: case XOR: \ case ABS: case NOT: \ CC_STATUS_SET (XEXP (exp, 0), XEXP (exp, 1)); \ } \ } \ } \ } #define CC_STATUS_SET(V1, V2) \ { \ cc_status.flags = 0; \ cc_status.value1 = (V1); \ cc_status.value2 = (V2); \ if (cc_status.value1 \ && reg_mentioned_p (cc_status.value1, cc_status.value2)) \ cc_status.value2 = 0; \ } #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ { if (cc_status.flags & CC_NO_OVERFLOW) return NO_OV; return NORMAL; } /* Control the assembler format that we output. */ #define TEXT_SECTION_ASM_OP "* Program text area" #define DATA_SECTION_ASM_OP "* Program data area" #define INIT_SECTION_ASM_OP "* Program initialization area" #define CTOR_LIST_BEGIN /* NO OP */ #define CTOR_LIST_END /* NO OP */ /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ #define REGISTER_NAMES \ { "0", "1", "2", "3", "4", "5", "6", "7", \ "8", "9", "10", "11", "12", "13", "14", "15", \ "0", "2", "4", "6" \ } /* How to renumber registers for dbx and gdb. */ #define DBX_REGISTER_NUMBER(REGNO) (REGNO) #define ASM_FILE_START(FILE) fputs ("\tCSECT\n", FILE); #define ASM_FILE_END(FILE) fputs ("\tEND\n", FILE); #define ASM_IDENTIFY_GCC(FILE) #define ASM_COMMENT_START "*" #define ASM_APP_OFF "" #define ASM_APP_ON "" #define ASM_OUTPUT_LABEL(FILE, NAME) \ { assemble_name (FILE, NAME); fputs ("\tEQU\t*\n", FILE); } #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) /* NO OP */ #define ASM_GLOBALIZE_LABEL(FILE, NAME) \ { fputs ("\tENTRY\t", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE); } /* MVS externals are limited to 8 characters, upper case only. The '_' is mapped to '@', except for MVS functions, then '#'. */ #define MAX_MVS_LABEL_SIZE 8 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ { \ char *bp, ch, temp[MAX_MVS_LABEL_SIZE + 1]; \ if (strlen (NAME) > MAX_MVS_LABEL_SIZE) \ { \ strncpy (temp, NAME, MAX_MVS_LABEL_SIZE); \ temp[MAX_MVS_LABEL_SIZE] = '\0'; \ } \ else \ strcpy (temp,NAME); \ if (!strcmp (temp,"main")) \ strcpy (temp,"gccmain"); \ if (mvs_function_check (temp)) \ ch = '#'; \ else \ ch = '@'; \ for (bp = temp; *bp; bp++) \ { \ if (islower (*bp)) *bp = toupper (*bp); \ if (*bp == '_') *bp = ch; \ } \ fprintf (FILE, "%s", temp); \ } #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ sprintf (LABEL, "*%s%d", PREFIX, NUM) /* Generate internal label. Since we can branch here from off page, we must reload the base register. */ #define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM) \ { \ if (!strcmp (PREFIX,"L")) \ { \ mvs_add_label(NUM); \ mvs_label_emited = 1; \ } \ fprintf (FILE, "%s%d\tEQU\t*\n", PREFIX, NUM); \ } /* Generate case label. */ #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, TABLE) \ fprintf (FILE, "%s%d\tEQU\t*\n", PREFIX, NUM) /* This is how to output an element of a case-vector that is absolute. */ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ mvs_check_page (FILE, 4, 0); \ fprintf (FILE, "\tDC\tA(L%d)\n", VALUE) /* This is how to output an element of a case-vector that is relative. */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ mvs_check_page (FILE, 4, 0); \ fprintf (FILE, "\tDC\tA(L%d-L%d)\n", VALUE, REL) /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ mvs_check_page (FILE, 8, 4); \ fprintf (FILE, "\tS\t13,=F'4'\n\tST\t%s,%d(13)\n", \ reg_names[REGNO], STACK_POINTER_OFFSET) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ mvs_check_page (FILE, 8, 0); \ fprintf (FILE, "\tL\t%s,%d(13)\n\tLA\t13,4(13)\n", \ reg_names[REGNO], STACK_POINTER_OFFSET) /* This is how to output an assembler line defining a `double' constant. */ #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \ fprintf (FILE, "\tDC\tD'%.18G'\n", (VALUE)) /* This is how to output an assembler line defining a `float' constant. */ #define ASM_OUTPUT_FLOAT(FILE, VALUE) \ fprintf (FILE, "\tDC\tE'%.9G'\n", (VALUE)) /* This outputs an integer, if not a CONST_INT must be address constant. */ #define ASM_OUTPUT_INT(FILE, EXP) \ { \ if (GET_CODE (EXP) == CONST_INT) \ { \ fprintf (FILE, "\tDC\tF'"); \ output_addr_const (FILE, EXP); \ fprintf (FILE, "'\n"); \ } \ else \ { \ fprintf (FILE, "\tDC\tA("); \ output_addr_const (FILE, EXP); \ fprintf (FILE, ")\n"); \ } \ } /* This outputs a short integer. */ #define ASM_OUTPUT_SHORT(FILE, EXP) \ { \ fprintf (FILE, "\tDC\tH'"); \ output_addr_const (FILE, EXP); \ fprintf (FILE, "'\n"); \ } /* This outputs a byte sized integer. */ #define ASM_OUTPUT_CHAR(FILE, EXP) \ fprintf (FILE, "\tDC\tX'%02X'\n", INTVAL (EXP) ) #define ASM_OUTPUT_BYTE(FILE, VALUE) \ fprintf (FILE, "\tDC\tX'%02X'\n", VALUE) /* This outputs a text string. The string are chopped up to fit into an 80 byte record. Also, control and special characters, interpreted by the IBM assembler, are output numerically. */ #define MVS_ASCII_TEXT_LENGTH 48 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) \ { \ int i, j; \ int c; \ for (j = 0, i = 0; i < LEN; j++, i++) \ { \ c = PTR[i]; \ if (iscntrl (c) || c == '&') \ { \ if (j % MVS_ASCII_TEXT_LENGTH != 0 ) \ fprintf (FILE, "'\n"); \ j = -1; \ if (c == '&') c = MAP_CHARACTER (c); \ fprintf (FILE, "\tDC\tX'%X'\n", c ); \ } \ else \ { \ if (j % MVS_ASCII_TEXT_LENGTH == 0) \ fprintf (FILE, "\tDC\tC'%c", c); \ else \ { \ if ( c == '\'' ) \ fprintf (FILE, "%c%c", c, c); \ else \ fprintf (FILE, "%c", c); \ if (j % MVS_ASCII_TEXT_LENGTH \ == MVS_ASCII_TEXT_LENGTH - 1) \ fprintf (FILE, "'\n" ); \ } \ } \ } \ if (j % MVS_ASCII_TEXT_LENGTH != 0) \ fprintf (FILE, "'\n"); \ } /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #define ASM_OUTPUT_ALIGN(FILE, LOG) \ if (LOG) \ { \ if ((LOG) == 1) \ fprintf (FILE, "\tDS\t0H\n" ); \ else \ fprintf (FILE, "\tDS\t0F\n" ); \ } \ /* The maximum length of memory that the IBM assembler will allow in one DS operation. */ #define MAX_CHUNK 32767 /* A C statement to output to the stdio stream FILE an assembler instruction to advance the location counter by SIZE bytes. Those bytes should be zero when loaded. */ #define ASM_OUTPUT_SKIP(FILE, SIZE) \ { \ int s, k; \ for (s = (SIZE); s > 0; s -= MAX_CHUNK) \ { \ if (s > MAX_CHUNK) \ k = MAX_CHUNK; \ else \ k = s; \ fprintf (FILE, "\tDS\tXL%d\n", k); \ } \ } /* A C statement (sans semicolon) to output to the stdio stream FILE the assembler definition of a common-label named NAME whose size is SIZE bytes. The variable ROUNDED is the size rounded up to whatever alignment the caller wants. */ #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ { \ fputs ("\tENTRY\t", FILE); \ assemble_name (FILE, NAME); \ fputs ("\n", FILE); \ fprintf (FILE, "\tDS\t0F\n"); \ ASM_OUTPUT_LABEL (FILE,NAME); \ ASM_OUTPUT_SKIP (FILE,SIZE); \ } /* A C statement (sans semicolon) to output to the stdio stream FILE the assembler definition of a local-common-label named NAME whose size is SIZE bytes. The variable ROUNDED is the size rounded up to whatever alignment the caller wants. */ #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ { \ fprintf (FILE, "\tDS\t0F\n"); \ ASM_OUTPUT_LABEL (FILE,NAME); \ ASM_OUTPUT_SKIP (FILE,SIZE); \ } /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ { \ (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10); \ sprintf ((OUTPUT), "%s%d", (NAME), (LABELNO)); \ } /* Define the parentheses used to group arithmetic operations in assembler code. */ #define ASM_OPEN_PAREN "(" #define ASM_CLOSE_PAREN ")" /* Define results of standard character escape sequences. */ #define TARGET_BELL 47 #define TARGET_BS 22 #define TARGET_TAB 5 #define TARGET_NEWLINE 21 #define TARGET_VT 11 #define TARGET_FF 12 #define TARGET_CR 13 /* Print operand X (an rtx) in assembler syntax to file FILE. CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. For `%' followed by punctuation, CODE is the punctuation and X is null. */ #define PRINT_OPERAND(FILE, X, CODE) \ { \ switch (GET_CODE (X)) \ { \ static char curreg[4]; \ case REG: \ if (CODE == 'N') \ strcpy (curreg, reg_names[REGNO (X) + 1]); \ else \ strcpy (curreg, reg_names[REGNO (X)]); \ fprintf (FILE, "%s", curreg); \ break; \ case MEM: \ { \ rtx addr = XEXP (X, 0); \ if (CODE == 'O') \ { \ if (GET_CODE (addr) == PLUS) \ fprintf (FILE, "%d", INTVAL (XEXP (addr, 1))); \ else \ fprintf (FILE, "0"); \ } \ else if (CODE == 'R') \ { \ if (GET_CODE (addr) == PLUS) \ fprintf (FILE, "%s", reg_names[REGNO (XEXP (addr, 0))]);\ else \ fprintf (FILE, "%s", reg_names[REGNO (addr)]); \ } \ else \ output_address (XEXP (X, 0)); \ } \ break; \ case SYMBOL_REF: \ case LABEL_REF: \ mvs_page_lit += 4; \ if (SYMBOL_REF_FLAG (X)) fprintf (FILE, "=V("); \ else fprintf (FILE, "=A("); \ output_addr_const (FILE, X); \ fprintf (FILE, ")"); \ break; \ case CONST_INT: \ if (CODE == 'B') \ fprintf (FILE, "%d", INTVAL (X) & 0xff); \ else if (CODE == 'X') \ fprintf (FILE, "%02X", INTVAL (X) & 0xff); \ else if (CODE == 'h') \ fprintf (FILE, "%d", (INTVAL (X) << 16) >> 16); \ else if (CODE == 'H') \ { \ mvs_page_lit += 4; \ fprintf (FILE, "=F'%d'", (INTVAL (X) << 16) >> 16); \ } \ else \ { \ mvs_page_lit += 4; \ fprintf (FILE, "=F'%d'", INTVAL (X)); \ } \ break; \ case CONST_DOUBLE: \ if (GET_MODE (X) == DImode) \ { \ if (CODE == 'M') \ { \ mvs_page_lit += 4; \ fprintf (FILE, "=XL4'%08X'", CONST_DOUBLE_LOW (X)); \ } \ else if (CODE == 'L') \ { \ mvs_page_lit += 4; \ fprintf (FILE, "=XL4'%08X'", CONST_DOUBLE_HIGH (X)); \ } \ else \ { \ mvs_page_lit += 8; \ fprintf (FILE, "=XL8'%08X%08X'", CONST_DOUBLE_LOW (X), \ CONST_DOUBLE_HIGH (X)); \ } \ } \ else \ { \ union { double d; int i[2]; } u; \ u.i[0] = CONST_DOUBLE_LOW (X); \ u.i[1] = CONST_DOUBLE_HIGH (X); \ if (GET_MODE (X) == SFmode) \ { \ mvs_page_lit += 4; \ fprintf (FILE, "=E'%.9G'", u.d); \ } \ else \ { \ mvs_page_lit += 8; \ fprintf (FILE, "=D'%.18G'", u.d); \ } \ } \ break; \ case CONST: \ if (GET_CODE (XEXP (X, 0)) == PLUS \ && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF) \ { \ mvs_page_lit += 4; \ if (SYMBOL_REF_FLAG (XEXP (XEXP (X, 0), 0))) \ { \ fprintf (FILE, "=V("); \ ASM_OUTPUT_LABELREF (FILE, \ XSTR (XEXP (XEXP (X, 0), 0), 0)); \ fprintf (FILE, ")\n\tA\t%s,=F'%d'", curreg, \ INTVAL (XEXP (XEXP (X, 0), 1))); \ } \ else \ { \ fprintf (FILE, "=A("); \ output_addr_const (FILE, X); \ fprintf (FILE, ")"); \ } \ } \ else \ { \ mvs_page_lit += 4; \ fprintf (FILE, "=F'"); \ output_addr_const (FILE, X); \ fprintf (FILE, "'"); \ } \ break; \ default: \ abort(); \ } \ } #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ { \ rtx breg, xreg, offset, plus; \ \ switch (GET_CODE (ADDR)) \ { \ case REG: \ fprintf (FILE, "0(%s)", reg_names[REGNO (ADDR)]); \ break; \ case PLUS: \ breg = 0; \ xreg = 0; \ offset = 0; \ if (GET_CODE (XEXP (ADDR, 0)) == PLUS) \ { \ if (GET_CODE (XEXP (ADDR, 1)) == REG) \ breg = XEXP (ADDR, 1); \ else \ offset = XEXP (ADDR, 1); \ plus = XEXP (ADDR, 0); \ } \ else \ { \ if (GET_CODE (XEXP (ADDR, 0)) == REG) \ breg = XEXP (ADDR, 0); \ else \ offset = XEXP (ADDR, 0); \ plus = XEXP (ADDR, 1); \ } \ if (GET_CODE (plus) == PLUS) \ { \ if (GET_CODE (XEXP (plus, 0)) == REG) \ { \ if (breg) \ xreg = XEXP (plus, 0); \ else \ breg = XEXP (plus, 0); \ } \ else \ { \ offset = XEXP (plus, 0); \ } \ if (GET_CODE (XEXP (plus, 1)) == REG) \ { \ if (breg) \ xreg = XEXP (plus, 1); \ else \ breg = XEXP (plus, 1); \ } \ else \ { \ offset = XEXP (plus, 1); \ } \ } \ else if (GET_CODE (plus) == REG) \ { \ if (breg) \ xreg = plus; \ else \ breg = plus; \ } \ else \ { \ offset = plus; \ } \ if (offset) \ { \ if (GET_CODE (offset) == LABEL_REF) \ fprintf (FILE, "L%d", \ CODE_LABEL_NUMBER (XEXP (offset, 0))); \ else \ output_addr_const (FILE, offset); \ } \ else \ fprintf (FILE, "0"); \ if (xreg) \ fprintf (FILE, "(%s,%s)", \ reg_names[REGNO (xreg)], reg_names[REGNO (breg)]); \ else \ fprintf (FILE, "(%s)", reg_names[REGNO (breg)]); \ break; \ default: \ mvs_page_lit += 4; \ if (SYMBOL_REF_FLAG (ADDR)) fprintf (FILE, "=V("); \ else fprintf (FILE, "=A("); \ output_addr_const (FILE, ADDR); \ fprintf (FILE, ")"); \ break; \ } \ } gcc-2.5.8/config/i370/mvs370.c100444 22011 13 35771 5453625445 14166 0ustar kenneruser/* Subroutines for insn-output.c for System/370. Copyright (C) 1989, 1993 Free Software Foundation, Inc. Contributed by Jan Stein (jan@cd.chalmers.se). Modified for MVS C/370 by Dave Pitts (pitts@mcdata.com) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include #include #include "config.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "output.h" #include "insn-attr.h" #include "flags.h" #include "recog.h" /* Label node, this structure is used to keep track of labels on the current page. */ typedef struct label_node { struct label_node *label_next; int label_id; int label_page; } label_node_t; /* Is 1 when a label has been generated and the base register must be reloaded. */ int mvs_label_emited = 0; /* Current function starting base page. */ int function_base_page; /* Length of the current page code. */ int mvs_page_code; /* Length of the current page literals. */ int mvs_page_lit; /* Current function name. */ char *mvs_function_name = 0; /* Current function name length. */ int mvs_function_name_length = 0; /* Page number for multi-page functions. */ int mvs_page_num = 0; /* Label node list anchor. */ static label_node_t *label_anchor = 0; /* Label node free list anchor. */ static label_node_t *free_anchor = 0; /* Assembler source file decriptor. */ static FILE *assembler_source = 0; /* Define the length of the internal MVS function table. */ #define MVS_FUNCTION_TABLE_LENGTH 32 /* C/370 internal function table. These functions use non-standard linkage and must handled in a special manner. */ static char *mvs_function_table[MVS_FUNCTION_TABLE_LENGTH] = { "ceil", "edc_acos", "edc_asin", "edc_ata2", "edc_atan", "edc_cos", "edc_cosh", "edc_erf", "edc_erfc", "edc_exp", "edc_gamm", "edc_lg10", "edc_log", "edc_sin", "edc_sinh", "edc_sqrt", "edc_tan", "edc_tanh", "fabs", "floor", "fmod", "frexp", "hypot", "j0", "j1", "jn", "ldexp", "modf", "pow", "y0", "y1", "yn" }; /* ASCII to EBCDIC conversion table. */ #if defined(TARGET_EBCDIC) && !defined(HOST_EBCDIC) static unsigned char ascebc[256] = { /*00 NL SH SX EX ET NQ AK BL */ 0x00, 0x01, 0x02, 0x03, 0x37, 0x2D, 0x2E, 0x2F, /*08 BS HT LF VT FF CR SO SI */ 0x16, 0x05, 0x15, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, /*10 DL D1 D2 D3 D4 NK SN EB */ 0x10, 0x11, 0x12, 0x13, 0x3C, 0x3D, 0x32, 0x26, /*18 CN EM SB EC FS GS RS US */ 0x18, 0x19, 0x3F, 0x27, 0x1C, 0x1D, 0x1E, 0x1F, /*20 SP ! " # $ % & ' */ 0x40, 0x5A, 0x7F, 0x7B, 0x5B, 0x6C, 0x50, 0x7D, /*28 ( ) * + , - . / */ 0x4D, 0x5D, 0x5C, 0x4E, 0x6B, 0x60, 0x4B, 0x61, /*30 0 1 2 3 4 5 6 7 */ 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, /*38 8 9 : ; < = > ? */ 0xF8, 0xF9, 0x7A, 0x5E, 0x4C, 0x7E, 0x6E, 0x6F, /*40 @ A B C D E F G */ 0x7C, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, /*48 H I J K L M N O */ 0xC8, 0xC9, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, /*50 P Q R S T U V W */ 0xD7, 0xD8, 0xD9, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, /*58 X Y Z [ \ ] ^ _ */ 0xE7, 0xE8, 0xE9, 0xAD, 0xE0, 0xBD, 0x5F, 0x6D, /*60 ` a b c d e f g */ 0x79, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, /*68 h i j k l m n o */ 0x88, 0x89, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, /*70 p q r s t u v w */ 0x97, 0x98, 0x99, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, /*78 x y z { | } ~ DL */ 0xA7, 0xA8, 0xA9, 0xC0, 0x4F, 0xD0, 0xA1, 0x07, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0xFF }; #endif /* EBCDIC to ASCII conversion table. */ #if defined(HOST_EBCDIC) && !defined(TARGET_EBCDIC) unsigned char ebcasc[256] = { /*00 NU SH SX EX PF HT LC DL */ 0x00, 0x01, 0x02, 0x03, 0x00, 0x09, 0x00, 0x7F, /*08 SM VT FF CR SO SI */ 0x00, 0x00, 0x00, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, /*10 DE D1 D2 TM RS NL BS IL */ 0x10, 0x11, 0x12, 0x13, 0x14, 0x0A, 0x08, 0x00, /*18 CN EM CC C1 FS GS RS US */ 0x18, 0x19, 0x00, 0x00, 0x1C, 0x1D, 0x1E, 0x1F, /*20 DS SS FS BP LF EB EC */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x17, 0x1B, /*28 SM C2 EQ AK BL */ 0x00, 0x00, 0x00, 0x00, 0x05, 0x06, 0x07, 0x00, /*30 SY PN RS UC ET */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, /*38 C3 D4 NK SU */ 0x00, 0x00, 0x00, 0x00, 0x14, 0x15, 0x00, 0x1A, /*40 SP */ 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*48 . < ( + | */ 0x00, 0x00, 0x00, 0x2E, 0x3C, 0x28, 0x2B, 0x7C, /*50 & */ 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*58 ! $ * ) ; ^ */ 0x00, 0x00, 0x21, 0x24, 0x2A, 0x29, 0x3B, 0x5E, /*60 - / */ 0x2D, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*68 , % _ > ? */ 0x00, 0x00, 0x00, 0x2C, 0x25, 0x5F, 0x3E, 0x3F, /*70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*78 ` : # @ ' = " */ 0x00, 0x60, 0x3A, 0x23, 0x40, 0x27, 0x3D, 0x22, /*80 a b c d e f g */ 0x00, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, /*88 h i { */ 0x68, 0x69, 0x00, 0x7B, 0x00, 0x00, 0x00, 0x00, /*90 j k l m n o p */ 0x00, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, /*98 q r } */ 0x71, 0x72, 0x00, 0x7D, 0x00, 0x00, 0x00, 0x00, /*A0 ~ s t u v w x */ 0x00, 0x7E, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, /*A8 y z [ */ 0x79, 0x7A, 0x00, 0x00, 0x00, 0x5B, 0x00, 0x00, /*B0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*B8 ] */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x5D, 0x00, 0x00, /*C0 { A B C D E F G */ 0x7B, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, /*C8 H I */ 0x48, 0x49, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*D0 } J K L M N O P */ 0x7D, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, /*D8 Q R */ 0x51, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*E0 \ S T U V W X */ 0x5C, 0x00, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, /*E8 Y Z */ 0x59, 0x5A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*F0 0 1 2 3 4 5 6 7 */ 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, /*F8 8 9 */ 0x38, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF }; #endif /* Map characters from one character set to another. C is the character to be translated. */ char mvs_map_char (c) char c; { #if defined(TARGET_EBCDIC) && !defined(HOST_EBCDIC) return ascebc[c]; #else #if defined(HOST_EBCDIC) && !defined(TARGET_EBCDIC) return ebcasc[c]; #else return c; #endif #endif } /* Emit reload of base register if indicated. This is to eliminate multiple reloads when several labels are generated pointing to the same place in the code. */ int check_label_emit (void) { if (mvs_label_emited) { mvs_label_emited = 0; mvs_page_code += 4; fprintf (assembler_source, "\tL\t%d,%d(,%d)\n", BASE_REGISTER, (mvs_page_num - function_base_page) * 4, PAGE_REGISTER); } } /* Add the label to the current page label list. If a free element is available it will be used for the new label. Otherwise, a label element will be allocated from memory. ID is the label number of the label being added to the list. */ int mvs_add_label (id) int id; { label_node_t *lp; if (free_anchor) { lp = free_anchor; free_anchor = lp->label_next; } else { lp = (label_node_t *) malloc (sizeof (label_node_t)); if (lp == 0) { fatal ("virtual memory exhausted\n"); abort (); } } lp->label_id = id; lp->label_page = mvs_page_num; lp->label_next = label_anchor; label_anchor = lp; } /* Check to see if the label is in the list. If 1 is returned then a load and branch on register must be generated. ID is the label number of the label being checked. */ int mvs_check_label (id) int id; { label_node_t *lp; for (lp = label_anchor; lp; lp = lp->label_next) { if (lp->label_id == id) return 1; } return 0; } /* The label list for the current page freed by linking the list onto the free label element chain. */ int mvs_free_label (void) { if (label_anchor) { if (free_anchor) label_anchor->label_next = free_anchor; free_anchor = label_anchor; } label_anchor = 0; } /* If the page size limit is reached a new code page is started, and the base register is set to it. This page break point is counted conservatively, most literals that have the same value are collapsed by the assembler. True is returned when a new page is started. FILE is the assembler output file descriptor. CODE is the length, in bytes, of the instruction to be emitted. LIT is the length of the literal to be emitted. */ int mvs_check_page (file, code, lit) FILE *file; int code, lit; { if (file) assembler_source = file; if (mvs_page_code + code + mvs_page_lit + lit > MAX_MVS_PAGE_LENGTH) { fprintf (assembler_source, "\tB\tPGE%d\n", mvs_page_num); fprintf (assembler_source, "\tDS\t0F\n"); fprintf (assembler_source, "\tLTORG\n"); fprintf (assembler_source, "\tDS\t0F\n"); fprintf (assembler_source, "PGE%d\tEQU\t*\n", mvs_page_num); fprintf (assembler_source, "\tDROP\t%d\n", BASE_REGISTER); mvs_page_num++; fprintf (assembler_source, "\tBALR\t%d,0\n", BASE_REGISTER); fprintf (assembler_source, "PG%d\tEQU\t*\n", mvs_page_num); fprintf (assembler_source, "\tUSING\t*,%d\n", BASE_REGISTER); mvs_free_label (); mvs_page_code = code; mvs_page_lit = lit; return 1; } mvs_page_code += code; mvs_page_lit += lit; return 0; } /* Check for C/370 runtime function, they don't use standard calling conventions. True is returned if the function is in the table. NAME is the name of the current function. */ int mvs_function_check (name) char *name; { int lower, middle, upper; int i; lower = 0; upper = MVS_FUNCTION_TABLE_LENGTH - 1; while (lower <= upper) { middle = (lower + upper) / 2; i = strcmp (name, mvs_function_table[middle]); if (i == 0) return 1; if (i < 0) upper = middle - 1; else lower = middle + 1; } return 0; } /* Return 1 if OP is a valid S operand for an RS, SI or SS type instruction. OP is the current operation. MODE is the current operation mode. */ int s_operand (op, mode) register rtx op; enum machine_mode mode; { extern int volatile_ok; register enum rtx_code code = GET_CODE (op); if (CONSTANT_ADDRESS_P (op)) return 1; if (mode == VOIDmode || GET_MODE (op) != mode) return 0; if (code == MEM) { register rtx x = XEXP (op, 0); if (!volatile_ok && op->volatil) return 0; if (REG_P (x) && REG_OK_FOR_BASE_P (x)) return 1; if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0)) && REG_OK_FOR_BASE_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) == CONST_INT && (unsigned) INTVAL (XEXP (x, 1)) < 4096) return 1; } return 0; } /* Return 1 if OP is a valid R or S operand for an RS, SI or SS type instruction. OP is the current operation. MODE is the current operation mode. */ int r_or_s_operand (op, mode) register rtx op; enum machine_mode mode; { extern int volatile_ok; register enum rtx_code code = GET_CODE (op); if (CONSTANT_ADDRESS_P (op)) return 1; if (mode == VOIDmode || GET_MODE (op) != mode) return 0; if (code == REG) return 1; else if (code == MEM) { register rtx x = XEXP (op, 0); if (!volatile_ok && op->volatil) return 0; if (REG_P (x) && REG_OK_FOR_BASE_P (x)) return 1; if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0)) && REG_OK_FOR_BASE_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) == CONST_INT && (unsigned) INTVAL (XEXP (x, 1)) < 4096) return 1; } return 0; } /* Return 1 if the next instruction is an unsigned jump instruction. INSN is the current instruction. */ unsigned_jump_follows_p (insn) register rtx insn; { insn = NEXT_INSN (insn); if (GET_CODE (insn) != JUMP_INSN) return 0; insn = XEXP (insn, 3); if (GET_CODE (insn) != SET) return 0; if (GET_CODE (XEXP (insn, 0)) != PC) return 0; insn = XEXP (insn, 1); if (GET_CODE (insn) != IF_THEN_ELSE) return 0; insn = XEXP (insn, 0); return GET_CODE (insn) != GE && GET_CODE (insn) != GT && GET_CODE (insn) != LE && GET_CODE (insn) != LT; } gcc-2.5.8/config/i370/xm-mvs.h100444 22011 13 3117 5413066605 14321 0ustar kenneruser/* Configuration for GNU C-compiler for System/370. Copyright (C) 1989, 1993 Free Software Foundation, Inc. Contributed by Jan Stein (jan@cd.chalmers.se). Modifed for MVS C/370 by Dave Pitts (pitts@mcdata.com) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* #defines that need visibility everywhere. */ #define FALSE 0 #define TRUE 1 /* This describes the machine the compiler is hosted on. */ #define HOST_BITS_PER_CHAR 8 #define HOST_BITS_PER_SHORT 16 #define HOST_BITS_PER_INT 32 #define HOST_BITS_PER_LONG 32 #define HOST_FLOAT_FORMAT IBM_FLOAT_FORMAT #define HOST_EBCDIC 1 #define USG #ifndef MVS #define MVS #endif /* Target machine dependencies. tm.h is a symbolic link to the actual target specific file. */ #include "tm.h" #define bcopy(a,b,c) memcpy (b,a,c) #define bzero(a,b) memset (a,0,b) #define bcmp(a,b,c) memcmp (a,b,c) /* Arguments to use with `exit'. */ #define SUCCESS_EXIT_CODE 0 #define FATAL_EXIT_CODE 12 #define NO_DBX_FORMAT gcc-2.5.8/config/i386/ 40777 22011 13 0 5520736515 12642 5ustar kennerusergcc-2.5.8/config/i386/386bsd.h100444 22011 13 4506 5453234504 14114 0ustar kenneruser/* Configuration for an i386 running 386BSD as the target machine. */ /* This is tested by i386gas.h. */ #define YES_UNDERSCORES #include "i386/gstabs.h" /* Get perform_* macros to build libgcc.a. */ #include "i386/perform.h" #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dunix -Di386 -D____386BSD____ -D__386BSD__ -DBSD_NET2 -Asystem(unix) -Asystem(bsd) -Acpu(i386) -Amachine(i386)" /* Like the default, except no -lg. */ #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" #undef SIZE_TYPE #define SIZE_TYPE "unsigned int" #undef PTRDIFF_TYPE #define PTRDIFF_TYPE "int" #undef WCHAR_TYPE #define WCHAR_TYPE "short unsigned int" #define WCHAR_UNSIGNED 1 #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE 16 /* 386BSD does have atexit. */ #define HAVE_ATEXIT /* Redefine this to use %eax instead of %edx. */ #undef FUNCTION_PROFILER #define FUNCTION_PROFILER(FILE, LABELNO) \ { \ if (flag_pic) \ { \ fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%eax\n", \ LPREFIX, (LABELNO)); \ fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n"); \ } \ else \ { \ fprintf (FILE, "\tmovl $%sP%d,%%eax\n", LPREFIX, (LABELNO)); \ fprintf (FILE, "\tcall mcount\n"); \ } \ } /* There are conflicting reports about whether this system uses a different assembler syntax. wilson@cygnus.com says # is right. */ #undef COMMENT_BEGIN #define COMMENT_BEGIN "#" #undef ASM_APP_ON #define ASM_APP_ON "#APP\n" #undef ASM_APP_OFF #define ASM_APP_OFF "#NO_APP\n" /* The following macros are stolen from i386v4.h */ /* These have to be defined to get PIC code correct */ /* This is how to output an element of a case-vector that is relative. This is only used for PIC code. See comments by the `casesi' insn in i386.md for an explanation of the expression this outputs. */ #undef ASM_OUTPUT_ADDR_DIFF_ELT #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE) /* Indicate that jump tables go in the text section. This is necessary when compiling PIC code. */ #define JUMP_TABLES_IN_TEXT_SECTION /* Don't default to pcc-struct-return, because gcc is the only compiler, and we want to retain compatibility with older gcc versions. */ #define DEFAULT_PCC_STRUCT_RETURN 0 gcc-2.5.8/config/i386/aix386.h100444 22011 13 4217 5410150657 14123 0ustar kenneruser/* Definitions for IBM PS2 running AIX/386 with gas. From: Minh Tran-Le Copyright (C) 1988 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* * This configuration file is for gcc with gas-2.x and gnu ld 2.x * with aix ps/2 1.3.x. */ /* Define USE_GAS if you have the new version of gas that can handle * multiple segments and .section pseudo op. This will allow gcc to * use the .init section for g++ ctor/dtor. * * If you don't have gas then undefined USE_GAS. You will also have * to use collect if you want to use g++ */ #define USE_GAS #include "i386/aix386ng.h" /* Use crt1.o as a startup file and crtn.o as a closing file. And add crtbegin.o and crtend.o for ctors and dtors */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} crtbegin.o%s" #undef ENDFILE_SPEC #define ENDFILE_SPEC \ "crtend.o%s crtn.o%s" /* Removed the -K flags because the gnu ld does not handle it */ #undef LINK_SPEC #define LINK_SPEC "%{T*} %{z:-lm}" /* Define a few machine-specific details of the implementation of constructors. */ #undef INIT_SECTION_ASM_OP #define INIT_SECTION_ASM_OP ".section .init,\"x\"" #define CTOR_LIST_BEGIN \ asm (INIT_SECTION_ASM_OP); \ asm ("pushl $0") #define CTOR_LIST_END CTOR_LIST_BEGIN #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ do { \ init_section (); \ fprintf (FILE, "\tpushl $"); \ assemble_name (FILE, NAME); \ fprintf (FILE, "\n"); \ } while (0) gcc-2.5.8/config/i386/aix386ng.h100444 22011 13 10326 5453234506 14471 0ustar kenneruser/* Definitions for IBM PS2 running AIX/386. From: Minh Tran-Le Copyright (C) 1988 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "i386/i386.h" /* Get the generic definitions for system V.3. */ #include "svr3.h" /* Use the ATT assembler syntax. This overrides at least one macro (ASM_OUTPUT_LABELREF) from svr3.h. */ #include "i386/att.h" /* Use crt1.o as a startup file and crtn.o as a closing file. */ #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}" #define ENDFILE_SPEC "crtn.o%s" #define LIB_SPEC "%{shlib:-lc_s} -lc" /* Special flags for the linker. I don't know what they do. */ #define LINK_SPEC "%{K} %{!K:-K} %{T*} %{z:-lm}" /* Specify predefined symbols in preprocessor. */ #define CPP_PREDEFINES "-Dps2 -Dunix -Di386 -Asystem(unix) -Asystem(aix) -Acpu(i386) -Amachine(i386)" #define CPP_SPEC \ "%{posix:-D_POSIX_SOURCE}%{!posix:-DAIX} -D_I386 -D_AIX -D_MBCS" /* special flags for the aix assembler to generate the short form for all qualifying forward reference */ /* The buggy /bin/as of aix ps/2 1.2.x cannot always handle it. */ #if 0 #define ASM_SPEC "-s2" #endif /* 0 */ #undef ASM_FILE_START #define ASM_FILE_START(FILE) \ do { fprintf (FILE, "\t.file\t"); \ output_quoted_string (FILE, dump_base_name); \ fprintf (FILE, "\n"); \ if (optimize) \ ASM_FILE_START_1 (FILE); \ else \ fprintf (FILE, "\t.noopt\n"); \ } while (0) /* This was suggested, but it shouldn't be right for DBX output. -- RMS #define ASM_OUTPUT_SOURCE_FILENAME(FILE, NAME) */ /* Writing `int' for a bitfield forces int alignment for the structure. */ #define PCC_BITFIELD_TYPE_MATTERS 1 #ifndef USE_GAS /* Don't write a `.optim' pseudo; this assembler is said to have a bug when .optim is used. */ #undef ASM_FILE_START_1 #define ASM_FILE_START_1(FILE) fprintf (FILE, "\t.noopt\n") #endif /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ #undef FUNCTION_PROFILER #define FUNCTION_PROFILER(FILE, LABELNO) \ fprintf (FILE, "\tleal %sP%d,%%eax\n\tcall mcount\n", LPREFIX, (LABELNO)); /* Note that using bss_section here caused errors in building shared libraries on system V.3. but AIX 1.2 does not have yet shareable libraries on PS2 */ #undef ASM_OUTPUT_LOCAL #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ (bss_section (), \ ASM_OUTPUT_LABEL ((FILE), (NAME)), \ fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED))) /* Undef all the .init and .fini section stuff if we are not using gas and * gnu ld so that we can use collect because the standard /bin/as and /bin/ld * cannot handle those. */ #ifndef USE_GAS # undef INIT_SECTION_ASM_OP # undef FINI_SECTION_ASM_OP # undef CTORS_SECTION_ASM_OP # undef DTORS_SECTION_ASM_OP # undef ASM_OUTPUT_CONSTRUCTOR # undef ASM_OUTPUT_DESTRUCTOR # undef DO_GLOBAL_CTORS_BODY # undef CTOR_LIST_BEGIN # define CTOR_LIST_BEGIN # undef CTOR_LIST_END # define CTOR_LIST_END # undef DTOR_LIST_BEGIN # define DTOR_LIST_BEGIN # undef DTOR_LIST_END # define DTOR_LIST_END # undef CONST_SECTION_FUNCTION # define CONST_SECTION_FUNCTION \ void \ const_section () \ { \ extern void text_section(); \ text_section(); \ } # undef EXTRA_SECTION_FUNCTIONS # define EXTRA_SECTION_FUNCTIONS \ CONST_SECTION_FUNCTION \ BSS_SECTION_FUNCTION /* for collect2 */ # define OBJECT_FORMAT_COFF # define MY_ISCOFF(magic) \ ((magic) == I386MAGIC || (magic) == I386SVMAGIC) #endif /* !USE_GAS */ gcc-2.5.8/config/i386/att.h100444 22011 13 6737 5450477110 13702 0ustar kenneruser/* Definitions for AT&T assembler syntax for the Intel 80386. Copyright (C) 1988 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Include common aspects of all 386 Unix assemblers. */ #include "i386/unix.h" #define TARGET_VERSION fprintf (stderr, " (80386, ATT syntax)"); /* Define the syntax of instructions and addresses. */ /* Prefix for internally generated assembler labels. */ #define LPREFIX ".L" /* Assembler pseudos to introduce constants of various size. */ /* #define ASM_BYTE_OP "\t.byte" Now in svr3.h or svr4.h. */ #define ASM_SHORT "\t.value" #define ASM_LONG "\t.long" #define ASM_DOUBLE "\t.double" /* How to output an ASCII string constant. */ #define ASM_OUTPUT_ASCII(FILE, p, size) \ do \ { int i = 0; \ while (i < (size)) \ { if (i%10 == 0) { if (i!=0) fprintf ((FILE), "\n"); \ fprintf ((FILE), "%s ", ASM_BYTE_OP); } \ else fprintf ((FILE), ","); \ fprintf ((FILE), "0x%x", ((p)[i++] & 0377)) ;} \ fprintf ((FILE), "\n"); \ } while (0) /* Do use .optim by default on this machine. */ #undef ASM_FILE_START_1 #define ASM_FILE_START_1(FILE) fprintf (FILE, "\t.optim\n") /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG)) /* This is how to output an assembler line that says to advance the location counter by SIZE bytes. */ #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf ((FILE), "\t.set .,.+%u\n", (SIZE)) /* Can't use ASM_OUTPUT_SKIP in text section; it doesn't leave 0s. */ #define ASM_NO_SKIP_IN_TEXT 1 #undef BSS_SECTION_FUNCTION /* Override the definition from svr3.h. */ #define BSS_SECTION_FUNCTION \ void \ bss_section () \ { \ if (in_section != in_bss) \ { \ fprintf (asm_out_file, "%s\n", BSS_SECTION_ASM_OP); \ in_section = in_bss; \ } \ } /* Define the syntax of labels and symbol definitions/declarations. */ /* This is how to store into the string BUF the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #undef ASM_GENERATE_INTERNAL_LABEL #define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ sprintf ((BUF), ".%s%d", (PREFIX), (NUMBER)) /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #undef ASM_OUTPUT_INTERNAL_LABEL #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, ".%s%d:\n", PREFIX, NUM) /* This is how to output a reference to a user-level label named NAME. */ #undef ASM_OUTPUT_LABELREF #define ASM_OUTPUT_LABELREF(FILE,NAME) \ fprintf (FILE, "%s", NAME) gcc-2.5.8/config/i386/bsd.h100444 22011 13 10415 5453662477 13705 0ustar kenneruser/* Definitions for BSD assembler syntax for Intel 386 (actually AT&T syntax for insns and operands, adapted to BSD conventions for symbol names and debugging.) Copyright (C) 1988 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Include common aspects of all 386 Unix assemblers. */ #include "i386/unix.h" /* Use the Sequent Symmetry assembler syntax. */ #define TARGET_VERSION fprintf (stderr, " (80386, BSD syntax)"); /* Define the syntax of pseudo-ops, labels and comments. */ /* Prefix for internally generated assembler labels. If we aren't using underscores, we are using prefix `.'s to identify labels that should be ignored, as in `i386/gas.h' --karl@cs.umb.edu */ #ifdef NO_UNDERSCORES #define LPREFIX ".L" #else #define LPREFIX "L" #endif /* not NO_UNDERSCORES */ /* Assembler pseudos to introduce constants of various size. */ #define ASM_BYTE_OP "\t.byte" #define ASM_SHORT "\t.word" #define ASM_LONG "\t.long" #define ASM_DOUBLE "\t.double" /* Output at beginning of assembler file. ??? I am skeptical of this -- RMS. */ #define ASM_FILE_START(FILE) \ do { fprintf (FILE, "\t.file\t"); \ output_quoted_string (FILE, dump_base_name); \ fprintf (FILE, "\n"); \ } while (0) /* This was suggested, but it shouldn't be right for DBX output. -- RMS #define ASM_OUTPUT_SOURCE_FILENAME(FILE, NAME) */ /* Define the syntax of labels and symbol definitions/declarations. */ /* This is how to output an assembler line that says to advance the location counter by SIZE bytes. */ #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t.space %u\n", (SIZE)) /* Define the syntax of labels and symbol definitions/declarations. */ /* This says how to output an assembler line to define a global common symbol. */ #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fputs (".comm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (ROUNDED))) /* This says how to output an assembler line to define a local common symbol. */ #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( fputs (".lcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (ROUNDED))) /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", (LOG)) /* This is how to store into the string BUF the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #ifdef NO_UNDERSCORES #define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ sprintf ((BUF), "*.%s%d", (PREFIX), (NUMBER)) #else #define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ sprintf ((BUF), "*%s%d", (PREFIX), (NUMBER)) #endif /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #ifdef NO_UNDERSCORES #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, ".%s%d:\n", PREFIX, NUM) #else #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, "%s%d:\n", PREFIX, NUM) #endif /* This is how to output a reference to a user-level label named NAME. */ #ifdef NO_UNDERSCORES #define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "%s", NAME) #else #define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "_%s", NAME) #endif /* not NO_UNDERSCORES */ /* Sequent has some changes in the format of DBX symbols. */ #define DBX_NO_XREFS 1 /* Don't split DBX symbols into continuations. */ #define DBX_CONTIN_LENGTH 0 gcc-2.5.8/config/i386/gas.h100444 22011 13 12000 5520605413 13655 0ustar kenneruser/* Definitions for Intel 386 running system V with gnu tools Copyright (C) 1988, 1993, 1994 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Note that i386/seq-gas.h is a GAS configuration that does not use this file. */ #include "i386/i386.h" #ifndef YES_UNDERSCORES /* Define this now, because i386/bsd.h tests it. */ #define NO_UNDERSCORES #endif /* Use the bsd assembler syntax. */ /* we need to do this because gas is really a bsd style assembler, * and so doesn't work well this these att-isms: * * ASM_OUTPUT_SKIP is .set .,.+N, which isn't implemented in gas * ASM_OUTPUT_LOCAL is done with .set .,.+N, but that can't be * used to define bss static space * * Next is the question of whether to uses underscores. RMS didn't * like this idea at first, but since it is now obvious that we * need this separate tm file for use with gas, at least to get * dbx debugging info, I think we should also switch to underscores. * We can keep i386v for real att style output, and the few * people who want both form will have to compile twice. */ #include "i386/bsd.h" /* these come from i386/bsd.h, but are specific to sequent */ #undef DBX_NO_XREFS #undef DBX_CONTIN_LENGTH /* Ask for COFF symbols. */ #define SDB_DEBUGGING_INFO /* Specify predefined symbols in preprocessor. */ #define CPP_PREDEFINES "-Dunix -Di386 -Asystem(unix) -Acpu(i386) -Amachine(i386)" #define CPP_SPEC "%{posix:-D_POSIX_SOURCE}" /* Allow #sccs in preprocessor. */ #define SCCS_DIRECTIVE /* Output #ident as a .ident. */ #define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME); /* Implicit library calls should use memcpy, not bcopy, etc. */ #define TARGET_MEM_FUNCTIONS #if 0 /* People say gas uses the log as the arg to .align. */ /* When using gas, .align N aligns to an N-byte boundary. */ #undef ASM_OUTPUT_ALIGN #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG)) #endif /* Align labels, etc. at 4-byte boundaries. For the 486, align to 16-byte boundary for sake of cache. */ #undef ASM_OUTPUT_ALIGN_CODE #define ASM_OUTPUT_ALIGN_CODE(FILE) \ fprintf ((FILE), "\t.align %d,0x90\n", \ TARGET_486 ? 4 : 2); /* Use log of 16 or log of 4 as arg. */ /* Align start of loop at 4-byte boundary. */ #undef ASM_OUTPUT_LOOP_ALIGN #define ASM_OUTPUT_LOOP_ALIGN(FILE) \ fprintf ((FILE), "\t.align 2,0x90\n"); /* Use log of 4 as arg. */ /* A C statement or statements which output an assembler instruction opcode to the stdio stream STREAM. The macro-operand PTR is a variable of type `char *' which points to the opcode name in its "internal" form--the form that is written in the machine description. GAS version 1.38.1 doesn't understand the `repz' opcode mnemonic. So use `repe' instead. */ #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ { \ if ((PTR)[0] == 'r' \ && (PTR)[1] == 'e' \ && (PTR)[2] == 'p') \ { \ if ((PTR)[3] == 'z') \ { \ fprintf (STREAM, "repe"); \ (PTR) += 4; \ } \ else if ((PTR)[3] == 'n' && (PTR)[4] == 'z') \ { \ fprintf (STREAM, "repne"); \ (PTR) += 5; \ } \ } \ } /* Define macro used to output shift-double opcodes when the shift count is in %cl. Some assemblers require %cl as an argument; some don't. GAS requires the %cl argument, so override i386/unix.h. */ #undef AS3_SHIFT_DOUBLE #define AS3_SHIFT_DOUBLE(a,b,c,d) AS3 (a,b,c,d) /* Print opcodes the way that GAS expects them. */ #define GAS_MNEMONICS 1 #ifdef NO_UNDERSCORES /* If user-symbols don't have underscores, then it must take more than `L' to identify a label that should be ignored. */ /* This is how to store into the string BUF the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #undef ASM_GENERATE_INTERNAL_LABEL #define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ sprintf ((BUF), ".%s%d", (PREFIX), (NUMBER)) /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #undef ASM_OUTPUT_INTERNAL_LABEL #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, ".%s%d:\n", PREFIX, NUM) #endif /* NO_UNDERSCORES */ gcc-2.5.8/config/i386/go32.h100444 22011 13 2573 5464235466 13671 0ustar kenneruser/* Configuration for an i386 running MS-DOS with djgpp/go32. */ #define YES_UNDERSCORES #include "i386/gas.h" #ifdef CPP_PREDEFINES #undef CPP_PREDEFINES #endif #define CPP_PREDEFINES "-Dunix -Di386 -DGO32 -DMSDOS \ -Asystem(unix) -Asystem(msdos) -Acpu(i386) -Amachine(i386)" #undef EXTRA_SECTIONS #define EXTRA_SECTIONS in_ctor, in_dtor #undef EXTRA_SECTION_FUNCTIONS #define EXTRA_SECTION_FUNCTIONS \ CTOR_SECTION_FUNCTION \ DTOR_SECTION_FUNCTION #define CTOR_SECTION_FUNCTION \ void \ ctor_section () \ { \ if (in_section != in_ctor) \ { \ fprintf (asm_out_file, "\t.section .ctor\n"); \ in_section = in_ctor; \ } \ } #define DTOR_SECTION_FUNCTION \ void \ dtor_section () \ { \ if (in_section != in_dtor) \ { \ fprintf (asm_out_file, "\t.section .dtor\n"); \ in_section = in_dtor; \ } \ } #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ do { \ ctor_section (); \ fprintf (FILE, "%s\t", ASM_LONG); \ assemble_name (FILE, NAME); \ fprintf (FILE, "\n"); \ } while (0) #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ do { \ dtor_section (); \ fprintf (FILE, "%s\t", ASM_LONG); \ assemble_name (FILE, NAME); \ fprintf (FILE, "\n"); \ } while (0) gcc-2.5.8/config/i386/gstabs.h100444 22011 13 276 5317431332 14343 0ustar kenneruser#include "i386/gas.h" /* We do not want to output SDB debugging information. */ #undef SDB_DEBUGGING_INFO /* We want to output DBX debugging information. */ #define DBX_DEBUGGING_INFO gcc-2.5.8/config/i386/i386.c100444 22011 13 155633 5464562645 13653 0ustar kenneruser/* Subroutines for insn-output.c for Intel 80386. Copyright (C) 1988, 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include #include "config.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "output.h" #include "insn-attr.h" #include "tree.h" #include "flags.h" #include "function.h" #ifdef EXTRA_CONSTRAINT /* If EXTRA_CONSTRAINT is defined, then the 'S' constraint in REG_CLASS_FROM_LETTER will no longer work, and various asm statements that need 'S' for class SIREG will break. */ error EXTRA_CONSTRAINT conflicts with S constraint letter /* The previous line used to be #error, but some compilers barf even if the conditional was untrue. */ #endif #define AT_BP(mode) (gen_rtx (MEM, (mode), frame_pointer_rtx)) extern FILE *asm_out_file; extern char *strcat (); char *singlemove_string (); char *output_move_const_single (); char *output_fp_cc0_set (); char *hi_reg_name[] = HI_REGISTER_NAMES; char *qi_reg_name[] = QI_REGISTER_NAMES; char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES; /* Array of the smallest class containing reg number REGNO, indexed by REGNO. Used by REGNO_REG_CLASS in i386.h. */ enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] = { /* ax, dx, cx, bx */ AREG, DREG, CREG, BREG, /* si, di, bp, sp */ SIREG, DIREG, INDEX_REGS, GENERAL_REGS, /* FP registers */ FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, /* arg pointer */ INDEX_REGS }; /* Test and compare insns in i386.md store the information needed to generate branch and scc insns here. */ struct rtx_def *i386_compare_op0, *i386_compare_op1; struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); /* Output an insn whose source is a 386 integer register. SRC is the rtx for the register, and TEMPLATE is the op-code template. SRC may be either SImode or DImode. The template will be output with operands[0] as SRC, and operands[1] as a pointer to the top of the 386 stack. So a call from floatsidf2 would look like this: output_op_from_reg (operands[1], AS1 (fild%z0,%1)); where %z0 corresponds to the caller's operands[1], and is used to emit the proper size suffix. ??? Extend this to handle HImode - a 387 can load and store HImode values directly. */ void output_op_from_reg (src, template) rtx src; char *template; { rtx xops[4]; int size = GET_MODE_SIZE (GET_MODE (src)); xops[0] = src; xops[1] = AT_SP (Pmode); xops[2] = GEN_INT (size); xops[3] = stack_pointer_rtx; if (size > UNITS_PER_WORD) { rtx high; if (size > 2 * UNITS_PER_WORD) { high = gen_rtx (REG, SImode, REGNO (src) + 2); output_asm_insn (AS1 (push%L0,%0), &high); } high = gen_rtx (REG, SImode, REGNO (src) + 1); output_asm_insn (AS1 (push%L0,%0), &high); } output_asm_insn (AS1 (push%L0,%0), &src); output_asm_insn (template, xops); output_asm_insn (AS2 (add%L3,%2,%3), xops); } /* Output an insn to pop an value from the 387 top-of-stack to 386 register DEST. The 387 register stack is popped if DIES is true. If the mode of DEST is an integer mode, a `fist' integer store is done, otherwise a `fst' float store is done. */ void output_to_reg (dest, dies) rtx dest; int dies; { rtx xops[4]; int size = GET_MODE_SIZE (GET_MODE (dest)); xops[0] = AT_SP (Pmode); xops[1] = stack_pointer_rtx; xops[2] = GEN_INT (size); xops[3] = dest; output_asm_insn (AS2 (sub%L1,%2,%1), xops); if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_INT) { if (dies) output_asm_insn (AS1 (fistp%z3,%y0), xops); else output_asm_insn (AS1 (fist%z3,%y0), xops); } else if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_FLOAT) { if (dies) output_asm_insn (AS1 (fstp%z3,%y0), xops); else { if (GET_MODE (dest) == XFmode) { output_asm_insn (AS1 (fstp%z3,%y0), xops); output_asm_insn (AS1 (fld%z3,%y0), xops); } else output_asm_insn (AS1 (fst%z3,%y0), xops); } } else abort (); output_asm_insn (AS1 (pop%L0,%0), &dest); if (size > UNITS_PER_WORD) { dest = gen_rtx (REG, SImode, REGNO (dest) + 1); output_asm_insn (AS1 (pop%L0,%0), &dest); if (size > 2 * UNITS_PER_WORD) { dest = gen_rtx (REG, SImode, REGNO (dest) + 1); output_asm_insn (AS1 (pop%L0,%0), &dest); } } } char * singlemove_string (operands) rtx *operands; { rtx x; if (GET_CODE (operands[0]) == MEM && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC) { if (XEXP (x, 0) != stack_pointer_rtx) abort (); return "push%L1 %1"; } else if (GET_CODE (operands[1]) == CONST_DOUBLE) { return output_move_const_single (operands); } else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG) return AS2 (mov%L0,%1,%0); else if (CONSTANT_P (operands[1])) return AS2 (mov%L0,%1,%0); else { output_asm_insn ("push%L1 %1", operands); return "pop%L0 %0"; } } /* Return a REG that occurs in ADDR with coefficient 1. ADDR can be effectively incremented by incrementing REG. */ static rtx find_addr_reg (addr) rtx addr; { while (GET_CODE (addr) == PLUS) { if (GET_CODE (XEXP (addr, 0)) == REG) addr = XEXP (addr, 0); else if (GET_CODE (XEXP (addr, 1)) == REG) addr = XEXP (addr, 1); else if (CONSTANT_P (XEXP (addr, 0))) addr = XEXP (addr, 1); else if (CONSTANT_P (XEXP (addr, 1))) addr = XEXP (addr, 0); else abort (); } if (GET_CODE (addr) == REG) return addr; abort (); } /* Output an insn to add the constant N to the register X. */ static void asm_add (n, x) int n; rtx x; { rtx xops[2]; xops[1] = x; if (n < 0) { xops[0] = GEN_INT (-n); output_asm_insn (AS2 (sub%L0,%0,%1), xops); } else if (n > 0) { xops[0] = GEN_INT (n); output_asm_insn (AS2 (add%L0,%0,%1), xops); } } /* Output assembler code to perform a doubleword move insn with operands OPERANDS. */ char * output_move_double (operands) rtx *operands; { enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1; rtx latehalf[2]; rtx middlehalf[2]; rtx xops[2]; rtx addreg0 = 0, addreg1 = 0; int dest_overlapped_low = 0; int size = GET_MODE_SIZE (GET_MODE (operands[1])); middlehalf[0] = 0; middlehalf[1] = 0; /* First classify both operands. */ if (REG_P (operands[0])) optype0 = REGOP; else if (offsettable_memref_p (operands[0])) optype0 = OFFSOP; else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) optype0 = POPOP; else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) optype0 = PUSHOP; else if (GET_CODE (operands[0]) == MEM) optype0 = MEMOP; else optype0 = RNDOP; if (REG_P (operands[1])) optype1 = REGOP; else if (CONSTANT_P (operands[1])) optype1 = CNSTOP; else if (offsettable_memref_p (operands[1])) optype1 = OFFSOP; else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) optype1 = POPOP; else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) optype1 = PUSHOP; else if (GET_CODE (operands[1]) == MEM) optype1 = MEMOP; else optype1 = RNDOP; /* Check for the cases that the operand constraints are not supposed to allow to happen. Abort if we get one, because generating code for these cases is painful. */ if (optype0 == RNDOP || optype1 == RNDOP) abort (); /* If one operand is decrementing and one is incrementing decrement the former register explicitly and change that operand into ordinary indexing. */ if (optype0 == PUSHOP && optype1 == POPOP) { /* ??? Can this ever happen on i386? */ operands[0] = XEXP (XEXP (operands[0], 0), 0); asm_add (-size, operands[0]); if (GET_MODE (operands[1]) == XFmode) operands[0] = gen_rtx (MEM, XFmode, operands[0]); else if (GET_MODE (operands[0]) == DFmode) operands[0] = gen_rtx (MEM, DFmode, operands[0]); else operands[0] = gen_rtx (MEM, DImode, operands[0]); optype0 = OFFSOP; } if (optype0 == POPOP && optype1 == PUSHOP) { /* ??? Can this ever happen on i386? */ operands[1] = XEXP (XEXP (operands[1], 0), 0); asm_add (-size, operands[1]); if (GET_MODE (operands[1]) == XFmode) operands[1] = gen_rtx (MEM, XFmode, operands[1]); else if (GET_MODE (operands[1]) == DFmode) operands[1] = gen_rtx (MEM, DFmode, operands[1]); else operands[1] = gen_rtx (MEM, DImode, operands[1]); optype1 = OFFSOP; } /* If an operand is an unoffsettable memory ref, find a register we can increment temporarily to make it refer to the second word. */ if (optype0 == MEMOP) addreg0 = find_addr_reg (XEXP (operands[0], 0)); if (optype1 == MEMOP) addreg1 = find_addr_reg (XEXP (operands[1], 0)); /* Ok, we can do one word at a time. Normally we do the low-numbered word first, but if either operand is autodecrementing then we do the high-numbered word first. In either case, set up in LATEHALF the operands to use for the high-numbered word and in some cases alter the operands in OPERANDS to be suitable for the low-numbered word. */ if (size == 12) { if (optype0 == REGOP) { middlehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2); } else if (optype0 == OFFSOP) { middlehalf[0] = adj_offsettable_operand (operands[0], 4); latehalf[0] = adj_offsettable_operand (operands[0], 8); } else { middlehalf[0] = operands[0]; latehalf[0] = operands[0]; } if (optype1 == REGOP) { middlehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); } else if (optype1 == OFFSOP) { middlehalf[1] = adj_offsettable_operand (operands[1], 4); latehalf[1] = adj_offsettable_operand (operands[1], 8); } else if (optype1 == CNSTOP) { if (GET_CODE (operands[1]) == CONST_DOUBLE) { REAL_VALUE_TYPE r; long l[3]; REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); operands[1] = GEN_INT (l[0]); middlehalf[1] = GEN_INT (l[1]); latehalf[1] = GEN_INT (l[2]); } else if (CONSTANT_P (operands[1])) /* No non-CONST_DOUBLE constant should ever appear here. */ abort (); } else { middlehalf[1] = operands[1]; latehalf[1] = operands[1]; } } else /* size is not 12: */ { if (optype0 == REGOP) latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); else if (optype0 == OFFSOP) latehalf[0] = adj_offsettable_operand (operands[0], 4); else latehalf[0] = operands[0]; if (optype1 == REGOP) latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); else if (optype1 == OFFSOP) latehalf[1] = adj_offsettable_operand (operands[1], 4); else if (optype1 == CNSTOP) { if (GET_CODE (operands[1]) == CONST_DOUBLE) split_double (operands[1], &operands[1], &latehalf[1]); else if (CONSTANT_P (operands[1])) { /* ??? jrv: Can this really happen? A DImode constant that isn't a CONST_DOUBLE? */ if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0) latehalf[1] = constm1_rtx; else latehalf[1] = const0_rtx; } } else latehalf[1] = operands[1]; } /* If insn is effectively movd N (sp),-(sp) then we will do the high word first. We should use the adjusted operand 1 (which is N+4 (sp) or N+8 (sp)) for the low word and middle word as well, to compensate for the first decrement of sp. */ if (optype0 == PUSHOP && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) middlehalf[1] = operands[1] = latehalf[1]; /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), if the upper part of reg N does not appear in the MEM, arrange to emit the move late-half first. Otherwise, compute the MEM address into the upper part of N and use that as a pointer to the memory operand. */ if (optype0 == REGOP && (optype1 == OFFSOP || optype1 == MEMOP)) { if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)) && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0))) { /* If both halves of dest are used in the src memory address, compute the address into latehalf of dest. */ compadr: xops[0] = latehalf[0]; xops[1] = XEXP (operands[1], 0); output_asm_insn (AS2 (lea%L0,%a1,%0), xops); if( GET_MODE (operands[1]) == XFmode ) { /* abort (); */ operands[1] = gen_rtx (MEM, XFmode, latehalf[0]); middlehalf[1] = adj_offsettable_operand (operands[1], size-8); latehalf[1] = adj_offsettable_operand (operands[1], size-4); } else { operands[1] = gen_rtx (MEM, DImode, latehalf[0]); latehalf[1] = adj_offsettable_operand (operands[1], size-4); } } else if (size == 12 && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0))) { /* Check for two regs used by both source and dest. */ if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)) || reg_mentioned_p (latehalf[0], XEXP (operands[1], 0))) goto compadr; /* JRV says this can't happen: */ if (addreg0 || addreg1) abort(); /* Only the middle reg conflicts; simply put it last. */ output_asm_insn (singlemove_string (operands), operands); output_asm_insn (singlemove_string (latehalf), latehalf); output_asm_insn (singlemove_string (middlehalf), middlehalf); return ""; } else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))) /* If the low half of dest is mentioned in the source memory address, the arrange to emit the move late half first. */ dest_overlapped_low = 1; } /* If one or both operands autodecrementing, do the two words, high-numbered first. */ /* Likewise, the first move would clobber the source of the second one, do them in the other order. This happens only for registers; such overlap can't happen in memory unless the user explicitly sets it up, and that is an undefined circumstance. */ /* if (optype0 == PUSHOP || optype1 == PUSHOP || (optype0 == REGOP && optype1 == REGOP && REGNO (operands[0]) == REGNO (latehalf[1])) || dest_overlapped_low) */ if (optype0 == PUSHOP || optype1 == PUSHOP || (optype0 == REGOP && optype1 == REGOP && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) || REGNO (operands[0]) == REGNO (latehalf[1]))) || dest_overlapped_low) { /* Make any unoffsettable addresses point at high-numbered word. */ if (addreg0) asm_add (size-4, addreg0); if (addreg1) asm_add (size-4, addreg1); /* Do that word. */ output_asm_insn (singlemove_string (latehalf), latehalf); /* Undo the adds we just did. */ if (addreg0) asm_add (-4, addreg0); if (addreg1) asm_add (-4, addreg1); if (size == 12) { output_asm_insn (singlemove_string (middlehalf), middlehalf); if (addreg0) asm_add (-4, addreg0); if (addreg1) asm_add (-4, addreg1); } /* Do low-numbered word. */ return singlemove_string (operands); } /* Normal case: do the two words, low-numbered first. */ output_asm_insn (singlemove_string (operands), operands); /* Do the middle one of the three words for long double */ if (size == 12) { if (addreg0) asm_add (4, addreg0); if (addreg1) asm_add (4, addreg1); output_asm_insn (singlemove_string (middlehalf), middlehalf); } /* Make any unoffsettable addresses point at high-numbered word. */ if (addreg0) asm_add (4, addreg0); if (addreg1) asm_add (4, addreg1); /* Do that word. */ output_asm_insn (singlemove_string (latehalf), latehalf); /* Undo the adds we just did. */ if (addreg0) asm_add (4-size, addreg0); if (addreg1) asm_add (4-size, addreg1); return ""; } int standard_80387_constant_p (x) rtx x; { #if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) REAL_VALUE_TYPE d; jmp_buf handler; int is0, is1; if (setjmp (handler)) return 0; set_float_handler (handler); REAL_VALUE_FROM_CONST_DOUBLE (d, x); is0 = REAL_VALUES_EQUAL (d, dconst0); is1 = REAL_VALUES_EQUAL (d, dconst1); set_float_handler (NULL_PTR); if (is0) return 1; if (is1) return 2; /* Note that on the 80387, other constants, such as pi, are much slower to load as standard constants than to load from doubles in memory! */ #endif return 0; } char * output_move_const_single (operands) rtx *operands; { if (FP_REG_P (operands[0])) { int conval = standard_80387_constant_p (operands[1]); if (conval == 1) return "fldz"; if (conval == 2) return "fld1"; } if (GET_CODE (operands[1]) == CONST_DOUBLE) { REAL_VALUE_TYPE r; long l; if (GET_MODE (operands[1]) == XFmode) abort (); REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); REAL_VALUE_TO_TARGET_SINGLE (r, l); operands[1] = GEN_INT (l); } return singlemove_string (operands); } /* Returns 1 if OP is either a symbol reference or a sum of a symbol reference and a constant. */ int symbolic_operand (op, mode) register rtx op; enum machine_mode mode; { switch (GET_CODE (op)) { case SYMBOL_REF: case LABEL_REF: return 1; case CONST: op = XEXP (op, 0); return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF || GET_CODE (XEXP (op, 0)) == LABEL_REF) && GET_CODE (XEXP (op, 1)) == CONST_INT); default: return 0; } } /* Test for a valid operand for a call instruction. Don't allow the arg pointer register or virtual regs since they may change into reg + const, which the patterns can't handle yet. */ int call_insn_operand (op, mode) rtx op; enum machine_mode mode; { if (GET_CODE (op) == MEM && ((CONSTANT_ADDRESS_P (XEXP (op, 0)) /* This makes a difference for PIC. */ && general_operand (XEXP (op, 0), Pmode)) || (GET_CODE (XEXP (op, 0)) == REG && XEXP (op, 0) != arg_pointer_rtx && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) return 1; return 0; } /* Like call_insn_operand but allow (mem (symbol_ref ...)) even if pic. */ int expander_call_insn_operand (op, mode) rtx op; enum machine_mode mode; { if (GET_CODE (op) == MEM && (CONSTANT_ADDRESS_P (XEXP (op, 0)) || (GET_CODE (XEXP (op, 0)) == REG && XEXP (op, 0) != arg_pointer_rtx && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) return 1; return 0; } /* Returns 1 if OP contains a symbol reference */ int symbolic_reference_mentioned_p (op) rtx op; { register char *fmt; register int i; if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) return 1; fmt = GET_RTX_FORMAT (GET_CODE (op)); for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) { if (fmt[i] == 'E') { register int j; for (j = XVECLEN (op, i) - 1; j >= 0; j--) if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) return 1; } else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) return 1; } return 0; } /* Return a legitimate reference for ORIG (an address) using the register REG. If REG is 0, a new pseudo is generated. There are three types of references that must be handled: 1. Global data references must load the address from the GOT, via the PIC reg. An insn is emitted to do this load, and the reg is returned. 2. Static data references must compute the address as an offset from the GOT, whose base is in the PIC reg. An insn is emitted to compute the address into a reg, and the reg is returned. Static data objects have SYMBOL_REF_FLAG set to differentiate them from global data objects. 3. Constant pool addresses must be handled special. They are considered legitimate addresses, but only if not used with regs. When printed, the output routines know to print the reference with the PIC reg, even though the PIC reg doesn't appear in the RTL. GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC reg also appears in the address (except for constant pool references, noted above). "switch" statements also require special handling when generating PIC code. See comments by the `casesi' insn in i386.md for details. */ rtx legitimize_pic_address (orig, reg) rtx orig; rtx reg; { rtx addr = orig; rtx new = orig; if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF) { if (GET_CODE (addr) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (addr)) reg = new = orig; else { if (reg == 0) reg = gen_reg_rtx (Pmode); if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FLAG (addr)) new = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig); else new = gen_rtx (MEM, Pmode, gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig)); emit_move_insn (reg, new); } current_function_uses_pic_offset_table = 1; return reg; } else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) { rtx base; if (GET_CODE (addr) == CONST) { addr = XEXP (addr, 0); if (GET_CODE (addr) != PLUS) abort (); } if (XEXP (addr, 0) == pic_offset_table_rtx) return orig; if (reg == 0) reg = gen_reg_rtx (Pmode); base = legitimize_pic_address (XEXP (addr, 0), reg); addr = legitimize_pic_address (XEXP (addr, 1), base == reg ? NULL_RTX : reg); if (GET_CODE (addr) == CONST_INT) return plus_constant (base, INTVAL (addr)); if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1))) { base = gen_rtx (PLUS, Pmode, base, XEXP (addr, 0)); addr = XEXP (addr, 1); } return gen_rtx (PLUS, Pmode, base, addr); } return new; } /* Emit insns to move operands[1] into operands[0]. */ void emit_pic_move (operands, mode) rtx *operands; enum machine_mode mode; { rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1])) operands[1] = (rtx) force_reg (SImode, operands[1]); else operands[1] = legitimize_pic_address (operands[1], temp); } /* This function generates the assembly code for function entry. FILE is an stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. */ void function_prologue (file, size) FILE *file; int size; { register int regno; int limit; rtx xops[4]; int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table || current_function_uses_const_pool); xops[0] = stack_pointer_rtx; xops[1] = frame_pointer_rtx; xops[2] = GEN_INT (size); if (frame_pointer_needed) { output_asm_insn ("push%L1 %1", xops); output_asm_insn (AS2 (mov%L0,%0,%1), xops); } if (size) output_asm_insn (AS2 (sub%L0,%2,%0), xops); /* Note If use enter it is NOT reversed args. This one is not reversed from intel!! I think enter is slower. Also sdb doesn't like it. But if you want it the code is: { xops[3] = const0_rtx; output_asm_insn ("enter %2,%3", xops); } */ limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); for (regno = limit - 1; regno >= 0; regno--) if ((regs_ever_live[regno] && ! call_used_regs[regno]) || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) { xops[0] = gen_rtx (REG, SImode, regno); output_asm_insn ("push%L0 %0", xops); } if (pic_reg_used) { xops[0] = pic_offset_table_rtx; xops[1] = (rtx) gen_label_rtx (); output_asm_insn (AS1 (call,%P1), xops); ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (xops[1])); output_asm_insn (AS1 (pop%L0,%0), xops); output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops); } } /* Return 1 if it is appropriate to emit `ret' instructions in the body of a function. Do this only if the epilogue is simple, needing a couple of insns. Prior to reloading, we can't tell how many registers must be saved, so return 0 then. If NON_SAVING_SETJMP is defined and true, then it is not possible for the epilogue to be simple, so return 0. This is a special case since NON_SAVING_SETJMP will not cause regs_ever_live to change until final, but jump_optimize may need to know sooner if a `return' is OK. */ int simple_386_epilogue () { int regno; int nregs = 0; int reglimit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table || current_function_uses_const_pool); #ifdef NON_SAVING_SETJMP if (NON_SAVING_SETJMP && current_function_calls_setjmp) return 0; #endif if (! reload_completed) return 0; for (regno = reglimit - 1; regno >= 0; regno--) if ((regs_ever_live[regno] && ! call_used_regs[regno]) || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) nregs++; return nregs == 0 || ! frame_pointer_needed; } /* This function generates the assembly code for function exit. FILE is an stdio stream to output the code to. SIZE is an int: how many units of temporary storage to deallocate. */ void function_epilogue (file, size) FILE *file; int size; { register int regno; register int nregs, limit; int offset; rtx xops[3]; int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table || current_function_uses_const_pool); /* Compute the number of registers to pop */ limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); nregs = 0; for (regno = limit - 1; regno >= 0; regno--) if ((regs_ever_live[regno] && ! call_used_regs[regno]) || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) nregs++; /* sp is often unreliable so we must go off the frame pointer, */ /* In reality, we may not care if sp is unreliable, because we can restore the register relative to the frame pointer. In theory, since each move is the same speed as a pop, and we don't need the leal, this is faster. For now restore multiple registers the old way. */ offset = -size - (nregs * UNITS_PER_WORD); xops[2] = stack_pointer_rtx; if (nregs > 1 || ! frame_pointer_needed) { if (frame_pointer_needed) { xops[0] = adj_offsettable_operand (AT_BP (Pmode), offset); output_asm_insn (AS2 (lea%L2,%0,%2), xops); } for (regno = 0; regno < limit; regno++) if ((regs_ever_live[regno] && ! call_used_regs[regno]) || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) { xops[0] = gen_rtx (REG, SImode, regno); output_asm_insn ("pop%L0 %0", xops); } } else for (regno = 0; regno < limit; regno++) if ((regs_ever_live[regno] && ! call_used_regs[regno]) || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) { xops[0] = gen_rtx (REG, SImode, regno); xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset); output_asm_insn (AS2 (mov%L0,%1,%0), xops); offset += 4; } if (frame_pointer_needed) { /* On i486, mov & pop is faster than "leave". */ if (TARGET_486) { xops[0] = frame_pointer_rtx; output_asm_insn (AS2 (mov%L2,%0,%2), xops); output_asm_insn ("pop%L0 %0", xops); } else output_asm_insn ("leave", xops); } else if (size) { /* If there is no frame pointer, we must still release the frame. */ xops[0] = GEN_INT (size); output_asm_insn (AS2 (add%L2,%0,%2), xops); } if (current_function_pops_args && current_function_args_size) { xops[1] = GEN_INT (current_function_pops_args); /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If asked to pop more, pop return address, do explicit add, and jump indirectly to the caller. */ if (current_function_pops_args >= 32768) { /* ??? Which register to use here? */ xops[0] = gen_rtx (REG, SImode, 2); output_asm_insn ("pop%L0 %0", xops); output_asm_insn (AS2 (add%L2,%1,%2), xops); output_asm_insn ("jmp %*%0", xops); } else output_asm_insn ("ret %1", xops); } else output_asm_insn ("ret", xops); } /* Print an integer constant expression in assembler syntax. Addition and subtraction are the only arithmetic that may appear in these expressions. FILE is the stdio stream to write to, X is the rtx, and CODE is the operand print code from the output string. */ static void output_pic_addr_const (file, x, code) FILE *file; rtx x; int code; { char buf[256]; switch (GET_CODE (x)) { case PC: if (flag_pic) putc ('.', file); else abort (); break; case SYMBOL_REF: case LABEL_REF: if (GET_CODE (x) == SYMBOL_REF) assemble_name (file, XSTR (x, 0)); else { ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (x, 0))); assemble_name (asm_out_file, buf); } if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) fprintf (file, "@GOTOFF(%%ebx)"); else if (code == 'P') fprintf (file, "@PLT"); else if (GET_CODE (x) == LABEL_REF || ! SYMBOL_REF_FLAG (x)) fprintf (file, "@GOT"); else fprintf (file, "@GOTOFF"); break; case CODE_LABEL: ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); assemble_name (asm_out_file, buf); break; case CONST_INT: fprintf (file, "%d", INTVAL (x)); break; case CONST: /* This used to output parentheses around the expression, but that does not work on the 386 (either ATT or BSD assembler). */ output_pic_addr_const (file, XEXP (x, 0), code); break; case CONST_DOUBLE: if (GET_MODE (x) == VOIDmode) { /* We can use %d if the number is <32 bits and positive. */ if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0) fprintf (file, "0x%x%08x", CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x)); else fprintf (file, "%d", CONST_DOUBLE_LOW (x)); } else /* We can't handle floating point constants; PRINT_OPERAND must handle them. */ output_operand_lossage ("floating constant misused"); break; case PLUS: /* Some assemblers need integer constants to appear last (eg masm). */ if (GET_CODE (XEXP (x, 0)) == CONST_INT) { output_pic_addr_const (file, XEXP (x, 1), code); if (INTVAL (XEXP (x, 0)) >= 0) fprintf (file, "+"); output_pic_addr_const (file, XEXP (x, 0), code); } else { output_pic_addr_const (file, XEXP (x, 0), code); if (INTVAL (XEXP (x, 1)) >= 0) fprintf (file, "+"); output_pic_addr_const (file, XEXP (x, 1), code); } break; case MINUS: output_pic_addr_const (file, XEXP (x, 0), code); fprintf (file, "-"); output_pic_addr_const (file, XEXP (x, 1), code); break; default: output_operand_lossage ("invalid expression as operand"); } } /* Meaning of CODE: f -- float insn (print a CONST_DOUBLE as a float rather than in hex). D,L,W,B,Q,S -- print the opcode suffix for specified size of operand. R -- print the prefix for register names. z -- print the opcode suffix for the size of the current operand. * -- print a star (in certain assembler syntax) w -- print the operand as if it's a "word" (HImode) even if it isn't. c -- don't print special prefixes before constant operands. */ void print_operand (file, x, code) FILE *file; rtx x; int code; { if (code) { switch (code) { case '*': if (USE_STAR) putc ('*', file); return; case 'L': PUT_OP_SIZE (code, 'l', file); return; case 'W': PUT_OP_SIZE (code, 'w', file); return; case 'B': PUT_OP_SIZE (code, 'b', file); return; case 'Q': PUT_OP_SIZE (code, 'l', file); return; case 'S': PUT_OP_SIZE (code, 's', file); return; case 'T': PUT_OP_SIZE (code, 't', file); return; case 'z': /* 387 opcodes don't get size suffixes if the operands are registers. */ if (STACK_REG_P (x)) return; /* this is the size of op from size of operand */ switch (GET_MODE_SIZE (GET_MODE (x))) { case 1: PUT_OP_SIZE ('B', 'b', file); return; case 2: PUT_OP_SIZE ('W', 'w', file); return; case 4: if (GET_MODE (x) == SFmode) { PUT_OP_SIZE ('S', 's', file); return; } else PUT_OP_SIZE ('L', 'l', file); return; case 12: PUT_OP_SIZE ('T', 't', file); return; case 8: if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) { #ifdef GAS_MNEMONICS PUT_OP_SIZE ('Q', 'q', file); return; #else PUT_OP_SIZE ('Q', 'l', file); /* Fall through */ #endif } PUT_OP_SIZE ('Q', 'l', file); return; } case 'b': case 'w': case 'k': case 'h': case 'y': case 'P': break; default: { char str[50]; sprintf (str, "invalid operand code `%c'", code); output_operand_lossage (str); } } } if (GET_CODE (x) == REG) { PRINT_REG (x, code, file); } else if (GET_CODE (x) == MEM) { PRINT_PTR (x, file); if (CONSTANT_ADDRESS_P (XEXP (x, 0))) { if (flag_pic) output_pic_addr_const (file, XEXP (x, 0), code); else output_addr_const (file, XEXP (x, 0)); } else output_address (XEXP (x, 0)); } else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) { REAL_VALUE_TYPE r; long l; REAL_VALUE_FROM_CONST_DOUBLE (r, x); REAL_VALUE_TO_TARGET_SINGLE (r, l); PRINT_IMMED_PREFIX (file); fprintf (file, "0x%x", l); } /* These float cases don't actually occur as immediate operands. */ else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) { REAL_VALUE_TYPE r; char dstr[30]; REAL_VALUE_FROM_CONST_DOUBLE (r, x); REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); fprintf (file, "%s", dstr); } else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode) { REAL_VALUE_TYPE r; char dstr[30]; REAL_VALUE_FROM_CONST_DOUBLE (r, x); REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); fprintf (file, "%s", dstr); } else { if (code != 'P') { if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) PRINT_IMMED_PREFIX (file); else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) PRINT_OFFSET_PREFIX (file); } if (flag_pic) output_pic_addr_const (file, x, code); else output_addr_const (file, x); } } /* Print a memory operand whose address is ADDR. */ void print_operand_address (file, addr) FILE *file; register rtx addr; { register rtx reg1, reg2, breg, ireg; rtx offset; switch (GET_CODE (addr)) { case REG: ADDR_BEG (file); fprintf (file, "%se", RP); fputs (hi_reg_name[REGNO (addr)], file); ADDR_END (file); break; case PLUS: reg1 = 0; reg2 = 0; ireg = 0; breg = 0; offset = 0; if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) { offset = XEXP (addr, 0); addr = XEXP (addr, 1); } else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) { offset = XEXP (addr, 1); addr = XEXP (addr, 0); } if (GET_CODE (addr) != PLUS) ; else if (GET_CODE (XEXP (addr, 0)) == MULT) { reg1 = XEXP (addr, 0); addr = XEXP (addr, 1); } else if (GET_CODE (XEXP (addr, 1)) == MULT) { reg1 = XEXP (addr, 1); addr = XEXP (addr, 0); } else if (GET_CODE (XEXP (addr, 0)) == REG) { reg1 = XEXP (addr, 0); addr = XEXP (addr, 1); } else if (GET_CODE (XEXP (addr, 1)) == REG) { reg1 = XEXP (addr, 1); addr = XEXP (addr, 0); } if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT) { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } if (offset != 0) { if (addr != 0) abort (); addr = offset; } if ((reg1 && GET_CODE (reg1) == MULT) || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) { breg = reg2; ireg = reg1; } else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) { breg = reg1; ireg = reg2; } if (ireg != 0 || breg != 0) { int scale = 1; if (addr != 0) { if (GET_CODE (addr) == LABEL_REF) output_asm_label (addr); else { if (flag_pic) output_pic_addr_const (file, addr, 0); else output_addr_const (file, addr); } } if (ireg != 0 && GET_CODE (ireg) == MULT) { scale = INTVAL (XEXP (ireg, 1)); ireg = XEXP (ireg, 0); } /* The stack pointer can only appear as a base register, never an index register, so exchange the regs if it is wrong. */ if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM) { rtx tmp; tmp = breg; breg = ireg; ireg = tmp; } /* output breg+ireg*scale */ PRINT_B_I_S (breg, ireg, scale, file); break; } case MULT: { int scale; if (GET_CODE (XEXP (addr, 0)) == CONST_INT) { scale = INTVAL (XEXP (addr, 0)); ireg = XEXP (addr, 1); } else { scale = INTVAL (XEXP (addr, 1)); ireg = XEXP (addr, 0); } output_addr_const (file, const0_rtx); PRINT_B_I_S ((rtx) 0, ireg, scale, file); } break; default: if (GET_CODE (addr) == CONST_INT && INTVAL (addr) < 0x8000 && INTVAL (addr) >= -0x8000) fprintf (file, "%d", INTVAL (addr)); else { if (flag_pic) output_pic_addr_const (file, addr, 0); else output_addr_const (file, addr); } } } /* Set the cc_status for the results of an insn whose pattern is EXP. On the 80386, we assume that only test and compare insns, as well as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, ASHIFT, LSHIFT, ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully. Also, we assume that jumps, moves and sCOND don't affect the condition codes. All else clobbers the condition codes, by assumption. We assume that ALL integer add, minus, etc. instructions effect the condition codes. This MUST be consistent with i386.md. We don't record any float test or compare - the redundant test & compare check in final.c does not handle stack-like regs correctly. */ void notice_update_cc (exp) rtx exp; { if (GET_CODE (exp) == SET) { /* Jumps do not alter the cc's. */ if (SET_DEST (exp) == pc_rtx) return; /* Moving register or memory into a register: it doesn't alter the cc's, but it might invalidate the RTX's which we remember the cc's came from. (Note that moving a constant 0 or 1 MAY set the cc's). */ if (REG_P (SET_DEST (exp)) && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) { if (cc_status.value1 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)) cc_status.value1 = 0; if (cc_status.value2 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)) cc_status.value2 = 0; return; } /* Moving register into memory doesn't alter the cc's. It may invalidate the RTX's which we remember the cc's came from. */ if (GET_CODE (SET_DEST (exp)) == MEM && (REG_P (SET_SRC (exp)) || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) { if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM) cc_status.value1 = 0; if (cc_status.value2 && GET_CODE (cc_status.value2) == MEM) cc_status.value2 = 0; return; } /* Function calls clobber the cc's. */ else if (GET_CODE (SET_SRC (exp)) == CALL) { CC_STATUS_INIT; return; } /* Tests and compares set the cc's in predictable ways. */ else if (SET_DEST (exp) == cc0_rtx) { CC_STATUS_INIT; cc_status.value1 = SET_SRC (exp); return; } /* Certain instructions effect the condition codes. */ else if (GET_MODE (SET_SRC (exp)) == SImode || GET_MODE (SET_SRC (exp)) == HImode || GET_MODE (SET_SRC (exp)) == QImode) switch (GET_CODE (SET_SRC (exp))) { case ASHIFTRT: case LSHIFTRT: case ASHIFT: case LSHIFT: /* Shifts on the 386 don't set the condition codes if the shift count is zero. */ if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT) { CC_STATUS_INIT; break; } /* We assume that the CONST_INT is non-zero (this rtx would have been deleted if it were zero. */ case PLUS: case MINUS: case NEG: case AND: case IOR: case XOR: cc_status.flags = CC_NO_OVERFLOW; cc_status.value1 = SET_SRC (exp); cc_status.value2 = SET_DEST (exp); break; default: CC_STATUS_INIT; } else { CC_STATUS_INIT; } } else if (GET_CODE (exp) == PARALLEL && GET_CODE (XVECEXP (exp, 0, 0)) == SET) { if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx) return; if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx) { CC_STATUS_INIT; if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0)))) cc_status.flags |= CC_IN_80387; else cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0)); return; } CC_STATUS_INIT; } else { CC_STATUS_INIT; } } /* Split one or more DImode RTL references into pairs of SImode references. The RTL can be REG, offsettable MEM, integer constant, or CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to split and "num" is its length. lo_half and hi_half are output arrays that parallel "operands". */ void split_di (operands, num, lo_half, hi_half) rtx operands[]; int num; rtx lo_half[], hi_half[]; { while (num--) { if (GET_CODE (operands[num]) == REG) { lo_half[num] = gen_rtx (REG, SImode, REGNO (operands[num])); hi_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]) + 1); } else if (CONSTANT_P (operands[num])) { split_double (operands[num], &lo_half[num], &hi_half[num]); } else if (offsettable_memref_p (operands[num])) { lo_half[num] = operands[num]; hi_half[num] = adj_offsettable_operand (operands[num], 4); } else abort(); } } /* Return 1 if this is a valid binary operation on a 387. OP is the expression matched, and MODE is its mode. */ int binary_387_op (op, mode) register rtx op; enum machine_mode mode; { if (mode != VOIDmode && mode != GET_MODE (op)) return 0; switch (GET_CODE (op)) { case PLUS: case MINUS: case MULT: case DIV: return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT; default: return 0; } } /* Return 1 if this is a valid conversion operation on a 387. OP is the expression matched, and MODE is its mode. */ int convert_387_op (op, mode) register rtx op; enum machine_mode mode; { if (mode != VOIDmode && mode != GET_MODE (op)) return 0; switch (GET_CODE (op)) { case FLOAT: return GET_MODE (XEXP (op, 0)) == SImode; case FLOAT_EXTEND: return ((mode == DFmode && GET_MODE (XEXP (op, 0)) == SFmode) || (mode == XFmode && GET_MODE (XEXP (op, 0)) == DFmode) || (mode == XFmode && GET_MODE (XEXP (op, 0)) == SFmode)); default: return 0; } } /* Return 1 if this is a valid shift or rotate operation on a 386. OP is the expression matched, and MODE is its mode. */ int shift_op (op, mode) register rtx op; enum machine_mode mode; { rtx operand = XEXP (op, 0); if (mode != VOIDmode && mode != GET_MODE (op)) return 0; if (GET_MODE (operand) != GET_MODE (op) || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT) return 0; return (GET_CODE (op) == ASHIFT || GET_CODE (op) == ASHIFTRT || GET_CODE (op) == LSHIFTRT || GET_CODE (op) == ROTATE || GET_CODE (op) == ROTATERT); } /* Return 1 if OP is COMPARE rtx with mode VOIDmode. MODE is not used. */ int VOIDmode_compare_op (op, mode) register rtx op; enum machine_mode mode; { return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode; } /* Output code to perform a 387 binary operation in INSN, one of PLUS, MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3] is the expression of the binary operation. The output may either be emitted here, or returned to the caller, like all output_* functions. There is no guarantee that the operands are the same mode, as they might be within FLOAT or FLOAT_EXTEND expressions. */ char * output_387_binary_op (insn, operands) rtx insn; rtx *operands; { rtx temp; char *base_op; static char buf[100]; switch (GET_CODE (operands[3])) { case PLUS: if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) base_op = "fiadd"; else base_op = "fadd"; break; case MINUS: if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) base_op = "fisub"; else base_op = "fsub"; break; case MULT: if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) base_op = "fimul"; else base_op = "fmul"; break; case DIV: if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) base_op = "fidiv"; else base_op = "fdiv"; break; default: abort (); } strcpy (buf, base_op); switch (GET_CODE (operands[3])) { case MULT: case PLUS: if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) { temp = operands[2]; operands[2] = operands[1]; operands[1] = temp; } if (GET_CODE (operands[2]) == MEM) return strcat (buf, AS1 (%z2,%2)); if (NON_STACK_REG_P (operands[1])) { output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1))); RET; } else if (NON_STACK_REG_P (operands[2])) { output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1))); RET; } if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) return strcat (buf, AS2 (p,%2,%0)); if (STACK_TOP_P (operands[0])) return strcat (buf, AS2 (,%y2,%0)); else return strcat (buf, AS2 (,%2,%0)); case MINUS: case DIV: if (GET_CODE (operands[1]) == MEM) return strcat (buf, AS1 (r%z1,%1)); if (GET_CODE (operands[2]) == MEM) return strcat (buf, AS1 (%z2,%2)); if (NON_STACK_REG_P (operands[1])) { output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1))); RET; } else if (NON_STACK_REG_P (operands[2])) { output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1))); RET; } if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2])) abort (); if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) return strcat (buf, AS2 (rp,%2,%0)); if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return strcat (buf, AS2 (p,%1,%0)); if (STACK_TOP_P (operands[0])) { if (STACK_TOP_P (operands[1])) return strcat (buf, AS2 (,%y2,%0)); else return strcat (buf, AS2 (r,%y1,%0)); } else if (STACK_TOP_P (operands[1])) return strcat (buf, AS2 (,%1,%0)); else return strcat (buf, AS2 (r,%2,%0)); default: abort (); } } /* Output code for INSN to convert a float to a signed int. OPERANDS are the insn operands. The output may be SFmode or DFmode and the input operand may be SImode or DImode. As a special case, make sure that the 387 stack top dies if the output mode is DImode, because the hardware requires this. */ char * output_fix_trunc (insn, operands) rtx insn; rtx *operands; { int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; rtx xops[2]; if (! STACK_TOP_P (operands[1]) || (GET_MODE (operands[0]) == DImode && ! stack_top_dies)) abort (); xops[0] = GEN_INT (12); xops[1] = operands[4]; output_asm_insn (AS1 (fnstc%W2,%2), operands); output_asm_insn (AS2 (mov%L2,%2,%4), operands); output_asm_insn (AS2 (mov%B1,%0,%h1), xops); output_asm_insn (AS2 (mov%L4,%4,%3), operands); output_asm_insn (AS1 (fldc%W3,%3), operands); if (NON_STACK_REG_P (operands[0])) output_to_reg (operands[0], stack_top_dies); else if (GET_CODE (operands[0]) == MEM) { if (stack_top_dies) output_asm_insn (AS1 (fistp%z0,%0), operands); else output_asm_insn (AS1 (fist%z0,%0), operands); } else abort (); return AS1 (fldc%W2,%2); } /* Output code for INSN to compare OPERANDS. The two operands might not have the same mode: one might be within a FLOAT or FLOAT_EXTEND expression. If the compare is in mode CCFPEQmode, use an opcode that will not fault if a qNaN is present. */ char * output_float_compare (insn, operands) rtx insn; rtx *operands; { int stack_top_dies; rtx body = XVECEXP (PATTERN (insn), 0, 0); int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode; if (! STACK_TOP_P (operands[0])) abort (); stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; if (STACK_REG_P (operands[1]) && stack_top_dies && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) && REGNO (operands[1]) != FIRST_STACK_REG) { /* If both the top of the 387 stack dies, and the other operand is also a stack register that dies, then this must be a `fcompp' float compare */ if (unordered_compare) output_asm_insn ("fucompp", operands); else output_asm_insn ("fcompp", operands); } else { static char buf[100]; /* Decide if this is the integer or float compare opcode, or the unordered float compare. */ if (unordered_compare) strcpy (buf, "fucom"); else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT) strcpy (buf, "fcom"); else strcpy (buf, "ficom"); /* Modify the opcode if the 387 stack is to be popped. */ if (stack_top_dies) strcat (buf, "p"); if (NON_STACK_REG_P (operands[1])) output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1))); else output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands); } /* Now retrieve the condition code. */ return output_fp_cc0_set (insn); } /* Output opcodes to transfer the results of FP compare or test INSN from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the result of the compare or test is unordered, no comparison operator succeeds except NE. Return an output template, if any. */ char * output_fp_cc0_set (insn) rtx insn; { rtx xops[3]; rtx unordered_label; rtx next; enum rtx_code code; xops[0] = gen_rtx (REG, HImode, 0); output_asm_insn (AS1 (fnsts%W0,%0), xops); if (! TARGET_IEEE_FP) return "sahf"; next = next_cc0_user (insn); if (next == NULL_RTX) abort (); if (GET_CODE (next) == JUMP_INSN && GET_CODE (PATTERN (next)) == SET && SET_DEST (PATTERN (next)) == pc_rtx && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) { code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); } else if (GET_CODE (PATTERN (next)) == SET) { code = GET_CODE (SET_SRC (PATTERN (next))); } else abort (); xops[0] = gen_rtx (REG, QImode, 0); switch (code) { case GT: xops[1] = GEN_INT (0x45); output_asm_insn (AS2 (and%B0,%1,%h0), xops); /* je label */ break; case LT: xops[1] = GEN_INT (0x45); xops[2] = GEN_INT (0x01); output_asm_insn (AS2 (and%B0,%1,%h0), xops); output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); /* je label */ break; case GE: xops[1] = GEN_INT (0x05); output_asm_insn (AS2 (and%B0,%1,%h0), xops); /* je label */ break; case LE: xops[1] = GEN_INT (0x45); xops[2] = GEN_INT (0x40); output_asm_insn (AS2 (and%B0,%1,%h0), xops); output_asm_insn (AS1 (dec%B0,%h0), xops); output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); /* jb label */ break; case EQ: xops[1] = GEN_INT (0x45); xops[2] = GEN_INT (0x40); output_asm_insn (AS2 (and%B0,%1,%h0), xops); output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); /* je label */ break; case NE: xops[1] = GEN_INT (0x44); xops[2] = GEN_INT (0x40); output_asm_insn (AS2 (and%B0,%1,%h0), xops); output_asm_insn (AS2 (xor%B0,%2,%h0), xops); /* jne label */ break; case GTU: case LTU: case GEU: case LEU: default: abort (); } RET; } #define MAX_386_STACK_LOCALS 2 static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; /* Define the structure for the machine field in struct function. */ struct machine_function { rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; }; /* Functions to save and restore i386_stack_locals. These will be called, via pointer variables, from push_function_context and pop_function_context. */ void save_386_machine_status (p) struct function *p; { p->machine = (struct machine_function *) xmalloc (sizeof i386_stack_locals); bcopy (i386_stack_locals, p->machine->i386_stack_locals, sizeof i386_stack_locals); } void restore_386_machine_status (p) struct function *p; { bcopy (p->machine->i386_stack_locals, i386_stack_locals, sizeof i386_stack_locals); free (p->machine); } /* Clear stack slot assignments remembered from previous functions. This is called from INIT_EXPANDERS once before RTL is emitted for each function. */ void clear_386_stack_locals () { enum machine_mode mode; int n; for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE; mode = (enum machine_mode) ((int) mode + 1)) for (n = 0; n < MAX_386_STACK_LOCALS; n++) i386_stack_locals[(int) mode][n] = NULL_RTX; /* Arrange to save and restore i386_stack_locals around nested functions. */ save_machine_status = save_386_machine_status; restore_machine_status = restore_386_machine_status; } /* Return a MEM corresponding to a stack slot with mode MODE. Allocate a new slot if necessary. The RTL for a function can have several slots available: N is which slot to use. */ rtx assign_386_stack_local (mode, n) enum machine_mode mode; int n; { if (n < 0 || n >= MAX_386_STACK_LOCALS) abort (); if (i386_stack_locals[(int) mode][n] == NULL_RTX) i386_stack_locals[(int) mode][n] = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); return i386_stack_locals[(int) mode][n]; } gcc-2.5.8/config/i386/i386.h100444 22011 13 165720 5456715005 13645 0ustar kenneruser/* Definitions of target machine for GNU compiler for Intel 80386. Copyright (C) 1988, 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* The purpose of this file is to define the characteristics of the i386, independent of assembler syntax or operating system. Three other files build on this one to describe a specific assembler syntax: bsd386.h, att386.h, and sun386.h. The actual tm.h file for a particular system should include this file, and then the file for the appropriate assembler syntax. Many macros that specify assembler syntax are omitted entirely from this file because they really belong in the files for particular assemblers. These include AS1, AS2, AS3, RP, IP, LPREFIX, L_SIZE, PUT_OP_SIZE, USE_STAR, ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many that start with ASM_ or end in ASM_OP. */ /* Names to predefine in the preprocessor for this target machine. */ #define I386 1 /* Stubs for half-pic support if not OSF/1 reference platform. */ #ifndef HALF_PIC_P #define HALF_PIC_P() 0 #define HALF_PIC_NUMBER_PTRS 0 #define HALF_PIC_NUMBER_REFS 0 #define HALF_PIC_ENCODE(DECL) #define HALF_PIC_DECLARE(NAME) #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.") #define HALF_PIC_ADDRESS_P(X) 0 #define HALF_PIC_PTR(X) X #define HALF_PIC_FINISH(STREAM) #endif /* Run-time compilation parameters selecting different hardware subsets. */ extern int target_flags; /* Macros used in the machine description to test the flags. */ /* configure can arrage to make this 2, to force a 486. */ #ifndef TARGET_CPU_DEFAULT #define TARGET_CPU_DEFAULT 0 #endif /* Compile 80387 insns for floating point (not library calls). */ #define TARGET_80387 (target_flags & 1) /* Compile code for an i486. */ #define TARGET_486 (target_flags & 2) /* Compile using ret insn that pops args. This will not work unless you use prototypes at least for all functions that can take varying numbers of args. */ #define TARGET_RTD (target_flags & 8) /* Compile passing first two args in regs 0 and 1. This exists only to test compiler features that will be needed for RISC chips. It is not usable and is not intended to be usable on this cpu. */ #define TARGET_REGPARM (target_flags & 020) /* Put uninitialized locals into bss, not data. Meaningful only on svr3. */ #define TARGET_SVR3_SHLIB (target_flags & 040) /* Use IEEE floating point comparisons. These handle correctly the cases where the result of a comparison is unordered. Normally SIGFPE is generated in such cases, in which case this isn't needed. */ #define TARGET_IEEE_FP (target_flags & 0100) /* Functions that return a floating point value may return that value in the 387 FPU or in 386 integer registers. If set, this flag causes the 387 to be used, which is compatible with most calling conventions. */ #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & 0200) /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */ #define TARGET_SWITCHES \ { { "80387", 1}, \ { "no-80387", -1}, \ { "soft-float", -1}, \ { "no-soft-float", 1}, \ { "486", 2}, \ { "no-486", -2}, \ { "386", -2}, \ { "rtd", 8}, \ { "no-rtd", -8}, \ { "regparm", 020}, \ { "no-regparm", -020}, \ { "svr3-shlib", 040}, \ { "no-svr3-shlib", -040}, \ { "ieee-fp", 0100}, \ { "no-ieee-fp", -0100}, \ { "fp-ret-in-387", 0200}, \ { "no-fp-ret-in-387", -0200}, \ SUBTARGET_SWITCHES \ { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT}} /* This is meant to be redefined in the host dependent files */ #define SUBTARGET_SWITCHES #define OVERRIDE_OPTIONS \ { \ SUBTARGET_OVERRIDE_OPTIONS \ } /* This is meant to be redefined in the host dependent files */ #define SUBTARGET_OVERRIDE_OPTIONS /* target machine storage layout */ /* Define for XFmode extended real floating point support. This will automatically cause REAL_ARITHMETIC to be defined. */ #define LONG_DOUBLE_TYPE_SIZE 96 /* Define if you don't want extended real, but do want to use the software floating point emulator for REAL_ARITHMETIC and decimal <-> binary conversion. */ /* #define REAL_ARITHMETIC */ /* Define this if most significant byte of a word is the lowest numbered. */ /* That is true on the 80386. */ #define BITS_BIG_ENDIAN 0 /* Define this if most significant byte of a word is the lowest numbered. */ /* That is not true on the 80386. */ #define BYTES_BIG_ENDIAN 0 /* Define this if most significant word of a multiword number is the lowest numbered. */ /* Not true for 80386 */ #define WORDS_BIG_ENDIAN 0 /* number of bits in an addressable storage unit */ #define BITS_PER_UNIT 8 /* Width in bits of a "word", which is the contents of a machine register. Note that this is not necessarily the width of data type `int'; if using 16-bit ints on a 80386, this would still be 32. But on a machine with 16-bit registers, this would be 16. */ #define BITS_PER_WORD 32 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 4 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ #define POINTER_SIZE 32 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ #define PARM_BOUNDARY 32 /* Boundary (in *bits*) on which stack pointer should be aligned. */ #define STACK_BOUNDARY 32 /* Allocation boundary (in *bits*) for the code of a function. For i486, we get better performance by aligning to a cache line (i.e. 16 byte) boundary. */ #define FUNCTION_BOUNDARY (TARGET_486 ? 128 : 32) /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 32 /* Minimum size in bits of the largest boundary to which any and all fundamental data types supported by the hardware might need to be aligned. No data type wants to be aligned rounder than this. The i386 supports 64-bit floating point quantities, but these can be aligned on any 32-bit boundary. */ #define BIGGEST_ALIGNMENT 32 /* Set this non-zero if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 0 /* If bit field type is int, don't let it cross an int, and give entire struct the alignment of an int. */ /* Required on the 386 since it doesn't have bitfield insns. */ #define PCC_BITFIELD_TYPE_MATTERS 1 /* Align loop starts for optimal branching. */ #define ASM_OUTPUT_LOOP_ALIGN(FILE) \ ASM_OUTPUT_ALIGN (FILE, 2) /* This is how to align an instruction for optimal branching. On i486 we'll get better performance by aligning on a cache line (i.e. 16 byte) boundary. */ #define ASM_OUTPUT_ALIGN_CODE(FILE) \ ASM_OUTPUT_ALIGN ((FILE), (TARGET_486 ? 4 : 2)) /* Standard register usage. */ /* This processor has special stack-like registers. See reg-stack.c for details. */ #define STACK_REGS /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. In the 80386 we give the 8 general purpose registers the numbers 0-7. We number the floating point registers 8-15. Note that registers 0-7 can be accessed as a short or int, while only 0-3 may be used with byte `mov' instructions. Reg 16 does not correspond to any hardware register, but instead appears in the RTL as an argument pointer prior to reload, and is eliminated during reloading in favor of either the stack or frame pointer. */ #define FIRST_PSEUDO_REGISTER 17 /* 1 for registers that have pervasive standard uses and are not available for the register allocator. On the 80386, the stack pointer is such, as is the arg pointer. */ #define FIXED_REGISTERS \ /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 } /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. */ #define CALL_USED_REGISTERS \ /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ { 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } /* Macro to conditionally modify fixed_regs/call_used_regs. */ #define CONDITIONAL_REGISTER_USAGE \ { \ if (flag_pic) \ { \ fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ } \ if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ { \ int i; \ HARD_REG_SET x; \ COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ if (TEST_HARD_REG_BIT (x, i)) \ fixed_regs[i] = call_used_regs[i] = 1; \ } \ } /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. Actually there are no two word move instructions for consecutive registers. And only registers 0-3 may have mov byte instructions applied to them. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ (FP_REGNO_P (REGNO) ? 1 \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On the 80386, the first 4 cpu registers can hold any mode while the floating point registers may hold only floating point. Make it clear that the fp regs could not hold a 16-byte float. */ /* The casts to int placate a compiler on a microvax, for cross-compiler testing. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ((REGNO) < 2 ? 1 \ : (REGNO) < 4 ? 1 \ : FP_REGNO_P (REGNO) \ ? (((int) GET_MODE_CLASS (MODE) == (int) MODE_FLOAT \ || (int) GET_MODE_CLASS (MODE) == (int) MODE_COMPLEX_FLOAT) \ && GET_MODE_UNIT_SIZE (MODE) <= 12) \ : (int) (MODE) != (int) QImode) /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. */ #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2)) /* A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2. On the i386, copying between floating-point and fixed-point registers is expensive. */ #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ (((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2)) \ || (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2))) ? 10 \ : 2) /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ /* on the 386 the pc register is %eip, and is not usable as a general register. The ordinary mov instructions won't work */ /* #define PC_REGNUM */ /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM 7 /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM 6 /* First floating point reg */ #define FIRST_FLOAT_REG 8 /* First & last stack-like regs */ #define FIRST_STACK_REG FIRST_FLOAT_REG #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */ #define FRAME_POINTER_REQUIRED 0 /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM 16 /* Register in which static-chain is passed to a function. */ #define STATIC_CHAIN_REGNUM 2 /* Register to hold the addressing base for position independent code access to data items. */ #define PIC_OFFSET_TABLE_REGNUM 3 /* Register in which address to store a structure value arrives in the function. On the 386, the prologue copies this from the stack to register %eax. */ #define STRUCT_VALUE_INCOMING 0 /* Place in which caller passes the structure value address. 0 means push the value on the stack like an argument. */ #define STRUCT_VALUE 0 /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. One of the classes must always be named ALL_REGS and include all hard regs. If there is more than one class, another class must be named NO_REGS and contain no registers. The name GENERAL_REGS must be the name of a class (or an alias for another name such as ALL_REGS). This is the class of registers that is allowed by "g" or "r" in a register constraint. Also, registers outside this class are allocated only when instructions express preferences for them. The classes must be numbered in nondecreasing order; that is, a larger-numbered class must never be contained completely in a smaller-numbered class. For any two classes, it is very desirable that there be another class that represents their union. It might seem that class BREG is unnecessary, since no useful 386 opcode needs reg %ebx. But some systems pass args to the OS in ebx, and the "b" register constraint is useful in asms for syscalls. */ enum reg_class { NO_REGS, AREG, DREG, CREG, BREG, Q_REGS, /* %eax %ebx %ecx %edx */ SIREG, DIREG, INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES #define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS)) /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ { "NO_REGS", \ "AREG", "DREG", "CREG", "BREG", \ "Q_REGS", \ "SIREG", "DIREG", \ "INDEX_REGS", \ "GENERAL_REGS", \ "FP_TOP_REG", "FP_SECOND_REG", \ "FLOAT_REGS", \ "ALL_REGS" } /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS \ { 0, \ 0x1, 0x2, 0x4, 0x8, /* AREG, DREG, CREG, BREG */ \ 0xf, /* Q_REGS */ \ 0x10, 0x20, /* SIREG, DIREG */ \ 0x1007f, /* INDEX_REGS */ \ 0x100ff, /* GENERAL_REGS */ \ 0x0100, 0x0200, /* FP_TOP_REG, FP_SECOND_REG */ \ 0xff00, /* FLOAT_REGS */ \ 0x1ffff } /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ extern enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) /* When defined, the compiler allows registers explicitly used in the rtl to be used as spill registers but prevents the compiler from extending the lifetime of these registers. */ #define SMALL_REGISTER_CLASSES #define QI_REG_P(X) \ (REG_P (X) && REGNO (X) < 4) #define NON_QI_REG_P(X) \ (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) #define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) #define STACK_REG_P(xop) (REG_P (xop) && \ REGNO (xop) >= FIRST_STACK_REG && \ REGNO (xop) <= LAST_STACK_REG) #define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop)) #define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG) /* Try to maintain the accuracy of the death notes for regs satisfying the following. Important for stack like regs, to know when to pop. */ /* #define PRESERVE_DEATH_INFO_REGNO_P(x) FP_REGNO_P(x) */ /* 1 if register REGNO can magically overlap other regs. Note that nonzero values work only in very special circumstances. */ /* #define OVERLAPPING_REGNO_P(REGNO) FP_REGNO_P (REGNO) */ /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS INDEX_REGS #define BASE_REG_CLASS GENERAL_REGS /* Get reg_class from a letter such as appears in the machine description. */ #define REG_CLASS_FROM_LETTER(C) \ ((C) == 'r' ? GENERAL_REGS : \ (C) == 'q' ? Q_REGS : \ (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ ? FLOAT_REGS \ : NO_REGS) : \ (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ ? FP_TOP_REG \ : NO_REGS) : \ (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ ? FP_SECOND_REG \ : NO_REGS) : \ (C) == 'a' ? AREG : \ (C) == 'b' ? BREG : \ (C) == 'c' ? CREG : \ (C) == 'd' ? DREG : \ (C) == 'D' ? DIREG : \ (C) == 'S' ? SIREG : NO_REGS) /* The letters I, J, K, L and M in a register constraint string can be used to stand for particular ranges of immediate operands. This macro defines what the ranges are. C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. I is for non-DImode shifts. J is for DImode shifts. K and L are for an `andsi' optimization. M is for shifts that can be executed by the "lea" opcode. */ #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 : \ (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 : \ (C) == 'K' ? (VALUE) == 0xff : \ (C) == 'L' ? (VALUE) == 0xffff : \ (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 : \ 0) /* Similar, but for floating constants, and defining letters G and H. Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if TARGET_387 isn't set, because the stack register converter may need to load 0.0 into the function value register. */ #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'G' ? standard_80387_constant_p (VALUE) : 0) /* Place additional restrictions on the register class to use when it is necessary to be able to hold a value of mode MODE in a reload register for which class CLASS would ordinarily be used. */ #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ ((MODE) == QImode && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \ ? Q_REGS : (CLASS)) /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. On the 80386 series, we prevent floating constants from being reloaded into floating registers (since no move-insn can do that) and we ensure that QImodes aren't reloaded into the esi or edi reg. */ /* Put float CONST_DOUBLE in the constant pool instead of fp regs. QImode must go into class Q_REGS. Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and movdf to do mem-to-mem moves through integer regs. */ #define PREFERRED_RELOAD_CLASS(X,CLASS) \ (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode ? NO_REGS \ : GET_MODE (X) == QImode && ! reg_class_subset_p (CLASS, Q_REGS) ? Q_REGS \ : ((CLASS) == ALL_REGS \ && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) ? GENERAL_REGS \ : (CLASS)) /* If we are copying between general and FP registers, we need a memory location. */ #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ ((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2)) \ || (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2))) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ /* On the 80386, this is the size of MODE in words, except in the FP regs, where a single reg is always enough. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ (FLOAT_CLASS_P (CLASS) ? 1 : \ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack makes the stack pointer a smaller address. */ #define STACK_GROWS_DOWNWARD /* Define this if the nominal address of the stack frame is at the high-address end of the local variables; that is, each additional local variable allocated goes at a more negative offset in the frame. */ #define FRAME_GROWS_DOWNWARD /* Offset within stack frame to start allocating local variables at. If FRAME_GROWS_DOWNWARD, this is the offset to the END of the first local allocated. Otherwise, it is the offset to the BEGINNING of the first local allocated. */ #define STARTING_FRAME_OFFSET 0 /* If we generate an insn to push BYTES bytes, this says how many the stack pointer really advances by. On 386 pushw decrements by exactly 2 no matter what the position was. On the 386 there is no pushb; we use pushw instead, and this has the effect of rounding up to 2. */ #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & (-2)) /* Offset of first parameter from the argument pointer register value. */ #define FIRST_PARM_OFFSET(FNDECL) 0 /* Value is the number of bytes of arguments automatically popped when returning from a subroutine call. FUNTYPE is the data type of the function (as a tree), or for a library call it is an identifier node for the subroutine name. SIZE is the number of bytes of arguments passed on the stack. On the 80386, the RTD insn may be used to pop them if the number of args is fixed, but if the number is variable then the caller must pop them all. RTD can't be used for library calls now because the library is compiled with the Unix compiler. Use of RTD is a selectable option, since it is incompatible with standard Unix calling sequences. If the option is not selected, the caller must always pop the args. */ #define RETURN_POPS_ARGS(FUNTYPE,SIZE) \ (TREE_CODE (FUNTYPE) == IDENTIFIER_NODE ? 0 \ : (TARGET_RTD \ && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ == void_type_node))) ? (SIZE) \ : (aggregate_value_p (TREE_TYPE (FUNTYPE))) ? GET_MODE_SIZE (Pmode) : 0) /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ gen_rtx (REG, TYPE_MODE (VALTYPE), \ VALUE_REGNO (TYPE_MODE (VALTYPE))) /* Define how to find the value returned by a library function assuming the value has mode MODE. */ #define LIBCALL_VALUE(MODE) \ gen_rtx (REG, MODE, VALUE_REGNO (MODE)) /* Define the size of the result block used for communication between untyped_call and untyped_return. The block contains a DImode value followed by the block used by fnsave and frstor. */ #define APPLY_RESULT_SIZE (8+108) /* 1 if N is a possible register number for function argument passing. On the 80386, no registers are used in this way. *NOTE* -mregparm does not work. It exists only to test register calling conventions. */ #define FUNCTION_ARG_REGNO_P(N) 0 /* Define a data type for recording info about an argument list during the scan of that argument list. This data type should hold all necessary information about the function itself and about the args processed so far, enough to enable macros such as FUNCTION_ARG to determine where the next arg should go. On the 80386, this is a single integer, which is a number of bytes of arguments scanned so far. */ #define CUMULATIVE_ARGS int /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. On the 80386, the offset starts at 0. */ #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ ((CUM) = 0) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ ((CUM) += ((MODE) != BLKmode \ ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ : (int_size_in_bytes (TYPE) + 3) & ~3)) /* Define where to put the arguments to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. MODE is the argument's machine mode. TYPE is the data type of the argument (as a tree). This is null for libcalls where that information may not be available. CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called. NAMED is nonzero if this argument is a named parameter (otherwise it is an extra parameter matching an ellipsis). */ /* On the 80386 all args are pushed, except if -mregparm is specified then the first two words of arguments are passed in EAX, EDX. *NOTE* -mregparm does not work. It exists only to test register calling conventions. */ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0) /* For an arg passed partly in registers and partly in memory, this is the number of registers used. For args passed entirely in registers or entirely in memory, zero. */ #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ ((TARGET_REGPARM && (CUM) < 8 \ && 8 < ((CUM) + ((MODE) == BLKmode \ ? int_size_in_bytes (TYPE) \ : GET_MODE_SIZE (MODE)))) \ ? 2 - (CUM) / 4 : 0) /* This macro generates the assembly code for function entry. FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. Refer to the array `regs_ever_live' to determine which registers to save; `regs_ever_live[I]' is nonzero if register number I is ever used in the function. This macro is responsible for knowing which registers should not be saved even if used. */ #define FUNCTION_PROLOGUE(FILE, SIZE) \ function_prologue (FILE, SIZE) /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ #define FUNCTION_PROFILER(FILE, LABELNO) \ { \ if (flag_pic) \ { \ fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \ LPREFIX, (LABELNO)); \ fprintf (FILE, "\tcall *_mcount@GOT(%%ebx)\n"); \ } \ else \ { \ fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO)); \ fprintf (FILE, "\tcall _mcount\n"); \ } \ } /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, the stack pointer does not matter. The value is tested only in functions that have frame pointers. No definition is equivalent to always zero. */ /* Note on the 386 it might be more efficient not to define this since we have to restore it ourselves from the frame pointer, in order to use pop */ #define EXIT_IGNORE_STACK 1 /* This macro generates the assembly code for function exit, on machines that need it. If FUNCTION_EPILOGUE is not defined then individual return instructions are generated for each return statement. Args are same as for FUNCTION_PROLOGUE. The function epilogue should not depend on the current stack pointer! It should use the frame pointer only. This is mandatory because of alloca; we also take advantage of it to omit stack adjustments before returning. If the last non-note insn in the function is a BARRIER, then there is no need to emit a function prologue, because control does not fall off the end. This happens if the function ends in an "exit" call, or if a `return' insn is emitted directly into the function. */ #define FUNCTION_EPILOGUE(FILE, SIZE) \ do { \ rtx last = get_last_insn (); \ if (last && GET_CODE (last) == NOTE) \ last = prev_nonnote_insn (last); \ if (! last || GET_CODE (last) != BARRIER) \ function_epilogue (FILE, SIZE); \ } while (0) /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. */ /* On the 386, the trampoline contains three instructions: mov #STATIC,ecx mov #FUNCTION,eax jmp @eax */ #define TRAMPOLINE_TEMPLATE(FILE) \ { \ ASM_OUTPUT_CHAR (FILE, GEN_INT (0xb9)); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_CHAR (FILE, GEN_INT (0xb8)); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_CHAR (FILE, GEN_INT (0xff)); \ ASM_OUTPUT_CHAR (FILE, GEN_INT (0xe0)); \ } /* Length in units of the trampoline for entering a nested function. */ #define TRAMPOLINE_SIZE 12 /* Emit RTL insns to initialize the variable parts of a trampoline. FNADDR is an RTX for the address of the function's pure code. CXT is an RTX for the static chain value for the function. */ #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 1)), CXT); \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 6)), FNADDR); \ } /* Definitions for register eliminations. This is an array of structures. Each structure initializes one pair of eliminable registers. The "from" register number is given first, followed by "to". Eliminations of the same "from" register are listed in order of preference. We have two registers that can be eliminated on the i386. First, the frame pointer register can often be eliminated in favor of the stack pointer register. Secondly, the argument pointer register can always be eliminated; it is replaced with either the stack or frame pointer. */ #define ELIMINABLE_REGS \ {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} /* Given FROM and TO register numbers, say whether this elimination is allowed. Frame pointer elimination is automatically handled. For the i386, if frame pointer elimination is being done, we would like to convert ap into sp, not fp. All other eliminations are valid. */ #define CAN_ELIMINATE(FROM, TO) \ ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ ? ! frame_pointer_needed \ : 1) /* Define the offset between two registers, one to be eliminated, and the other its replacement, at the start of a routine. */ #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ { \ if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ (OFFSET) = 8; /* Skip saved PC and previous frame pointer */ \ else \ { \ int regno; \ int offset = 0; \ \ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \ if ((regs_ever_live[regno] && ! call_used_regs[regno]) \ || (current_function_uses_pic_offset_table \ && regno == PIC_OFFSET_TABLE_REGNUM)) \ offset += 4; \ \ (OFFSET) = offset + get_frame_size (); \ \ if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ (OFFSET) += 4; /* Skip saved PC */ \ } \ } /* Addressing modes, and classification of registers for them. */ /* #define HAVE_POST_INCREMENT */ /* #define HAVE_POST_DECREMENT */ /* #define HAVE_PRE_DECREMENT */ /* #define HAVE_PRE_INCREMENT */ /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. */ #define REGNO_OK_FOR_INDEX_P(REGNO) \ ((REGNO) < STACK_POINTER_REGNUM \ || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM) #define REGNO_OK_FOR_BASE_P(REGNO) \ ((REGNO) <= STACK_POINTER_REGNUM \ || (REGNO) == ARG_POINTER_REGNUM \ || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM) #define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4) #define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5) /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. The usual definition accepts all pseudo regs; the other rejects them unless they have been allocated suitable hard regs. The symbol REG_OK_STRICT causes the latter definition to be used. Most source files want to accept pseudo regs in the hope that they will get allocated to the class that the insn wants them to be in. Source files for reload pass need to be strict. After reload, it makes no difference, since pseudo regs have been eliminated by then. */ #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ #define REG_OK_FOR_INDEX_P(X) \ (REGNO (X) < STACK_POINTER_REGNUM \ || REGNO (X) >= FIRST_PSEUDO_REGISTER) /* Nonzero if X is a hard reg that can be used as a base reg of if it is a pseudo reg. */ /* ?wfs */ #define REG_OK_FOR_BASE_P(X) \ (REGNO (X) <= STACK_POINTER_REGNUM \ || REGNO (X) == ARG_POINTER_REGNUM \ || REGNO(X) >= FIRST_PSEUDO_REGISTER) #define REG_OK_FOR_STRREG_P(X) \ (REGNO (X) == 4 || REGNO (X) == 5 || REGNO (X) >= FIRST_PSEUDO_REGISTER) #else /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) #define REG_OK_FOR_STRREG_P(X) \ (REGNO_OK_FOR_DIREG_P (REGNO (X)) || REGNO_OK_FOR_SIREG_P (REGNO (X))) #endif /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, except for CONSTANT_ADDRESS_P which is usually machine-independent. See legitimize_pic_address in i386.c for details as to what constitutes a legitimate address when -fpic is used. */ #define MAX_REGS_PER_ADDRESS 2 #define CONSTANT_ADDRESS_P(X) \ (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ || GET_CODE (X) == HIGH) /* Nonzero if the constant value X is a legitimate general operand. It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ #define LEGITIMATE_CONSTANT_P(X) 1 #define GO_IF_INDEXABLE_BASE(X, ADDR) \ if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR #define LEGITIMATE_INDEX_REG_P(X) \ (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) /* Return 1 if X is an index or an index times a scale. */ #define LEGITIMATE_INDEX_P(X) \ (LEGITIMATE_INDEX_REG_P (X) \ || (GET_CODE (X) == MULT \ && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ && GET_CODE (XEXP (X, 1)) == CONST_INT \ && (INTVAL (XEXP (X, 1)) == 2 \ || INTVAL (XEXP (X, 1)) == 4 \ || INTVAL (XEXP (X, 1)) == 8))) /* Go to ADDR if X is an index term, a base reg, or a sum of those. */ #define GO_IF_INDEXING(X, ADDR) \ { if (LEGITIMATE_INDEX_P (X)) goto ADDR; \ GO_IF_INDEXABLE_BASE (X, ADDR); \ if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } /* We used to allow this, but it isn't ever used. || ((GET_CODE (X) == POST_DEC || GET_CODE (X) == POST_INC) \ && REG_P (XEXP (X, 0)) \ && REG_OK_FOR_STRREG_P (XEXP (X, 0))) \ */ #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { \ if (CONSTANT_ADDRESS_P (X) \ && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ goto ADDR; \ GO_IF_INDEXING (X, ADDR); \ if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ { \ rtx x0 = XEXP (X, 0); \ if (! flag_pic || ! SYMBOLIC_CONST (XEXP (X, 1))) \ { GO_IF_INDEXING (x0, ADDR); } \ else if (x0 == pic_offset_table_rtx) \ goto ADDR; \ else if (GET_CODE (x0) == PLUS) \ { \ if (XEXP (x0, 0) == pic_offset_table_rtx) \ { GO_IF_INDEXABLE_BASE (XEXP (x0, 1), ADDR); } \ if (XEXP (x0, 1) == pic_offset_table_rtx) \ { GO_IF_INDEXABLE_BASE (XEXP (x0, 0), ADDR); } \ } \ } \ } /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. OLDX is the address as it was before break_out_memory_refs was called. In some cases it is useful to look at this to decide what needs to be done. MODE and WIN are passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. It is always safe for this macro to do nothing. It exists to recognize opportunities to optimize the output. For the 80386, we handle X+REG by loading X into a register R and using R+REG. R will go in a general reg and indexing will be used. However, if REG is a broken-out memory address or multiplication, nothing needs to be done because REG can certainly go in a general reg. When -fpic is used, special handling is needed for symbolic references. See comments by legitimize_pic_address in i386.c for details. */ #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ { extern rtx legitimize_pic_address (); \ int ch = (X) != (OLDX); \ if (flag_pic && SYMBOLIC_CONST (X)) \ { \ (X) = legitimize_pic_address (X, 0); \ if (memory_address_p (MODE, X)) \ goto WIN; \ } \ if (GET_CODE (X) == PLUS) \ { if (GET_CODE (XEXP (X, 0)) == MULT) \ ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0); \ if (GET_CODE (XEXP (X, 1)) == MULT) \ ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0); \ if (ch && GET_CODE (XEXP (X, 1)) == REG \ && GET_CODE (XEXP (X, 0)) == REG) \ goto WIN; \ if (flag_pic && SYMBOLIC_CONST (XEXP (X, 1))) \ ch = 1, (X) = legitimize_pic_address (X, 0); \ if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ if (GET_CODE (XEXP (X, 0)) == REG) \ { register rtx temp = gen_reg_rtx (Pmode); \ register rtx val = force_operand (XEXP (X, 1), temp); \ if (val != temp) emit_move_insn (temp, val); \ XEXP (X, 1) = temp; \ goto WIN; } \ else if (GET_CODE (XEXP (X, 1)) == REG) \ { register rtx temp = gen_reg_rtx (Pmode); \ register rtx val = force_operand (XEXP (X, 0), temp); \ if (val != temp) emit_move_insn (temp, val); \ XEXP (X, 0) = temp; \ goto WIN; }}} /* Nonzero if the constant value X is a legitimate general operand when generating PIC code. It is given that flag_pic is on and that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ #define LEGITIMATE_PIC_OPERAND_P(X) \ (! SYMBOLIC_CONST (X) \ || (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))) #define SYMBOLIC_CONST(X) \ (GET_CODE (X) == SYMBOL_REF \ || GET_CODE (X) == LABEL_REF \ || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) /* Go to LABEL if ADDR (a legitimate address expression) has an effect that depends on the machine mode it is used for. On the 80386, only postdecrement and postincrement address depend thus (the amount of decrement or increment being the length of the operand). */ #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL /* Define this macro if references to a symbol must be treated differently depending on something about the variable or function named by the symbol (such as what section it is in). On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol so that we may access it directly in the GOT. */ #define ENCODE_SECTION_INFO(DECL) \ do \ { \ if (flag_pic) \ { \ rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \ SYMBOL_REF_FLAG (XEXP (rtl, 0)) \ = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ || ! TREE_PUBLIC (DECL)); \ } \ } \ while (0) /* Initialize data used by insn expanders. This is called from init_emit, once for each function, before code is generated. For 386, clear stack slot assignments remembered from previous functions. */ #define INIT_EXPANDERS clear_386_stack_locals () /* The `FINALIZE_PIC' macro serves as a hook to emit these special codes once the function is being compiled into assembly code, but not before. (It is not done before, because in the case of compiling an inline function, it would lead to multiple PIC prologues being included in functions which used inline functions and were compiled to assembly language.) */ #define FINALIZE_PIC \ do \ { \ extern int current_function_uses_pic_offset_table; \ \ current_function_uses_pic_offset_table |= profile_flag | profile_block_flag; \ } \ while (0) /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE Pmode /* Define this if the tablejump instruction expects the table to contain offsets from the address of the table. Do not define this if the table should contain absolute addresses. */ /* #define CASE_VECTOR_PC_RELATIVE */ /* Specify the tree operation to be used to convert reals to integers. This should be changed to take advantage of fist --wfs ?? */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR /* This is the kind of divide that is easiest to do in the general case. */ #define EASY_DIV_EXPR TRUNC_DIV_EXPR /* Define this as 1 if `char' should by default be signed; else as 0. */ #define DEFAULT_SIGNED_CHAR 1 /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ #define MOVE_MAX 4 /* MOVE_RATIO is the number of move instructions that is better than a block move. Make this large on i386, since the block move is very inefficient with small blocks, and the hard register needs of the block move require much reload work. */ #define MOVE_RATIO 5 /* Define this if zero-extension is slow (more than one real instruction). */ /* #define SLOW_ZERO_EXTEND */ /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS 0 /* Define if shifts truncate the shift count which implies one can omit a sign-extension or zero-extension of a shift count. */ /* One i386, shifts do truncate the count. But bit opcodes don't. */ /* #define SHIFT_COUNT_TRUNCATED */ /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 /* We assume that the store-condition-codes instructions store 0 for false and some other value for true. This is the value stored for true. */ #define STORE_FLAG_VALUE 1 /* When a prototype says `char' or `short', really pass an `int'. (The 386 can't easily push less than an int.) */ #define PROMOTE_PROTOTYPES /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ #define Pmode SImode /* A function address in a call instruction is a byte address (for indexing purposes) so give the MEM rtx a byte's mode. */ #define FUNCTION_MODE QImode /* Define this if addresses of constant functions shouldn't be put through pseudo regs where they can be cse'd. Desirable on the 386 because a CALL with a constant address is not much slower than one with a register address. */ #define NO_FUNCTION_CSE /* Provide the costs of a rtl expression. This is in the body of a switch on CODE. */ #define RTX_COSTS(X,CODE,OUTER_CODE) \ case MULT: \ return COSTS_N_INSNS (10); \ case DIV: \ case UDIV: \ case MOD: \ case UMOD: \ return COSTS_N_INSNS (40); \ case PLUS: \ if (GET_CODE (XEXP (X, 0)) == REG \ && GET_CODE (XEXP (X, 1)) == CONST_INT) \ return 1; \ break; /* Compute the cost of computing a constant rtl expression RTX whose rtx-code is CODE. The body of this macro is a portion of a switch statement. If the code is computed here, return it with a return statement. Otherwise, break from the switch. */ #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ case CONST: \ case LABEL_REF: \ case SYMBOL_REF: \ return flag_pic && SYMBOLIC_CONST (RTX) ? 2 : 0; \ case CONST_DOUBLE: \ { \ int code; \ if (GET_MODE (RTX) == VOIDmode) \ return 2; \ code = standard_80387_constant_p (RTX); \ return code == 1 ? 0 : \ code == 2 ? 1 : \ 2; \ } /* Compute the cost of an address. This is meant to approximate the size and/or execution delay of an insn using that address. If the cost is approximated by the RTL complexity, including CONST_COSTS above, as is usually the case for CISC machines, this macro should not be defined. For aggressively RISCy machines, only one insn format is allowed, so this macro should be a constant. The value of this macro only matters for valid addresses. For i386, it is better to use a complex address than let gcc copy the address into a reg and make a new pseudo. But not if the address requires to two regs - that would mean more pseudos with longer lifetimes. */ #define ADDRESS_COST(RTX) \ ((CONSTANT_P (RTX) \ || (GET_CODE (RTX) == PLUS && CONSTANT_P (XEXP (RTX, 1)) \ && REG_P (XEXP (RTX, 0)))) ? 0 \ : REG_P (RTX) ? 1 \ : 2) /* Add any extra modes needed to represent the condition code. For the i386, we need separate modes when floating-point equality comparisons are being done. */ #define EXTRA_CC_MODES CCFPEQmode /* Define the names for the modes specified above. */ #define EXTRA_CC_NAMES "CCFPEQ" /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, return the mode to be used for the comparison. For floating-point equality comparisons, CCFPEQmode should be used. VOIDmode should be used in all other cases. */ #define SELECT_CC_MODE(OP,X,Y) \ (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ && ((OP) == EQ || (OP) == NE) ? CCFPEQmode : VOIDmode) /* Define the information needed to generate branch and scc insns. This is stored from the compare operation. Note that we can't use "rtx" here since it hasn't been defined! */ extern struct rtx_def *i386_compare_op0, *i386_compare_op1; extern struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); /* Tell final.c how to eliminate redundant test instructions. */ /* Here we define machine-dependent flags and fields in cc_status (see `conditions.h'). */ /* Set if the cc value is actually in the 80387, so a floating point conditional branch must be output. */ #define CC_IN_80387 04000 /* Set if the CC value was stored in a nonstandard way, so that the state of equality is indicated by zero in the carry bit. */ #define CC_Z_IN_NOT_C 010000 /* Store in cc_status the expressions that the condition codes will describe after execution of an instruction whose pattern is EXP. Do not alter them if the instruction would not alter the cc's. */ #define NOTICE_UPDATE_CC(EXP, INSN) \ notice_update_cc((EXP)) /* Output a signed jump insn. Use template NORMAL ordinarily, or FLOAT following a floating point comparison. Use NO_OV following an arithmetic insn that set the cc's before a test insn that was deleted. NO_OV may be zero, meaning final should reinsert the test insn because the jump cannot be handled properly without it. */ #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ { \ if (cc_prev_status.flags & CC_IN_80387) \ return FLOAT; \ if (cc_prev_status.flags & CC_NO_OVERFLOW) \ return NO_OV; \ return NORMAL; \ } /* Control the assembler format that we output, to the extent this does not vary between assemblers. */ /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ /* In order to refer to the first 8 regs as 32 bit regs prefix an "e" For non floating point regs, the following are the HImode names. For float regs, the stack top is sometimes referred to as "%st(0)" instead of just "%st". PRINT_REG handles this with the "y" code. */ #define HI_REGISTER_NAMES \ {"ax","dx","cx","bx","si","di","bp","sp", \ "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","" } #define REGISTER_NAMES HI_REGISTER_NAMES /* Table of additional register names to use in user input. */ #define ADDITIONAL_REGISTER_NAMES \ { "eax", 0, "edx", 1, "ecx", 2, "ebx", 3, \ "esi", 4, "edi", 5, "ebp", 6, "esp", 7, \ "al", 0, "dl", 1, "cl", 2, "bl", 3, \ "ah", 0, "dh", 1, "ch", 2, "bh", 3 } /* Note we are omitting these since currently I don't know how to get gcc to use these, since they want the same but different number as al, and ax. */ /* note the last four are not really qi_registers, but the md will have to never output movb into one of them only a movw . There is no movb into the last four regs */ #define QI_REGISTER_NAMES \ {"al", "dl", "cl", "bl", "si", "di", "bp", "sp",} /* These parallel the array above, and can be used to access bits 8:15 of regs 0 through 3. */ #define QI_HIGH_REGISTER_NAMES \ {"ah", "dh", "ch", "bh", } /* How to renumber registers for dbx and gdb. */ /* {0,2,1,3,6,7,4,5,12,13,14,15,16,17} */ #define DBX_REGISTER_NUMBER(n) \ ((n) == 0 ? 0 : \ (n) == 1 ? 2 : \ (n) == 2 ? 1 : \ (n) == 3 ? 3 : \ (n) == 4 ? 6 : \ (n) == 5 ? 7 : \ (n) == 6 ? 4 : \ (n) == 7 ? 5 : \ (n) + 4) /* This is how to output the definition of a user-level label named NAME, such as the label on a static function or variable NAME. */ #define ASM_OUTPUT_LABEL(FILE,NAME) \ (assemble_name (FILE, NAME), fputs (":\n", FILE)) /* This is how to output an assembler line defining a `double' constant. */ #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { long l[2]; \ REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ if (sizeof (int) == sizeof (long)) \ fprintf (FILE, "%s 0x%x,0x%x\n", ASM_LONG, l[0], l[1]); \ else \ fprintf (FILE, "%s 0x%lx,0x%lx\n", ASM_LONG, l[0], l[1]); \ } while (0) /* This is how to output a `long double' extended real constant. */ #undef ASM_OUTPUT_LONG_DOUBLE #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ do { long l[3]; \ REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ if (sizeof (int) == sizeof (long)) \ fprintf (FILE, "%s 0x%x,0x%x,0x%x\n", ASM_LONG, l[0], l[1], l[2]); \ else \ fprintf (FILE, "%s 0x%lx,0x%lx,0x%lx\n", ASM_LONG, l[0], l[1], l[2]); \ } while (0) /* This is how to output an assembler line defining a `float' constant. */ #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { long l; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ if (sizeof (int) == sizeof (long)) \ fprintf ((FILE), "%s 0x%x\n", ASM_LONG, l); \ else \ fprintf ((FILE), "%s 0x%lx\n", ASM_LONG, l); \ } while (0) /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) /* This is how to output an assembler line defining an `int' constant. */ #define ASM_OUTPUT_INT(FILE,VALUE) \ ( fprintf (FILE, "%s ", ASM_LONG), \ output_addr_const (FILE,(VALUE)), \ putc('\n',FILE)) /* Likewise for `char' and `short' constants. */ /* is this supposed to do align too?? */ #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "%s ", ASM_SHORT), \ output_addr_const (FILE,(VALUE)), \ putc('\n',FILE)) /* #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "%s ", ASM_BYTE_OP), \ output_addr_const (FILE,(VALUE)), \ fputs (",", FILE), \ output_addr_const (FILE,(VALUE)), \ fputs (" >> 8\n",FILE)) */ #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ( fprintf (FILE, "%s ", ASM_BYTE_OP), \ output_addr_const (FILE, (VALUE)), \ putc ('\n', FILE)) /* This is how to output an assembler line for a numeric constant byte. */ #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf ((FILE), "%s 0x%x\n", ASM_BYTE_OP, (VALUE)) /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tpushl e%s\n", reg_names[REGNO]) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tpopl e%s\n", reg_names[REGNO]) /* This is how to output an element of a case-vector that is absolute. */ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "%s %s%d\n", ASM_LONG, LPREFIX, VALUE) /* This is how to output an element of a case-vector that is relative. We don't use these on the 386 yet, because the ATT assembler can't do forward reference the differences. */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\t.word %s%d-%s%d\n",LPREFIX, VALUE,LPREFIX, REL) /* Define the parentheses used to group arithmetic operations in assembler code. */ #define ASM_OPEN_PAREN "" #define ASM_CLOSE_PAREN "" /* Define results of standard character escape sequences. */ #define TARGET_BELL 007 #define TARGET_BS 010 #define TARGET_TAB 011 #define TARGET_NEWLINE 012 #define TARGET_VT 013 #define TARGET_FF 014 #define TARGET_CR 015 /* Print operand X (an rtx) in assembler syntax to file FILE. CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. The CODE z takes the size of operand from the following digit, and outputs b,w,or l respectively. On the 80386, we use several such letters: f -- float insn (print a CONST_DOUBLE as a float rather than in hex). L,W,B,Q,S,T -- print the opcode suffix for specified size of operand. R -- print the prefix for register names. z -- print the opcode suffix for the size of the current operand. * -- print a star (in certain assembler syntax) w -- print the operand as if it's a "word" (HImode) even if it isn't. b -- print the operand as if it's a byte (QImode) even if it isn't. c -- don't print special prefixes before constant operands. */ #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ ((CODE) == '*') /* Print the name of a register based on its machine mode and number. If CODE is 'w', pretend the mode is HImode. If CODE is 'b', pretend the mode is QImode. If CODE is 'k', pretend the mode is SImode. If CODE is 'h', pretend the reg is the `high' byte register. If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ extern char *hi_reg_name[]; extern char *qi_reg_name[]; extern char *qi_high_reg_name[]; #define PRINT_REG(X, CODE, FILE) \ do { if (REGNO (X) == ARG_POINTER_REGNUM) \ abort (); \ fprintf (FILE, "%s", RP); \ switch ((CODE == 'w' ? 2 \ : CODE == 'b' ? 1 \ : CODE == 'k' ? 4 \ : CODE == 'y' ? 3 \ : CODE == 'h' ? 0 \ : GET_MODE_SIZE (GET_MODE (X)))) \ { \ case 3: \ if (STACK_TOP_P (X)) \ { \ fputs ("st(0)", FILE); \ break; \ } \ case 4: \ case 8: \ case 12: \ if (! FP_REG_P (X)) fputs ("e", FILE); \ case 2: \ fputs (hi_reg_name[REGNO (X)], FILE); \ break; \ case 1: \ fputs (qi_reg_name[REGNO (X)], FILE); \ break; \ case 0: \ fputs (qi_high_reg_name[REGNO (X)], FILE); \ break; \ } \ } while (0) #define PRINT_OPERAND(FILE, X, CODE) \ print_operand (FILE, X, CODE) #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ print_operand_address (FILE, ADDR) /* Print the name of a register for based on its machine mode and number. This macro is used to print debugging output. This macro is different from PRINT_REG in that it may be used in programs that are not linked with aux-output.o. */ #define DEBUG_PRINT_REG(X, CODE, FILE) \ do { static char *hi_name[] = HI_REGISTER_NAMES; \ static char *qi_name[] = QI_REGISTER_NAMES; \ fprintf (FILE, "%d %s", REGNO (X), RP); \ if (REGNO (X) == ARG_POINTER_REGNUM) \ { fputs ("argp", FILE); break; } \ if (STACK_TOP_P (X)) \ { fputs ("st(0)", FILE); break; } \ switch (GET_MODE_SIZE (GET_MODE (X))) \ { \ case 12: \ case 8: \ case 4: \ if (! FP_REG_P (X)) fputs ("e", FILE); \ case 2: \ fputs (hi_name[REGNO (X)], FILE); \ break; \ case 1: \ fputs (qi_name[REGNO (X)], FILE); \ break; \ } \ } while (0) /* Output the prefix for an immediate operand, or for an offset operand. */ #define PRINT_IMMED_PREFIX(FILE) fputs (IP, (FILE)) #define PRINT_OFFSET_PREFIX(FILE) fputs (IP, (FILE)) /* Routines in libgcc that return floats must return them in an fp reg, just as other functions do which return such values. These macros make that happen. */ #define FLOAT_VALUE_TYPE float #define INTIFY(FLOATVAL) FLOATVAL /* Nonzero if INSN magically clobbers register REGNO. */ /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) \ (FP_REGNO_P (REGNO) \ && (GET_CODE (INSN) == JUMP_INSN || GET_CODE (INSN) == BARRIER)) */ /* a letter which is not needed by the normal asm syntax, which we can use for operand syntax in the extended asm */ #define ASM_OPERAND_LETTER '#' #define RET return "" #define AT_SP(mode) (gen_rtx (MEM, (mode), stack_pointer_rtx)) /* Local variables: version-control: t End: */ gcc-2.5.8/config/i386/i386.md100444 22011 13 424416 5454204624 14014 0ustar kenneruser;; GCC machine description for Intel 80386. ;; Copyright (C) 1988 Free Software Foundation, Inc. ;; Mostly by William Schelter. ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ;; The original PO technology requires these to be ordered by speed, ;; so that assigner will pick the fastest. ;; See file "rtl.def" for documentation on define_insn, match_*, et. al. ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code ;; updates for most instructions. ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register ;; constraint letters. ;; the special asm out single letter directives following a '%' are: ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of ;; operands[1]. ;; 'L' Print the opcode suffix for a 32-bit integer opcode. ;; 'W' Print the opcode suffix for a 16-bit integer opcode. ;; 'B' Print the opcode suffix for an 8-bit integer opcode. ;; 'S' Print the opcode suffix for a 32-bit float opcode. ;; 'Q' Print the opcode suffix for a 64-bit float opcode. ;; 'b' Print the QImode name of the register for the indicated operand. ;; %b0 would print %al if operands[0] is reg 0. ;; 'w' Likewise, print the HImode name of the register. ;; 'k' Likewise, print the SImode name of the register. ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh. ;; 'y' Print "st(0)" instead of "st" as a register. ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode. ;; UNSPEC usage: ;; 0 This is a `scas' operation. The mode of the UNSPEC is always SImode. ;; operand 0 is the memory address to scan. ;; operand 1 is a register containing the value to scan for. The mode ;; of the scas opcode will be the same as the mode of this operand. ;; operand 2 is the known alignment of operand 0. ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT. ;; operand 0 is the argument for `sin'. ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT. ;; operand 0 is the argument for `cos'. ;; "movl MEM,REG / testl REG,REG" is faster on a 486 than "cmpl $0,MEM". ;; But restricting MEM here would mean that gcc could not remove a redundant ;; test in cases like "incl MEM / je TARGET". ;; ;; We don't want to allow a constant operand for test insns because ;; (set (cc0) (const_int foo)) has no mode information. Such insns will ;; be folded while optimizing anyway. ;; All test insns have expanders that save the operands away without ;; actually generating RTL. The bCOND or sCOND (emitted immediately ;; after the tstM or cmp) will actually emit the tstM or cmpM. (define_insn "tstsi_1" [(set (cc0) (match_operand:SI 0 "nonimmediate_operand" "rm"))] "" "* { if (REG_P (operands[0])) return AS2 (test%L0,%0,%0); operands[1] = const0_rtx; return AS2 (cmp%L0,%1,%0); }") (define_expand "tstsi" [(set (cc0) (match_operand:SI 0 "nonimmediate_operand" ""))] "" " { i386_compare_gen = gen_tstsi_1; i386_compare_op0 = operands[0]; DONE; }") (define_insn "tsthi_1" [(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "rm"))] "" "* { if (REG_P (operands[0])) return AS2 (test%W0,%0,%0); operands[1] = const0_rtx; return AS2 (cmp%W0,%1,%0); }") (define_expand "tsthi" [(set (cc0) (match_operand:HI 0 "nonimmediate_operand" ""))] "" " { i386_compare_gen = gen_tsthi_1; i386_compare_op0 = operands[0]; DONE; }") (define_insn "tstqi_1" [(set (cc0) (match_operand:QI 0 "nonimmediate_operand" "qm"))] "" "* { if (REG_P (operands[0])) return AS2 (test%B0,%0,%0); operands[1] = const0_rtx; return AS2 (cmp%B0,%1,%0); }") (define_expand "tstqi" [(set (cc0) (match_operand:QI 0 "nonimmediate_operand" ""))] "" " { i386_compare_gen = gen_tstqi_1; i386_compare_op0 = operands[0]; DONE; }") (define_insn "tstsf_cc" [(set (cc0) (match_operand:SF 0 "register_operand" "f")) (clobber (match_scratch:HI 1 "=a"))] "TARGET_80387 && ! TARGET_IEEE_FP" "* { if (! STACK_TOP_P (operands[0])) abort (); output_asm_insn (\"ftst\", operands); if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) output_asm_insn (AS1 (fstp,%y0), operands); return (char *) output_fp_cc0_set (insn); }") ;; Don't generate tstsf if generating IEEE code, since the `ftst' opcode ;; isn't IEEE compliant. (define_expand "tstsf" [(parallel [(set (cc0) (match_operand:SF 0 "register_operand" "")) (clobber (match_scratch:HI 1 ""))])] "TARGET_80387 && ! TARGET_IEEE_FP" " { i386_compare_gen = gen_tstsf_cc; i386_compare_op0 = operands[0]; DONE; }") (define_insn "tstdf_cc" [(set (cc0) (match_operand:DF 0 "register_operand" "f")) (clobber (match_scratch:HI 1 "=a"))] "TARGET_80387 && ! TARGET_IEEE_FP" "* { if (! STACK_TOP_P (operands[0])) abort (); output_asm_insn (\"ftst\", operands); if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) output_asm_insn (AS1 (fstp,%y0), operands); return (char *) output_fp_cc0_set (insn); }") ;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode ;; isn't IEEE compliant. (define_expand "tstdf" [(parallel [(set (cc0) (match_operand:DF 0 "register_operand" "")) (clobber (match_scratch:HI 1 ""))])] "TARGET_80387 && ! TARGET_IEEE_FP" " { i386_compare_gen = gen_tstdf_cc; i386_compare_op0 = operands[0]; DONE; }") (define_insn "tstxf_cc" [(set (cc0) (match_operand:XF 0 "register_operand" "f")) (clobber (match_scratch:HI 1 "=a"))] "TARGET_80387 && ! TARGET_IEEE_FP" "* { if (! STACK_TOP_P (operands[0])) abort (); output_asm_insn (\"ftst\", operands); if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) output_asm_insn (AS1 (fstp,%y0), operands); return (char *) output_fp_cc0_set (insn); }") ;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode ;; isn't IEEE compliant. (define_expand "tstxf" [(parallel [(set (cc0) (match_operand:XF 0 "register_operand" "")) (clobber (match_scratch:HI 1 ""))])] "TARGET_80387 && ! TARGET_IEEE_FP" " { i386_compare_gen = gen_tstxf_cc; i386_compare_op0 = operands[0]; DONE; }") ;;- compare instructions. See comments above tstM patterns about ;; expansion of these insns. (define_insn "cmpsi_1" [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "mr,r") (match_operand:SI 1 "general_operand" "ri,mr")))] "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" "* { if (CONSTANT_P (operands[0]) || GET_CODE (operands[1]) == MEM) { cc_status.flags |= CC_REVERSED; return AS2 (cmp%L0,%0,%1); } return AS2 (cmp%L0,%1,%0); }") (define_expand "cmpsi" [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "") (match_operand:SI 1 "general_operand" "")))] "" " { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) operands[0] = force_reg (SImode, operands[0]); i386_compare_gen = gen_cmpsi_1; i386_compare_op0 = operands[0]; i386_compare_op1 = operands[1]; DONE; }") (define_insn "cmphi_1" [(set (cc0) (compare (match_operand:HI 0 "nonimmediate_operand" "mr,r") (match_operand:HI 1 "general_operand" "ri,mr")))] "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" "* { if (CONSTANT_P (operands[0]) || GET_CODE (operands[1]) == MEM) { cc_status.flags |= CC_REVERSED; return AS2 (cmp%W0,%0,%1); } return AS2 (cmp%W0,%1,%0); }") (define_expand "cmphi" [(set (cc0) (compare (match_operand:HI 0 "nonimmediate_operand" "") (match_operand:HI 1 "general_operand" "")))] "" " { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) operands[0] = force_reg (HImode, operands[0]); i386_compare_gen = gen_cmphi_1; i386_compare_op0 = operands[0]; i386_compare_op1 = operands[1]; DONE; }") (define_insn "cmpqi_1" [(set (cc0) (compare (match_operand:QI 0 "nonimmediate_operand" "q,mq") (match_operand:QI 1 "general_operand" "qm,nq")))] "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" "* { if (CONSTANT_P (operands[0]) || GET_CODE (operands[1]) == MEM) { cc_status.flags |= CC_REVERSED; return AS2 (cmp%B0,%0,%1); } return AS2 (cmp%B0,%1,%0); }") (define_expand "cmpqi" [(set (cc0) (compare (match_operand:QI 0 "nonimmediate_operand" "") (match_operand:QI 1 "general_operand" "")))] "" " { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) operands[0] = force_reg (QImode, operands[0]); i386_compare_gen = gen_cmpqi_1; i386_compare_op0 = operands[0]; i386_compare_op1 = operands[1]; DONE; }") ;; These implement float point compares. For each of DFmode and ;; SFmode, there is the normal insn, and an insn where the second operand ;; is converted to the desired mode. (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(match_operand:XF 0 "nonimmediate_operand" "f") (match_operand:XF 1 "nonimmediate_operand" "f")])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(match_operand:XF 0 "register_operand" "f") (float:XF (match_operand:SI 1 "nonimmediate_operand" "rm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(float:XF (match_operand:SI 0 "nonimmediate_operand" "rm")) (match_operand:XF 1 "register_operand" "f")])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(match_operand:XF 0 "register_operand" "f") (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(match_operand:XF 0 "register_operand" "f") (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (compare:CCFPEQ (match_operand:XF 0 "register_operand" "f") (match_operand:XF 1 "register_operand" "f"))) (clobber (match_scratch:HI 2 "=a"))] "TARGET_80387" "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(match_operand:DF 0 "nonimmediate_operand" "f,fm") (match_operand:DF 1 "nonimmediate_operand" "fm,f")])) (clobber (match_scratch:HI 3 "=a,a"))] "TARGET_80387 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(match_operand:DF 0 "register_operand" "f") (float:DF (match_operand:SI 1 "nonimmediate_operand" "rm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(float:DF (match_operand:SI 0 "nonimmediate_operand" "rm")) (match_operand:DF 1 "register_operand" "f")])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(match_operand:DF 0 "register_operand" "f") (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(float_extend:DF (match_operand:SF 0 "nonimmediate_operand" "fm")) (match_operand:DF 1 "register_operand" "f")])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (compare:CCFPEQ (match_operand:DF 0 "register_operand" "f") (match_operand:DF 1 "register_operand" "f"))) (clobber (match_scratch:HI 2 "=a"))] "TARGET_80387" "* return (char *) output_float_compare (insn, operands);") ;; These two insns will never be generated by combine due to the mode of ;; the COMPARE. ;(define_insn "" ; [(set (cc0) ; (compare:CCFPEQ (match_operand:DF 0 "register_operand" "f") ; (float_extend:DF ; (match_operand:SF 1 "register_operand" "f")))) ; (clobber (match_scratch:HI 2 "=a"))] ; "TARGET_80387" ; "* return (char *) output_float_compare (insn, operands);") ; ;(define_insn "" ; [(set (cc0) ; (compare:CCFPEQ (float_extend:DF ; (match_operand:SF 0 "register_operand" "f")) ; (match_operand:DF 1 "register_operand" "f"))) ; (clobber (match_scratch:HI 2 "=a"))] ; "TARGET_80387" ; "* return (char *) output_float_compare (insn, operands);") (define_insn "cmpsf_cc_1" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(match_operand:SF 0 "nonimmediate_operand" "f,fm") (match_operand:SF 1 "nonimmediate_operand" "fm,f")])) (clobber (match_scratch:HI 3 "=a,a"))] "TARGET_80387 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(match_operand:SF 0 "register_operand" "f") (float:SF (match_operand:SI 1 "nonimmediate_operand" "rm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(float:SF (match_operand:SI 0 "nonimmediate_operand" "rm")) (match_operand:SF 1 "register_operand" "f")])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (compare:CCFPEQ (match_operand:SF 0 "register_operand" "f") (match_operand:SF 1 "register_operand" "f"))) (clobber (match_scratch:HI 2 "=a"))] "TARGET_80387" "* return (char *) output_float_compare (insn, operands);") (define_expand "cmpxf" [(set (cc0) (compare (match_operand:XF 0 "register_operand" "") (match_operand:XF 1 "nonimmediate_operand" "")))] "TARGET_80387" " { i386_compare_gen = gen_cmpxf_cc; i386_compare_gen_eq = gen_cmpxf_ccfpeq; i386_compare_op0 = operands[0]; i386_compare_op1 = operands[1]; DONE; }") (define_expand "cmpdf" [(set (cc0) (compare (match_operand:DF 0 "register_operand" "") (match_operand:DF 1 "nonimmediate_operand" "")))] "TARGET_80387" " { i386_compare_gen = gen_cmpdf_cc; i386_compare_gen_eq = gen_cmpdf_ccfpeq; i386_compare_op0 = operands[0]; i386_compare_op1 = operands[1]; DONE; }") (define_expand "cmpsf" [(set (cc0) (compare (match_operand:SF 0 "register_operand" "") (match_operand:SF 1 "nonimmediate_operand" "")))] "TARGET_80387" " { i386_compare_gen = gen_cmpsf_cc; i386_compare_gen_eq = gen_cmpsf_ccfpeq; i386_compare_op0 = operands[0]; i386_compare_op1 = operands[1]; DONE; }") (define_expand "cmpxf_cc" [(parallel [(set (cc0) (compare (match_operand:XF 0 "register_operand" "") (match_operand:XF 1 "register_operand" ""))) (clobber (match_scratch:HI 2 ""))])] "TARGET_80387" "") (define_expand "cmpxf_ccfpeq" [(parallel [(set (cc0) (compare:CCFPEQ (match_operand:XF 0 "register_operand" "") (match_operand:XF 1 "register_operand" ""))) (clobber (match_scratch:HI 2 ""))])] "TARGET_80387" " { if (! register_operand (operands[1], XFmode)) operands[1] = copy_to_mode_reg (XFmode, operands[1]); }") (define_expand "cmpdf_cc" [(parallel [(set (cc0) (compare (match_operand:DF 0 "register_operand" "") (match_operand:DF 1 "register_operand" ""))) (clobber (match_scratch:HI 2 ""))])] "TARGET_80387" "") (define_expand "cmpdf_ccfpeq" [(parallel [(set (cc0) (compare:CCFPEQ (match_operand:DF 0 "register_operand" "") (match_operand:DF 1 "register_operand" ""))) (clobber (match_scratch:HI 2 ""))])] "TARGET_80387" " { if (! register_operand (operands[1], DFmode)) operands[1] = copy_to_mode_reg (DFmode, operands[1]); }") (define_expand "cmpsf_cc" [(parallel [(set (cc0) (compare (match_operand:SF 0 "register_operand" "") (match_operand:SF 1 "register_operand" ""))) (clobber (match_scratch:HI 2 ""))])] "TARGET_80387" "") (define_expand "cmpsf_ccfpeq" [(parallel [(set (cc0) (compare:CCFPEQ (match_operand:SF 0 "register_operand" "") (match_operand:SF 1 "register_operand" ""))) (clobber (match_scratch:HI 2 ""))])] "TARGET_80387" " { if (! register_operand (operands[1], SFmode)) operands[1] = copy_to_mode_reg (SFmode, operands[1]); }") ;; logical compare (define_insn "" [(set (cc0) (and:SI (match_operand:SI 0 "general_operand" "%ro") (match_operand:SI 1 "general_operand" "ri")))] "" "* { /* For small integers, we may actually use testb. */ if (GET_CODE (operands[1]) == CONST_INT && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) && (! REG_P (operands[0]) || QI_REG_P (operands[0]))) { /* We may set the sign bit spuriously. */ if ((INTVAL (operands[1]) & ~0xff) == 0) { cc_status.flags |= CC_NOT_NEGATIVE; return AS2 (test%B0,%1,%b0); } if ((INTVAL (operands[1]) & ~0xff00) == 0) { cc_status.flags |= CC_NOT_NEGATIVE; operands[1] = GEN_INT (INTVAL (operands[1]) >> 8); if (QI_REG_P (operands[0])) return AS2 (test%B0,%1,%h0); else { operands[0] = adj_offsettable_operand (operands[0], 1); return AS2 (test%B0,%1,%b0); } } if (GET_CODE (operands[0]) == MEM && (INTVAL (operands[1]) & ~0xff0000) == 0) { cc_status.flags |= CC_NOT_NEGATIVE; operands[1] = GEN_INT (INTVAL (operands[1]) >> 16); operands[0] = adj_offsettable_operand (operands[0], 2); return AS2 (test%B0,%1,%b0); } if (GET_CODE (operands[0]) == MEM && (INTVAL (operands[1]) & ~0xff000000) == 0) { operands[1] = GEN_INT ((INTVAL (operands[1]) >> 24) & 0xff); operands[0] = adj_offsettable_operand (operands[0], 3); return AS2 (test%B0,%1,%b0); } } if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) return AS2 (test%L0,%1,%0); return AS2 (test%L1,%0,%1); }") (define_insn "" [(set (cc0) (and:HI (match_operand:HI 0 "general_operand" "%ro") (match_operand:HI 1 "general_operand" "ri")))] "" "* { if (GET_CODE (operands[1]) == CONST_INT && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) && (! REG_P (operands[0]) || QI_REG_P (operands[0]))) { if ((INTVAL (operands[1]) & 0xff00) == 0) { /* ??? This might not be necessary. */ if (INTVAL (operands[1]) & 0xffff0000) operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); /* We may set the sign bit spuriously. */ cc_status.flags |= CC_NOT_NEGATIVE; return AS2 (test%B0,%1,%b0); } if ((INTVAL (operands[1]) & 0xff) == 0) { operands[1] = GEN_INT ((INTVAL (operands[1]) >> 8) & 0xff); if (QI_REG_P (operands[0])) return AS2 (test%B0,%1,%h0); else { operands[0] = adj_offsettable_operand (operands[0], 1); return AS2 (test%B0,%1,%b0); } } } if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) return AS2 (test%W0,%1,%0); return AS2 (test%W1,%0,%1); }") (define_insn "" [(set (cc0) (and:QI (match_operand:QI 0 "general_operand" "%qm") (match_operand:QI 1 "general_operand" "qi")))] "" "* { if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) return AS2 (test%B0,%1,%0); return AS2 (test%B1,%0,%1); }") ;; move instructions. ;; There is one for each machine mode, ;; and each is preceded by a corresponding push-insn pattern ;; (since pushes are not general_operands on the 386). (define_insn "" [(set (match_operand:SI 0 "push_operand" "=<") (match_operand:SI 1 "general_operand" "g"))] "! TARGET_486" "push%L0 %1") ;; On a 486, it is faster to move MEM to a REG and then push, rather than ;; push MEM directly. (define_insn "" [(set (match_operand:SI 0 "push_operand" "=<") (match_operand:SI 1 "general_operand" "ri"))] "TARGET_486" "push%L0 %1") ;; General case of fullword move. ;; If generating PIC code and operands[1] is a symbolic CONST, emit a ;; move to get the address of the symbolic object from the GOT. (define_expand "movsi" [(set (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))] "" " { extern int flag_pic; if (flag_pic && SYMBOLIC_CONST (operands[1])) emit_pic_move (operands, SImode); }") ;; On i486, incl reg is faster than movl $1,reg. (define_insn "" [(set (match_operand:SI 0 "general_operand" "=g,r") (match_operand:SI 1 "general_operand" "ri,m"))] "" "* { rtx link; if (operands[1] == const0_rtx && REG_P (operands[0])) return AS2 (xor%L0,%0,%0); if (operands[1] == const1_rtx && (link = find_reg_note (insn, REG_WAS_0, 0)) /* Make sure the insn that stored the 0 is still present. */ && ! INSN_DELETED_P (XEXP (link, 0)) && GET_CODE (XEXP (link, 0)) != NOTE /* Make sure cross jumping didn't happen here. */ && no_labels_between_p (XEXP (link, 0), insn) /* Make sure the reg hasn't been clobbered. */ && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) /* Fastest way to change a 0 to a 1. */ return AS1 (inc%L0,%0); return AS2 (mov%L0,%1,%0); }") (define_insn "" [(set (match_operand:HI 0 "push_operand" "=<") (match_operand:HI 1 "general_operand" "g"))] "" "push%W0 %1") ;; On i486, an incl and movl are both faster than incw and movw. (define_insn "movhi" [(set (match_operand:HI 0 "general_operand" "=g,r") (match_operand:HI 1 "general_operand" "ri,m"))] "" "* { rtx link; if (REG_P (operands[0]) && operands[1] == const0_rtx) return AS2 (xor%L0,%k0,%k0); if (REG_P (operands[0]) && operands[1] == const1_rtx && (link = find_reg_note (insn, REG_WAS_0, 0)) /* Make sure the insn that stored the 0 is still present. */ && ! INSN_DELETED_P (XEXP (link, 0)) && GET_CODE (XEXP (link, 0)) != NOTE /* Make sure cross jumping didn't happen here. */ && no_labels_between_p (XEXP (link, 0), insn) /* Make sure the reg hasn't been clobbered. */ && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) /* Fastest way to change a 0 to a 1. */ return AS1 (inc%L0,%k0); if (REG_P (operands[0])) { if (REG_P (operands[1])) return AS2 (mov%L0,%k1,%k0); else if (CONSTANT_P (operands[1])) return AS2 (mov%L0,%1,%k0); } return AS2 (mov%W0,%1,%0); }") (define_insn "movstricthi" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+g,r")) (match_operand:HI 1 "general_operand" "ri,m"))] "" "* { rtx link; if (operands[1] == const0_rtx && REG_P (operands[0])) return AS2 (xor%W0,%0,%0); if (operands[1] == const1_rtx && (link = find_reg_note (insn, REG_WAS_0, 0)) /* Make sure the insn that stored the 0 is still present. */ && ! INSN_DELETED_P (XEXP (link, 0)) && GET_CODE (XEXP (link, 0)) != NOTE /* Make sure cross jumping didn't happen here. */ && no_labels_between_p (XEXP (link, 0), insn) /* Make sure the reg hasn't been clobbered. */ && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) /* Fastest way to change a 0 to a 1. */ return AS1 (inc%W0,%0); return AS2 (mov%W0,%1,%0); }") ;; emit_push_insn when it calls move_by_pieces ;; requires an insn to "push a byte". ;; But actually we use pushw, which has the effect of rounding ;; the amount pushed up to a halfword. (define_insn "" [(set (match_operand:QI 0 "push_operand" "=<") (match_operand:QI 1 "general_operand" "q"))] "" "* { operands[1] = gen_rtx (REG, HImode, REGNO (operands[1])); return AS1 (push%W0,%1); }") ;; On i486, incb reg is faster than movb $1,reg. ;; ??? Do a recognizer for zero_extract that looks just like this, but reads ;; or writes %ah, %bh, %ch, %dh. (define_insn "movqi" [(set (match_operand:QI 0 "general_operand" "=q,*r,qm") (match_operand:QI 1 "general_operand" "*g,q,qn"))] "" "* { rtx link; if (operands[1] == const0_rtx && REG_P (operands[0])) return AS2 (xor%B0,%0,%0); if (operands[1] == const1_rtx && (link = find_reg_note (insn, REG_WAS_0, 0)) /* Make sure the insn that stored the 0 is still present. */ && ! INSN_DELETED_P (XEXP (link, 0)) && GET_CODE (XEXP (link, 0)) != NOTE /* Make sure cross jumping didn't happen here. */ && no_labels_between_p (XEXP (link, 0), insn) /* Make sure the reg hasn't been clobbered. */ && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) /* Fastest way to change a 0 to a 1. */ return AS1 (inc%B0,%0); /* If mov%B0 isn't allowed for one of these regs, use mov%L0. */ if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1])) return (AS2 (mov%L0,%k1,%k0)); return (AS2 (mov%B0,%1,%0)); }") ;; If it becomes necessary to support movstrictqi into %esi or %edi, ;; use the insn sequence: ;; ;; shrdl $8,srcreg,dstreg ;; rorl $24,dstreg ;; ;; If operands[1] is a constant, then an andl/orl sequence would be ;; faster. (define_insn "movstrictqi" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+qm,q")) (match_operand:QI 1 "general_operand" "*qn,m"))] "" "* { rtx link; if (operands[1] == const0_rtx && REG_P (operands[0])) return AS2 (xor%B0,%0,%0); if (operands[1] == const1_rtx && (link = find_reg_note (insn, REG_WAS_0, 0)) /* Make sure the insn that stored the 0 is still present. */ && ! INSN_DELETED_P (XEXP (link, 0)) && GET_CODE (XEXP (link, 0)) != NOTE /* Make sure cross jumping didn't happen here. */ && no_labels_between_p (XEXP (link, 0), insn) /* Make sure the reg hasn't been clobbered. */ && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) /* Fastest way to change a 0 to a 1. */ return AS1 (inc%B0,%0); /* If mov%B0 isn't allowed for one of these regs, use mov%L0. */ if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1])) { abort (); return (AS2 (mov%L0,%k1,%k0)); } return AS2 (mov%B0,%1,%0); }") (define_insn "" [(set (match_operand:SF 0 "push_operand" "=<,<") (match_operand:SF 1 "general_operand" "gF,f"))] "" "* { if (STACK_REG_P (operands[1])) { rtx xops[3]; if (! STACK_TOP_P (operands[1])) abort (); xops[0] = AT_SP (SFmode); xops[1] = GEN_INT (4); xops[2] = stack_pointer_rtx; output_asm_insn (AS2 (sub%L2,%1,%2), xops); if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) output_asm_insn (AS1 (fstp%S0,%0), xops); else output_asm_insn (AS1 (fst%S0,%0), xops); RET; } return AS1 (push%L1,%1); }") ;; Allow MEM-MEM moves before reload. The reload class for such a ;; move will be ALL_REGS. PREFERRED_RELOAD_CLASS will narrow this to ;; GENERAL_REGS. For the purposes of regclass, prefer FLOAT_REGS. (define_insn "movsf" [(set (match_operand:SF 0 "general_operand" "=*rfm,*rf,f,!*rm") (match_operand:SF 1 "general_operand" "*rf,*rfm,fG,fF"))] "" "* { int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; /* First handle a `pop' insn or a `fld %st(0)' */ if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1])) { if (stack_top_dies) return AS1 (fstp,%y0); else return AS1 (fld,%y0); } /* Handle a transfer between the 387 and a 386 register */ if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) { output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); RET; } if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) { output_to_reg (operands[0], stack_top_dies); RET; } /* Handle other kinds of writes from the 387 */ if (STACK_TOP_P (operands[1])) { if (stack_top_dies) return AS1 (fstp%z0,%y0); else return AS1 (fst%z0,%y0); } /* Handle other kinds of reads to the 387 */ if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) return (char *) output_move_const_single (operands); if (STACK_TOP_P (operands[0])) return AS1 (fld%z1,%y1); /* Handle all SFmode moves not involving the 387 */ return (char *) singlemove_string (operands); }") ;;should change to handle the memory operands[1] without doing df push.. (define_insn "" [(set (match_operand:DF 0 "push_operand" "=<,<") (match_operand:DF 1 "general_operand" "gF,f"))] "" "* { if (STACK_REG_P (operands[1])) { rtx xops[3]; xops[0] = AT_SP (SFmode); xops[1] = GEN_INT (8); xops[2] = stack_pointer_rtx; output_asm_insn (AS2 (sub%L2,%1,%2), xops); if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) output_asm_insn (AS1 (fstp%Q0,%0), xops); else output_asm_insn (AS1 (fst%Q0,%0), xops); RET; } else return (char *) output_move_double (operands); }") (define_insn "swapdf" [(set (match_operand:DF 0 "register_operand" "f") (match_operand:DF 1 "register_operand" "f")) (set (match_dup 1) (match_dup 0))] "" "* { if (STACK_TOP_P (operands[0])) return AS1 (fxch,%1); else return AS1 (fxch,%0); }") ;; Allow MEM-MEM moves before reload. The reload class for such a ;; move will be ALL_REGS. PREFERRED_RELOAD_CLASS will narrow this to ;; GENERAL_REGS. For the purposes of regclass, prefer FLOAT_REGS. (define_insn "movdf" [(set (match_operand:DF 0 "general_operand" "=*rfm,*rf,f,!*rm") (match_operand:DF 1 "general_operand" "*rf,*rfm,fG,fF"))] "" "* { int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; /* First handle a `pop' insn or a `fld %st(0)' */ if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1])) { if (stack_top_dies) return AS1 (fstp,%y0); else return AS1 (fld,%y0); } /* Handle a transfer between the 387 and a 386 register */ if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) { output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); RET; } if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) { output_to_reg (operands[0], stack_top_dies); RET; } /* Handle other kinds of writes from the 387 */ if (STACK_TOP_P (operands[1])) { if (stack_top_dies) return AS1 (fstp%z0,%y0); else return AS1 (fst%z0,%y0); } /* Handle other kinds of reads to the 387 */ if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) return (char *) output_move_const_single (operands); if (STACK_TOP_P (operands[0])) return AS1 (fld%z1,%y1); /* Handle all DFmode moves not involving the 387 */ return (char *) output_move_double (operands); }") (define_insn "" [(set (match_operand:XF 0 "push_operand" "=<,<") (match_operand:XF 1 "general_operand" "gF,f"))] "" "* { if (STACK_REG_P (operands[1])) { rtx xops[3]; xops[0] = AT_SP (SFmode); xops[1] = GEN_INT (12); xops[2] = stack_pointer_rtx; output_asm_insn (AS2 (sub%L2,%1,%2), xops); output_asm_insn (AS1 (fstp%T0,%0), xops); if (! find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) output_asm_insn (AS1 (fld%T0,%0), xops); RET; } else return (char *) output_move_double (operands); }") (define_insn "swapxf" [(set (match_operand:XF 0 "register_operand" "f") (match_operand:XF 1 "register_operand" "f")) (set (match_dup 1) (match_dup 0))] "" "* { if (STACK_TOP_P (operands[0])) return AS1 (fxch,%1); else return AS1 (fxch,%0); }") (define_insn "movxf" [(set (match_operand:XF 0 "general_operand" "=f,fm,!*rf,!*rm") (match_operand:XF 1 "general_operand" "fmG,f,*rfm,*rfF"))] ;; [(set (match_operand:XF 0 "general_operand" "=*rf,*rfm,f,!*rm") ;; (match_operand:XF 1 "general_operand" "*rfm,*rf,fG,fF"))] "" "* { int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; /* First handle a `pop' insn or a `fld %st(0)' */ if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1])) { if (stack_top_dies) return AS1 (fstp,%y0); else return AS1 (fld,%y0); } /* Handle a transfer between the 387 and a 386 register */ if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) { output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); RET; } if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) { output_to_reg (operands[0], stack_top_dies); RET; } /* Handle other kinds of writes from the 387 */ if (STACK_TOP_P (operands[1])) { output_asm_insn (AS1 (fstp%z0,%y0), operands); if (! stack_top_dies) return AS1 (fld%z0,%y0); RET; } /* Handle other kinds of reads to the 387 */ if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) return (char *) output_move_const_single (operands); if (STACK_TOP_P (operands[0])) return AS1 (fld%z1,%y1); /* Handle all XFmode moves not involving the 387 */ return (char *) output_move_double (operands); }") (define_insn "" [(set (match_operand:DI 0 "push_operand" "=<") (match_operand:DI 1 "general_operand" "roiF"))] "" "* { return (char *) output_move_double (operands); }") (define_insn "movdi" [(set (match_operand:DI 0 "general_operand" "=r,rm") (match_operand:DI 1 "general_operand" "m,riF"))] "" "* { return (char *) output_move_double (operands); }") ;;- conversion instructions ;;- NONE ;;- zero extension instructions ;; See comments by `andsi' for when andl is faster than movzx. (define_insn "zero_extendhisi2" [(set (match_operand:SI 0 "general_operand" "=r") (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] "" "* { if ((TARGET_486 || REGNO (operands[0]) == 0) && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) { rtx xops[2]; xops[0] = operands[0]; xops[1] = GEN_INT (0xffff); output_asm_insn (AS2 (and%L0,%1,%k0), xops); RET; } #ifdef INTEL_SYNTAX return AS2 (movzx,%1,%0); #else return AS2 (movz%W0%L0,%1,%0); #endif }") (define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "general_operand" "=r") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))] "" "* { if ((TARGET_486 || REGNO (operands[0]) == 0) && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) { rtx xops[2]; xops[0] = operands[0]; xops[1] = GEN_INT (0xff); output_asm_insn (AS2 (and%L0,%1,%k0), xops); RET; } #ifdef INTEL_SYNTAX return AS2 (movzx,%1,%0); #else return AS2 (movz%B0%W0,%1,%0); #endif }") (define_insn "zero_extendqisi2" [(set (match_operand:SI 0 "general_operand" "=r") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))] "" "* { if ((TARGET_486 || REGNO (operands[0]) == 0) && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) { rtx xops[2]; xops[0] = operands[0]; xops[1] = GEN_INT (0xff); output_asm_insn (AS2 (and%L0,%1,%k0), xops); RET; } #ifdef INTEL_SYNTAX return AS2 (movzx,%1,%0); #else return AS2 (movz%B0%L0,%1,%0); #endif }") (define_insn "zero_extendsidi2" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (match_operand:SI 1 "register_operand" "0")))] "" "* { operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); return AS2 (xor%L0,%0,%0); }") ;;- sign extension instructions (define_insn "extendsidi2" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (match_operand:SI 1 "register_operand" "0")))] "" "* { if (REGNO (operands[0]) == 0) { /* This used to be cwtl, but that extends HI to SI somehow. */ #ifdef INTEL_SYNTAX return \"cdq\"; #else return \"cltd\"; #endif } operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); output_asm_insn (AS2 (mov%L0,%0,%1), operands); operands[0] = GEN_INT (31); return AS2 (sar%L1,%0,%1); }") ;; Note that the i386 programmers' manual says that the opcodes ;; are named movsx..., but the assembler on Unix does not accept that. ;; We use what the Unix assembler expects. (define_insn "extendhisi2" [(set (match_operand:SI 0 "general_operand" "=r") (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] "" "* { if (REGNO (operands[0]) == 0 && REG_P (operands[1]) && REGNO (operands[1]) == 0) #ifdef INTEL_SYNTAX return \"cwde\"; #else return \"cwtl\"; #endif #ifdef INTEL_SYNTAX return AS2 (movsx,%1,%0); #else return AS2 (movs%W0%L0,%1,%0); #endif }") (define_insn "extendqihi2" [(set (match_operand:HI 0 "general_operand" "=r") (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))] "" "* { if (REGNO (operands[0]) == 0 && REG_P (operands[1]) && REGNO (operands[1]) == 0) return \"cbtw\"; #ifdef INTEL_SYNTAX return AS2 (movsx,%1,%0); #else return AS2 (movs%B0%W0,%1,%0); #endif }") (define_insn "extendqisi2" [(set (match_operand:SI 0 "general_operand" "=r") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))] "" "* { #ifdef INTEL_SYNTAX return AS2 (movsx,%1,%0); #else return AS2 (movs%B0%L0,%1,%0); #endif }") ;; Conversions between float and double. (define_insn "extendsfdf2" [(set (match_operand:DF 0 "general_operand" "=fm,f") (float_extend:DF (match_operand:SF 1 "general_operand" "f,fm")))] "TARGET_80387" "* { int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; if (NON_STACK_REG_P (operands[1])) { output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); RET; } if (NON_STACK_REG_P (operands[0])) { output_to_reg (operands[0], stack_top_dies); RET; } if (STACK_TOP_P (operands[0])) return AS1 (fld%z1,%y1); if (GET_CODE (operands[0]) == MEM) { if (stack_top_dies) return AS1 (fstp%z0,%y0); else return AS1 (fst%z0,%y0); } abort (); }") (define_insn "extenddfxf2" [(set (match_operand:XF 0 "general_operand" "=fm,f,f,!*r") (float_extend:XF (match_operand:DF 1 "general_operand" "f,fm,!*r,f")))] "TARGET_80387" "* { int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; if (NON_STACK_REG_P (operands[1])) { output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); RET; } if (NON_STACK_REG_P (operands[0])) { output_to_reg (operands[0], stack_top_dies); RET; } if (STACK_TOP_P (operands[0])) return AS1 (fld%z1,%y1); if (GET_CODE (operands[0]) == MEM) { output_asm_insn (AS1 (fstp%z0,%y0), operands); if (! stack_top_dies) return AS1 (fld%z0,%y0); RET; } abort (); }") (define_insn "extendsfxf2" [(set (match_operand:XF 0 "general_operand" "=fm,f,f,!*r") (float_extend:XF (match_operand:SF 1 "general_operand" "f,fm,!*r,f")))] "TARGET_80387" "* { int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; if (NON_STACK_REG_P (operands[1])) { output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); RET; } if (NON_STACK_REG_P (operands[0])) { output_to_reg (operands[0], stack_top_dies); RET; } if (STACK_TOP_P (operands[0])) return AS1 (fld%z1,%y1); if (GET_CODE (operands[0]) == MEM) { output_asm_insn (AS1 (fstp%z0,%y0), operands); if (! stack_top_dies) return AS1 (fld%z0,%y0); RET; } abort (); }") (define_expand "truncdfsf2" [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") (float_truncate:SF (match_operand:DF 1 "register_operand" ""))) (clobber (match_dup 2))])] "TARGET_80387" " { operands[2] = (rtx) assign_386_stack_local (SFmode, 0); }") ;; This cannot output into an f-reg because there is no way to be sure ;; of truncating in that case. Otherwise this is just like a simple move ;; insn. So we pretend we can output to a reg in order to get better ;; register preferencing, but we really use a stack slot. (define_insn "" [(set (match_operand:SF 0 "nonimmediate_operand" "=f,m") (float_truncate:SF (match_operand:DF 1 "register_operand" "0,f"))) (clobber (match_operand:SF 2 "memory_operand" "m,m"))] "TARGET_80387" "* { int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; if (GET_CODE (operands[0]) == MEM) { if (stack_top_dies) return AS1 (fstp%z0,%0); else return AS1 (fst%z0,%0); } else if (STACK_TOP_P (operands[0])) { output_asm_insn (AS1 (fstp%z2,%y2), operands); return AS1 (fld%z2,%y2); } else abort (); }") (define_insn "truncxfsf2" [(set (match_operand:SF 0 "general_operand" "=m,!*r") (float_truncate:SF (match_operand:XF 1 "register_operand" "f,f")))] "TARGET_80387" "* { int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; if (NON_STACK_REG_P (operands[0])) { if (stack_top_dies == 0) { output_asm_insn (AS1 (fld,%y1), operands); stack_top_dies = 1; } output_to_reg (operands[0], stack_top_dies); RET; } else if (GET_CODE (operands[0]) == MEM) { if (stack_top_dies) return AS1 (fstp%z0,%0); else { output_asm_insn (AS1 (fld,%y1), operands); return AS1 (fstp%z0,%0); } } else abort (); }") (define_insn "truncxfdf2" [(set (match_operand:DF 0 "general_operand" "=m,!*r") (float_truncate:DF (match_operand:XF 1 "register_operand" "f,f")))] "TARGET_80387" "* { int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; if (NON_STACK_REG_P (operands[0])) { if (stack_top_dies == 0) { output_asm_insn (AS1 (fld,%y1), operands); stack_top_dies = 1; } output_to_reg (operands[0], stack_top_dies); RET; } else if (GET_CODE (operands[0]) == MEM) { if (stack_top_dies) return AS1 (fstp%z0,%0); else { output_asm_insn (AS1 (fld,%y1), operands); return AS1 (fstp%z0,%0); } } else abort (); }") ;; The 387 requires that the stack top dies after converting to DImode. ;; Represent an unsigned conversion from SImode to MODE_FLOAT by first ;; doing a signed conversion to DImode, and then taking just the low ;; part. (define_expand "fixuns_truncxfsi2" [(set (match_dup 4) (match_operand:XF 1 "register_operand" "")) (parallel [(set (match_dup 2) (fix:DI (fix:XF (match_dup 4)))) (clobber (match_dup 4)) (clobber (match_dup 5)) (clobber (match_dup 6)) (clobber (match_scratch:SI 7 ""))]) (set (match_operand:SI 0 "general_operand" "") (match_dup 3))] "TARGET_80387" " { operands[2] = gen_reg_rtx (DImode); operands[3] = gen_lowpart (SImode, operands[2]); operands[4] = gen_reg_rtx (XFmode); operands[5] = (rtx) assign_386_stack_local (SImode, 0); operands[6] = (rtx) assign_386_stack_local (SImode, 1); }") (define_expand "fixuns_truncdfsi2" [(set (match_dup 4) (match_operand:DF 1 "register_operand" "")) (parallel [(set (match_dup 2) (fix:DI (fix:DF (match_dup 4)))) (clobber (match_dup 4)) (clobber (match_dup 5)) (clobber (match_dup 6)) (clobber (match_scratch:SI 7 ""))]) (set (match_operand:SI 0 "general_operand" "") (match_dup 3))] "TARGET_80387" " { operands[2] = gen_reg_rtx (DImode); operands[3] = gen_lowpart (SImode, operands[2]); operands[4] = gen_reg_rtx (DFmode); operands[5] = (rtx) assign_386_stack_local (SImode, 0); operands[6] = (rtx) assign_386_stack_local (SImode, 1); }") (define_expand "fixuns_truncsfsi2" [(set (match_dup 4) (match_operand:SF 1 "register_operand" "")) (parallel [(set (match_dup 2) (fix:DI (fix:SF (match_dup 4)))) (clobber (match_dup 4)) (clobber (match_dup 5)) (clobber (match_dup 6)) (clobber (match_scratch:SI 7 ""))]) (set (match_operand:SI 0 "general_operand" "") (match_dup 3))] "TARGET_80387" " { operands[2] = gen_reg_rtx (DImode); operands[3] = gen_lowpart (SImode, operands[2]); operands[4] = gen_reg_rtx (SFmode); operands[5] = (rtx) assign_386_stack_local (SImode, 0); operands[6] = (rtx) assign_386_stack_local (SImode, 1); }") ;; Signed conversion to DImode. (define_expand "fix_truncxfdi2" [(set (match_dup 2) (match_operand:XF 1 "register_operand" "")) (parallel [(set (match_operand:DI 0 "general_operand" "") (fix:DI (fix:XF (match_dup 2)))) (clobber (match_dup 2)) (clobber (match_dup 3)) (clobber (match_dup 4)) (clobber (match_scratch:SI 5 ""))])] "TARGET_80387" " { operands[1] = copy_to_mode_reg (XFmode, operands[1]); operands[2] = gen_reg_rtx (XFmode); operands[3] = (rtx) assign_386_stack_local (SImode, 0); operands[4] = (rtx) assign_386_stack_local (SImode, 1); }") (define_expand "fix_truncdfdi2" [(set (match_dup 2) (match_operand:DF 1 "register_operand" "")) (parallel [(set (match_operand:DI 0 "general_operand" "") (fix:DI (fix:DF (match_dup 2)))) (clobber (match_dup 2)) (clobber (match_dup 3)) (clobber (match_dup 4)) (clobber (match_scratch:SI 5 ""))])] "TARGET_80387" " { operands[1] = copy_to_mode_reg (DFmode, operands[1]); operands[2] = gen_reg_rtx (DFmode); operands[3] = (rtx) assign_386_stack_local (SImode, 0); operands[4] = (rtx) assign_386_stack_local (SImode, 1); }") (define_expand "fix_truncsfdi2" [(set (match_dup 2) (match_operand:SF 1 "register_operand" "")) (parallel [(set (match_operand:DI 0 "general_operand" "") (fix:DI (fix:SF (match_dup 2)))) (clobber (match_dup 2)) (clobber (match_dup 3)) (clobber (match_dup 4)) (clobber (match_scratch:SI 5 ""))])] "TARGET_80387" " { operands[1] = copy_to_mode_reg (SFmode, operands[1]); operands[2] = gen_reg_rtx (SFmode); operands[3] = (rtx) assign_386_stack_local (SImode, 0); operands[4] = (rtx) assign_386_stack_local (SImode, 1); }") ;; These match a signed conversion of either DFmode or SFmode to DImode. (define_insn "" [(set (match_operand:DI 0 "general_operand" "=rm") (fix:DI (fix:XF (match_operand:XF 1 "register_operand" "f")))) (clobber (match_dup 1)) (clobber (match_operand:SI 2 "memory_operand" "m")) (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" "* return (char *) output_fix_trunc (insn, operands);") (define_insn "" [(set (match_operand:DI 0 "general_operand" "=rm") (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f")))) (clobber (match_dup 1)) (clobber (match_operand:SI 2 "memory_operand" "m")) (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" "* return (char *) output_fix_trunc (insn, operands);") (define_insn "" [(set (match_operand:DI 0 "general_operand" "=rm") (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f")))) (clobber (match_dup 1)) (clobber (match_operand:SI 2 "memory_operand" "m")) (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" "* return (char *) output_fix_trunc (insn, operands);") ;; Signed MODE_FLOAT conversion to SImode. (define_expand "fix_truncxfsi2" [(parallel [(set (match_operand:SI 0 "general_operand" "") (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "")))) (clobber (match_dup 2)) (clobber (match_dup 3)) (clobber (match_scratch:SI 4 ""))])] "TARGET_80387" " { operands[2] = (rtx) assign_386_stack_local (SImode, 0); operands[3] = (rtx) assign_386_stack_local (SImode, 1); }") (define_expand "fix_truncdfsi2" [(parallel [(set (match_operand:SI 0 "general_operand" "") (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "")))) (clobber (match_dup 2)) (clobber (match_dup 3)) (clobber (match_scratch:SI 4 ""))])] "TARGET_80387" " { operands[2] = (rtx) assign_386_stack_local (SImode, 0); operands[3] = (rtx) assign_386_stack_local (SImode, 1); }") (define_expand "fix_truncsfsi2" [(parallel [(set (match_operand:SI 0 "general_operand" "") (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "")))) (clobber (match_dup 2)) (clobber (match_dup 3)) (clobber (match_scratch:SI 4 ""))])] "TARGET_80387" " { operands[2] = (rtx) assign_386_stack_local (SImode, 0); operands[3] = (rtx) assign_386_stack_local (SImode, 1); }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=rm") (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f")))) (clobber (match_operand:SI 2 "memory_operand" "m")) (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" "* return (char *) output_fix_trunc (insn, operands);") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=rm") (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f")))) (clobber (match_operand:SI 2 "memory_operand" "m")) (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" "* return (char *) output_fix_trunc (insn, operands);") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=rm") (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f")))) (clobber (match_operand:SI 2 "memory_operand" "m")) (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" "* return (char *) output_fix_trunc (insn, operands);") ;; Conversion between fixed point and floating point. ;; The actual pattern that matches these is at the end of this file. ;; ??? Possibly represent floatunssidf2 here in gcc2. (define_expand "floatsisf2" [(set (match_operand:SF 0 "register_operand" "") (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] "TARGET_80387" "") (define_expand "floatdisf2" [(set (match_operand:SF 0 "register_operand" "") (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))] "TARGET_80387" "") (define_expand "floatsidf2" [(set (match_operand:DF 0 "register_operand" "") (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))] "TARGET_80387" "") (define_expand "floatdidf2" [(set (match_operand:DF 0 "register_operand" "") (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))] "TARGET_80387" "") (define_expand "floatsixf2" [(set (match_operand:XF 0 "register_operand" "") (float:XF (match_operand:SI 1 "nonimmediate_operand" "")))] "TARGET_80387" "") (define_expand "floatdixf2" [(set (match_operand:XF 0 "register_operand" "") (float:XF (match_operand:DI 1 "nonimmediate_operand" "")))] "TARGET_80387" "") ;; This will convert from SImode or DImode to MODE_FLOAT. (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") (float:XF (match_operand:DI 1 "general_operand" "rm")))] "TARGET_80387" "* { if (NON_STACK_REG_P (operands[1])) { output_op_from_reg (operands[1], AS1 (fild%z0,%1)); RET; } else if (GET_CODE (operands[1]) == MEM) return AS1 (fild%z1,%1); else abort (); }") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (float:DF (match_operand:DI 1 "nonimmediate_operand" "rm")))] "TARGET_80387" "* { if (NON_STACK_REG_P (operands[1])) { output_op_from_reg (operands[1], AS1 (fild%z0,%1)); RET; } else if (GET_CODE (operands[1]) == MEM) return AS1 (fild%z1,%1); else abort (); }") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=f") (float:SF (match_operand:DI 1 "nonimmediate_operand" "rm")))] "TARGET_80387" "* { if (NON_STACK_REG_P (operands[1])) { output_op_from_reg (operands[1], AS1 (fild%z0,%1)); RET; } else if (GET_CODE (operands[1]) == MEM) return AS1 (fild%z1,%1); else abort (); }") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (float:DF (match_operand:SI 1 "nonimmediate_operand" "rm")))] "TARGET_80387" "* { if (NON_STACK_REG_P (operands[1])) { output_op_from_reg (operands[1], AS1 (fild%z0,%1)); RET; } else if (GET_CODE (operands[1]) == MEM) return AS1 (fild%z1,%1); else abort (); }") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f,f") (float:XF (match_operand:SI 1 "general_operand" "m,!*r")))] "TARGET_80387" "* { if (NON_STACK_REG_P (operands[1])) { output_op_from_reg (operands[1], AS1 (fild%z0,%1)); RET; } else if (GET_CODE (operands[1]) == MEM) return AS1 (fild%z1,%1); else abort (); }") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=f") (float:SF (match_operand:SI 1 "nonimmediate_operand" "rm")))] "TARGET_80387" "* { if (NON_STACK_REG_P (operands[1])) { output_op_from_reg (operands[1], AS1 (fild%z0,%1)); RET; } else if (GET_CODE (operands[1]) == MEM) return AS1 (fild%z1,%1); else abort (); }") ;;- add instructions (define_insn "adddi3" [(set (match_operand:DI 0 "general_operand" "=&r,ro") (plus:DI (match_operand:DI 1 "general_operand" "%0,0") (match_operand:DI 2 "general_operand" "o,riF")))] "" "* { rtx low[3], high[3]; CC_STATUS_INIT; split_di (operands, 3, low, high); if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0) { output_asm_insn (AS2 (add%L0,%2,%0), low); output_asm_insn (AS2 (adc%L0,%2,%0), high); } else output_asm_insn (AS2 (add%L0,%2,%0), high); RET; }") ;; On a 486, it is faster to do movl/addl than to do a single leal if ;; operands[1] and operands[2] are both registers. (define_insn "addsi3" [(set (match_operand:SI 0 "general_operand" "=?r,rm,r") (plus:SI (match_operand:SI 1 "general_operand" "%r,0,0") (match_operand:SI 2 "general_operand" "ri,ri,rm")))] "" "* { if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1])) { if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) return AS2 (add%L0,%1,%0); if (! TARGET_486 || ! REG_P (operands[2])) { CC_STATUS_INIT; if (operands[2] == stack_pointer_rtx) { rtx temp; temp = operands[1]; operands[1] = operands[2]; operands[2] = temp; } if (operands[2] != stack_pointer_rtx) { operands[1] = SET_SRC (PATTERN (insn)); return AS2 (lea%L0,%a1,%0); } } output_asm_insn (AS2 (mov%L0,%1,%0), operands); } if (operands[2] == const1_rtx) return AS1 (inc%L0,%0); if (operands[2] == constm1_rtx) return AS1 (dec%L0,%0); return AS2 (add%L0,%2,%0); }") ;; ??? `lea' here, for three operand add? If leaw is used, only %bx, ;; %si and %di can appear in SET_SRC, and output_asm_insn might not be ;; able to handle the operand. But leal always works? (define_insn "addhi3" [(set (match_operand:HI 0 "general_operand" "=rm,r") (plus:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_operand" "ri,rm")))] "" "* { /* ??? what about offsettable memory references? */ if (QI_REG_P (operands[0]) && GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0xff) == 0) { CC_STATUS_INIT; operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); if (operands[2] == const1_rtx) return AS1 (inc%B0,%h0); if (operands[2] == constm1_rtx) return AS1 (dec%B0,%h0); return AS2 (add%B0,%2,%h0); } if (operands[2] == const1_rtx) return AS1 (inc%W0,%0); if (operands[2] == constm1_rtx) return AS1 (dec%W0,%0); return AS2 (add%W0,%2,%0); }") (define_insn "addqi3" [(set (match_operand:QI 0 "general_operand" "=qm,q") (plus:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_operand" "qn,qmn")))] "" "* { if (operands[2] == const1_rtx) return AS1 (inc%B0,%0); if (operands[2] == constm1_rtx) return AS1 (dec%B0,%0); return AS2 (add%B0,%2,%0); }") ;Lennart Augustsson ;says this pattern just makes slower code: ; pushl %ebp ; addl $-80,(%esp) ;instead of ; leal -80(%ebp),%eax ; pushl %eax ; ;(define_insn "" ; [(set (match_operand:SI 0 "push_operand" "=<") ; (plus:SI (match_operand:SI 1 "general_operand" "%r") ; (match_operand:SI 2 "general_operand" "ri")))] ; "" ; "* ;{ ; rtx xops[4]; ; xops[0] = operands[0]; ; xops[1] = operands[1]; ; xops[2] = operands[2]; ; xops[3] = gen_rtx (MEM, SImode, stack_pointer_rtx); ; output_asm_insn (\"push%z1 %1\", xops); ; output_asm_insn (AS2 (add%z3,%2,%3), xops); ; RET; ;}") ;; addsi3 is faster, so put this after. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:QI 1 "address_operand" "p"))] "" "* { CC_STATUS_INIT; /* Adding a constant to a register is faster with an add. */ /* ??? can this ever happen? */ if (GET_CODE (operands[1]) == PLUS && GET_CODE (XEXP (operands[1], 1)) == CONST_INT && rtx_equal_p (operands[0], XEXP (operands[1], 0))) { operands[1] = XEXP (operands[1], 1); if (operands[1] == const1_rtx) return AS1 (inc%L0,%0); if (operands[1] == constm1_rtx) return AS1 (dec%L0,%0); return AS2 (add%L0,%1,%0); } return AS2 (lea%L0,%a1,%0); }") ;; The patterns that match these are at the end of this file. (define_expand "addxf3" [(set (match_operand:XF 0 "register_operand" "") (plus:XF (match_operand:XF 1 "nonimmediate_operand" "") (match_operand:XF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") (define_expand "adddf3" [(set (match_operand:DF 0 "register_operand" "") (plus:DF (match_operand:DF 1 "nonimmediate_operand" "") (match_operand:DF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") (define_expand "addsf3" [(set (match_operand:SF 0 "register_operand" "") (plus:SF (match_operand:SF 1 "nonimmediate_operand" "") (match_operand:SF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") ;;- subtract instructions (define_insn "subdi3" [(set (match_operand:DI 0 "general_operand" "=&r,ro") (minus:DI (match_operand:DI 1 "general_operand" "0,0") (match_operand:DI 2 "general_operand" "o,riF")))] "" "* { rtx low[3], high[3]; CC_STATUS_INIT; split_di (operands, 3, low, high); if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0) { output_asm_insn (AS2 (sub%L0,%2,%0), low); output_asm_insn (AS2 (sbb%L0,%2,%0), high); } else output_asm_insn (AS2 (sub%L0,%2,%0), high); RET; }") (define_insn "subsi3" [(set (match_operand:SI 0 "general_operand" "=rm,r") (minus:SI (match_operand:SI 1 "general_operand" "0,0") (match_operand:SI 2 "general_operand" "ri,rm")))] "" "* return AS2 (sub%L0,%2,%0);") (define_insn "subhi3" [(set (match_operand:HI 0 "general_operand" "=rm,r") (minus:HI (match_operand:HI 1 "general_operand" "0,0") (match_operand:HI 2 "general_operand" "ri,rm")))] "" "* return AS2 (sub%W0,%2,%0);") (define_insn "subqi3" [(set (match_operand:QI 0 "general_operand" "=qm,q") (minus:QI (match_operand:QI 1 "general_operand" "0,0") (match_operand:QI 2 "general_operand" "qn,qmn")))] "" "* return AS2 (sub%B0,%2,%0);") ;; The patterns that match these are at the end of this file. (define_expand "subxf3" [(set (match_operand:XF 0 "register_operand" "") (minus:XF (match_operand:XF 1 "nonimmediate_operand" "") (match_operand:XF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") (define_expand "subdf3" [(set (match_operand:DF 0 "register_operand" "") (minus:DF (match_operand:DF 1 "nonimmediate_operand" "") (match_operand:DF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") (define_expand "subsf3" [(set (match_operand:SF 0 "register_operand" "") (minus:SF (match_operand:SF 1 "nonimmediate_operand" "") (match_operand:SF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") ;;- multiply instructions ;(define_insn "mulqi3" ; [(set (match_operand:QI 0 "general_operand" "=a") ; (mult:QI (match_operand:QI 1 "general_operand" "%0") ; (match_operand:QI 2 "general_operand" "qm")))] ; "" ; "imul%B0 %2,%0") (define_insn "" [(set (match_operand:HI 0 "general_operand" "=r") (mult:SI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "r")))] "GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x80" "* return AS2 (imul%W0,%2,%0);") (define_insn "mulhi3" [(set (match_operand:HI 0 "general_operand" "=r,r") (mult:SI (match_operand:HI 1 "general_operand" "%0,rm") (match_operand:HI 2 "general_operand" "g,i")))] "" "* { if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == REGNO (operands[0]) && (GET_CODE (operands[2]) == MEM || GET_CODE (operands[2]) == REG)) /* Assembler has weird restrictions. */ return AS2 (imul%W0,%2,%0); return AS3 (imul%W0,%2,%1,%0); }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=r") (mult:SI (match_operand:SI 1 "general_operand" "%0") (match_operand:SI 2 "general_operand" "r")))] "GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x80" "* return AS2 (imul%L0,%2,%0);") (define_insn "mulsi3" [(set (match_operand:SI 0 "general_operand" "=r,r") (mult:SI (match_operand:SI 1 "general_operand" "%0,rm") (match_operand:SI 2 "general_operand" "g,i")))] "" "* { if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == REGNO (operands[0]) && (GET_CODE (operands[2]) == MEM || GET_CODE (operands[2]) == REG)) /* Assembler has weird restrictions. */ return AS2 (imul%L0,%2,%0); return AS3 (imul%L0,%2,%1,%0); }") (define_insn "" [(set (match_operand:HI 0 "general_operand" "=a") (mult:SI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))] "" "mul%B0 %2") ;; The patterns that match these are at the end of this file. (define_expand "mulxf3" [(set (match_operand:XF 0 "register_operand" "") (mult:XF (match_operand:XF 1 "nonimmediate_operand" "") (match_operand:XF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") (define_expand "muldf3" [(set (match_operand:DF 0 "register_operand" "") (mult:DF (match_operand:DF 1 "nonimmediate_operand" "") (match_operand:DF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") (define_expand "mulsf3" [(set (match_operand:SF 0 "register_operand" "") (mult:SF (match_operand:SF 1 "nonimmediate_operand" "") (match_operand:SF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") ;;- divide instructions (define_insn "divqi3" [(set (match_operand:QI 0 "general_operand" "=a") (div:QI (match_operand:HI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "qm")))] "" "idiv%B0 %2") (define_insn "udivqi3" [(set (match_operand:QI 0 "general_operand" "=a") (udiv:QI (match_operand:HI 1 "general_operand" "0") (match_operand:QI 2 "general_operand" "qm")))] "" "div%B0 %2") ;; The patterns that match these are at the end of this file. (define_expand "divxf3" [(set (match_operand:XF 0 "register_operand" "") (div:XF (match_operand:XF 1 "nonimmediate_operand" "") (match_operand:XF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") (define_expand "divdf3" [(set (match_operand:DF 0 "register_operand" "") (div:DF (match_operand:DF 1 "nonimmediate_operand" "") (match_operand:DF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") (define_expand "divsf3" [(set (match_operand:SF 0 "register_operand" "") (div:SF (match_operand:SF 1 "nonimmediate_operand" "") (match_operand:SF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") ;; Remainder instructions. (define_insn "divmodsi4" [(set (match_operand:SI 0 "register_operand" "=a") (div:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "general_operand" "rm"))) (set (match_operand:SI 3 "register_operand" "=&d") (mod:SI (match_dup 1) (match_dup 2)))] "" "* { #ifdef INTEL_SYNTAX output_asm_insn (\"cdq\", operands); #else output_asm_insn (\"cltd\", operands); #endif return AS1 (idiv%L0,%2); }") (define_insn "divmodhi4" [(set (match_operand:HI 0 "register_operand" "=a") (div:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "rm"))) (set (match_operand:HI 3 "register_operand" "=&d") (mod:HI (match_dup 1) (match_dup 2)))] "" "cwtd\;idiv%W0 %2") ;; ??? Can we make gcc zero extend operand[0]? (define_insn "udivmodsi4" [(set (match_operand:SI 0 "register_operand" "=a") (udiv:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "general_operand" "rm"))) (set (match_operand:SI 3 "register_operand" "=&d") (umod:SI (match_dup 1) (match_dup 2)))] "" "* { output_asm_insn (AS2 (xor%L3,%3,%3), operands); return AS1 (div%L0,%2); }") ;; ??? Can we make gcc zero extend operand[0]? (define_insn "udivmodhi4" [(set (match_operand:HI 0 "register_operand" "=a") (udiv:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "rm"))) (set (match_operand:HI 3 "register_operand" "=&d") (umod:HI (match_dup 1) (match_dup 2)))] "" "* { output_asm_insn (AS2 (xor%W0,%3,%3), operands); return AS1 (div%W0,%2); }") /* ;;this should be a valid double division which we may want to add (define_insn "" [(set (match_operand:SI 0 "register_operand" "=a") (udiv:DI (match_operand:DI 1 "register_operand" "a") (match_operand:SI 2 "general_operand" "rm"))) (set (match_operand:SI 3 "register_operand" "=d") (umod:SI (match_dup 1) (match_dup 2)))] "" "div%L0 %2,%0") */ ;;- and instructions ;; On i386, ;; movzbl %bl,%ebx ;; is faster than ;; andl $255,%ebx ;; ;; but if the reg is %eax, then the "andl" is faster. ;; ;; On i486, the "andl" is always faster than the "movzbl". ;; ;; On both i386 and i486, a three operand AND is as fast with movzbl or ;; movzwl as with andl, if operands[0] != operands[1]. ;; The `r' in `rm' for operand 3 looks redundant, but it causes ;; optional reloads to be generated if op 3 is a pseudo in a stack slot. ;; ??? What if we only change one byte of an offsettable memory reference? (define_insn "andsi3" [(set (match_operand:SI 0 "general_operand" "=r,r,rm,r") (and:SI (match_operand:SI 1 "general_operand" "%rm,qm,0,0") (match_operand:SI 2 "general_operand" "L,K,ri,rm")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) { if (INTVAL (operands[2]) == 0xffff && REG_P (operands[0]) && (! REG_P (operands[1]) || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) && (! TARGET_486 || ! rtx_equal_p (operands[0], operands[1]))) { /* ??? tege: Should forget CC_STATUS only if we clobber a remembered operand. Fix that later. */ CC_STATUS_INIT; #ifdef INTEL_SYNTAX return AS2 (movzx,%w1,%0); #else return AS2 (movz%W0%L0,%w1,%0); #endif } if (INTVAL (operands[2]) == 0xff && REG_P (operands[0]) && !(REG_P (operands[1]) && NON_QI_REG_P (operands[1])) && (! REG_P (operands[1]) || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) && (! TARGET_486 || ! rtx_equal_p (operands[0], operands[1]))) { /* ??? tege: Should forget CC_STATUS only if we clobber a remembered operand. Fix that later. */ CC_STATUS_INIT; #ifdef INTEL_SYNTAX return AS2 (movzx,%b1,%0); #else return AS2 (movz%B0%L0,%b1,%0); #endif } if (QI_REG_P (operands[0]) && ~(INTVAL (operands[2]) | 0xff) == 0) { CC_STATUS_INIT; if (INTVAL (operands[2]) == 0xffffff00) { operands[2] = const0_rtx; return AS2 (mov%B0,%2,%b0); } operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); return AS2 (and%B0,%2,%b0); } if (QI_REG_P (operands[0]) && ~(INTVAL (operands[2]) | 0xff00) == 0) { CC_STATUS_INIT; if (INTVAL (operands[2]) == 0xffff00ff) { operands[2] = const0_rtx; return AS2 (mov%B0,%2,%h0); } operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); return AS2 (and%B0,%2,%h0); } if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) == 0xffff0000) { operands[2] = const0_rtx; return AS2 (mov%W0,%2,%w0); } } return AS2 (and%L0,%2,%0); }") (define_insn "andhi3" [(set (match_operand:HI 0 "general_operand" "=rm,r") (and:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_operand" "ri,rm")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) { /* Can we ignore the upper byte? */ if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) && (INTVAL (operands[2]) & 0xff00) == 0xff00) { CC_STATUS_INIT; if ((INTVAL (operands[2]) & 0xff) == 0) { operands[2] = const0_rtx; return AS2 (mov%B0,%2,%b0); } operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); return AS2 (and%B0,%2,%b0); } /* Can we ignore the lower byte? */ /* ??? what about offsettable memory references? */ if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & 0xff) == 0xff) { CC_STATUS_INIT; if ((INTVAL (operands[2]) & 0xff00) == 0) { operands[2] = const0_rtx; return AS2 (mov%B0,%2,%h0); } operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); return AS2 (and%B0,%2,%h0); } } return AS2 (and%W0,%2,%0); }") (define_insn "andqi3" [(set (match_operand:QI 0 "general_operand" "=qm,q") (and:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_operand" "qn,qmn")))] "" "* return AS2 (and%B0,%2,%0);") /* I am nervous about these two.. add them later.. ;I presume this means that we have something in say op0= eax which is small ;and we want to and it with memory so we can do this by just an ;andb m,%al and have success. (define_insn "" [(set (match_operand:SI 0 "general_operand" "=r") (and:SI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")) (match_operand:SI 2 "general_operand" "0")))] "GET_CODE (operands[2]) == CONST_INT && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (HImode))" "and%W0 %1,%0") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=q") (and:SI (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")) (match_operand:SI 2 "general_operand" "0")))] "GET_CODE (operands[2]) == CONST_INT && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (QImode))" "and%L0 %1,%0") */ ;;- Bit set (inclusive or) instructions ;; ??? What if we only change one byte of an offsettable memory reference? (define_insn "iorsi3" [(set (match_operand:SI 0 "general_operand" "=rm,r") (ior:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_operand" "ri,rm")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) { if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) && (INTVAL (operands[2]) & ~0xff) == 0) { CC_STATUS_INIT; if (INTVAL (operands[2]) == 0xff) return AS2 (mov%B0,%2,%b0); return AS2 (or%B0,%2,%b0); } if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0) { CC_STATUS_INIT; operands[2] = GEN_INT (INTVAL (operands[2]) >> 8); if (INTVAL (operands[2]) == 0xff) return AS2 (mov%B0,%2,%h0); return AS2 (or%B0,%2,%h0); } } return AS2 (or%L0,%2,%0); }") (define_insn "iorhi3" [(set (match_operand:HI 0 "general_operand" "=rm,r") (ior:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_operand" "ri,rm")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) { /* Can we ignore the upper byte? */ if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) && (INTVAL (operands[2]) & 0xff00) == 0) { CC_STATUS_INIT; if (INTVAL (operands[2]) & 0xffff0000) operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); if (INTVAL (operands[2]) == 0xff) return AS2 (mov%B0,%2,%b0); return AS2 (or%B0,%2,%b0); } /* Can we ignore the lower byte? */ /* ??? what about offsettable memory references? */ if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & 0xff) == 0) { CC_STATUS_INIT; operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); if (INTVAL (operands[2]) == 0xff) return AS2 (mov%B0,%2,%h0); return AS2 (or%B0,%2,%h0); } } return AS2 (or%W0,%2,%0); }") (define_insn "iorqi3" [(set (match_operand:QI 0 "general_operand" "=qm,q") (ior:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_operand" "qn,qmn")))] "" "* return AS2 (or%B0,%2,%0);") ;;- xor instructions ;; ??? What if we only change one byte of an offsettable memory reference? (define_insn "xorsi3" [(set (match_operand:SI 0 "general_operand" "=rm,r") (xor:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_operand" "ri,rm")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) { if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) && (INTVAL (operands[2]) & ~0xff) == 0) { CC_STATUS_INIT; if (INTVAL (operands[2]) == 0xff) return AS1 (not%B0,%b0); return AS2 (xor%B0,%2,%b0); } if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0) { CC_STATUS_INIT; operands[2] = GEN_INT (INTVAL (operands[2]) >> 8); if (INTVAL (operands[2]) == 0xff) return AS1 (not%B0,%h0); return AS2 (xor%B0,%2,%h0); } } return AS2 (xor%L0,%2,%0); }") (define_insn "xorhi3" [(set (match_operand:HI 0 "general_operand" "=rm,r") (xor:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_operand" "ri,rm")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) { /* Can we ignore the upper byte? */ if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) && (INTVAL (operands[2]) & 0xff00) == 0) { CC_STATUS_INIT; if (INTVAL (operands[2]) & 0xffff0000) operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); if (INTVAL (operands[2]) == 0xff) return AS1 (not%B0,%b0); return AS2 (xor%B0,%2,%b0); } /* Can we ignore the lower byte? */ /* ??? what about offsettable memory references? */ if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & 0xff) == 0) { CC_STATUS_INIT; operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); if (INTVAL (operands[2]) == 0xff) return AS1 (not%B0,%h0); return AS2 (xor%B0,%2,%h0); } } return AS2 (xor%W0,%2,%0); }") (define_insn "xorqi3" [(set (match_operand:QI 0 "general_operand" "=qm,q") (xor:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_operand" "qn,qm")))] "" "* return AS2 (xor%B0,%2,%0);") ;;- negation instructions (define_insn "negdi2" [(set (match_operand:DI 0 "general_operand" "=&ro") (neg:DI (match_operand:DI 1 "general_operand" "0")))] "" "* { rtx xops[2], low[1], high[1]; CC_STATUS_INIT; split_di (operands, 1, low, high); xops[0] = const0_rtx; xops[1] = high[0]; output_asm_insn (AS1 (neg%L0,%0), low); output_asm_insn (AS2 (adc%L1,%0,%1), xops); output_asm_insn (AS1 (neg%L0,%0), high); RET; }") (define_insn "negsi2" [(set (match_operand:SI 0 "general_operand" "=rm") (neg:SI (match_operand:SI 1 "general_operand" "0")))] "" "neg%L0 %0") (define_insn "neghi2" [(set (match_operand:HI 0 "general_operand" "=rm") (neg:HI (match_operand:HI 1 "general_operand" "0")))] "" "neg%W0 %0") (define_insn "negqi2" [(set (match_operand:QI 0 "general_operand" "=qm") (neg:QI (match_operand:QI 1 "general_operand" "0")))] "" "neg%B0 %0") (define_insn "negsf2" [(set (match_operand:SF 0 "register_operand" "=f") (neg:SF (match_operand:SF 1 "general_operand" "0")))] "TARGET_80387" "fchs") (define_insn "negdf2" [(set (match_operand:DF 0 "register_operand" "=f") (neg:DF (match_operand:DF 1 "general_operand" "0")))] "TARGET_80387" "fchs") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (neg:DF (float_extend:DF (match_operand:SF 1 "general_operand" "0"))))] "TARGET_80387" "fchs") (define_insn "negxf2" [(set (match_operand:XF 0 "register_operand" "=f") (neg:XF (match_operand:XF 1 "general_operand" "0")))] "TARGET_80387" "fchs") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") (neg:XF (float_extend:XF (match_operand:DF 1 "general_operand" "0"))))] "TARGET_80387" "fchs") ;; Absolute value instructions (define_insn "abssf2" [(set (match_operand:SF 0 "register_operand" "=f") (abs:SF (match_operand:SF 1 "general_operand" "0")))] "TARGET_80387" "fabs") (define_insn "absdf2" [(set (match_operand:DF 0 "register_operand" "=f") (abs:DF (match_operand:DF 1 "general_operand" "0")))] "TARGET_80387" "fabs") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (abs:DF (float_extend:DF (match_operand:SF 1 "general_operand" "0"))))] "TARGET_80387" "fabs") (define_insn "absxf2" [(set (match_operand:XF 0 "register_operand" "=f") (abs:XF (match_operand:XF 1 "general_operand" "0")))] "TARGET_80387" "fabs") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") (abs:XF (float_extend:XF (match_operand:DF 1 "general_operand" "0"))))] "TARGET_80387" "fabs") (define_insn "sqrtsf2" [(set (match_operand:SF 0 "register_operand" "=f") (sqrt:SF (match_operand:SF 1 "general_operand" "0")))] "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" "fsqrt") (define_insn "sqrtdf2" [(set (match_operand:DF 0 "register_operand" "=f") (sqrt:DF (match_operand:DF 1 "general_operand" "0")))] "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" "fsqrt") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (sqrt:DF (float_extend:DF (match_operand:SF 1 "general_operand" "0"))))] "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" "fsqrt") (define_insn "sqrtxf2" [(set (match_operand:XF 0 "register_operand" "=f") (sqrt:XF (match_operand:XF 1 "general_operand" "0")))] "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" "fsqrt") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") (sqrt:XF (float_extend:XF (match_operand:DF 1 "general_operand" "0"))))] "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" "fsqrt") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") (sqrt:XF (float_extend:XF (match_operand:SF 1 "general_operand" "0"))))] "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" "fsqrt") (define_insn "sindf2" [(set (match_operand:DF 0 "register_operand" "=f") (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))] "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" "fsin") (define_insn "sinsf2" [(set (match_operand:SF 0 "register_operand" "=f") (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))] "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" "fsin") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (unspec:DF [(float_extend:DF (match_operand:SF 1 "register_operand" "0"))] 1))] "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" "fsin") (define_insn "cosdf2" [(set (match_operand:DF 0 "register_operand" "=f") (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))] "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" "fcos") (define_insn "cossf2" [(set (match_operand:SF 0 "register_operand" "=f") (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))] "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" "fcos") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (unspec:DF [(float_extend:DF (match_operand:SF 1 "register_operand" "0"))] 2))] "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" "fcos") ;;- one complement instructions (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "general_operand" "=rm") (not:SI (match_operand:SI 1 "general_operand" "0")))] "" "not%L0 %0") (define_insn "one_cmplhi2" [(set (match_operand:HI 0 "general_operand" "=rm") (not:HI (match_operand:HI 1 "general_operand" "0")))] "" "not%W0 %0") (define_insn "one_cmplqi2" [(set (match_operand:QI 0 "general_operand" "=qm") (not:QI (match_operand:QI 1 "general_operand" "0")))] "" "not%B0 %0") ;;- arithmetic shift instructions ;; DImode shifts are implemented using the i386 "shift double" opcode, ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count ;; is variable, then the count is in %cl and the "imm" operand is dropped ;; from the assembler input. ;; This instruction shifts the target reg/mem as usual, but instead of ;; shifting in zeros, bits are shifted in from reg operand. If the insn ;; is a left shift double, bits are taken from the high order bits of ;; reg, else if the insn is a shift right double, bits are taken from the ;; low order bits of reg. So if %eax is "1234" and %edx is "5678", ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345". ;; Since sh[lr]d does not change the `reg' operand, that is done ;; separately, making all shifts emit pairs of shift double and normal ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to ;; support a 63 bit shift, each shift where the count is in a reg expands ;; to three pairs. If the overall shift is by N bits, then the first two ;; pairs shift by N / 2 and the last pair by N & 1. ;; If the shift count is a constant, we need never emit more than one ;; shift pair, instead using moves and sign extension for counts greater ;; than 31. (define_expand "ashldi3" [(set (match_operand:DI 0 "register_operand" "") (ashift:DI (match_operand:DI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] "" " { if (GET_CODE (operands[2]) != CONST_INT || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) { operands[2] = copy_to_mode_reg (QImode, operands[2]); emit_insn (gen_ashldi3_non_const_int (operands[0], operands[1], operands[2])); } else emit_insn (gen_ashldi3_const_int (operands[0], operands[1], operands[2])); DONE; }") (define_insn "ashldi3_const_int" [(set (match_operand:DI 0 "register_operand" "=&r") (ashift:DI (match_operand:DI 1 "register_operand" "0") (match_operand:QI 2 "const_int_operand" "J")))] "" "* { rtx xops[4], low[1], high[1]; CC_STATUS_INIT; split_di (operands, 1, low, high); xops[0] = operands[2]; xops[1] = const1_rtx; xops[2] = low[0]; xops[3] = high[0]; if (INTVAL (xops[0]) > 31) { output_asm_insn (AS2 (mov%L3,%2,%3), xops); /* Fast shift by 32 */ output_asm_insn (AS2 (xor%L2,%2,%2), xops); if (INTVAL (xops[0]) > 32) { xops[0] = GEN_INT (INTVAL (xops[0]) - 32); output_asm_insn (AS2 (sal%L3,%0,%3), xops); /* Remaining shift */ } } else { output_asm_insn (AS3 (shld%L3,%0,%2,%3), xops); output_asm_insn (AS2 (sal%L2,%0,%2), xops); } RET; }") (define_insn "ashldi3_non_const_int" [(set (match_operand:DI 0 "register_operand" "=&r") (ashift:DI (match_operand:DI 1 "register_operand" "0") (match_operand:QI 2 "register_operand" "c"))) (clobber (match_dup 2))] "" "* { rtx xops[4], low[1], high[1]; CC_STATUS_INIT; split_di (operands, 1, low, high); xops[0] = operands[2]; xops[1] = const1_rtx; xops[2] = low[0]; xops[3] = high[0]; output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); output_asm_insn (AS2 (sal%L2,%0,%2), xops); output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); output_asm_insn (AS2 (sal%L2,%0,%2), xops); xops[1] = GEN_INT (7); /* shift count & 1 */ output_asm_insn (AS2 (shr%B0,%1,%0), xops); output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); output_asm_insn (AS2 (sal%L2,%0,%2), xops); RET; }") ;; On i386 and i486, "addl reg,reg" is faster than "sall $1,reg" ;; On i486, movl/sall appears slightly faster than leal, but the leal ;; is smaller - use leal for now unless the shift count is 1. (define_insn "ashlsi3" [(set (match_operand:SI 0 "general_operand" "=r,rm") (ashift:SI (match_operand:SI 1 "general_operand" "r,0") (match_operand:SI 2 "nonmemory_operand" "M,cI")))] "" "* { if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1])) { if (TARGET_486 && INTVAL (operands[2]) == 1) { output_asm_insn (AS2 (mov%L0,%1,%0), operands); return AS2 (add%L0,%1,%0); } else { CC_STATUS_INIT; if (operands[1] == stack_pointer_rtx) { output_asm_insn (AS2 (mov%L0,%1,%0), operands); operands[1] = operands[0]; } operands[1] = gen_rtx (MULT, SImode, operands[1], GEN_INT (1 << INTVAL (operands[2]))); return AS2 (lea%L0,%a1,%0); } } if (REG_P (operands[2])) return AS2 (sal%L0,%b2,%0); if (REG_P (operands[0]) && operands[2] == const1_rtx) return AS2 (add%L0,%0,%0); return AS2 (sal%L0,%2,%0); }") (define_insn "ashlhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (ashift:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "nonmemory_operand" "cI")))] "" "* { if (REG_P (operands[2])) return AS2 (sal%W0,%b2,%0); if (REG_P (operands[0]) && operands[2] == const1_rtx) return AS2 (add%W0,%0,%0); return AS2 (sal%W0,%2,%0); }") (define_insn "ashlqi3" [(set (match_operand:QI 0 "general_operand" "=qm") (ashift:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "nonmemory_operand" "cI")))] "" "* { if (REG_P (operands[2])) return AS2 (sal%B0,%b2,%0); if (REG_P (operands[0]) && operands[2] == const1_rtx) return AS2 (add%B0,%0,%0); return AS2 (sal%B0,%2,%0); }") ;; See comment above `ashldi3' about how this works. (define_expand "ashrdi3" [(set (match_operand:DI 0 "register_operand" "") (ashiftrt:DI (match_operand:DI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] "" " { if (GET_CODE (operands[2]) != CONST_INT || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) { operands[2] = copy_to_mode_reg (QImode, operands[2]); emit_insn (gen_ashrdi3_non_const_int (operands[0], operands[1], operands[2])); } else emit_insn (gen_ashrdi3_const_int (operands[0], operands[1], operands[2])); DONE; }") (define_insn "ashrdi3_const_int" [(set (match_operand:DI 0 "register_operand" "=&r") (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:QI 2 "const_int_operand" "J")))] "" "* { rtx xops[4], low[1], high[1]; CC_STATUS_INIT; split_di (operands, 1, low, high); xops[0] = operands[2]; xops[1] = const1_rtx; xops[2] = low[0]; xops[3] = high[0]; if (INTVAL (xops[0]) > 31) { xops[1] = GEN_INT (31); output_asm_insn (AS2 (mov%L2,%3,%2), xops); output_asm_insn (AS2 (sar%L3,%1,%3), xops); /* shift by 32 */ if (INTVAL (xops[0]) > 32) { xops[0] = GEN_INT (INTVAL (xops[0]) - 32); output_asm_insn (AS2 (sar%L2,%0,%2), xops); /* Remaining shift */ } } else { output_asm_insn (AS3 (shrd%L2,%0,%3,%2), xops); output_asm_insn (AS2 (sar%L3,%0,%3), xops); } RET; }") (define_insn "ashrdi3_non_const_int" [(set (match_operand:DI 0 "register_operand" "=&r") (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:QI 2 "register_operand" "c"))) (clobber (match_dup 2))] "" "* { rtx xops[4], low[1], high[1]; CC_STATUS_INIT; split_di (operands, 1, low, high); xops[0] = operands[2]; xops[1] = const1_rtx; xops[2] = low[0]; xops[3] = high[0]; output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); output_asm_insn (AS2 (sar%L3,%0,%3), xops); output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); output_asm_insn (AS2 (sar%L3,%0,%3), xops); xops[1] = GEN_INT (7); /* shift count & 1 */ output_asm_insn (AS2 (shr%B0,%1,%0), xops); output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); output_asm_insn (AS2 (sar%L3,%0,%3), xops); RET; }") (define_insn "ashrsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (ashiftrt:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "nonmemory_operand" "cI")))] "" "* { if (REG_P (operands[2])) return AS2 (sar%L0,%b2,%0); else return AS2 (sar%L0,%2,%0); }") (define_insn "ashrhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "nonmemory_operand" "cI")))] "" "* { if (REG_P (operands[2])) return AS2 (sar%W0,%b2,%0); else return AS2 (sar%W0,%2,%0); }") (define_insn "ashrqi3" [(set (match_operand:QI 0 "general_operand" "=qm") (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "nonmemory_operand" "cI")))] "" "* { if (REG_P (operands[2])) return AS2 (sar%B0,%b2,%0); else return AS2 (sar%B0,%2,%0); }") ;;- logical shift instructions ;; See comment above `ashldi3' about how this works. (define_expand "lshrdi3" [(set (match_operand:DI 0 "register_operand" "") (lshiftrt:DI (match_operand:DI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] "" " { if (GET_CODE (operands[2]) != CONST_INT || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) { operands[2] = copy_to_mode_reg (QImode, operands[2]); emit_insn (gen_lshrdi3_non_const_int (operands[0], operands[1], operands[2])); } else emit_insn (gen_lshrdi3_const_int (operands[0], operands[1], operands[2])); DONE; }") (define_insn "lshrdi3_const_int" [(set (match_operand:DI 0 "register_operand" "=&r") (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:QI 2 "const_int_operand" "J")))] "" "* { rtx xops[4], low[1], high[1]; CC_STATUS_INIT; split_di (operands, 1, low, high); xops[0] = operands[2]; xops[1] = const1_rtx; xops[2] = low[0]; xops[3] = high[0]; if (INTVAL (xops[0]) > 31) { output_asm_insn (AS2 (mov%L2,%3,%2), xops); /* Fast shift by 32 */ output_asm_insn (AS2 (xor%L3,%3,%3), xops); if (INTVAL (xops[0]) > 32) { xops[0] = GEN_INT (INTVAL (xops[0]) - 32); output_asm_insn (AS2 (shr%L2,%0,%2), xops); /* Remaining shift */ } } else { output_asm_insn (AS3 (shrd%L2,%0,%3,%2), xops); output_asm_insn (AS2 (shr%L3,%0,%3), xops); } RET; }") (define_insn "lshrdi3_non_const_int" [(set (match_operand:DI 0 "register_operand" "=&r") (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:QI 2 "register_operand" "c"))) (clobber (match_dup 2))] "" "* { rtx xops[4], low[1], high[1]; CC_STATUS_INIT; split_di (operands, 1, low, high); xops[0] = operands[2]; xops[1] = const1_rtx; xops[2] = low[0]; xops[3] = high[0]; output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); output_asm_insn (AS2 (shr%L3,%0,%3), xops); output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); output_asm_insn (AS2 (shr%L3,%0,%3), xops); xops[1] = GEN_INT (7); /* shift count & 1 */ output_asm_insn (AS2 (shr%B0,%1,%0), xops); output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); output_asm_insn (AS2 (shr%L3,%0,%3), xops); RET; }") (define_insn "lshrsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "nonmemory_operand" "cI")))] "" "* { if (REG_P (operands[2])) return AS2 (shr%L0,%b2,%0); else return AS2 (shr%L0,%2,%1); }") (define_insn "lshrhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "nonmemory_operand" "cI")))] "" "* { if (REG_P (operands[2])) return AS2 (shr%W0,%b2,%0); else return AS2 (shr%W0,%2,%0); }") (define_insn "lshrqi3" [(set (match_operand:QI 0 "general_operand" "=qm") (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "nonmemory_operand" "cI")))] "" "* { if (REG_P (operands[2])) return AS2 (shr%B0,%b2,%0); else return AS2 (shr%B0,%2,%0); }") ;;- rotate instructions (define_insn "rotlsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (rotate:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "nonmemory_operand" "cI")))] "" "* { if (REG_P (operands[2])) return AS2 (rol%L0,%b2,%0); else return AS2 (rol%L0,%2,%0); }") (define_insn "rotlhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (rotate:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "nonmemory_operand" "cI")))] "" "* { if (REG_P (operands[2])) return AS2 (rol%W0,%b2,%0); else return AS2 (rol%W0,%2,%0); }") (define_insn "rotlqi3" [(set (match_operand:QI 0 "general_operand" "=qm") (rotate:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "nonmemory_operand" "cI")))] "" "* { if (REG_P (operands[2])) return AS2 (rol%B0,%b2,%0); else return AS2 (rol%B0,%2,%0); }") (define_insn "rotrsi3" [(set (match_operand:SI 0 "general_operand" "=rm") (rotatert:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "nonmemory_operand" "cI")))] "" "* { if (REG_P (operands[2])) return AS2 (ror%L0,%b2,%0); else return AS2 (ror%L0,%2,%0); }") (define_insn "rotrhi3" [(set (match_operand:HI 0 "general_operand" "=rm") (rotatert:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "nonmemory_operand" "cI")))] "" "* { if (REG_P (operands[2])) return AS2 (ror%W0,%b2,%0); else return AS2 (ror%W0,%2,%0); }") (define_insn "rotrqi3" [(set (match_operand:QI 0 "general_operand" "=qm") (rotatert:QI (match_operand:QI 1 "general_operand" "0") (match_operand:QI 2 "nonmemory_operand" "cI")))] "" "* { if (REG_P (operands[2])) return AS2 (ror%B0,%b2,%0); else return AS2 (ror%B0,%2,%0); }") /* ;; This usually looses. But try a define_expand to recognize a few case ;; we can do efficiently, such as accessing the "high" QImode registers, ;; %ah, %bh, %ch, %dh. (define_insn "insv" [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+&r") (match_operand:SI 1 "general_operand" "i") (match_operand:SI 2 "general_operand" "i")) (match_operand:SI 3 "general_operand" "ri"))] "" "* { if (INTVAL (operands[1]) + INTVAL (operands[2]) > GET_MODE_BITSIZE (SImode)) abort (); if (GET_CODE (operands[3]) == CONST_INT) { unsigned int mask = (1 << INTVAL (operands[1])) - 1; operands[1] = GEN_INT (~(mask << INTVAL (operands[2]))); output_asm_insn (AS2 (and%L0,%1,%0), operands); operands[3] = GEN_INT (INTVAL (operands[3]) << INTVAL (operands[2])); output_asm_insn (AS2 (or%L0,%3,%0), operands); } else { operands[0] = gen_rtx (REG, SImode, REGNO (operands[0])); if (INTVAL (operands[2])) output_asm_insn (AS2 (ror%L0,%2,%0), operands); output_asm_insn (AS3 (shrd%L0,%1,%3,%0), operands); operands[2] = GEN_INT (BITS_PER_WORD - INTVAL (operands[1]) - INTVAL (operands[2])); if (INTVAL (operands[2])) output_asm_insn (AS2 (ror%L0,%2,%0), operands); } RET; }") */ /* ;; ??? There are problems with the mode of operand[3]. The point of this ;; is to represent an HImode move to a "high byte" register. (define_expand "insv" [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "immediate_operand" "") (match_operand:SI 2 "immediate_operand" "")) (match_operand:QI 3 "general_operand" "ri"))] "" " { if (GET_CODE (operands[1]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT) FAIL; if (! (INTVAL (operands[1]) == 8 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 0)) && ! INTVAL (operands[1]) == 1) FAIL; }") ;; ??? Are these constraints right? (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+&qo") (const_int 8) (const_int 8)) (match_operand:QI 1 "general_operand" "qn"))] "" "* { if (REG_P (operands[0])) return AS2 (mov%B0,%1,%h0); operands[0] = adj_offsettable_operand (operands[0], 1); return AS2 (mov%B0,%1,%0); }") */ ;; On i386, the register count for a bit operation is *not* truncated, ;; so SHIFT_COUNT_TRUNCATED must not be defined. ;; On i486, the shift & or/and code is faster than bts or btr. If ;; operands[0] is a MEM, the bt[sr] is half as fast as the normal code. ;; On i386, bts is a little faster if operands[0] is a reg, and a ;; little slower if operands[0] is a MEM, than the shift & or/and code. ;; Use bts & btr, since they reload better. ;; General bit set and clear. (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+rm") (const_int 1) (match_operand:SI 2 "general_operand" "r")) (match_operand:SI 3 "const_int_operand" "n"))] "! TARGET_486 && GET_CODE (operands[2]) != CONST_INT" "* { CC_STATUS_INIT; if (INTVAL (operands[3]) == 1) return AS2 (bts%L0,%2,%0); else return AS2 (btr%L0,%2,%0); }") ;; Bit complement. See comments on previous pattern. ;; ??? Is this really worthwhile? (define_insn "" [(set (match_operand:SI 0 "general_operand" "=rm") (xor:SI (ashift:SI (const_int 1) (match_operand:SI 1 "general_operand" "r")) (match_operand:SI 2 "general_operand" "0")))] "! TARGET_486 && GET_CODE (operands[1]) != CONST_INT" "* { CC_STATUS_INIT; return AS2 (btc%L0,%1,%0); }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=rm") (xor:SI (match_operand:SI 1 "general_operand" "0") (ashift:SI (const_int 1) (match_operand:SI 2 "general_operand" "r"))))] "! TARGET_486 && GET_CODE (operands[2]) != CONST_INT" "* { CC_STATUS_INIT; return AS2 (btc%L0,%2,%0); }") ;; Recognizers for bit-test instructions. ;; The bt opcode allows a MEM in operands[0]. But on both i386 and ;; i486, it is faster to copy a MEM to REG and then use bt, than to use ;; bt on the MEM directly. ;; ??? The first argument of a zero_extract must not be reloaded, so ;; don't allow a MEM in the operand predicate without allowing it in the ;; constraint. (define_insn "" [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r") (const_int 1) (match_operand:SI 1 "general_operand" "r")))] "GET_CODE (operands[1]) != CONST_INT" "* { cc_status.flags |= CC_Z_IN_NOT_C; return AS2 (bt%L0,%1,%0); }") (define_insn "" [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "const_int_operand" "n") (match_operand:SI 2 "const_int_operand" "n")))] "" "* { unsigned int mask; mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]); operands[1] = GEN_INT (mask); if (QI_REG_P (operands[0])) { if ((mask & ~0xff) == 0) { cc_status.flags |= CC_NOT_NEGATIVE; return AS2 (test%B0,%1,%b0); } if ((mask & ~0xff00) == 0) { cc_status.flags |= CC_NOT_NEGATIVE; operands[1] = GEN_INT (mask >> 8); return AS2 (test%B0,%1,%h0); } } return AS2 (test%L0,%1,%0); }") ;; ??? All bets are off if operand 0 is a volatile MEM reference. ;; The CPU may access unspecified bytes around the actual target byte. (define_insn "" [(set (cc0) (zero_extract (match_operand:QI 0 "general_operand" "rm") (match_operand:SI 1 "const_int_operand" "n") (match_operand:SI 2 "const_int_operand" "n")))] "GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0])" "* { unsigned int mask; mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]); operands[1] = GEN_INT (mask); if (! REG_P (operands[0]) || QI_REG_P (operands[0])) { if ((mask & ~0xff) == 0) { cc_status.flags |= CC_NOT_NEGATIVE; return AS2 (test%B0,%1,%b0); } if ((mask & ~0xff00) == 0) { cc_status.flags |= CC_NOT_NEGATIVE; operands[1] = GEN_INT (mask >> 8); if (QI_REG_P (operands[0])) return AS2 (test%B0,%1,%h0); else { operands[0] = adj_offsettable_operand (operands[0], 1); return AS2 (test%B0,%1,%b0); } } if (GET_CODE (operands[0]) == MEM && (mask & ~0xff0000) == 0) { cc_status.flags |= CC_NOT_NEGATIVE; operands[1] = GEN_INT (mask >> 16); operands[0] = adj_offsettable_operand (operands[0], 2); return AS2 (test%B0,%1,%b0); } if (GET_CODE (operands[0]) == MEM && (mask & ~0xff000000) == 0) { cc_status.flags |= CC_NOT_NEGATIVE; operands[1] = GEN_INT (mask >> 24); operands[0] = adj_offsettable_operand (operands[0], 3); return AS2 (test%B0,%1,%b0); } } if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) return AS2 (test%L0,%1,%0); return AS2 (test%L1,%0,%1); }") ;; Store-flag instructions. ;; For all sCOND expanders, also expand the compare or test insn that ;; generates cc0. Generate an equality comparison if `seq' or `sne'. ;; The 386 sCOND opcodes can write to memory. But a gcc sCOND insn may ;; not have any input reloads. A MEM write might need an input reload ;; for the address of the MEM. So don't allow MEM as the SET_DEST. (define_expand "seq" [(match_dup 1) (set (match_operand:QI 0 "register_operand" "") (eq:QI (cc0) (const_int 0)))] "" " { if (TARGET_IEEE_FP && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); else operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); }") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=q") (eq:QI (cc0) (const_int 0)))] "" "* { if (cc_prev_status.flags & CC_Z_IN_NOT_C) return AS1 (setnb,%0); else return AS1 (sete,%0); }") (define_expand "sne" [(match_dup 1) (set (match_operand:QI 0 "register_operand" "") (ne:QI (cc0) (const_int 0)))] "" " { if (TARGET_IEEE_FP && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); else operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); }") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=q") (ne:QI (cc0) (const_int 0)))] "" "* { if (cc_prev_status.flags & CC_Z_IN_NOT_C) return AS1 (setb,%0); else return AS1 (setne,%0); } ") (define_expand "sgt" [(match_dup 1) (set (match_operand:QI 0 "register_operand" "") (gt:QI (cc0) (const_int 0)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=q") (gt:QI (cc0) (const_int 0)))] "" "* { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (sete,%0); OUTPUT_JUMP (\"setg %0\", \"seta %0\", NULL_PTR); }") (define_expand "sgtu" [(match_dup 1) (set (match_operand:QI 0 "register_operand" "") (gtu:QI (cc0) (const_int 0)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=q") (gtu:QI (cc0) (const_int 0)))] "" "* return \"seta %0\"; ") (define_expand "slt" [(match_dup 1) (set (match_operand:QI 0 "register_operand" "") (lt:QI (cc0) (const_int 0)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=q") (lt:QI (cc0) (const_int 0)))] "" "* { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (sete,%0); OUTPUT_JUMP (\"setl %0\", \"setb %0\", \"sets %0\"); }") (define_expand "sltu" [(match_dup 1) (set (match_operand:QI 0 "register_operand" "") (ltu:QI (cc0) (const_int 0)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=q") (ltu:QI (cc0) (const_int 0)))] "" "* return \"setb %0\"; ") (define_expand "sge" [(match_dup 1) (set (match_operand:QI 0 "register_operand" "") (ge:QI (cc0) (const_int 0)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=q") (ge:QI (cc0) (const_int 0)))] "" "* { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (sete,%0); OUTPUT_JUMP (\"setge %0\", \"setae %0\", \"setns %0\"); }") (define_expand "sgeu" [(match_dup 1) (set (match_operand:QI 0 "register_operand" "") (geu:QI (cc0) (const_int 0)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=q") (geu:QI (cc0) (const_int 0)))] "" "* return \"setae %0\"; ") (define_expand "sle" [(match_dup 1) (set (match_operand:QI 0 "register_operand" "") (le:QI (cc0) (const_int 0)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=q") (le:QI (cc0) (const_int 0)))] "" "* { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (setb,%0); OUTPUT_JUMP (\"setle %0\", \"setbe %0\", NULL_PTR); }") (define_expand "sleu" [(match_dup 1) (set (match_operand:QI 0 "register_operand" "") (leu:QI (cc0) (const_int 0)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=q") (leu:QI (cc0) (const_int 0)))] "" "* return \"setbe %0\"; ") ;; Basic conditional jump instructions. ;; We ignore the overflow flag for signed branch instructions. ;; For all bCOND expanders, also expand the compare or test insn that ;; generates cc0. Generate an equality comparison if `beq' or `bne'. (define_expand "beq" [(match_dup 1) (set (pc) (if_then_else (eq (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { if (TARGET_IEEE_FP && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); else operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); }") (define_insn "" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { if (cc_prev_status.flags & CC_Z_IN_NOT_C) return \"jnc %l0\"; else return \"je %l0\"; }") (define_expand "bne" [(match_dup 1) (set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { if (TARGET_IEEE_FP && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); else operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); }") (define_insn "" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { if (cc_prev_status.flags & CC_Z_IN_NOT_C) return \"jc %l0\"; else return \"jne %l0\"; }") (define_expand "bgt" [(match_dup 1) (set (pc) (if_then_else (gt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (je,%l0); OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR); }") (define_expand "bgtu" [(match_dup 1) (set (pc) (if_then_else (gtu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "ja %l0") (define_expand "blt" [(match_dup 1) (set (pc) (if_then_else (lt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (je,%l0); OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\"); }") (define_expand "bltu" [(match_dup 1) (set (pc) (if_then_else (ltu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "jb %l0") (define_expand "bge" [(match_dup 1) (set (pc) (if_then_else (ge (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (je,%l0); OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\"); }") (define_expand "bgeu" [(match_dup 1) (set (pc) (if_then_else (geu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "jae %l0") (define_expand "ble" [(match_dup 1) (set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (jb,%l0); OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR); }") (define_expand "bleu" [(match_dup 1) (set (pc) (if_then_else (leu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") (define_insn "" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "jbe %l0") ;; Negated conditional jump instructions. (define_insn "" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { if (cc_prev_status.flags & CC_Z_IN_NOT_C) return \"jc %l0\"; else return \"jne %l0\"; }") (define_insn "" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { if (cc_prev_status.flags & CC_Z_IN_NOT_C) return \"jnc %l0\"; else return \"je %l0\"; }") (define_insn "" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (jne,%l0); OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR); }") (define_insn "" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "jbe %l0") (define_insn "" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (jne,%l0); OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\"); }") (define_insn "" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "jae %l0") (define_insn "" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (jne,%l0); OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\"); }") (define_insn "" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "jb %l0") (define_insn "" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (jae,%l0); OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR); }") (define_insn "" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "ja %l0") ;; Unconditional and other jump instructions (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "jmp %l0") (define_insn "indirect_jump" [(set (pc) (match_operand:SI 0 "general_operand" "rm"))] "" "* { CC_STATUS_INIT; return AS1 (jmp,%*%0); }") ;; Implement switch statements when generating PIC code. Switches are ;; implemented by `tablejump' when not using -fpic. ;; Emit code here to do the range checking and make the index zero based. (define_expand "casesi" [(set (match_dup 5) (minus:SI (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))) (set (cc0) (compare:CC (match_dup 5) (match_operand:SI 2 "general_operand" ""))) (set (pc) (if_then_else (gtu (cc0) (const_int 0)) (label_ref (match_operand 4 "" "")) (pc))) (parallel [(set (pc) (minus:SI (reg:SI 3) (mem:SI (plus:SI (mult:SI (match_dup 5) (const_int 4)) (label_ref (match_operand 3 "" "")))))) (clobber (match_scratch:SI 6 ""))])] "flag_pic" " { operands[5] = gen_reg_rtx (SImode); current_function_uses_pic_offset_table = 1; }") ;; Implement a casesi insn. ;; Each entry in the "addr_diff_vec" looks like this as the result of the ;; two rules below: ;; ;; .long _GLOBAL_OFFSET_TABLE_+[.-.L2] ;; ;; 1. An expression involving an external reference may only use the ;; addition operator, and only with an assembly-time constant. ;; The example above satisfies this because ".-.L2" is a constant. ;; ;; 2. The symbol _GLOBAL_OFFSET_TABLE_ is magic, and at link time is ;; given the value of "GOT - .", where GOT is the actual address of ;; the Global Offset Table. Therefore, the .long above actually ;; stores the value "( GOT - . ) + [ . - .L2 ]", or "GOT - .L2". The ;; expression "GOT - .L2" by itself would generate an error from as(1). ;; ;; The pattern below emits code that looks like this: ;; ;; movl %ebx,reg ;; subl TABLE@GOTOFF(%ebx,index,4),reg ;; jmp reg ;; ;; The addr_diff_vec contents may be directly referenced with @GOTOFF, since ;; the addr_diff_vec is known to be part of this module. ;; ;; The subl above calculates "GOT - (( GOT - . ) + [ . - .L2 ])", which ;; evaluates to just ".L2". (define_insn "" [(set (pc) (minus:SI (reg:SI 3) (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "r") (const_int 4)) (label_ref (match_operand 1 "" "")))))) (clobber (match_scratch:SI 2 "=&r"))] "" "* { rtx xops[4]; xops[0] = operands[0]; xops[1] = operands[1]; xops[2] = operands[2]; xops[3] = pic_offset_table_rtx; output_asm_insn (AS2 (mov%L2,%3,%2), xops); output_asm_insn (\"sub%L2 %l1@GOTOFF(%3,%0,4),%2\", xops); output_asm_insn (AS1 (jmp,%*%2), xops); ASM_OUTPUT_ALIGN_CODE (asm_out_file); RET; }") (define_insn "tablejump" [(set (pc) (match_operand:SI 0 "general_operand" "rm")) (use (label_ref (match_operand 1 "" "")))] "" "* { CC_STATUS_INIT; return AS1 (jmp,%*%0); }") ;; Call insns. ;; If generating PIC code, the predicate indirect_operand will fail ;; for operands[0] containing symbolic references on all of the named ;; call* patterns. Each named pattern is followed by an unnamed pattern ;; that matches any call to a symbolic CONST (ie, a symbol_ref). The ;; unnamed patterns are only used while generating PIC code, because ;; otherwise the named patterns match. ;; Call subroutine returning no value. (define_expand "call_pop" [(parallel [(call (match_operand:QI 0 "indirect_operand" "") (match_operand:SI 1 "general_operand" "")) (set (reg:SI 7) (plus:SI (reg:SI 7) (match_operand:SI 3 "immediate_operand" "")))])] "" " { rtx addr; if (flag_pic) current_function_uses_pic_offset_table = 1; /* With half-pic, force the address into a register. */ addr = XEXP (operands[0], 0); if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) XEXP (operands[0], 0) = force_reg (Pmode, addr); if (! expander_call_insn_operand (operands[0], QImode)) operands[0] = change_address (operands[0], VOIDmode, copy_to_mode_reg (Pmode, XEXP (operands[0], 0))); }") (define_insn "" [(call (match_operand:QI 0 "call_insn_operand" "m") (match_operand:SI 1 "general_operand" "g")) (set (reg:SI 7) (plus:SI (reg:SI 7) (match_operand:SI 3 "immediate_operand" "i")))] "" "* { if (GET_CODE (operands[0]) == MEM && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) { operands[0] = XEXP (operands[0], 0); return AS1 (call,%*%0); } else return AS1 (call,%P0); }") (define_insn "" [(call (mem:QI (match_operand:SI 0 "symbolic_operand" "")) (match_operand:SI 1 "general_operand" "g")) (set (reg:SI 7) (plus:SI (reg:SI 7) (match_operand:SI 3 "immediate_operand" "i")))] "!HALF_PIC_P ()" "call %P0") (define_expand "call" [(call (match_operand:QI 0 "indirect_operand" "") (match_operand:SI 1 "general_operand" ""))] ;; Operand 1 not used on the i386. "" " { rtx addr; if (flag_pic) current_function_uses_pic_offset_table = 1; /* With half-pic, force the address into a register. */ addr = XEXP (operands[0], 0); if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) XEXP (operands[0], 0) = force_reg (Pmode, addr); if (! expander_call_insn_operand (operands[0], QImode)) operands[0] = change_address (operands[0], VOIDmode, copy_to_mode_reg (Pmode, XEXP (operands[0], 0))); }") (define_insn "" [(call (match_operand:QI 0 "call_insn_operand" "m") (match_operand:SI 1 "general_operand" "g"))] ;; Operand 1 not used on the i386. "" "* { if (GET_CODE (operands[0]) == MEM && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) { operands[0] = XEXP (operands[0], 0); return AS1 (call,%*%0); } else return AS1 (call,%P0); }") (define_insn "" [(call (mem:QI (match_operand:SI 0 "symbolic_operand" "")) (match_operand:SI 1 "general_operand" "g"))] ;; Operand 1 not used on the i386. "!HALF_PIC_P ()" "call %P0") ;; Call subroutine, returning value in operand 0 ;; (which must be a hard register). (define_expand "call_value_pop" [(parallel [(set (match_operand 0 "" "") (call (match_operand:QI 1 "indirect_operand" "") (match_operand:SI 2 "general_operand" ""))) (set (reg:SI 7) (plus:SI (reg:SI 7) (match_operand:SI 4 "immediate_operand" "")))])] "" " { rtx addr; if (flag_pic) current_function_uses_pic_offset_table = 1; /* With half-pic, force the address into a register. */ addr = XEXP (operands[1], 0); if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) XEXP (operands[1], 0) = force_reg (Pmode, addr); if (! expander_call_insn_operand (operands[1], QImode)) operands[1] = change_address (operands[1], VOIDmode, copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); }") (define_insn "" [(set (match_operand 0 "" "=rf") (call (match_operand:QI 1 "call_insn_operand" "m") (match_operand:SI 2 "general_operand" "g"))) (set (reg:SI 7) (plus:SI (reg:SI 7) (match_operand:SI 4 "immediate_operand" "i")))] "" "* { if (GET_CODE (operands[1]) == MEM && ! CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) { operands[1] = XEXP (operands[1], 0); output_asm_insn (AS1 (call,%*%1), operands); } else output_asm_insn (AS1 (call,%P1), operands); RET; }") (define_insn "" [(set (match_operand 0 "" "=rf") (call (mem:QI (match_operand:SI 1 "symbolic_operand" "")) (match_operand:SI 2 "general_operand" "g"))) (set (reg:SI 7) (plus:SI (reg:SI 7) (match_operand:SI 4 "immediate_operand" "i")))] "!HALF_PIC_P ()" "call %P1") (define_expand "call_value" [(set (match_operand 0 "" "") (call (match_operand:QI 1 "indirect_operand" "") (match_operand:SI 2 "general_operand" "")))] ;; Operand 2 not used on the i386. "" " { rtx addr; if (flag_pic) current_function_uses_pic_offset_table = 1; /* With half-pic, force the address into a register. */ addr = XEXP (operands[1], 0); if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) XEXP (operands[1], 0) = force_reg (Pmode, addr); if (! expander_call_insn_operand (operands[1], QImode)) operands[1] = change_address (operands[1], VOIDmode, copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); }") (define_insn "" [(set (match_operand 0 "" "=rf") (call (match_operand:QI 1 "call_insn_operand" "m") (match_operand:SI 2 "general_operand" "g")))] ;; Operand 2 not used on the i386. "" "* { if (GET_CODE (operands[1]) == MEM && ! CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) { operands[1] = XEXP (operands[1], 0); output_asm_insn (AS1 (call,%*%1), operands); } else output_asm_insn (AS1 (call,%P1), operands); RET; }") (define_insn "" [(set (match_operand 0 "" "=rf") (call (mem:QI (match_operand:SI 1 "symbolic_operand" "")) (match_operand:SI 2 "general_operand" "g")))] ;; Operand 2 not used on the i386. "!HALF_PIC_P ()" "call %P1") (define_expand "untyped_call" [(parallel [(call (match_operand:QI 0 "indirect_operand" "") (const_int 0)) (match_operand:BLK 1 "memory_operand" "") (match_operand 2 "" "")])] "" " { rtx addr; if (flag_pic) current_function_uses_pic_offset_table = 1; /* With half-pic, force the address into a register. */ addr = XEXP (operands[0], 0); if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) XEXP (operands[0], 0) = force_reg (Pmode, addr); operands[1] = change_address (operands[1], DImode, XEXP (operands[1], 0)); if (! expander_call_insn_operand (operands[1], QImode)) operands[1] = change_address (operands[1], VOIDmode, copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); }") (define_insn "" [(call (match_operand:QI 0 "call_insn_operand" "m") (const_int 0)) (match_operand:DI 1 "memory_operand" "o") (match_operand 2 "" "")] "" "* { rtx addr = operands[1]; if (GET_CODE (operands[0]) == MEM && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) { operands[0] = XEXP (operands[0], 0); output_asm_insn (AS1 (call,%*%0), operands); } else output_asm_insn (AS1 (call,%P0), operands); operands[2] = gen_rtx (REG, SImode, 0); output_asm_insn (AS2 (mov%L2,%2,%1), operands); operands[2] = gen_rtx (REG, SImode, 1); operands[1] = adj_offsettable_operand (addr, 4); output_asm_insn (AS2 (mov%L2,%2,%1), operands); operands[1] = adj_offsettable_operand (addr, 8); return AS1 (fnsave,%1); }") (define_insn "" [(call (mem:QI (match_operand:SI 0 "symbolic_operand" "")) (const_int 0)) (match_operand:DI 1 "memory_operand" "o") (match_operand 2 "" "")] "!HALF_PIC_P ()" "* { rtx addr = operands[1]; output_asm_insn (AS1 (call,%P0), operands); operands[2] = gen_rtx (REG, SImode, 0); output_asm_insn (AS2 (mov%L2,%2,%1), operands); operands[2] = gen_rtx (REG, SImode, 1); operands[1] = adj_offsettable_operand (addr, 4); output_asm_insn (AS2 (mov%L2,%2,%1), operands); operands[1] = adj_offsettable_operand (addr, 8); return AS1 (fnsave,%1); }") ;; We use fnsave and frstor to save and restore the floating point result. ;; These are expensive instructions and require a large space to save the ;; FPU state. An more complicated alternative is to use fnstenv to store ;; the FPU environment and test whether the stack top is valid. Store the ;; result of the test, and if it is valid, pop and save the value. The ;; untyped_return would check the test and optionally push the saved value. (define_expand "untyped_return" [(match_operand:BLK 0 "memory_operand" "") (match_operand 1 "" "")] "" " { rtx valreg1 = gen_rtx (REG, SImode, 0); rtx valreg2 = gen_rtx (REG, SImode, 1); rtx result = operands[0]; /* Restore the FPU state. */ emit_insn (gen_update_return (change_address (result, SImode, plus_constant (XEXP (result, 0), 8)))); /* Reload the function value registers. */ emit_move_insn (valreg1, change_address (result, SImode, XEXP (result, 0))); emit_move_insn (valreg2, change_address (result, SImode, plus_constant (XEXP (result, 0), 4))); /* Put USE insns before the return. */ emit_insn (gen_rtx (USE, VOIDmode, valreg1)); emit_insn (gen_rtx (USE, VOIDmode, valreg2)); /* Construct the return. */ expand_null_return (); DONE; }") (define_insn "update_return" [(unspec:SI [(match_operand:SI 0 "memory_operand" "m")] 0)] "" "frstor %0") ;; Insn emitted into the body of a function to return from a function. ;; This is only done if the function's epilogue is known to be simple. ;; See comments for simple_386_epilogue in i386.c. (define_insn "return" [(return)] "simple_386_epilogue ()" "* { function_epilogue (asm_out_file, get_frame_size ()); RET; }") (define_insn "nop" [(const_int 0)] "" "nop") (define_expand "movstrsi" [(parallel [(set (match_operand:BLK 0 "memory_operand" "") (match_operand:BLK 1 "memory_operand" "")) (use (match_operand:SI 2 "const_int_operand" "")) (use (match_operand:SI 3 "const_int_operand" "")) (clobber (match_scratch:SI 4 "")) (clobber (match_dup 5)) (clobber (match_dup 6))])] "" " { rtx addr0, addr1; if (GET_CODE (operands[2]) != CONST_INT) FAIL; addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); operands[5] = addr0; operands[6] = addr1; operands[0] = gen_rtx (MEM, BLKmode, addr0); operands[1] = gen_rtx (MEM, BLKmode, addr1); }") ;; It might seem that operands 0 & 1 could use predicate register_operand. ;; But strength reduction might offset the MEM expression. So we let ;; reload put the address into %edi & %esi. (define_insn "" [(set (mem:BLK (match_operand:SI 0 "address_operand" "D")) (mem:BLK (match_operand:SI 1 "address_operand" "S"))) (use (match_operand:SI 2 "const_int_operand" "n")) (use (match_operand:SI 3 "immediate_operand" "i")) (clobber (match_scratch:SI 4 "=&c")) (clobber (match_dup 0)) (clobber (match_dup 1))] "" "* { rtx xops[2]; output_asm_insn (\"cld\", operands); if (GET_CODE (operands[2]) == CONST_INT) { if (INTVAL (operands[2]) & ~0x03) { xops[0] = GEN_INT ((INTVAL (operands[2]) >> 2) & 0x3fffffff); xops[1] = operands[4]; output_asm_insn (AS2 (mov%L1,%0,%1), xops); #ifdef INTEL_SYNTAX output_asm_insn (\"rep movsd\", xops); #else output_asm_insn (\"rep\;movsl\", xops); #endif } if (INTVAL (operands[2]) & 0x02) output_asm_insn (\"movsw\", operands); if (INTVAL (operands[2]) & 0x01) output_asm_insn (\"movsb\", operands); } else abort (); RET; }") (define_expand "cmpstrsi" [(parallel [(set (match_operand:SI 0 "general_operand" "") (compare:SI (match_operand:BLK 1 "general_operand" "") (match_operand:BLK 2 "general_operand" ""))) (use (match_operand:SI 3 "general_operand" "")) (use (match_operand:SI 4 "immediate_operand" "")) (clobber (match_dup 5)) (clobber (match_dup 6)) (clobber (match_dup 3))])] "" " { rtx addr1, addr2; addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0)); operands[3] = copy_to_mode_reg (SImode, operands[3]); operands[5] = addr1; operands[6] = addr2; operands[1] = gen_rtx (MEM, BLKmode, addr1); operands[2] = gen_rtx (MEM, BLKmode, addr2); }") ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is ;; zero. Emit extra code to make sure that a zero-length compare is EQ. ;; It might seem that operands 0 & 1 could use predicate register_operand. ;; But strength reduction might offset the MEM expression. So we let ;; reload put the address into %edi & %esi. ;; ??? Most comparisons have a constant length, and it's therefore ;; possible to know that the length is non-zero, and to avoid the extra ;; code to handle zero-length compares. (define_insn "" [(set (match_operand:SI 0 "general_operand" "=&r") (compare:SI (mem:BLK (match_operand:SI 1 "address_operand" "S")) (mem:BLK (match_operand:SI 2 "address_operand" "D")))) (use (match_operand:SI 3 "register_operand" "c")) (use (match_operand:SI 4 "immediate_operand" "i")) (clobber (match_dup 1)) (clobber (match_dup 2)) (clobber (match_dup 3))] "" "* { rtx xops[4], label; label = gen_label_rtx (); output_asm_insn (\"cld\", operands); output_asm_insn (AS2 (xor%L0,%0,%0), operands); output_asm_insn (\"repz\;cmps%B2\", operands); output_asm_insn (\"je %l0\", &label); xops[0] = operands[0]; xops[1] = gen_rtx (MEM, QImode, gen_rtx (PLUS, SImode, operands[1], constm1_rtx)); xops[2] = gen_rtx (MEM, QImode, gen_rtx (PLUS, SImode, operands[2], constm1_rtx)); xops[3] = operands[3]; output_asm_insn (AS2 (movz%B1%L0,%1,%0), xops); output_asm_insn (AS2 (movz%B2%L3,%2,%3), xops); output_asm_insn (AS2 (sub%L0,%3,%0), xops); ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (label)); RET; }") (define_insn "" [(set (cc0) (compare:SI (mem:BLK (match_operand:SI 0 "address_operand" "S")) (mem:BLK (match_operand:SI 1 "address_operand" "D")))) (use (match_operand:SI 2 "register_operand" "c")) (use (match_operand:SI 3 "immediate_operand" "i")) (clobber (match_dup 0)) (clobber (match_dup 1)) (clobber (match_dup 2))] "" "* { rtx xops[2]; cc_status.flags |= CC_NOT_SIGNED; xops[0] = gen_rtx (REG, QImode, 0); xops[1] = CONST0_RTX (QImode); output_asm_insn (\"cld\", operands); output_asm_insn (AS2 (test%B0,%1,%0), xops); return \"repz\;cmps%B2\"; }") (define_expand "ffssi2" [(set (match_dup 2) (plus:SI (ffs:SI (match_operand:SI 1 "general_operand" "")) (const_int -1))) (set (match_operand:SI 0 "general_operand" "") (plus:SI (match_dup 2) (const_int 1)))] "" "operands[2] = gen_reg_rtx (SImode);") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=&r") (plus:SI (ffs:SI (match_operand:SI 1 "general_operand" "rm")) (const_int -1)))] "" "* { rtx xops[3]; static int ffssi_label_number; char buffer[30]; xops[0] = operands[0]; xops[1] = operands[1]; xops[2] = constm1_rtx; /* Can there be a way to avoid the jump here? */ output_asm_insn (AS2 (bsf%L0,%1,%0), xops); #ifdef LOCAL_LABEL_PREFIX sprintf (buffer, \"jnz %sLFFSSI%d\", LOCAL_LABEL_PREFIX, ffssi_label_number); #else sprintf (buffer, \"jnz %sLFFSSI%d\", \"\", ffssi_label_number); #endif output_asm_insn (buffer, xops); output_asm_insn (AS2 (mov%L0,%2,%0), xops); #ifdef LOCAL_LABEL_PREFIX sprintf (buffer, \"%sLFFSSI%d:\", LOCAL_LABEL_PREFIX, ffssi_label_number); #else sprintf (buffer, \"%sLFFSSI%d:\", \"\", ffssi_label_number); #endif output_asm_insn (buffer, xops); ffssi_label_number++; return \"\"; }") (define_expand "ffshi2" [(set (match_dup 2) (plus:HI (ffs:HI (match_operand:HI 1 "general_operand" "")) (const_int -1))) (set (match_operand:HI 0 "general_operand" "") (plus:HI (match_dup 2) (const_int 1)))] "" "operands[2] = gen_reg_rtx (HImode);") (define_insn "" [(set (match_operand:HI 0 "general_operand" "=&r") (plus:HI (ffs:HI (match_operand:SI 1 "general_operand" "rm")) (const_int -1)))] "" "* { rtx xops[3]; static int ffshi_label_number; char buffer[30]; xops[0] = operands[0]; xops[1] = operands[1]; xops[2] = constm1_rtx; output_asm_insn (AS2 (bsf%W0,%1,%0), xops); #ifdef LOCAL_LABEL_PREFIX sprintf (buffer, \"jnz %sLFFSHI%d\", LOCAL_LABEL_PREFIX, ffshi_label_number); #else sprintf (buffer, \"jnz %sLFFSHI%d\", \"\", ffshi_label_number); #endif output_asm_insn (buffer, xops); output_asm_insn (AS2 (mov%W0,%2,%0), xops); #ifdef LOCAL_LABEL_PREFIX sprintf (buffer, \"%sLFFSHI%d:\", LOCAL_LABEL_PREFIX, ffshi_label_number); #else sprintf (buffer, \"%sLFFSHI%d:\", \"\", ffshi_label_number); #endif output_asm_insn (buffer, xops); ffshi_label_number++; return \"\"; }") ;; These patterns match the binary 387 instructions for addM3, subM3, ;; mulM3 and divM3. There are three patterns for each of DFmode and ;; SFmode. The first is the normal insn, the second the same insn but ;; with one operand a conversion, and the third the same insn but with ;; the other operand a conversion. The conversion may be SFmode or ;; SImode if the target mode DFmode, but only SImode if the target mode ;; is SFmode. (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f,f") (match_operator:DF 3 "binary_387_op" [(match_operand:DF 1 "nonimmediate_operand" "0,fm") (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))] "TARGET_80387" "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (match_operator:DF 3 "binary_387_op" [(float:DF (match_operand:SI 1 "general_operand" "rm")) (match_operand:DF 2 "general_operand" "0")]))] "TARGET_80387" "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f,f") (match_operator:XF 3 "binary_387_op" [(match_operand:XF 1 "nonimmediate_operand" "0,f") (match_operand:XF 2 "nonimmediate_operand" "f,0")]))] "TARGET_80387" "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") (match_operator:XF 3 "binary_387_op" [(float:XF (match_operand:SI 1 "general_operand" "rm")) (match_operand:XF 2 "general_operand" "0")]))] "TARGET_80387" "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f,f") (match_operator:XF 3 "binary_387_op" [(float_extend:XF (match_operand:SF 1 "general_operand" "fm,0")) (match_operand:XF 2 "general_operand" "0,f")]))] "TARGET_80387" "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") (match_operator:XF 3 "binary_387_op" [(match_operand:XF 1 "general_operand" "0") (float:XF (match_operand:SI 2 "general_operand" "rm"))]))] "TARGET_80387" "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f,f") (match_operator:XF 3 "binary_387_op" [(match_operand:XF 1 "general_operand" "0,f") (float_extend:XF (match_operand:SF 2 "general_operand" "fm,0"))]))] "TARGET_80387" "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f,f") (match_operator:DF 3 "binary_387_op" [(float_extend:DF (match_operand:SF 1 "general_operand" "fm,0")) (match_operand:DF 2 "general_operand" "0,f")]))] "TARGET_80387" "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (match_operator:DF 3 "binary_387_op" [(match_operand:DF 1 "general_operand" "0") (float:DF (match_operand:SI 2 "general_operand" "rm"))]))] "TARGET_80387" "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f,f") (match_operator:DF 3 "binary_387_op" [(match_operand:DF 1 "general_operand" "0,f") (float_extend:DF (match_operand:SF 2 "general_operand" "fm,0"))]))] "TARGET_80387" "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=f,f") (match_operator:SF 3 "binary_387_op" [(match_operand:SF 1 "nonimmediate_operand" "0,fm") (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))] "TARGET_80387" "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=f") (match_operator:SF 3 "binary_387_op" [(float:SF (match_operand:SI 1 "general_operand" "rm")) (match_operand:SF 2 "general_operand" "0")]))] "TARGET_80387" "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=f") (match_operator:SF 3 "binary_387_op" [(match_operand:SF 1 "general_operand" "0") (float:SF (match_operand:SI 2 "general_operand" "rm"))]))] "TARGET_80387" "* return (char *) output_387_binary_op (insn, operands);") (define_expand "strlensi" [(parallel [(set (match_dup 4) (unspec:SI [(mem:BLK (match_operand:BLK 1 "general_operand" "")) (match_operand:QI 2 "register_operand" "") (match_operand:SI 3 "immediate_operand" "")] 0)) (clobber (match_dup 1))]) (set (match_dup 5) (not:SI (match_dup 4))) (set (match_operand:SI 0 "register_operand" "") (minus:SI (match_dup 5) (const_int 1)))] "" " { operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); operands[4] = gen_reg_rtx (SImode); operands[5] = gen_reg_rtx (SImode); }") ;; It might seem that operands 0 & 1 could use predicate register_operand. ;; But strength reduction might offset the MEM expression. So we let ;; reload put the address into %edi. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=&c") (unspec:SI [(mem:BLK (match_operand:SI 1 "address_operand" "D")) (match_operand:QI 2 "register_operand" "a") (match_operand:SI 3 "immediate_operand" "i")] 0)) (clobber (match_dup 1))] "" "* { rtx xops[2]; xops[0] = operands[0]; xops[1] = constm1_rtx; output_asm_insn (\"cld\", operands); output_asm_insn (AS2 (mov%L0,%1,%0), xops); return \"repnz\;scas%B2\"; }") gcc-2.5.8/config/i386/i386iscgas.h100444 22011 13 4743 5451700405 14765 0ustar kenneruser/* Definitions for Intel 386 running Interactive Unix System V, producing stabs-in-coff output (using a slightly modified gas). Specifically, this is for recent versions that support POSIX; for version 2.0.2, use configuration option i386-sysv instead. */ /* Underscores are not used on ISC systems (probably not on any COFF system), despite the comments in i386/gas.h. If this is not defined, enquire (for example) will fail to link. --karl@cs.umb.edu */ #define NO_UNDERSCORES /* Mostly like other gas-using systems. */ #include "i386/gas.h" /* But with ISC-specific additions. */ #include "i386/isc.h" /* We do not want to output SDB debugging information. */ #undef SDB_DEBUGGING_INFO /* We want to output DBX debugging information. */ #define DBX_DEBUGGING_INFO /* The function `dbxout_init' in dbxout.c omits the first character of `ltext_label_name' when outputting the main source directory and main source filename. I don't understand why, but rather than making a system-independent change there, I override dbxout.c's defaults. Perhaps it would be better to use ".Ltext0" instead of `ltext_label_name', but we've already generated the label, so we just use it here. --karl@cs.umb.edu */ #define DBX_OUTPUT_MAIN_SOURCE_DIRECTORY(asmfile, cwd) \ do { fprintf (asmfile, "%s ", ASM_STABS_OP); \ output_quoted_string (asmfile, cwd); \ fprintf (asmfile, ",%d,0,0,%s\n", N_SO, ltext_label_name); \ } while (0) #define DBX_OUTPUT_MAIN_SOURCE_FILENAME(asmfile, input_file_name) \ fprintf (asmfile, "%s ", ASM_STABS_OP); \ output_quoted_string (input_file_name); \ fprintf (asmfile, ",%d,0,0,%s\n", N_SO, ltext_label_name); \ text_section (); \ ASM_OUTPUT_INTERNAL_LABEL (asmfile, "Ltext", 0) /* Because we don't include `svr3.h', we haven't yet defined SIZE_TYPE and PTRDIFF_TYPE. ISC's definitions don't match GCC's defaults, so: */ #undef SIZE_TYPE #define SIZE_TYPE "unsigned int" #undef PTRDIFF_TYPE #define PTRDIFF_TYPE "int" /* But we can't use crtbegin.o and crtend.o, because gas 1.38.1 doesn't grok .section. The definitions here are otherwise identical to those in i386/isc.h. */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{!shlib:%{posix:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\ %{!posix:%{pg:mcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}\ %{p:-L/lib/libp} %{pg:-L/lib/libp}}}\ %{shlib:%{posix:crtp1.o%s}%{!posix:crt1.o%s}}" #undef ENDFILE_SPEC #define ENDFILE_SPEC "crtn.o%s" gcc-2.5.8/config/i386/isc.h100444 22011 13 4172 5461144006 13654 0ustar kenneruser/* Assembler-independent definitions for an Intel 386 running Interactive Unix System V. Specifically, this is for recent versions that support POSIX. */ /* Use crt1.o, not crt0.o, as a startup file, and crtn.o as a closing file. */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{!shlib:%{posix:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\ %{!posix:%{pg:mcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}\ %{p:-L/lib/libp} %{pg:-L/lib/libp}}}\ %{shlib:%{posix:crtp1.o%s}%{!posix:crt1.o%s}} crtbegin.o%s" #define ENDFILE_SPEC "crtend.o%s crtn.o%s" /* Library spec */ #undef LIB_SPEC #define LIB_SPEC "%{shlib:-lc_s} %{posix:-lcposix} -lc -lg" /* ISC 2.2 uses `char' for `wchar_t'. */ #undef WCHAR_TYPE #define WCHAR_TYPE "char" #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE BITS_PER_UNIT #if 0 /* This is apparently not true: ISC versions up to 3.0, at least, use the standard calling sequence in which the called function pops the extra arg. */ /* caller has to pop the extra argument passed to functions that return structures. */ #undef RETURN_POPS_ARGS #define RETURN_POPS_ARGS(FUNTYPE,SIZE) \ (TREE_CODE (FUNTYPE) == IDENTIFIER_NODE ? 0 \ : (TARGET_RTD \ && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ == void_type_node))) ? (SIZE) \ : 0) /* On other 386 systems, the last line looks like this: : (aggregate_value_p (TREE_TYPE (FUNTYPE))) ? GET_MODE_SIZE (Pmode) : 0) */ #endif /* Handle #pragma pack and #pragma weak. */ #define HANDLE_SYSV_PRAGMA /* By default, target has a 80387, uses IEEE compatible arithmetic, and returns float values in the 387, ie, (TARGET_80387 | TARGET_FLOAT_RETURNS_IN_80387) ISC's software emulation of a 387 fails to handle the `fucomp' opcode. fucomp is only used when generating IEEE compliant code. So don't make TARGET_IEEE_FP default for ISC. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT 0201 /* The ISC 2.0.2 software FPU emulator apparently can't handle 80-bit XFmode insns, so don't generate them. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 gcc-2.5.8/config/i386/isccoff.h100444 22011 13 631 5402543501 14464 0ustar kenneruser/* Definitions for Intel 386 running Interactive Unix System V. Specifically, this is for recent versions that support POSIX; for version 2.0.2, use configuration option i386-sysv instead. (But set TARGET_DEFAULT to 0201 if you do that, if you don't have a real 80387.) */ /* Mostly it's like AT&T Unix System V. */ #include "i386/sysv3.h" /* But with a few changes. */ #include "i386/isc.h" gcc-2.5.8/config/i386/iscdbx.h100444 22011 13 2723 5447744644 14374 0ustar kenneruser/* Definitions for Intel 386 running Interactive Unix System V, using dbx-in-coff encapsulation. Specifically, this is for recent versions that support POSIX. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Mostly it's like AT&T Unix System V with dbx-in-coff. */ #include "i386/svr3dbx.h" /* But with a few changes. */ #undef ENDFILE_SPEC #include "i386/isc.h" /* Overridden defines for ifile usage. */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{!r:%{!z:svr3.ifile%s}%{z:svr3z.ifile%s}}\ %{!shlib:%{posix:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\ %{!posix:%{pg:mcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}}\ %{p:-L/usr/lib/libp} %{pg:-L/usr/lib/libp}}\ %{shlib:%{posix:crtp1.o%s}%{!posix:crt1.o%s}}" #undef ENDFILE_SPEC #define ENDFILE_SPEC "crtn.o%s" gcc-2.5.8/config/i386/linux.h100444 22011 13 5443 5464301024 14235 0ustar kenneruser/* Definitions for Intel 386 running Linux * Copyright (C) 1992 Free Software Foundation, Inc. * * Written by H.J. Lu (hlu@eecs.wsu.edu) * * Linux is a POSIX.1 compatible UNIX clone for i386, which uses GNU * stuffs as the native stuffs. */ #if 0 /* The FSF has fixed the known bugs. But ....... */ /* Linux has a hacked gas 1.38.1, which can handle repz, repnz * and fildll. */ #define GOOD_GAS #endif /* This is tested by i386/gas.h. */ #define YES_UNDERSCORES #ifndef LINUX_ELF #include "i386/gstabs.h" #endif /* Specify predefined symbols in preprocessor. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dunix -Di386 -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(i386) -Amachine(i386)" #undef CPP_SPEC #if TARGET_CPU_DEFAULT == 2 #define CPP_SPEC "%{!m386:-D__i486__} %{posix:-D_POSIX_SOURCE}" #else #define CPP_SPEC "%{m486:-D__i486__} %{posix:-D_POSIX_SOURCE}" #endif #undef SIZE_TYPE #define SIZE_TYPE "unsigned int" #undef PTRDIFF_TYPE #define PTRDIFF_TYPE "int" #undef WCHAR_TYPE #define WCHAR_TYPE "long int" #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE BITS_PER_WORD #undef HAVE_ATEXIT #define HAVE_ATEXIT /* Linux uses ctype from glibc.a. I am not sure how complete it is. * For now, we play safe. It may change later. */ #if 0 #undef MULTIBYTE_CHARS #define MULTIBYTE_CHARS 1 #endif #undef LIB_SPEC #define LIB_SPEC "%{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} %{!p:%{!pg:%{!g*:-lc} %{g*:-lg}}}" #undef STARTFILE_SPEC #undef GPLUSPLUS_INCLUDE_DIR #ifdef CROSS_COMPILE /* * For cross-compile, we just need to search `$(tooldir)/lib' */ #define STARTFILE_SPEC \ "%{pg:gcrt0.o%s -static} %{!pg:%{p:gcrt0.o%s -static} %{!p:crt0.o%s %{g*:-static} %{!static:%{nojump:-nojump}} %{static:-static}}} -L"TOOLDIR"/lib" /* *The cross-compile uses this. */ #define GPLUSPLUS_INCLUDE_DIR TOOLDIR"/g++-include" #else #define STARTFILE_SPEC \ "%{pg:gcrt0.o%s -static} %{!pg:%{p:gcrt0.o%s -static} %{!p:crt0.o%s %{g*:-static}%{!static:%{nojump:-nojump}} %{static:-static}}}" /* *The native Linux system uses this. */ #define GPLUSPLUS_INCLUDE_DIR "/usr/g++-include" #endif /* There are conflicting reports about whether this system uses a different assembler syntax. wilson@cygnus.com says # is right. */ #undef COMMENT_BEGIN #define COMMENT_BEGIN "#" #undef ASM_APP_ON #define ASM_APP_ON "#APP\n" #undef ASM_APP_OFF #define ASM_APP_OFF "#NO_APP\n" /* Don't default to pcc-struct-return, because gcc is the only compiler, and we want to retain compatibility with older gcc versions. */ #define DEFAULT_PCC_STRUCT_RETURN 0 /* We need that too. */ #define HANDLE_SYSV_PRAGMA #undef LINK_SPEC /* We want to pass -v to linker */ #if TARGET_CPU_DEFAULT == 2 #define LINK_SPEC "%{v:-dll-verbose} %{!m386:-m486}" #else #define LINK_SPEC "%{v:-dll-verbose} %{m486:-m486}" #endif gcc-2.5.8/config/i386/linuxelf.h100444 22011 13 11051 5455357157 14756 0ustar kenneruser/* Definitions for Intel 386 running Linux with ELF format Written by Eric Youngdale. */ /* A lie, I guess, but the general idea behind linux/ELF is that we are supposed to be outputting something that will assemble under SVr4. This gets us pretty close. */ #include "i386/i386.h" /* Base i386 target machine definitions */ #include "i386/att.h" /* Use the i386 AT&T assembler syntax */ #include "svr4.h" #undef MD_EXEC_PREFIX #undef MD_STARTFILE_PREFIX #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (i386 Linux/ELF)"); /* Output at beginning of assembler file. */ /* The .file command should always begin the output. */ #undef ASM_FILE_START #define ASM_FILE_START(FILE) \ do { \ output_file_directive (FILE, main_input_filename); \ fprintf (FILE, "\t.version\t\"01.01\"\n"); \ } while (0) /* The svr4 ABI for the i386 says that records and unions are returned in memory. */ #undef RETURN_IN_MEMORY #define RETURN_IN_MEMORY(TYPE) \ (TYPE_MODE (TYPE) == BLKmode) /* This is how to output an element of a case-vector that is relative. This is only used for PIC code. See comments by the `casesi' insn in i386.md for an explanation of the expression this outputs. */ #undef ASM_OUTPUT_ADDR_DIFF_ELT #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE) /* Indicate that jump tables go in the text section. This is necessary when compiling PIC code. */ #define JUMP_TABLES_IN_TEXT_SECTION /* Copy this from the svr4 specifications... */ /* Define the register numbers to be used in Dwarf debugging information. The SVR4 reference port C compiler uses the following register numbers in its Dwarf output code: 0 for %eax (gnu regno = 0) 1 for %ecx (gnu regno = 2) 2 for %edx (gnu regno = 1) 3 for %ebx (gnu regno = 3) 4 for %esp (gnu regno = 7) 5 for %ebp (gnu regno = 6) 6 for %esi (gnu regno = 4) 7 for %edi (gnu regno = 5) The following three DWARF register numbers are never generated by the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4 believes these numbers have these meanings. 8 for %eip (no gnu equivalent) 9 for %eflags (no gnu equivalent) 10 for %trapno (no gnu equivalent) It is not at all clear how we should number the FP stack registers for the x86 architecture. If the version of SDB on x86/svr4 were a bit less brain dead with respect to floating-point then we would have a precedent to follow with respect to DWARF register numbers for x86 FP registers, but the SDB on x86/svr4 is so completely broken with respect to FP registers that it is hardly worth thinking of it as something to strive for compatibility with. The verison of x86/svr4 SDB I have at the moment does (partially) seem to believe that DWARF register number 11 is associated with the x86 register %st(0), but that's about all. Higher DWARF register numbers don't seem to be associated with anything in particular, and even for DWARF regno 11, SDB only seems to under- stand that it should say that a variable lives in %st(0) (when asked via an `=' command) if we said it was in DWARF regno 11, but SDB still prints garbage when asked for the value of the variable in question (via a `/' command). (Also note that the labels SDB prints for various FP stack regs when doing an `x' command are all wrong.) Note that these problems generally don't affect the native SVR4 C compiler because it doesn't allow the use of -O with -g and because when it is *not* optimizing, it allocates a memory location for each floating-point variable, and the memory location is what gets described in the DWARF AT_location attribute for the variable in question. Regardless of the severe mental illness of the x86/svr4 SDB, we do something sensible here and we use the following DWARF register numbers. Note that these are all stack-top-relative numbers. 11 for %st(0) (gnu regno = 8) 12 for %st(1) (gnu regno = 9) 13 for %st(2) (gnu regno = 10) 14 for %st(3) (gnu regno = 11) 15 for %st(4) (gnu regno = 12) 16 for %st(5) (gnu regno = 13) 17 for %st(6) (gnu regno = 14) 18 for %st(7) (gnu regno = 15) */ #undef DBX_REGISTER_NUMBER #define DBX_REGISTER_NUMBER(n) \ ((n) == 0 ? 0 \ : (n) == 1 ? 2 \ : (n) == 2 ? 1 \ : (n) == 3 ? 3 \ : (n) == 4 ? 6 \ : (n) == 5 ? 7 \ : (n) == 6 ? 5 \ : (n) == 7 ? 4 \ : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \ : (-1)) #define LINUX_ELF #include "i386/linux.h" #undef YES_UNDERSCORE #undef DBX_DEBUGGING_INFO #define DWARF_DEBUGGING_INFO gcc-2.5.8/config/i386/lynx.h100444 22011 13 1705 5453234523 14074 0ustar kenneruser/* Definitions for Intel 386 running LynxOS. Copyright (C) 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "i386/gstabs.h" #include "lynx.h" #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dunix -Di386 -DI386 -DLynx -DIBITS32 -Asystem(unix) -Asystem(lynx) -Acpu(i386) -Amachine(i386)" gcc-2.5.8/config/i386/mach.h100444 22011 13 1275 5453234526 14017 0ustar kenneruser/* Configuration for an i386 running Mach as the target machine. */ /* We do want to add an underscore to the front of each user symbol. i386/gas.h checks this. */ #define YES_UNDERSCORES #include "i386/gstabs.h" /* Get perform_* macros to build libgcc.a. */ #include "i386/perform.h" #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dunix -Di386 -DMACH -Asystem(unix) -Asystem(mach) -Acpu(i386) -Amachine(i386)" /* Specify extra dir to search for include files. */ #define SYSTEM_INCLUDE_DIR "/usr/mach/include" /* Don't default to pcc-struct-return, because gcc is the only compiler, and we want to retain compatibility with older gcc versions. */ #define DEFAULT_PCC_STRUCT_RETURN 0 gcc-2.5.8/config/i386/next.c100444 22011 13 352 5361400405 14020 0ustar kenneruser/* next.c: Functions for NeXT as target machine for GNU C compiler. */ /* Note that the include below means that we can't debug routines in i386.c when running on a COFF system. */ #include "i386/i386.c" #include "nextstep.c" gcc-2.5.8/config/i386/next.h100444 22011 13 16103 5453662504 14102 0ustar kenneruser/* Target definitions for GNU compiler for Intel x86 CPU running NeXTSTEP Copyright (C) 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "i386/gas.h" #include "nextstep.h" /* By default, target has a 80387, with IEEE FP. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (1|0100) /* Implicit library calls should use memcpy, not bcopy, etc. */ #define TARGET_MEM_FUNCTIONS /* Machines that use the AT&T assembler syntax also return floating point values in an FP register. Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */ #undef VALUE_REGNO #define VALUE_REGNO(MODE) \ ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ ? FIRST_FLOAT_REG : 0) /* 1 if N is a possible register number for a function value. */ #undef FUNCTION_VALUE_REGNO_P #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N)== FIRST_FLOAT_REG) #ifdef REAL_VALUE_TO_TARGET_LONG_DOUBLE #undef ASM_OUTPUT_LONG_DOUBLE #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ do { \ long hex[3]; \ REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, hex); \ if (sizeof (int) == sizeof (long)) \ fprintf (FILE, "\t.long 0x%x\n\t.long 0x%x\n\t.long 0x%x\n", \ hex[0], hex[1], hex[2]); \ else \ fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n\t.long 0x%lx\n", \ hex[0], hex[1], hex[2]); \ } while (0) #endif #ifdef REAL_VALUE_TO_TARGET_DOUBLE #undef ASM_OUTPUT_DOUBLE #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { \ long hex[2]; \ REAL_VALUE_TO_TARGET_DOUBLE (VALUE, hex); \ if (sizeof (int) == sizeof (long)) \ fprintf (FILE, "\t.long 0x%x\n\t.long 0x%x\n", hex[0], hex[1]); \ else \ fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n", hex[0], hex[1]); \ } while (0) #endif /* This is how to output an assembler line defining a `float' constant. */ #ifdef REAL_VALUE_TO_TARGET_SINGLE #undef ASM_OUTPUT_FLOAT #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { \ long hex; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, hex); \ if (sizeof (int) == sizeof (long)) \ fprintf (FILE, "\t.long 0x%x\n", hex); \ else \ fprintf (FILE, "\t.long 0x%lx\n", hex); \ } while (0) #endif /* A C statement or statements which output an assembler instruction opcode to the stdio stream STREAM. The macro-operand PTR is a variable of type `char *' which points to the opcode name in its "internal" form--the form that is written in the machine description. GAS version 1.38.1 doesn't understand the `repz' opcode mnemonic. So use `repe' instead. */ #undef ASM_OUTPUT_OPCODE #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ { \ if ((PTR)[0] == 'r' \ && (PTR)[1] == 'e' \ && (PTR)[2] == 'p') \ { \ if ((PTR)[3] == 'z') \ { \ fprintf (STREAM, "repe"); \ (PTR) += 4; \ } \ else if ((PTR)[3] == 'n' && (PTR)[4] == 'z') \ { \ fprintf (STREAM, "repne"); \ (PTR) += 5; \ } \ } \ } /* Define macro used to output shift-double opcodes when the shift count is in %cl. Some assemblers require %cl as an argument; some don't. GAS requires the %cl argument, so override unx386.h. */ #undef AS3_SHIFT_DOUBLE #define AS3_SHIFT_DOUBLE(a,b,c,d) AS3 (a,b,c,d) /* Print opcodes the way that GAS expects them. */ #define GAS_MNEMONICS 1 /* Names to predefine in the preprocessor for this target machine. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Di386 -DNeXT -Dunix -D__MACH__ -D__LITTLE_ENDIAN__ -D__ARCHITECTURE__=\"i386\" -Asystem(unix) -Asystem(mach) -Acpu(i386) -Amachine(i386)" /* This accounts for the return pc and saved fp on the i386. */ #define OBJC_FORWARDING_STACK_OFFSET 8 #define OBJC_FORWARDING_MIN_OFFSET 8 /* We do not want a dot in internal labels. */ #undef LPREFIX #define LPREFIX "L" #undef ASM_GENERATE_INTERNAL_LABEL #define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ sprintf ((BUF), "*%s%d", (PREFIX), (NUMBER)) #undef ASM_OUTPUT_INTERNAL_LABEL #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, "%s%d:\n", PREFIX, NUM) /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ #undef ASM_APP_ON #define ASM_APP_ON "#APP\n" /* Output to assembler file text saying following lines no longer contain unusual constructs. */ #undef ASM_APP_OFF #define ASM_APP_OFF "#NO_APP\n" #undef ASM_OUTPUT_REG_PUSH #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tpushl %se%s\n", "%", reg_names[REGNO]) #undef ASM_OUTPUT_REG_POP #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tpopl %se%s\n", "%", reg_names[REGNO]) /* This is being overridden because the default i386 configuration generates calls to "_mcount". NeXT system libraries all use "mcount". */ #undef FUNCTION_PROFILER #define FUNCTION_PROFILER(FILE, LABELNO) \ { \ if (flag_pic) \ { \ fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \ LPREFIX, (LABELNO)); \ fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n"); \ } \ else \ { \ fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO)); \ fprintf (FILE, "\tcall mcount\n"); \ } \ } /* BEGIN Calling Convention CHANGES */ /* These changes violate the Intel/Unix ABI. Specifically, they change the way that space for a block return value is passed to a function. The ABI says that the pointer is passed on the stack. We change to pass the pointer in %ebx. This makes the NeXT Objective-C forwarding mechanism possible to implement on an i386. */ /* Do NOT pass address of structure values on the stack. */ #undef STRUCT_VALUE_INCOMING #undef STRUCT_VALUE /* Pass them in %ebx. */ #undef STRUCT_VALUE_REGNUM #define STRUCT_VALUE_REGNUM 3 /* Because we are passing the pointer in a register, we don't need to rely on the callee to pop it. */ #undef RETURN_POPS_ARGS #define RETURN_POPS_ARGS(FUNTYPE,SIZE) \ (TREE_CODE (FUNTYPE) == IDENTIFIER_NODE \ ? 0 \ : (TARGET_RTD \ && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ == void_type_node))) ? (SIZE) : 0) /* END Calling Convention CHANGES */ gcc-2.5.8/config/i386/os2.h100444 22011 13 4452 5520605412 13601 0ustar kenneruser/* Definitions of target machine for GNU compiler for an Intel i386 or later processor running OS/2 2.x. Copyright (C) 1993, 1994 Free Software Foundation, Inc. Contributed by Samuel Figueroa (figueroa@cs.nyu.edu) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef DEFAULT_TARGET_MACHINE #define DEFAULT_TARGET_MACHINE "i386-os2" #endif #ifndef STARTFILE_SPEC #define STARTFILE_SPEC "" #endif #ifndef MD_EXEC_PREFIX #define MD_EXEC_PREFIX "\\gcc\\bin\\" #endif #ifndef STANDARD_STARTFILE_PREFIX #define STANDARD_STARTFILE_PREFIX "\\gcc\\lib\\" #endif #ifndef LOCAL_INCLUDE_DIR #define LOCAL_INCLUDE_DIR "\\gcc\\include" #endif #ifndef PATH_SEPARATOR #define PATH_SEPARATOR ';' #endif #define YES_UNDERSCORES #include "i386/gstabs.h" #define USE_COLLECT #define BIGGEST_FIELD_ALIGNMENT \ (maximum_field_alignment ? maximum_field_alignment : 32) extern int maximum_field_alignment; #undef PCC_BITFIELD_TYPE_MATTERS #define PCC_BITFIELD_TYPE_MATTERS (maximum_field_alignment == 0) /* Define this macro if it is advisible to hold scalars in registers in a wider mode than that declared by the program. In such cases, the value is constrained to be within the bounds of the declared type, but kept valid in the wider mode. The signedness of the extension may differ from that of the type. */ #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ if (GET_MODE_CLASS (MODE) == MODE_INT \ && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ (MODE) = SImode; /* Define this if function arguments should also be promoted using the above procedure. */ #define PROMOTE_FUNCTION_ARGS /* Likewise, if the function return value is promoted. */ #define PROMOTE_FUNCTION_RETURN gcc-2.5.8/config/i386/osfelf.h100444 22011 13 5210 5461373464 14362 0ustar kenneruser/* Definitions of target machine for GNU compiler. Intel 386 (OSF/1 with ELF) version. Copyright (C) 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "config/i386/osfrose.h" #undef CPP_PREDEFINES #define CPP_PREDEFINES "-DOSF -DOSF1 -Dunix -Di386 -Asystem(unix) -Asystem(xpg4) -Acpu(i386) -Amachine(i386)" #undef CPP_SPEC #define CPP_SPEC "\ %{mrose: -D__ROSE__ %{!pic-none: -D__SHARED__}} \ %{!mrose: -D__ELF__ %{fpic: -D__SHARED__}} \ %{mno-underscores: -D__NO_UNDERSCORES__} \ %{!mrose: %{!munderscores: -D__NO_UNDERSCORES__}} \ %{.S: %{!ansi:%{!traditional:%{!traditional-cpp:%{!ftraditional: -traditional}}}}} \ %{.S: -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ %{.cc: -D__LANGUAGE_C_PLUS_PLUS} \ %{.cxx: -D__LANGUAGE_C_PLUS_PLUS} \ %{.C: -D__LANGUAGE_C_PLUS_PLUS} \ %{.m: -D__LANGUAGE_OBJECTIVE_C} \ %{!.S: -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}}" /* Turn on -mpic-extern by default (change to later use -fpic. */ #undef CC1_SPEC #define CC1_SPEC "\ %{!melf: %{!mrose: -melf }} \ %{!mrose: %{!munderscores: %{!mno-underscores: -mno-underscores }}} \ %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \ %{mrose: %{pic-none: -mno-half-pic} \ %{pic-extern: } %{pic-lib: } %{pic-calls: } %{pic-names*: } \ %{!pic-none: -mhalf-pic }}" #undef ASM_SPEC #define ASM_SPEC "%{v*: -v}" #undef LINK_SPEC #define LINK_SPEC "%{v*: -v} \ %{mrose: %{!noshrlib: %{pic-none: -noshrlib} %{!pic-none: -warn_nopic}} \ %{nostdlib} %{noshrlib} %{glue}} \ %{!mrose: %{dy} %{dn} %{glue: } \ %{h*} %{z*} \ %{static:-dn -Bstatic} \ %{shared:-G -dy} \ %{symbolic:-Bsymbolic -G -dy} \ %{G:-G} \ %{!dy: %{!dn: %{!static: %{!shared: %{!symbolic: \ %{noshrlib: -dn } %{pic-none: -dn } \ %{!noshrlib: %{!pic-none: -dy}}}}}}}}" #undef TARGET_VERSION_INTERNAL #undef TARGET_VERSION #undef I386_VERSION #define I386_VERSION " 80386, ELF objects" #define TARGET_VERSION_INTERNAL(STREAM) fputs (I386_VERSION, STREAM) #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr) #undef OBJECT_FORMAT_ROSE gcc-2.5.8/config/i386/osfrose.h100444 22011 13 107416 5461373463 14636 0ustar kenneruser/* Definitions of target machine for GNU compiler. Intel 386 (OSF/1 with OSF/rose) version. Copyright (C) 1991, 1992, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "halfpic.h" #include "i386/gstabs.h" /* Get perform_* macros to build libgcc.a. */ #include "i386/perform.h" #define OSF_OS #undef WORD_SWITCH_TAKES_ARG #define WORD_SWITCH_TAKES_ARG(STR) \ (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) || !strcmp (STR, "pic-names")) /* This defines which switch letters take arguments. On svr4, most of the normal cases (defined in gcc.c) apply, and we also have -h* and -z* options (for the linker). */ #define SWITCH_TAKES_ARG(CHAR) \ ( (CHAR) == 'D' \ || (CHAR) == 'U' \ || (CHAR) == 'o' \ || (CHAR) == 'e' \ || (CHAR) == 'T' \ || (CHAR) == 'u' \ || (CHAR) == 'I' \ || (CHAR) == 'm' \ || (CHAR) == 'L' \ || (CHAR) == 'A' \ || (CHAR) == 'h' \ || (CHAR) == 'z') #define MASK_HALF_PIC 0x40000000 /* Mask for half-pic code */ #define MASK_HALF_PIC_DEBUG 0x20000000 /* Debug flag */ #define MASK_ELF 0x10000000 /* ELF not rose */ #define MASK_NO_IDENT 0x08000000 /* suppress .ident */ #define MASK_NO_UNDERSCORES 0x04000000 /* suppress leading _ */ #define MASK_LARGE_ALIGN 0x02000000 /* align to >word boundaries */ #define MASK_NO_MCOUNT 0x01000000 /* profiling uses mcount_ptr */ #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC) #define TARGET_DEBUG (target_flags & MASK_HALF_PIC_DEBUG) #define HALF_PIC_DEBUG TARGET_DEBUG #define TARGET_ELF (target_flags & MASK_ELF) #define TARGET_ROSE ((target_flags & MASK_ELF) == 0) #define TARGET_IDENT ((target_flags & MASK_NO_IDENT) == 0) #define TARGET_UNDERSCORES ((target_flags & MASK_NO_UNDERSCORES) == 0) #define TARGET_LARGE_ALIGN (target_flags & MASK_LARGE_ALIGN) #define TARGET_MCOUNT ((target_flags & MASK_NO_MCOUNT) == 0) #undef SUBTARGET_SWITCHES #define SUBTARGET_SWITCHES \ { "half-pic", MASK_HALF_PIC}, \ { "no-half-pic", -MASK_HALF_PIC}, \ { "debug-half-pic", MASK_HALF_PIC_DEBUG}, \ { "debugb", MASK_HALF_PIC_DEBUG}, \ { "elf", MASK_ELF}, \ { "rose", -MASK_ELF}, \ { "ident", -MASK_NO_IDENT}, \ { "no-ident", MASK_NO_IDENT}, \ { "underscores", -MASK_NO_UNDERSCORES}, \ { "no-underscores", MASK_NO_UNDERSCORES}, \ { "large-align", MASK_LARGE_ALIGN}, \ { "no-large-align",-MASK_LARGE_ALIGN}, \ { "mcount", -MASK_NO_MCOUNT}, \ { "no-mcount", MASK_NO_MCOUNT}, /* OSF/rose uses stabs, not dwarf. */ #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG #ifndef DWARF_DEBUGGING_INFO #define DWARF_DEBUGGING_INFO /* enable dwarf debugging for testing */ #endif /* Handle #pragma weak and #pragma pack. */ #define HANDLE_SYSV_PRAGMA /* Change default predefines. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-DOSF -DOSF1 -Dunix -Di386 -Asystem(unix) -Asystem(xpg4) -Acpu(i386) -Amachine(i386)" #undef CPP_SPEC #define CPP_SPEC "\ %{!melf: -D__ROSE__ %{!pic-none: -D__SHARED__}} \ %{melf: -D__ELF__ %{fpic: -D__SHARED__}} \ %{mno-underscores: -D__NO_UNDERSCORES__} \ %{melf: %{!munderscores: -D__NO_UNDERSCORES__}} \ %{.S: %{!ansi:%{!traditional:%{!traditional-cpp:%{!ftraditional: -traditional}}}}} \ %{.S: -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ %{.cc: -D__LANGUAGE_C_PLUS_PLUS} \ %{.cxx: -D__LANGUAGE_C_PLUS_PLUS} \ %{.C: -D__LANGUAGE_C_PLUS_PLUS} \ %{.m: -D__LANGUAGE_OBJECTIVE_C} \ %{!.S: -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}}" /* Turn on -pic-extern by default. */ #undef CC1_SPEC #define CC1_SPEC "\ %{!melf: %{!mrose: -mrose }} \ %{melf: %{!munderscores: %{!mno-underscores: -mno-underscores }}} \ %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \ %{!melf: %{pic-none: -mno-half-pic} \ %{pic-extern: } %{pic-lib: } %{pic-calls: } %{pic-names*: } \ %{!pic-none: -mhalf-pic }}" #undef ASM_SPEC #define ASM_SPEC "%{v*: -v}" #undef LINK_SPEC #define LINK_SPEC "%{v*: -v} \ %{!melf: %{!noshrlib: %{pic-none: -noshrlib} %{!pic-none: -warn_nopic}} \ %{nostdlib} %{noshrlib} %{glue}} \ %{melf: %{dy} %{dn} %{glue: } \ %{h*} %{z*} \ %{static:-dn -Bstatic} \ %{shared:-G -dy} \ %{symbolic:-Bsymbolic -G -dy} \ %{G:-G} \ %{!dy: %{!dn: %{!static: %{!shared: %{!symbolic: \ %{noshrlib: -dn } %{pic-none: -dn } \ %{!noshrlib: %{!pic-none: -dy}}}}}}}}" #undef LIB_SPEC #define LIB_SPEC "-lc" #undef LIBG_SPEC #define LIBG_SPEC "" #undef STARTFILE_SPEC #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}" #undef TARGET_VERSION_INTERNAL #undef TARGET_VERSION #define I386_VERSION " 80386, OSF/rose objects" #define TARGET_VERSION_INTERNAL(STREAM) fputs (I386_VERSION, STREAM) #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr) #undef MD_EXEC_PREFIX #define MD_EXEC_PREFIX "/usr/ccs/gcc/" #undef MD_STARTFILE_PREFIX #define MD_STARTFILE_PREFIX "/usr/ccs/lib/" /* Specify size_t, ptrdiff_t, and wchar_t types. */ #undef SIZE_TYPE #undef PTRDIFF_TYPE #undef WCHAR_TYPE #undef WCHAR_TYPE_SIZE #define SIZE_TYPE "long unsigned int" #define PTRDIFF_TYPE "int" #define WCHAR_TYPE "unsigned int" #define WCHAR_TYPE_SIZE BITS_PER_WORD /* Temporarily turn off long double being 96 bits. */ #undef LONG_DOUBLE_TYPE_SIZE /* This macro generates the assembly code for function entry. FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. Refer to the array `regs_ever_live' to determine which registers to save; `regs_ever_live[I]' is nonzero if register number I is ever used in the function. This macro is responsible for knowing which registers should not be saved even if used. We override it here to allow for the new profiling code to go before the prologue and the old mcount code to go after the prologue (and after %ebx has been set up for ELF shared library support). */ #define OSF_PROFILE_BEFORE_PROLOGUE \ (!TARGET_MCOUNT \ && !current_function_needs_context \ && (!flag_pic \ || !frame_pointer_needed \ || (!current_function_uses_pic_offset_table \ && !current_function_uses_const_pool))) #undef FUNCTION_PROLOGUE #define FUNCTION_PROLOGUE(FILE, SIZE) \ do \ { \ char *prefix = (TARGET_UNDERSCORES) ? "_" : ""; \ char *lprefix = LPREFIX; \ int labelno = profile_label_no; \ \ if (profile_flag && OSF_PROFILE_BEFORE_PROLOGUE) \ { \ if (!flag_pic && !HALF_PIC_P ()) \ { \ fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno); \ fprintf (FILE, "\tcall *%s_mcount_ptr\n", prefix); \ } \ \ else if (HALF_PIC_P ()) \ { \ rtx symref; \ \ HALF_PIC_EXTERNAL ("_mcount_ptr"); \ symref = HALF_PIC_PTR (gen_rtx (SYMBOL_REF, Pmode, \ "_mcount_ptr")); \ \ fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno); \ fprintf (FILE, "\tmovl %s%s,%%eax\n", prefix, \ XSTR (symref, 0)); \ fprintf (FILE, "\tcall *(%%eax)\n"); \ } \ \ else \ { \ static int call_no = 0; \ \ fprintf (FILE, "\tcall %sPc%d\n", lprefix, call_no); \ fprintf (FILE, "%sPc%d:\tpopl %%eax\n", lprefix, call_no); \ fprintf (FILE, "\taddl $_GLOBAL_OFFSET_TABLE_+[.-%sPc%d],%%eax\n", \ lprefix, call_no++); \ fprintf (FILE, "\tleal $%sP%d@GOTOFF(%%eax),%%edx\n", \ lprefix, labelno); \ fprintf (FILE, "\tmovl %s_mcount_ptr@GOT(%%eax),%%eax\n", \ prefix); \ fprintf (FILE, "\tcall *(%%eax)\n"); \ } \ } \ \ function_prologue (FILE, SIZE); \ } \ while (0) /* A C statement or compound statement to output to FILE some assembler code to call the profiling subroutine `mcount'. Before calling, the assembler code must load the address of a counter variable into a register where `mcount' expects to find the address. The name of this variable is `LP' followed by the number LABELNO, so you would generate the name using `LP%d' in a `fprintf'. The details of how the address should be passed to `mcount' are determined by your operating system environment, not by GNU CC. To figure them out, compile a small program for profiling using the system's installed C compiler and look at the assembler code that results. */ #undef FUNCTION_PROFILER #define FUNCTION_PROFILER(FILE, LABELNO) \ do \ { \ if (!OSF_PROFILE_BEFORE_PROLOGUE) \ { \ char *prefix = (TARGET_UNDERSCORES) ? "_" : ""; \ char *lprefix = LPREFIX; \ int labelno = LABELNO; \ \ /* Note that OSF/rose blew it in terms of calling mcount, \ since OSF/rose prepends a leading underscore, but mcount's \ doesn't. At present, we keep this kludge for ELF as well \ to allow old kernels to build profiling. */ \ \ if (flag_pic \ && !current_function_uses_pic_offset_table \ && !current_function_uses_const_pool) \ abort (); \ \ if (TARGET_MCOUNT && flag_pic) \ { \ fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \ lprefix, labelno); \ fprintf (FILE, "\tcall *%smcount@GOT(%%ebx)\n", prefix); \ } \ \ else if (TARGET_MCOUNT && HALF_PIC_P ()) \ { \ rtx symdef; \ \ HALF_PIC_EXTERNAL ("mcount"); \ symdef = HALF_PIC_PTR (gen_rtx (SYMBOL_REF, Pmode, "mcount")); \ fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno); \ fprintf (FILE, "\tcall *%s%s\n", prefix, XSTR (symdef, 0)); \ } \ \ else if (TARGET_MCOUNT) \ { \ fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno); \ fprintf (FILE, "\tcall %smcount\n", prefix); \ } \ \ else if (flag_pic && frame_pointer_needed) \ { \ fprintf (FILE, "\tmovl 4(%%ebp),%%ecx\n"); \ fprintf (FILE, "\tpushl %%ecx\n"); \ fprintf (FILE, "\tleal $%sP%d@GOTOFF(%%ebx),%%edx\n", \ lprefix, labelno); \ fprintf (FILE, "\tmovl _mcount_ptr@GOT(%%eax),%%eax\n"); \ fprintf (FILE, "\tcall *(%%eax)\n"); \ fprintf (FILE, "\tpopl %%eax\n"); \ } \ \ else if (frame_pointer_needed) \ { \ fprintf (FILE, "\tmovl 4(%%ebp),%%ecx\n"); \ fprintf (FILE, "\tpushl %%ecx\n"); \ fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno); \ fprintf (FILE, "\tcall *_mcount_ptr\n"); \ fprintf (FILE, "\tpopl %%eax\n"); \ } \ \ else \ abort (); \ } \ } \ while (0) /* A C statement or compound statement to output to FILE some assembler code to initialize basic-block profiling for the current object module. This code should call the subroutine `__bb_init_func' once per object module, passing it as its sole argument the address of a block allocated in the object module. The name of the block is a local symbol made with this statement: ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); Of course, since you are writing the definition of `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you can take a short cut in the definition of this macro and use the name that you know will result. The first word of this block is a flag which will be nonzero if the object module has already been initialized. So test this word first, and do not call `__bb_init_func' if the flag is nonzero. */ #undef FUNCTION_BLOCK_PROFILER #define FUNCTION_BLOCK_PROFILER(STREAM, LABELNO) \ do \ { \ if (!flag_pic) \ { \ fprintf (STREAM, "\tcmpl $0,%sPBX0\n", LPREFIX); \ fprintf (STREAM, "\tjne 0f\n"); \ fprintf (STREAM, "\tpushl $%sPBX0\n", LPREFIX); \ fprintf (STREAM, "\tcall %s__bb_init_func\n", \ (TARGET_UNDERSCORES) ? "_" : ""); \ fprintf (STREAM, "0:\n"); \ } \ else \ { \ fprintf (STREAM, "\tpushl %eax\n"); \ fprintf (STREAM, "\tmovl %sPBX0@GOT(%ebx),%eax\n"); \ fprintf (STREAM, "\tcmpl $0,(%eax)\n"); \ fprintf (STREAM, "\tjne 0f\n"); \ fprintf (STREAM, "\tpushl %eax\n"); \ fprintf (STREAM, "\tcall %s__bb_init_func@PLT\n", \ (TARGET_UNDERSCORES) ? "_" : ""); \ fprintf (STREAM, "0:\n"); \ fprintf (STREAM, "\tpopl %eax\n"); \ } \ } \ while (0) /* A C statement or compound statement to increment the count associated with the basic block number BLOCKNO. Basic blocks are numbered separately from zero within each compilation. The count associated with block number BLOCKNO is at index BLOCKNO in a vector of words; the name of this array is a local symbol made with this statement: ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2); Of course, since you are writing the definition of `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you can take a short cut in the definition of this macro and use the name that you know will result. */ #undef BLOCK_PROFILER #define BLOCK_PROFILER(STREAM, BLOCKNO) \ do \ { \ if (!flag_pic) \ fprintf (STREAM, "\tincl %sPBX2+%d\n", LPREFIX, (BLOCKNO)*4); \ else \ { \ fprintf (STREAM, "\tpushl %eax\n"); \ fprintf (STREAM, "\tmovl %sPBX2@GOT(%ebx),%eax\n", LPREFIX); \ fprintf (STREAM, "\tincl %d(%eax)\n", (BLOCKNO)*4); \ fprintf (STREAM, "\tpopl %eax\n"); \ } \ } \ while (0) /* A C function or functions which are needed in the library to support block profiling. When support goes into libc, undo the #if 0. */ #if 0 #undef BLOCK_PROFILING_CODE #define BLOCK_PROFILING_CODE #endif /* Prefix for internally generated assembler labels. If we aren't using underscores, we are using prefix `.'s to identify labels that should be ignored, as in `i386/gas.h' --karl@cs.umb.edu */ #undef LPREFIX #define LPREFIX ((TARGET_UNDERSCORES) ? "L" : ".L") /* This is how to store into the string BUF the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #undef ASM_GENERATE_INTERNAL_LABEL #define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ sprintf ((BUF), "*%s%s%d", (TARGET_UNDERSCORES) ? "" : ".", \ (PREFIX), (NUMBER)) /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #undef ASM_OUTPUT_INTERNAL_LABEL #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, "%s%s%d:\n", (TARGET_UNDERSCORES) ? "" : ".", \ PREFIX, NUM) /* This is how to output a reference to a user-level label named NAME. */ #undef ASM_OUTPUT_LABELREF #define ASM_OUTPUT_LABELREF(FILE,NAME) \ fprintf (FILE, "%s%s", (TARGET_UNDERSCORES) ? "_" : "", NAME) /* This is how to output an element of a case-vector that is relative. This is only used for PIC code. See comments by the `casesi' insn in i386.md for an explanation of the expression this outputs. */ #undef ASM_OUTPUT_ADDR_DIFF_ELT #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE) /* A C expression to output text to align the location counter in the way that is desirable at a point in the code that is reached only by jumping. This macro need not be defined if you don't want any special alignment to be done at such a time. Most machine descriptions do not currently define the macro. */ #undef ASM_OUTPUT_ALIGN_CODE #define ASM_OUTPUT_ALIGN_CODE(STREAM) \ fprintf (STREAM, "\t.align\t%d\n", \ (TARGET_486 && TARGET_LARGE_ALIGN) ? 4 : 2) /* A C expression to output text to align the location counter in the way that is desirable at the beginning of a loop. This macro need not be defined if you don't want any special alignment to be done at such a time. Most machine descriptions do not currently define the macro. */ #undef ASM_OUTPUT_LOOP_ALIGN #define ASM_OUTPUT_LOOP_ALIGN(STREAM) \ fprintf (STREAM, "\t.align\t2\n") /* A C statement to output to the stdio stream STREAM an assembler command to advance the location counter to a multiple of 2 to the POWER bytes. POWER will be a C expression of type `int'. */ #undef ASM_OUTPUT_ALIGN #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ fprintf (STREAM, "\t.align\t%d\n", \ (!TARGET_LARGE_ALIGN && (POWER) > 2) ? 2 : (POWER)) /* A C expression that is 1 if the RTX X is a constant which is a valid address. On most machines, this can be defined as `CONSTANT_P (X)', but a few machines are more restrictive in which constant addresses are supported. `CONSTANT_P' accepts integer-values expressions whose values are not explicitly known, such as `symbol_ref', `label_ref', and `high' expressions and `const' arithmetic expressions, in addition to `const_int' and `const_double' expressions. */ #define CONSTANT_ADDRESS_P_ORIG(X) \ (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ || GET_CODE (X) == HIGH) #undef CONSTANT_ADDRESS_P #define CONSTANT_ADDRESS_P(X) \ ((CONSTANT_ADDRESS_P_ORIG (X)) && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X))) /* Nonzero if the constant value X is a legitimate general operand. It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ #undef LEGITIMATE_CONSTANT_P #define LEGITIMATE_CONSTANT_P(X) \ (!HALF_PIC_P () \ || GET_CODE (X) == CONST_DOUBLE \ || GET_CODE (X) == CONST_INT \ || !HALF_PIC_ADDRESS_P (X)) /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. */ #define GO_IF_LEGITIMATE_ADDRESS_ORIG(MODE, X, ADDR) \ { \ if (CONSTANT_ADDRESS_P (X) \ && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ goto ADDR; \ GO_IF_INDEXING (X, ADDR); \ if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ { \ rtx x0 = XEXP (X, 0); \ if (! flag_pic || ! SYMBOLIC_CONST (XEXP (X, 1))) \ { GO_IF_INDEXING (x0, ADDR); } \ else if (x0 == pic_offset_table_rtx) \ goto ADDR; \ else if (GET_CODE (x0) == PLUS) \ { \ if (XEXP (x0, 0) == pic_offset_table_rtx) \ { GO_IF_INDEXABLE_BASE (XEXP (x0, 1), ADDR); } \ if (XEXP (x0, 1) == pic_offset_table_rtx) \ { GO_IF_INDEXABLE_BASE (XEXP (x0, 0), ADDR); } \ } \ } \ } #undef GO_IF_LEGITIMATE_ADDRESS #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { \ if (! HALF_PIC_P ()) \ { \ GO_IF_LEGITIMATE_ADDRESS_ORIG(MODE, X, ADDR); \ } \ else \ { \ if (CONSTANT_P (X) && ! HALF_PIC_ADDRESS_P (X)) \ goto ADDR; \ \ GO_IF_INDEXING (X, ADDR); \ if (GET_CODE (X) == PLUS) \ { \ rtx x1 = XEXP (X, 1); \ \ if (CONSTANT_P (x1) && ! HALF_PIC_ADDRESS_P (x1)) \ { \ rtx x0 = XEXP (X, 0); \ GO_IF_INDEXING (x0, ADDR); \ } \ } \ } \ } /* Sometimes certain combinations of command options do not make sense on a particular target machine. You can define a macro `OVERRIDE_OPTIONS' to take account of this. This macro, if defined, is executed once just after all the command options have been parsed. */ #undef SUBTARGET_OVERRIDE_OPTIONS #define SUBTARGET_OVERRIDE_OPTIONS \ { \ /* \ if (TARGET_ELF && TARGET_HALF_PIC) \ { \ target_flags &= ~MASK_HALF_PIC; \ flag_pic = 1; \ } \ */ \ \ if (TARGET_ROSE && flag_pic) \ { \ target_flags |= MASK_HALF_PIC; \ flag_pic = 0; \ } \ \ if (TARGET_HALF_PIC) \ half_pic_init (); \ } /* Define this macro if references to a symbol must be treated differently depending on something about the variable or function named by the symbol (such as what section it is in). The macro definition, if any, is executed immediately after the rtl for DECL has been created and stored in `DECL_RTL (DECL)'. The value of the rtl will be a `mem' whose address is a `symbol_ref'. The usual thing for this macro to do is to a flag in the `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified name string in the `symbol_ref' (if one bit is not enough information). The best way to modify the name string is by adding text to the beginning, with suitable punctuation to prevent any ambiguity. Allocate the new name in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to remove and decode the added text and output the name accordingly. You can also check the information stored in the `symbol_ref' in the definition of `GO_IF_LEGITIMATE_ADDRESS' or `PRINT_OPERAND_ADDRESS'. */ #undef ENCODE_SECTION_INFO #define ENCODE_SECTION_INFO(DECL) \ do \ { \ if (HALF_PIC_P ()) \ HALF_PIC_ENCODE (DECL); \ \ else if (flag_pic) \ { \ rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \ SYMBOL_REF_FLAG (XEXP (rtl, 0)) \ = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ || ! TREE_PUBLIC (DECL)); \ } \ } \ while (0) /* On most machines, read-only variables, constants, and jump tables are placed in the text section. If this is not the case on your machine, this macro should be defined to be the name of a function (either `data_section' or a function defined in `EXTRA_SECTIONS') that switches to the section to be used for read-only items. If these items should be placed in the text section, this macro should not be defined. */ #if 0 #undef READONLY_DATA_SECTION #define READONLY_DATA_SECTION() \ do \ { \ if (TARGET_ELF) \ { \ if (in_section != in_rodata) \ { \ fprintf (asm_out_file, "\t.section \"rodata\"\n"); \ in_section = in_rodata; \ } \ } \ else \ text_section (); \ } \ while (0) #endif /* A list of names for sections other than the standard two, which are `in_text' and `in_data'. You need not define this macro on a system with no other sections (that GCC needs to use). */ #undef EXTRA_SECTIONS #define EXTRA_SECTIONS in_rodata, in_data1 /* Given a decl node or constant node, choose the section to output it in and select that section. */ #undef SELECT_RTX_SECTION #define SELECT_RTX_SECTION(MODE, RTX) \ do \ { \ if (MODE == Pmode && HALF_PIC_P () && HALF_PIC_ADDRESS_P (RTX)) \ data_section (); \ else \ readonly_data_section (); \ } \ while (0) #undef SELECT_SECTION #define SELECT_SECTION(DECL, RELOC) \ { \ if (RELOC && HALF_PIC_P ()) \ data_section (); \ \ else if (TREE_CODE (DECL) == STRING_CST) \ { \ if (flag_writable_strings) \ data_section (); \ else \ readonly_data_section (); \ } \ \ else if (TREE_CODE (DECL) != VAR_DECL) \ readonly_data_section (); \ \ else if (!TREE_READONLY (DECL)) \ data_section (); \ \ else \ readonly_data_section (); \ } /* Define the strings used for the special svr4 .type and .size directives. These strings generally do not vary from one system running svr4 to another, but if a given system (e.g. m88k running svr) needs to use different pseudo-op names for these, they may be overridden in the file which includes this one. */ #define TYPE_ASM_OP ".type" #define SIZE_ASM_OP ".size" #define WEAK_ASM_OP ".weak" #define SET_ASM_OP ".set" /* The following macro defines the format used to output the second operand of the .type assembler directive. Different svr4 assemblers expect various different forms for this operand. The one given here is just a default. You may need to override it in your machine- specific tm.h file (depending upon the particulars of your assembler). */ #define TYPE_OPERAND_FMT "@%s" /* A C statement (sans semicolon) to output to the stdio stream STREAM any text necessary for declaring the name NAME of an initialized variable which is being defined. This macro must output the label definition (perhaps using `ASM_OUTPUT_LABEL'). The argument DECL is the `VAR_DECL' tree node representing the variable. If this macro is not defined, then the variable name is defined in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */ #undef ASM_DECLARE_OBJECT_NAME #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ do \ { \ ASM_OUTPUT_LABEL(STREAM,NAME); \ HALF_PIC_DECLARE (NAME); \ if (TARGET_ELF) \ { \ fprintf (STREAM, "\t%s\t ", TYPE_ASM_OP); \ assemble_name (STREAM, NAME); \ putc (',', STREAM); \ fprintf (STREAM, TYPE_OPERAND_FMT, "object"); \ putc ('\n', STREAM); \ size_directive_output = 0; \ if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \ { \ size_directive_output = 1; \ fprintf (STREAM, "\t%s\t ", SIZE_ASM_OP); \ assemble_name (STREAM, NAME); \ fprintf (STREAM, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ } \ } \ } \ while (0) /* Output the size directive for a decl in rest_of_decl_compilation in the case where we did not do so before the initializer. Once we find the error_mark_node, we know that the value of size_directive_output was set by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */ #define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ do { \ char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ if (TARGET_ELF \ && !flag_inhibit_size_directive && DECL_SIZE (DECL) \ && ! AT_END && TOP_LEVEL \ && DECL_INITIAL (DECL) == error_mark_node \ && !size_directive_output) \ { \ fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ assemble_name (FILE, name); \ fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ } \ } while (0) /* This is how to declare a function name. */ #undef ASM_DECLARE_FUNCTION_NAME #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ do \ { \ ASM_OUTPUT_LABEL(STREAM,NAME); \ HALF_PIC_DECLARE (NAME); \ if (TARGET_ELF) \ { \ fprintf (STREAM, "\t%s\t ", TYPE_ASM_OP); \ assemble_name (STREAM, NAME); \ putc (',', STREAM); \ fprintf (STREAM, TYPE_OPERAND_FMT, "function"); \ putc ('\n', STREAM); \ ASM_DECLARE_RESULT (STREAM, DECL_RESULT (DECL)); \ } \ } \ while (0) /* Write the extra assembler code needed to declare a function's result. Most svr4 assemblers don't require any special declaration of the result value, but there are exceptions. */ #ifndef ASM_DECLARE_RESULT #define ASM_DECLARE_RESULT(FILE, RESULT) #endif /* This is how to declare the size of a function. */ #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ do \ { \ if (TARGET_ELF && !flag_inhibit_size_directive) \ { \ char label[256]; \ static int labelno; \ labelno++; \ ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \ ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno); \ fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ assemble_name (FILE, (FNAME)); \ fprintf (FILE, ","); \ assemble_name (FILE, label); \ fprintf (FILE, "-"); \ assemble_name (FILE, (FNAME)); \ putc ('\n', FILE); \ } \ } \ while (0) /* Attach a special .ident directive to the end of the file to identify the version of GCC which compiled this code. The format of the .ident string is patterned after the ones produced by native svr4 C compilers. */ #define IDENT_ASM_OP ".ident" /* Allow #sccs in preprocessor. */ #define SCCS_DIRECTIVE /* This says what to print at the end of the assembly file */ #define ASM_FILE_END(STREAM) \ do \ { \ if (HALF_PIC_P ()) \ HALF_PIC_FINISH (STREAM); \ \ if (TARGET_IDENT) \ { \ char *fstart = main_input_filename; \ char *fname; \ \ if (!fstart) \ fstart = ""; \ \ fname = fstart + strlen (fstart) - 1; \ while (fname > fstart && *fname != '/') \ fname--; \ \ if (*fname == '/') \ fname++; \ \ fprintf ((STREAM), "\t%s\t\"GCC: (GNU) %s %s -O%d", \ IDENT_ASM_OP, version_string, fname, optimize); \ \ if (write_symbols == PREFERRED_DEBUGGING_TYPE) \ fprintf ((STREAM), " -g%d", (int)debug_info_level); \ \ else if (write_symbols == DBX_DEBUG) \ fprintf ((STREAM), " -gstabs%d", (int)debug_info_level); \ \ else if (write_symbols == DWARF_DEBUG) \ fprintf ((STREAM), " -gdwarf%d", (int)debug_info_level); \ \ else if (write_symbols != NO_DEBUG) \ fprintf ((STREAM), " -g??%d", (int)debug_info_level); \ \ if (flag_omit_frame_pointer) \ fprintf ((STREAM), " -fomit-frame-pointer"); \ \ if (flag_strength_reduce) \ fprintf ((STREAM), " -fstrength-reduce"); \ \ if (flag_unroll_loops) \ fprintf ((STREAM), " -funroll-loops"); \ \ if (flag_force_mem) \ fprintf ((STREAM), " -fforce-mem"); \ \ if (flag_force_addr) \ fprintf ((STREAM), " -fforce-addr"); \ \ if (flag_inline_functions) \ fprintf ((STREAM), " -finline-functions"); \ \ if (flag_caller_saves) \ fprintf ((STREAM), " -fcaller-saves"); \ \ if (flag_pic) \ fprintf ((STREAM), (flag_pic > 1) ? " -fPIC" : " -fpic"); \ \ if (flag_inhibit_size_directive) \ fprintf ((STREAM), " -finhibit-size-directive"); \ \ if (flag_gnu_linker) \ fprintf ((STREAM), " -fgnu-linker"); \ \ if (profile_flag) \ fprintf ((STREAM), " -p"); \ \ if (profile_block_flag) \ fprintf ((STREAM), " -a"); \ \ if (TARGET_IEEE_FP) \ fprintf ((STREAM), " -mieee-fp"); \ \ if (TARGET_HALF_PIC) \ fprintf ((STREAM), " -mhalf-pic"); \ \ fprintf ((STREAM), (TARGET_486) ? " -m486" : " -m386"); \ fprintf ((STREAM), (TARGET_ELF) ? " -melf\"\n" : " -mrose\"\n"); \ } \ } \ while (0) /* Tell collect that the object format is OSF/rose. */ #define OBJECT_FORMAT_ROSE /* Tell collect where the appropriate binaries are. */ #define REAL_LD_FILE_NAME "/usr/ccs/gcc/gld" #define REAL_NM_FILE_NAME "/usr/ccs/bin/nm" #define REAL_STRIP_FILE_NAME "/usr/ccs/bin/strip" /* Use atexit for static constructors/destructors, instead of defining our own exit function. */ #define HAVE_ATEXIT /* Define this macro meaning that gcc should find the library 'libgcc.a' by hand, rather than passing the argument '-lgcc' to tell the linker to do the search */ #define LINK_LIBGCC_SPECIAL /* A C statement to output assembler commands which will identify the object file as having been compile with GNU CC. We don't need or want this for OSF1. GDB doesn't need it and kdb doesn't like it */ #define ASM_IDENTIFY_GCC(FILE) /* Identify the front-end which produced this file. To keep symbol space down, and not confuse kdb, only do this if the language is not C. */ #define ASM_IDENTIFY_LANGUAGE(STREAM) \ { \ if (strcmp (lang_identify (), "c") != 0) \ output_lang_identify (STREAM); \ } /* This is how to output an assembler line defining a `double' constant. Use "word" pseudos to avoid printing NaNs, infinity, etc. */ /* This is how to output an assembler line defining a `double' constant. */ #undef ASM_OUTPUT_DOUBLE #define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \ do \ { \ long value_long[2]; \ char dstr[30]; \ REAL_VALUE_TO_TARGET_DOUBLE (VALUE, value_long); \ REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ if (sizeof (int) == sizeof (long)) \ fprintf (STREAM, "\t.long\t0x%08x\t\t# %s\n\t.long\t0x%08x\n", \ value_long[0], dstr, value_long[1]); \ else \ fprintf (STREAM, "\t.long\t0x%08lx\t\t# %s\n\t.long\t0x%08lx\n", \ value_long[0], dstr, value_long[1]); \ } \ while (0) /* This is how to output an assembler line defining a `float' constant. */ #undef ASM_OUTPUT_FLOAT #define ASM_OUTPUT_FLOAT(STREAM, VALUE) \ do \ { \ long value_long; \ char dstr[30]; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, value_long); \ REAL_VALUE_TO_DECIMAL (VALUE, "%.12g", dstr); \ if (sizeof (int) == sizeof (long)) \ fprintf (STREAM, "\t.long\t0x%08x\t\t# %s (float)\n", \ value_long, dstr); \ else \ fprintf (STREAM, "\t.long\t0x%08lx\t\t# %s (float)\n", \ value_long, dstr); \ } \ while (0) /* This is how to output an assembler line for a `long double' constant. */ #undef ASM_OUTPUT_LONG_DOUBLE #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ do { long l[3]; \ char dstr[30]; \ REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ if (sizeof (int) == sizeof (long)) \ fprintf (FILE, \ "\t.long\t0x%08x\t\t# %s\n\t.long\t0x%08x\n\t.long\t0x%08x\n", \ l[0], dstr, l[1], l[2]); \ else \ fprintf (FILE, \ "\t.long\t0x%08lx\t\t# %s\n\t.long\t0x%08lx\n\t.long\t0x%08lx\n", \ l[0], dstr, l[1], l[2]); \ } while (0) /* Generate calls to memcpy, etc., not bcopy, etc. */ #define TARGET_MEM_FUNCTIONS /* Don't default to pcc-struct-return, because gcc is the only compiler, and we want to retain compatibility with older gcc versions. */ #define DEFAULT_PCC_STRUCT_RETURN 0 /* Map i386 registers to the numbers dwarf expects. Of course this is different from what stabs expects. */ #define DWARF_DBX_REGISTER_NUMBER(n) \ ((n) == 0 ? 0 \ : (n) == 1 ? 2 \ : (n) == 2 ? 1 \ : (n) == 3 ? 3 \ : (n) == 4 ? 6 \ : (n) == 5 ? 7 \ : (n) == 6 ? 5 \ : (n) == 7 ? 4 \ : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \ : (-1)) /* Now what stabs expects in the register. */ #define STABS_DBX_REGISTER_NUMBER(n) \ ((n) == 0 ? 0 : \ (n) == 1 ? 2 : \ (n) == 2 ? 1 : \ (n) == 3 ? 3 : \ (n) == 4 ? 6 : \ (n) == 5 ? 7 : \ (n) == 6 ? 4 : \ (n) == 7 ? 5 : \ (n) + 4) #undef DBX_REGISTER_NUMBER #define DBX_REGISTER_NUMBER(n) ((write_symbols == DWARF_DEBUG) \ ? DWARF_DBX_REGISTER_NUMBER(n) \ : STABS_DBX_REGISTER_NUMBER(n)) gcc-2.5.8/config/i386/perform.h100444 22011 13 5752 5473507046 14567 0ustar kenneruser/* Definitions for AT&T assembler syntax for the Intel 80386. Copyright (C) 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Defines to be able to build libgcc.a with GCC. */ /* It might seem that these are not important, since gcc 2 will never call libgcc for these functions. But programs might be linked with code compiled by gcc 1, and then these will be used. */ /* The arg names used to be a and b, but `a' appears inside strings and that confuses non-ANSI cpp. */ #define perform_udivsi3(arg0,arg1) \ { \ register int dx asm("dx"); \ register int ax asm("ax"); \ \ dx = 0; \ ax = arg0; \ asm ("divl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1), "d" (dx)); \ return ax; \ } #define perform_divsi3(arg0,arg1) \ { \ register int dx asm("dx"); \ register int ax asm("ax"); \ register int cx asm("cx"); \ \ ax = arg0; \ cx = arg1; \ asm ("cltd\n\tidivl %3" : "=a" (ax), "=&d" (dx) : "a" (ax), "c" (cx)); \ return ax; \ } #define perform_umodsi3(arg0,arg1) \ { \ register int dx asm("dx"); \ register int ax asm("ax"); \ \ dx = 0; \ ax = arg0; \ asm ("divl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1), "d" (dx)); \ return dx; \ } #define perform_modsi3(arg0,arg1) \ { \ register int dx asm("dx"); \ register int ax asm("ax"); \ register int cx asm("cx"); \ \ ax = arg0; \ cx = arg1; \ asm ("cltd\n\tidivl %3" : "=a" (ax), "=&d" (dx) : "a" (ax), "c" (cx)); \ return dx; \ } #define perform_fixdfsi(arg0) \ { \ auto unsigned short ostatus; \ auto unsigned short nstatus; \ auto int ret; \ auto double tmp; \ \ &ostatus; /* guarantee these land in memory */ \ &nstatus; \ &ret; \ &tmp; \ \ asm volatile ("fnstcw %0" : "=m" (ostatus)); \ nstatus = ostatus | 0x0c00; \ asm volatile ("fldcw %0" : /* no outputs */ : "m" (nstatus)); \ tmp = arg0; \ asm volatile ("fldl %0" : /* no outputs */ : "m" (tmp)); \ asm volatile ("fistpl %0" : "=m" (ret)); \ asm volatile ("fldcw %0" : /* no outputs */ : "m" (ostatus)); \ \ return ret; \ } gcc-2.5.8/config/i386/sco.h100444 22011 13 6076 5461144056 13674 0ustar kenneruser/* Definitions for Intel 386 running SCO Unix System V. */ /* Mostly it's like AT&T Unix System V. */ #include "i386/sysv3.h" /* By default, target has a 80387, uses IEEE compatible arithmetic, and returns float values in the 387, ie, (TARGET_80387 | TARGET_FLOAT_RETURNS_IN_80387) SCO's software emulation of a 387 fails to handle the `fucomp' opcode. fucomp is only used when generating IEEE compliant code. So don't make TARGET_IEEE_FP default for SCO. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT 0201 /* Let's guess that the SCO software FPU emulator can't handle 80-bit XFmode insns, so don't generate them. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 /* Use crt1.o as a startup file and crtn.o as a closing file. */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} crtbegin.o%s" #define ENDFILE_SPEC "crtend.o%s crtn.o%s" /* Library spec, including SCO international language support. */ #undef LIB_SPEC #define LIB_SPEC \ "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} %{scointl:libintl.a%s} -lc" /* Specify predefined symbols in preprocessor. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dunix -Di386 -DM_UNIX -DM_I386 -DM_COFF -DM_WORDSWAP -Asystem(unix) -Asystem(svr3) -Acpu(i386) -Amachine(i386)" #undef CPP_SPEC #define CPP_SPEC "%{scointl:-DM_INTERNAT}" /* This spec is used for telling cpp whether char is signed or not. */ #undef SIGNED_CHAR_SPEC #if DEFAULT_SIGNED_CHAR #define SIGNED_CHAR_SPEC \ "%{funsigned-char:-D__CHAR_UNSIGNED__ -D_CHAR_UNSIGNED}" #else #define SIGNED_CHAR_SPEC \ "%{!fsigned-char:-D__CHAR_UNSIGNED__ -D_CHAR_UNSIGNED}" #endif /* Use atexit for static destructors, instead of defining our own exit function. */ #define HAVE_ATEXIT /* Specify the size_t type. */ #define SIZE_TYPE "unsigned int" #if 0 /* Not yet certain whether this is needed. */ /* If no 387, use the general regs to return floating values, since this system does not emulate the 80387. */ #undef VALUE_REGNO #define VALUE_REGNO(MODE) \ ((TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode) ? FIRST_FLOAT_REG : 0) #undef HARD_REGNO_MODE_OK #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ((REGNO) < 2 ? 1 \ : (REGNO) < 4 ? 1 \ : FP_REGNO_P (REGNO) ? ((GET_MODE_CLASS (MODE) == MODE_FLOAT \ || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ && TARGET_80387 \ && GET_MODE_UNIT_SIZE (MODE) <= 8) \ : (MODE) != QImode) #endif /* caller has to pop the extra argument passed to functions that return structures. */ #undef RETURN_POPS_ARGS #define RETURN_POPS_ARGS(FUNTYPE,SIZE) \ (TREE_CODE (FUNTYPE) == IDENTIFIER_NODE ? 0 \ : (TARGET_RTD \ && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ == void_type_node))) ? (SIZE) \ : 0) /* On other 386 systems, the last line looks like this: : (aggregate_value_p (TREE_TYPE (FUNTYPE))) ? GET_MODE_SIZE (Pmode) : 0) */ gcc-2.5.8/config/i386/sco4.h100444 22011 13 4732 5453662517 13765 0ustar kenneruser/* Definitions for Intel 386 running SCO Unix System V 3.2 Version 4. Written by Chip Salzenberg. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Mostly it's like earlier SCO UNIX. */ #include "i386/sco.h" /* Use crt1.o as a startup file and crtn.o as a closing file. */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{scoxpg3:%{p:mcrt1X.o%s}%{!p:crt1X.o%s}} \ %{!scoxpg3:\ %{posix:%{p:mcrt1P.o%s}%{!p:crt1P.o%s}} \ %{!posix:\ %{ansi:%{p:mcrt1A.o%s}%{!p:crt1A.o%s}} \ %{!ansi:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}}}} \ crtbegin.o%s" #undef ENDFILE_SPEC #define ENDFILE_SPEC \ "crtend.o%s \ %{scoxpg3:crtnX.o%s} \ %{!scoxpg3:\ %{posix:crtnP.o%s} \ %{!posix:\ %{ansi:crtnA.o%s} \ %{!ansi:crtn.o%s}}}" /* Library spec. */ #undef LIB_SPEC #define LIB_SPEC \ "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} \ %{scoxpg3:-lcX -lcP -lcA} \ %{!scoxpg3:\ %{posix:-lcP -lcA} \ %{!posix:\ %{ansi:-lcA} \ %{!ansi:%{scointl:-lintl} -lc}}}" /* Macros, macros everywhere: Specify predefined symbols in preprocessor. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Di386 -Dunix -Asystem(unix) -Asystem(svr3) -Acpu(i386) -Amachine(i386)" #undef CPP_SPEC #define CPP_SPEC \ "-D_M_I386 -D_M_I86 -D_M_I86SM -D_M_SDATA -D_M_STEXT \ -D_M_UNIX -D_M_XENIX \ -D_M_SYS5 -D_M_SYSV -D_M_SYS3 -D_M_SYSIII \ -D_M_COFF -D_M_BITFIELDS -D_M_WORDSWAP \ %{scoxpg3:-D_XOPEN_SOURCE -D_STRICT_NAMES} \ %{!scoxpg3:%{posix:-D_POSIX_SOURCE -D_STRICT_NAMES}} \ %{!scoxpg3:%{!posix:\ %{ansi:-D_STRICT_NAMES}%{!ansi:\ -DM_I386 -DM_I86 -DM_I86SM -DM_SDATA -DM_STEXT \ -DM_UNIX -DM_XENIX \ -DM_SYS5 -DM_SYSV -DM_SYS3 -DM_SYSIII \ -DM_COFF -DM_BITFIELDS -DM_WORDSWAP \ %{scointl:-D_M_INTERNAT -DM_INTERNAT} \ %{traditional:-D_KR -D_SVID -D_NO_PROTOTYPE}}}}" gcc-2.5.8/config/i386/sco4dbx.h100444 22011 13 4760 5453234552 14456 0ustar kenneruser/* Definitions for Intel 386 running SCO Unix System V 3.2 Version 4.s, using dbx-in-coff encapsulation. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Mostly it's like earlier SCO UNIX. */ #include "i386/scodbx.h" /* Use crt1.o as a startup file and crtn.o as a closing file. */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{!r:%{!z:gcc.ifile%s}%{z:gccz.ifile%s}}\ %{scoxpg3:%{p:mcrt1X.o%s}%{!p:crt1X.o%s}} \ %{!scoxpg3:\ %{posix:%{p:mcrt1P.o%s}%{!p:crt1P.o%s}} \ %{!posix:\ %{ansi:%{p:mcrt1A.o%s}%{!p:crt1A.o%s}} \ %{!ansi:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}}}}" #undef ENDFILE_SPEC #define ENDFILE_SPEC \ "%{scoxpg3:crtnX.o%s} \ %{!scoxpg3:\ %{posix:crtnP.o%s} \ %{!posix:\ %{ansi:crtnA.o%s} \ %{!ansi:crtn.o%s}}}" /* Library spec. */ #undef LIB_SPEC #define LIB_SPEC \ "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} \ %{scoxpg3:-lcX -lcP -lcA} \ %{!scoxpg3:\ %{posix:-lcP -lcA} \ %{!posix:\ %{ansi:-lcA} \ %{!ansi:%{scointl:-lintl} -lc}}}" /* Macros, macros everywhere: Specify predefined symbols in preprocessor. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Di386 -Dunix -Asystem(unix) -Asystem(svr3) -Acpu(i386) -Amachine(i386)" #undef CPP_SPEC #define CPP_SPEC \ "-D_M_I386 -D_M_I86 -D_M_I86SM -D_M_SDATA -D_M_STEXT \ -D_M_UNIX -D_M_XENIX \ -D_M_SYS5 -D_M_SYSV -D_M_SYS3 -D_M_SYSIII \ -D_M_COFF -D_M_BITFIELDS -D_M_WORDSWAP \ %{scoxpg3:-D_XOPEN_SOURCE -D_STRICT_NAMES} \ %{!scoxpg3:%{posix:-D_POSIX_SOURCE -D_STRICT_NAMES}} \ %{!scoxpg3:%{!posix:\ %{ansi:-D_STRICT_NAMES}%{!ansi:\ -DM_I386 -DM_I86 -DM_I86SM -DM_SDATA -DM_STEXT \ -DM_UNIX -DM_XENIX \ -DM_SYS5 -DM_SYSV -DM_SYS3 -DM_SYSIII \ -DM_COFF -DM_BITFIELDS -DM_WORDSWAP \ %{scointl:-D_M_INTERNAT -DM_INTERNAT} \ %{traditional:-D_KR -D_SVID -D_NO_PROTOTYPE}}}}" gcc-2.5.8/config/i386/scodbx.h100444 22011 13 5703 5453234555 14373 0ustar kenneruser/* Definitions for Intel 386 running SCO Unix System V, using dbx-in-coff encapsulation. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "i386/svr3dbx.h" /* Overridden defines for SCO systems from sco.h. */ /* By default, target has a 80387, uses IEEE compatible arithmetic, and returns float values in the 387, ie, (TARGET_80387 | TARGET_FLOAT_RETURNS_IN_80387) SCO's software emulation of a 387 fails to handle the `fucomp' opcode. fucomp is only used when generating IEEE compliant code. So don't make TARGET_IEEE_FP default for SCO. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT 0201 /* Use crt1.o as a startup file and crtn.o as a closing file. */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{!r:%{!z:svr3.ifile%s}%{z:svr3z.ifile%s}}\ %{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}" /* Library spec, including SCO international language support. */ #undef LIB_SPEC #define LIB_SPEC \ "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} %{scointl:libintl.a%s} -lc" /* Specify predefined symbols in preprocessor. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dunix -Di386 -DM_UNIX -DM_I386 -DM_COFF -DM_WORDSWAP -Asystem(unix) -Asystem(svr3) -Acpu(i386) -Amachine(i386)" #undef CPP_SPEC #define CPP_SPEC "%{scointl:-DM_INTERNAT}" /* This spec is used for telling cpp whether char is signed or not. */ #undef SIGNED_CHAR_SPEC #if DEFAULT_SIGNED_CHAR #define SIGNED_CHAR_SPEC \ "%{funsigned-char:-D__CHAR_UNSIGNED__ -D_CHAR_UNSIGNED}" #else #define SIGNED_CHAR_SPEC \ "%{!fsigned-char:-D__CHAR_UNSIGNED__ -D_CHAR_UNSIGNED}" #endif /* Use atexit for static destructors, instead of defining our own exit function. */ #define HAVE_ATEXIT /* caller has to pop the extra argument passed to functions that return structures. */ #undef RETURN_POPS_ARGS #define RETURN_POPS_ARGS(FUNTYPE,SIZE) \ (TREE_CODE (FUNTYPE) == IDENTIFIER_NODE ? 0 \ : (TARGET_RTD \ && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ == void_type_node))) ? (SIZE) \ : 0) /* On other 386 systems, the last line looks like this: : (aggregate_value_p (TREE_TYPE (FUNTYPE))) ? GET_MODE_SIZE (Pmode) : 0) */ /* Use periods rather than dollar signs in special g++ assembler names. */ #define NO_DOLLAR_IN_LABEL gcc-2.5.8/config/i386/seq-gas.h100444 22011 13 2542 5317451261 14441 0ustar kenneruser/* Definitions for Sequent Intel 386 using GAS. Copyright (C) 1992 Free Software Foundation, Inc. /* Mostly it's like a Sequent 386 without GAS. */ #include "i386/sequent.h" /* A C statement or statements which output an assembler instruction opcode to the stdio stream STREAM. The macro-operand PTR is a variable of type `char *' which points to the opcode name in its "internal" form--the form that is written in the machine description. GAS version 1.38.1 doesn't understand the `repz' opcode mnemonic. So use `repe' instead. */ #undef ASM_OUTPUT_OPCODE #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ { \ if ((PTR)[0] == 'r' \ && (PTR)[1] == 'e' \ && (PTR)[2] == 'p') \ { \ if ((PTR)[3] == 'z') \ { \ fprintf (STREAM, "repe"); \ (PTR) += 4; \ } \ else if ((PTR)[3] == 'n' && (PTR)[4] == 'z') \ { \ fprintf (STREAM, "repne"); \ (PTR) += 5; \ } \ } \ } /* Define macro used to output shift-double opcodes when the shift count is in %cl. Some assemblers require %cl as an argument; some don't. GAS requires the %cl argument, so override i386/unix.h. */ #undef AS3_SHIFT_DOUBLE #define AS3_SHIFT_DOUBLE(a,b,c,d) AS3 (a,b,c,d) /* Print opcodes the way that GAS expects them. */ #define GAS_MNEMONICS 1 gcc-2.5.8/config/i386/seq-sysv3.h100444 22011 13 1436 5463103765 14764 0ustar kenneruser#include "i386/sysv3.h" /* Sequent Symmetry SVr3 doesn't have crtn.o; crt1.o doesn't work but crt0.o does. */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{pg:gcrt0.o%s}\ %{!pg:%{posix:%{p:mcrtp0.o%s}%{!p:crtp0.o%s}}\ %{!posix:%{p:mcrt0.o%s}%{!p:crt0.o%s}}} crtbegin.o%s\ %{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp}" #undef LIB_SPEC #define LIB_SPEC "%{posix:-lcposix} %{shlib:-lc_s} -lc crtend.o%s" #undef CPP_SPEC #define CPP_SPEC "%{posix:-D_POSIX_SOURCE} -D_SEQUENT_" /* Although the .init section is used, it is not automatically invoked. This because the _start() function in /lib/crt0.o never calls anything from the .init section */ #define INVOKE__main /* Use atexit for static destructors, instead of defining our own exit function. */ #define HAVE_ATEXIT gcc-2.5.8/config/i386/sequent.h100444 22011 13 11523 5453234560 14606 0ustar kenneruser/* Definitions for Sequent Intel 386. Copyright (C) 1988 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "i386/i386.h" /* Use the BSD assembler syntax. */ #include "i386/bsd.h" /* By default, don't use IEEE compatible arithmetic comparisons because the assembler can't handle the fucom insn. Return float values in the 387. (TARGET_80387 | TARGET_FLOAT_RETURNS_IN_80387) */ #undef TARGET_DEFAULT #define TARGET_DEFAULT 0201 /* Specify predefined symbols in preprocessor. */ #define CPP_PREDEFINES "-Dunix -Di386 -Dsequent -Asystem(unix) -Acpu(i386) -Amachine(i386)" /* Pass -Z and -ZO options to the linker. */ #define LINK_SPEC "%{Z*}" #if 0 /* Dynix 3.1 is said to accept -L. */ /* Dynix V3.0.12 doesn't accept -L at all. */ #define LINK_LIBGCC_SPECIAL #endif /* Link with libg.a when debugging, for dbx's sake. */ #define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} " /* We don't want to output SDB debugging information. */ #undef SDB_DEBUGGING_INFO /* We want to output DBX debugging information. */ #define DBX_DEBUGGING_INFO /* Sequent Symmetry has size_t defined as int in /usr/include/sys/types.h */ #define SIZE_TYPE "int" /* gcc order is ax, dx, cx, bx, si, di, bp, sp, st, st. * dbx order is ax, dx, cx, st(0), st(1), bx, si, di, st(2), st(3), * st(4), st(5), st(6), st(7), sp, bp */ /* ??? The right thing would be to change the ordering of the registers to correspond to the conventions of this system, and get rid of DBX_REGISTER_NUMBER. */ #undef DBX_REGISTER_NUMBER #define DBX_REGISTER_NUMBER(n) \ ((n) < 3 ? (n) : (n) < 6 ? (n) + 2 \ : (n) == 6 ? 15 : (n) == 7 ? 14 : 3) /* malcolmp@hydra.maths.unsw.EDU.AU says these two definitions fix trouble in dbx. */ #undef DBX_OUTPUT_LBRAC #define DBX_OUTPUT_LBRAC(file,name) \ fprintf (asmfile, "%s %d,0,%d,", ASM_STABN_OP, N_LBRAC, depth); \ assemble_name (asmfile, buf); \ fprintf (asmfile, "\n"); #undef DBX_OUTPUT_RBRAC #define DBX_OUTPUT_RBRAC(file,name) \ fprintf (asmfile, "%s %d,0,%d,", ASM_STABN_OP, N_RBRAC, depth); \ assemble_name (asmfile, buf); \ fprintf (asmfile, "\n"); /* Prevent anything from being allocated in the register pair cx/bx, since that would confuse GDB. */ #undef HARD_REGNO_MODE_OK #define HARD_REGNO_MODE_OK(REGNO, MODE) \ (((REGNO) < 2 ? 1 \ : (REGNO) < 4 ? 1 \ : FP_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_FLOAT \ || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ : (MODE) != QImode) \ && ! (REGNO == 2 && GET_MODE_UNIT_SIZE (MODE) > 4)) /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ #undef FUNCTION_PROFILER #define FUNCTION_PROFILER(FILE, LABELNO) \ fprintf (FILE, "\tmovl $.LP%d,%%eax\n\tcall mcount\n", (LABELNO)); /* Assembler pseudo-op for shared data segment. */ #define SHARED_SECTION_ASM_OP ".shdata" /* A C statement or statements which output an assembler instruction opcode to the stdio stream STREAM. The macro-operand PTR is a variable of type `char *' which points to the opcode name in its "internal" form--the form that is written in the machine description. The Sequent assembler (identified as "Balance 8000 Assembler 07/17/85 3.90" by "as -v") does not understand the `movs[bwl]' string move mnemonics - it uses `smov[bwl]' instead. Change "movs" into "smov", carefully avoiding the sign-extend opcodes. */ #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ { \ if ((PTR)[0] == 'm' \ && (PTR)[1] == 'o' \ && (PTR)[2] == 'v' \ && (PTR)[3] == 's' \ && ((PTR)[4] == 'b' || (PTR)[4] == 'w' || (PTR)[4] == 'l') \ && ((PTR)[5] == ' ' || (PTR)[5] == '\t'|| (PTR)[5] == '\0')) \ { \ fprintf (STREAM, "smov"); \ (PTR) += 4; \ } \ } /* 10-Aug-92 pes Local labels are prefixed with ".L" */ #undef LPREFIX #define LPREFIX ".L" #undef ASM_GENERATE_INTERNAL_LABEL #define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER)\ sprintf ((BUF), "*.%s%d", (PREFIX), (NUMBER)) #undef ASM_OUTPUT_INTERNAL_LABEL #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)\ fprintf (FILE, ".%s%d:\n", PREFIX, NUM) gcc-2.5.8/config/i386/sol2-c1.asm100444 22011 13 12211 5334576243 14633 0ustar kenneruser! crt1.s for Solaris 2, x86 ! Copyright (C) 1993 Free Software Foundation, Inc. ! Written By Fred Fish, Nov 1992 ! ! This file is free software; you can redistribute it and/or modify it ! under the terms of the GNU General Public License as published by the ! Free Software Foundation; either version 2, or (at your option) any ! later version. ! ! In addition to the permissions in the GNU General Public License, the ! Free Software Foundation gives you unlimited permission to link the ! compiled version of this file with other programs, and to distribute ! those programs without any restriction coming from the use of this ! file. (The General Public License restrictions do apply in other ! respects; for example, they cover modification of the file, and ! distribution when not linked into another program.) ! ! This file is distributed in the hope that it will be useful, but ! WITHOUT ANY WARRANTY; without even the implied warranty of ! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ! General Public License for more details. ! ! You should have received a copy of the GNU General Public License ! along with this program; see the file COPYING. If not, write to ! the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! ! As a special exception, if you link this library with files ! compiled with GCC to produce an executable, this does not cause ! the resulting executable to be covered by the GNU General Public License. ! This exception does not however invalidate any other reasons why ! the executable file might be covered by the GNU General Public License. ! ! This file takes control of the process from the kernel, as specified ! in section 3 of the System V Application Binary Interface, Intel386 ! Processor Supplement. It has been constructed from information obtained ! from the ABI, information obtained from single stepping existing ! Solaris executables through their startup code with gdb, and from ! information obtained by single stepping executables on other i386 SVR4 ! implementations. This file is the first thing linked into any executable. .file "crt1.s" .ident "GNU C crt1.s" .weak _cleanup .weak _DYNAMIC .text ! Start creating the initial frame by pushing a NULL value for the return ! address of the initial frame, and mark the end of the stack frame chain ! (the innermost stack frame) with a NULL value, per page 3-32 of the ABI. ! Initialize the first stack frame pointer in %ebp (the contents of which ! are unspecified at process initialization). .globl _start _start: pushl $0x0 pushl $0x0 movl %esp,%ebp ! As specified per page 3-32 of the ABI, %edx contains a function ! pointer that should be registered with atexit(), for proper ! shared object termination. Just push it onto the stack for now ! to preserve it. We want to register _cleanup() first. pushl %edx ! Check to see if there is an _cleanup() function linked in, and if ! so, register it with atexit() as the last thing to be run by ! atexit(). movl $_cleanup,%eax testl %eax,%eax je .L1 pushl $_cleanup call atexit addl $0x4,%esp .L1: ! Now check to see if we have an _DYNAMIC table, and if so then ! we need to register the function pointer previously in %edx, but ! now conveniently saved on the stack as the argument to pass to ! atexit(). movl $_DYNAMIC,%eax testl %eax,%eax je .L2 call atexit .L2: ! Register _fini() with atexit(). We will take care of calling _init() ! directly. pushl $_fini call atexit ! Compute the address of the environment vector on the stack and load ! it into the global variable _environ. Currently argc is at 8 off ! the frame pointer. Fetch the argument count into %eax, scale by the ! size of each arg (4 bytes) and compute the address of the environment ! vector which is 16 bytes (the two zero words we pushed, plus argc, ! plus the null word terminating the arg vector) further up the stack, ! off the frame pointer (whew!). movl 8(%ebp),%eax leal 16(%ebp,%eax,4),%edx movl %edx,_environ ! Push the environment vector pointer, the argument vector pointer, ! and the argument count on to the stack to set up the arguments ! for _init(), _fpstart(), and main(). Note that the environment ! vector pointer and the arg count were previously loaded into ! %edx and %eax respectively. The only new value we need to compute ! is the argument vector pointer, which is at a fixed address off ! the initial frame pointer. pushl %edx leal 12(%ebp),%edx pushl %edx pushl %eax ! Call _init(argc, argv, environ), _fpstart(argc, argv, environ), and ! main(argc, argv, environ). call _init call __fpstart call main ! Pop the argc, argv, and environ arguments off the stack, push the ! value returned from main(), and call exit(). addl $12,%esp pushl %eax call exit ! An inline equivalent of _exit, as specified in Figure 3-26 of the ABI. pushl $0x0 movl $0x1,%eax lcall $7,$0 ! If all else fails, just try a halt! hlt .type _start,@function .size _start,.-_start ! A dummy profiling support routine for non-profiling executables, ! in case we link in some objects that have been compiled for profiling. .globl _mcount _mcount: ret .type _mcount,@function .size _mcount,.-_mcount gcc-2.5.8/config/i386/sol2-ci.asm100444 22011 13 3661 5334576244 14715 0ustar kenneruser! crti.s for Solaris 2, x86. ! Copyright (C) 1993 Free Software Foundation, Inc. ! Written By Fred Fish, Nov 1992 ! ! This file is free software; you can redistribute it and/or modify it ! under the terms of the GNU General Public License as published by the ! Free Software Foundation; either version 2, or (at your option) any ! later version. ! ! In addition to the permissions in the GNU General Public License, the ! Free Software Foundation gives you unlimited permission to link the ! compiled version of this file with other programs, and to distribute ! those programs without any restriction coming from the use of this ! file. (The General Public License restrictions do apply in other ! respects; for example, they cover modification of the file, and ! distribution when not linked into another program.) ! ! This file is distributed in the hope that it will be useful, but ! WITHOUT ANY WARRANTY; without even the implied warranty of ! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ! General Public License for more details. ! ! You should have received a copy of the GNU General Public License ! along with this program; see the file COPYING. If not, write to ! the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! ! As a special exception, if you link this library with files ! compiled with GCC to produce an executable, this does not cause ! the resulting executable to be covered by the GNU General Public License. ! This exception does not however invalidate any other reasons why ! the executable file might be covered by the GNU General Public License. ! ! This file just supplies labeled starting points for the .init and .fini ! sections. It is linked in before the values-Xx.o files and also before ! crtbegin.o. .file "crti.s" .ident "GNU C crti.s" .section .init .globl _init .type _init,@function _init: .section .fini .globl _fini .type _fini,@function _fini: gcc-2.5.8/config/i386/sol2-cn.asm100444 22011 13 3476 5334576244 14726 0ustar kenneruser! crtn.s for Solaris 2, x86. ! Copyright (C) 1993 Free Software Foundation, Inc. ! Written By Fred Fish, Nov 1992 ! ! This file is free software; you can redistribute it and/or modify it ! under the terms of the GNU General Public License as published by the ! Free Software Foundation; either version 2, or (at your option) any ! later version. ! ! In addition to the permissions in the GNU General Public License, the ! Free Software Foundation gives you unlimited permission to link the ! compiled version of this file with other programs, and to distribute ! those programs without any restriction coming from the use of this ! file. (The General Public License restrictions do apply in other ! respects; for example, they cover modification of the file, and ! distribution when not linked into another program.) ! ! This file is distributed in the hope that it will be useful, but ! WITHOUT ANY WARRANTY; without even the implied warranty of ! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ! General Public License for more details. ! ! You should have received a copy of the GNU General Public License ! along with this program; see the file COPYING. If not, write to ! the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! ! As a special exception, if you link this library with files ! compiled with GCC to produce an executable, this does not cause ! the resulting executable to be covered by the GNU General Public License. ! This exception does not however invalidate any other reasons why ! the executable file might be covered by the GNU General Public License. ! ! This file just supplies returns for the .init and .fini sections. It is ! linked in after all other files. .file "crtn.o" .ident "GNU C crtn.o" .section .init ret $0x0 .section .fini ret $0x0 gcc-2.5.8/config/i386/sol2.h100444 22011 13 5405 5443060152 13754 0ustar kenneruser/* Target definitions for GNU compiler for Intel 80386 running Solaris 2 Copyright (C) 1993 Free Software Foundation, Inc. Written by Fred Fish (fnf@cygnus.com). This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "i386/sysv4.h" /* The Solaris 2.0 x86 linker botches alignment of code sections. It tries to align to a 16 byte boundary by padding with 0x00000090 ints, rather than 0x90 bytes (nop). This generates trash in the ".init" section since the contribution from crtbegin.o is only 7 bytes. The linker pads it to 16 bytes with a single 0x90 byte, and two 0x00000090 ints, which generates a segmentation violation when executed. This macro forces the assembler to do the padding, since it knows what it is doing. */ #define FORCE_INIT_SECTION_ALIGN do { asm (ALIGN_ASM_OP ## " 16"); } while (0) #undef CPP_SPEC #define CPP_SPEC "\ %{compat-bsd:-iwithprefixbefore ucbinclude -I/usr/ucbinclude}" #undef LIB_SPEC #define LIB_SPEC \ "%{compat-bsd:-lucb -lsocket -lnsl -lelf -laio} \ %{!shared:%{!symbolic:-lc}} \ crtend.o%s \ %{!shared:%{!symbolic:%{pg:crtn.o%s}%{!pg:crtn.o%s}}}" /* This should be the same as in svr4.h, except with -R added. */ #undef LINK_SPEC #define LINK_SPEC \ "%{h*} %{V} %{v:%{!V:-V}} \ %{b} %{Wl,*:%*} \ %{static:-dn -Bstatic} \ %{shared:-G -dy} \ %{symbolic:-Bsymbolic -G -dy} \ %{G:-G} \ %{YP,*} \ %{R*} \ %{compat-bsd: \ %{!YP,*:%{p:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ %{!p:-Y P,/usr/ucblib:/usr/ccs/lib:/usr/lib}} \ -R /usr/ucblib} \ %{!compat-bsd: \ %{!YP,*:%{p:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ %{!p:-Y P,/usr/ccs/lib:/usr/lib}}} \ %{Qy:} %{!Qn:-Qy}" /* This defines which switch letters take arguments. It is as in svr4.h but with -R added. */ #undef SWITCH_TAKES_ARG #define SWITCH_TAKES_ARG(CHAR) \ ( (CHAR) == 'D' \ || (CHAR) == 'U' \ || (CHAR) == 'o' \ || (CHAR) == 'e' \ || (CHAR) == 'u' \ || (CHAR) == 'I' \ || (CHAR) == 'm' \ || (CHAR) == 'L' \ || (CHAR) == 'R' \ || (CHAR) == 'A' \ || (CHAR) == 'h' \ || (CHAR) == 'z') gcc-2.5.8/config/i386/sun.h100444 22011 13 4503 5453234563 13712 0ustar kenneruser/* Definitions for Intel 386 running SunOS 4.0. Copyright (C) 1988 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "i386/i386.h" /* Use the Sun assembler syntax. */ #include "i386/sun386.h" /* Use crt0.o as a startup file. */ #define STARTFILE_SPEC \ "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}" #define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \ %{g:-lg} %{sun386:}" /* That last item is just to prevent a spurious error. */ #undef LINK_SPEC #define LINK_SPEC \ "%{!nostdlib:%{!r*:%{!e*:-e _start}}} -dc -dp %{static:-Bstatic}" /* Extra switches to give the assembler. */ #define ASM_SPEC "-i386" /* Specify predefined symbols in preprocessor. */ #define CPP_PREDEFINES "-Dunix -Di386 -Dsun386 -Dsun -Asystem(unix) -Asystem(bsd) -Acpu(i386) -Amachine(i386)" /* Allow #sccs in preprocessor. */ #define SCCS_DIRECTIVE /* Output #ident as a .ident. */ #define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME); /* We don't want to output SDB debugging information. */ #undef SDB_DEBUGGING_INFO /* We want to output DBX debugging information. */ #define DBX_DEBUGGING_INFO /* Implicit library calls should use memcpy, not bcopy, etc. */ #define TARGET_MEM_FUNCTIONS /* Force structure alignment to the type used for a bitfield. */ #define PCC_BITFIELD_TYPE_MATTERS 1 /* This is partly guess. */ #undef DBX_REGISTER_NUMBER #define DBX_REGISTER_NUMBER(n) \ ((n) == 0 ? 11 : (n) == 1 ? 9 : (n) == 2 ? 10 : (n) == 3 ? 8 \ : (n) == 4 ? 5 : (n) == 5 ? 4 : (n) == 6 ? 6 : (n)) /* Every debugger symbol must be in the text section. Otherwise the assembler or the linker screws up. */ #define DEBUG_SYMS_TEXT gcc-2.5.8/config/i386/sun386.h100444 22011 13 10764 5451700406 14171 0ustar kenneruser/* Definitions for Sun assembler syntax for the Intel 80386. Copyright (C) 1988 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Include common aspects of all 386 Unix assemblers. */ #include "i386/unix.h" #define TARGET_VERSION fprintf (stderr, " (80386, Sun syntax)"); /* Define the syntax of instructions and addresses. */ /* Prefix for internally generated assembler labels. */ #define LPREFIX ".L" /* Define the syntax of pseudo-ops, labels and comments. */ /* Assembler pseudos to introduce constants of various size. */ #define ASM_BYTE_OP "\t.byte" #define ASM_SHORT "\t.value" #define ASM_LONG "\t.long" #define ASM_DOUBLE "\t.double" /* How to output an ASCII string constant. */ #define ASM_OUTPUT_ASCII(FILE, p, size) \ do \ { int i = 0; \ while (i < (size)) \ { if (i%10 == 0) { if (i!=0) fprintf ((FILE), "\n"); \ fprintf ((FILE), "%s ", ASM_BYTE_OP); } \ else fprintf ((FILE), ","); \ fprintf ((FILE), "0x%x", ((p)[i++] & 0377)) ;} \ fprintf ((FILE), "\n"); \ } while (0) /* Output at beginning of assembler file. */ /* The .file command should always begin the output. */ #undef ASM_FILE_START #define ASM_FILE_START(FILE) \ do { \ extern char *version_string, *language_string; \ { \ int len = strlen (dump_base_name); \ char *na = dump_base_name + len; \ char shorter[15]; \ /* NA gets DUMP_BASE_NAME sans directory names. */\ while (na > dump_base_name) \ { \ if (na[-1] == '/') \ break; \ na--; \ } \ strncpy (shorter, na, 14); \ shorter[14] = 0; \ fprintf (FILE, "\t.file\t"); \ output_quoted_string (FILE, shorter); \ fprintf (FILE, "\n"); \ } \ fprintf (FILE, "\t.version\t\"%s %s\"\n", \ language_string, version_string); \ if (optimize) ASM_FILE_START_1 (FILE); \ } while (0) #define ASM_FILE_START_1(FILE) fprintf (FILE, "\t.optim\n") /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG)) /* This is how to output an assembler line that says to advance the location counter by SIZE bytes. */ #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf ((FILE), "\t.set\t.,.+%u\n", (SIZE)) /* Output before read-only data. */ #undef TEXT_SECTION_ASM_OP #define TEXT_SECTION_ASM_OP ".text" /* Output before writable data. */ #undef DATA_SECTION_ASM_OP #define DATA_SECTION_ASM_OP ".data" /* Define the syntax of labels and symbol definitions/declarations. */ /* This says how to output an assembler line to define a global common symbol. */ #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fputs (".comm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (ROUNDED))) /* This says how to output an assembler line to define a local common symbol. */ #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( fputs (".lcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (ROUNDED))) /* This is how to store into the string BUF the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ sprintf ((BUF), "*.%s%d", (PREFIX), (NUMBER)) /* This is how to output a reference to a user-level label named NAME. */ #define ASM_OUTPUT_LABELREF(FILE,NAME) \ fprintf (FILE, "%s", NAME) /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, ".%s%d:\n", PREFIX, NUM) gcc-2.5.8/config/i386/svr3.ifile100444 22011 13 2602 5450046724 14636 0ustar kenneruser/* * svr3.ifile - for collectless G++ on i386 System V. * Leaves memory configured at address 0. * * Install this file as $prefix/gcc-lib/TARGET/VERSION/gcc.ifile * * BLOCK to an offset that leaves room for many headers ( the value * here allows for a file header, an outheader, and up to 11 section * headers on most systems. * BIND to an address that includes page 0 in mapped memory. The value * used for BLOCK should be or'd into this value. Here I'm setting BLOCK * to 0x200 and BIND to ( value_used_for(BLOCK) ) * If you are using shared libraries, watch that you don't overlap the * address ranges assigned for shared libs. * * GROUP BIND to a location in the next segment. Here, the only value * that you should change (I think) is that within NEXT, which I've set * to my hardware segment size. You can always use a larger size, but not * a smaller one. */ SECTIONS { .text BIND(0x000200) BLOCK (0x200) : { /* plenty for room for headers */ *(.init) *(.text) vfork = fork; /* I got tired of editing peoples sloppy code */ *(.fini) } GROUP BIND( NEXT(0x400000) + (ADDR(.text) + (SIZEOF(.text)) % 0x1000)): { .data : { __CTOR_LIST__ = . ; . += 4 ; /* leading NULL */ *(.ctor) . += 4 ; /* trailing NULL */ __DTOR_LIST__ = . ; . += 4 ; /* leading NULL */ *(.dtor) . += 4 ; /* trailing NULL */ } .bss : { } } } gcc-2.5.8/config/i386/svr3dbx.h100444 22011 13 7153 5450046746 14505 0ustar kenneruser/* Definitions for Intel 386 running system V, using dbx-in-coff encapsulation. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "i386/svr3gas.h" /* We do not want to output SDB debugging information. */ #undef SDB_DEBUGGING_INFO /* We want to output DBX debugging information. */ #define DBX_DEBUGGING_INFO /* Compensate for botch in dbxout_init/dbxout_source_file which unconditionally drops the first character from ltext_label_name */ #undef ASM_GENERATE_INTERNAL_LABEL #define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ sprintf ((BUF), "*.%s%d", (PREFIX), (NUMBER)) /* With the current gas, .align N aligns to an N-byte boundary. This is done to be compatible with the system assembler. You have specify -DOTHER_ALIGN wenn building gas-1.38.1. */ #undef ASM_OUTPUT_ALIGN #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG)) /* Align labels, etc. at 4-byte boundaries. For the 486, align to 16-byte boundary for sake of cache. */ #undef ASM_OUTPUT_ALIGN_CODE #define ASM_OUTPUT_ALIGN_CODE(FILE) \ fprintf ((FILE), "\t.align %d,0x90\n", \ TARGET_486 ? 16 : 4); /* Use log of 16 or log of 4 as arg. */ /* Align start of loop at 4-byte boundary. */ #undef ASM_OUTPUT_LOOP_ALIGN #define ASM_OUTPUT_LOOP_ALIGN(FILE) \ fprintf ((FILE), "\t.align 4,0x90\n"); /* Additional overrides needed for dbx-in-coff gas, mostly taken from pbb.h */ /* Although the gas we use can create .ctor and .dtor sections from N_SETT stabs, it does not support section directives, so we need to have the loader define the lists. */ #define CTOR_LISTS_DEFINED_EXTERNALLY /* similar to default, but allows for the table defined by ld with svr3.ifile. nptrs is always 0. So we need to instead check that __DTOR_LIST__[1] != 0. The old check is left in so that the same macro can be used if and when a future version of gas does support section directives. */ #define DO_GLOBAL_DTORS_BODY {int nptrs = *(int *)__DTOR_LIST__; int i; \ if (nptrs == -1 || (__DTOR_LIST__[0] == 0 && __DTOR_LIST__[1] != 0)) \ for (nptrs = 0; __DTOR_LIST__[nptrs + 1] != 0; nptrs++); \ for (i = nptrs; i >= 1; i--) \ __DTOR_LIST__[i] (); } /* Use crt1.o as a startup file and crtn.o as a closing file. */ /* * The loader directive file svr3.ifile defines how to merge the constructor * sections into the data section. Also, since gas only puts out those * sections in response to N_SETT stabs, and does not (yet) have a * ".sections" directive, svr3.ifile also defines the list symbols * __DTOR_LIST__ and __CTOR_LIST__. */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{!r:%{!z:svr3.ifile%s}%{z:svr3z.ifile%s}}\ %{pg:gcrt1.o%s}%{!pg:%{posix:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}%{!posix:%{p:mcrt1.o%s}%{!p:crt1.o%s}}} \ %{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp}" #define ENDFILE_SPEC "crtn.o%s" #undef LIB_SPEC #define LIB_SPEC "%{posix:-lcposix} %{shlib:-lc_s} -lc -lg" gcc-2.5.8/config/i386/svr3gas.h100444 22011 13 22635 5450047063 14515 0ustar kenneruser/* Definitions for Intel 386 running system V, using gas. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "i386/gas.h" /* Add stuff that normally comes from i386/sysv3.h */ /* longjmp may fail to restore the registers if called from the same function that called setjmp. To compensate, the compiler avoids putting variables in registers in functions that use both setjmp and longjmp. */ #define NON_SAVING_SETJMP \ (current_function_calls_setjmp && current_function_calls_longjmp) /* longjmp may fail to restore the stack pointer if the saved frame pointer is the same as the caller's frame pointer. Requiring a frame pointer in any function that calls setjmp or longjmp avoids this problem, unless setjmp and longjmp are called from the same function. Since a frame pointer will be required in such a function, it is OK that the stack pointer is not restored. */ #undef FRAME_POINTER_REQUIRED #define FRAME_POINTER_REQUIRED \ (current_function_calls_setjmp || current_function_calls_longjmp) /* Modify ASM_OUTPUT_LOCAL slightly to test -msvr3-shlib, adapted to gas */ #undef ASM_OUTPUT_LOCAL #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ do { \ int align = exact_log2 (ROUNDED); \ if (align > 2) align = 2; \ if (TARGET_SVR3_SHLIB) \ { \ data_section (); \ ASM_OUTPUT_ALIGN ((FILE), align == -1 ? 2 : align); \ ASM_OUTPUT_LABEL ((FILE), (NAME)); \ fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED)); \ } \ else \ { \ fputs (".lcomm ", (FILE)); \ assemble_name ((FILE), (NAME)); \ fprintf ((FILE), ",%u\n", (ROUNDED)); \ } \ } while (0) /* Add stuff that normally comes from i386/sysv3.h via svr3.h */ /* Define the actual types of some ANSI-mandated types. These definitions should work for most SVR3 systems. */ #undef SIZE_TYPE #define SIZE_TYPE "unsigned int" #undef PTRDIFF_TYPE #define PTRDIFF_TYPE "int" #undef WCHAR_TYPE #define WCHAR_TYPE "long int" #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE BITS_PER_WORD /* ??? This stuff is copied from config/svr3.h. In the future, this file should be rewritten to include config/svr3.h and override what isn't right. */ /* Support const sections and the ctors and dtors sections for g++. Note that there appears to be two different ways to support const sections at the moment. You can either #define the symbol READONLY_DATA_SECTION (giving it some code which switches to the readonly data section) or else you can #define the symbols EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and SELECT_RTX_SECTION. We do both here just to be on the safe side. However, use of the const section is turned off by default unless the specific tm.h file turns it on by defining USE_CONST_SECTION as 1. */ /* Define a few machine-specific details of the implementation of constructors. The __CTORS_LIST__ goes in the .init section. Define CTOR_LIST_BEGIN and CTOR_LIST_END to contribute to the .init section an instruction to push a word containing 0 (or some equivalent of that). Define ASM_OUTPUT_CONSTRUCTOR to push the address of the constructor. */ #define USE_CONST_SECTION 0 #define INIT_SECTION_ASM_OP ".section\t.init" #define FINI_SECTION_ASM_OP ".section .fini,\"x\"" #define CONST_SECTION_ASM_OP ".section\t.rodata, \"x\"" #define CTORS_SECTION_ASM_OP INIT_SECTION_ASM_OP #define DTORS_SECTION_ASM_OP FINI_SECTION_ASM_OP /* CTOR_LIST_BEGIN and CTOR_LIST_END are machine-dependent because they push on the stack. */ #ifdef STACK_GROWS_DOWNWARD /* Constructor list on stack is in reverse order. Go to the end of the list and go backwards to call constructors in the right order. */ #define DO_GLOBAL_CTORS_BODY \ do { \ func_ptr *p, *beg = alloca (0); \ for (p = beg; *p; p++) \ ; \ while (p != beg) \ (*--p) (); \ } while (0) #else /* Constructor list on stack is in correct order. Just call them. */ #define DO_GLOBAL_CTORS_BODY \ do { \ func_ptr *p, *beg = alloca (0); \ for (p = beg; *p; ) \ (*p++) (); \ } while (0) #endif /* STACK_GROWS_DOWNWARD */ /* Add extra sections .init and .fini, in addition to .bss from att386.h. */ #undef EXTRA_SECTIONS #define EXTRA_SECTIONS in_const, in_bss, in_init, in_fini #undef EXTRA_SECTION_FUNCTIONS #define EXTRA_SECTION_FUNCTIONS \ CONST_SECTION_FUNCTION \ BSS_SECTION_FUNCTION \ INIT_SECTION_FUNCTION \ FINI_SECTION_FUNCTION #define BSS_SECTION_FUNCTION \ void \ bss_section () \ { \ if (in_section != in_bss) \ { \ fprintf (asm_out_file, "\t%s\n", BSS_SECTION_ASM_OP); \ in_section = in_bss; \ } \ } #define INIT_SECTION_FUNCTION \ void \ init_section () \ { \ if (in_section != in_init) \ { \ fprintf (asm_out_file, "\t%s\n", INIT_SECTION_ASM_OP); \ in_section = in_init; \ } \ } #define FINI_SECTION_FUNCTION \ void \ fini_section () \ { \ if (in_section != in_fini) \ { \ fprintf (asm_out_file, "\t%s\n", FINI_SECTION_ASM_OP); \ in_section = in_fini; \ } \ } #define READONLY_DATA_SECTION() const_section () #define CONST_SECTION_FUNCTION \ void \ const_section () \ { \ extern void text_section(); \ if (!USE_CONST_SECTION) \ text_section(); \ else if (in_section != in_const) \ { \ fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP); \ in_section = in_const; \ } \ } /* The ctors and dtors sections are not normally put into use by EXTRA_SECTIONS and EXTRA_SECTION_FUNCTIONS as defined in svr3.h, but it can't hurt to define these macros for whatever systems use them. */ #define CTORS_SECTION_FUNCTION \ void \ ctors_section () \ { \ if (in_section != in_ctors) \ { \ fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \ in_section = in_ctors; \ } \ } #define DTORS_SECTION_FUNCTION \ void \ dtors_section () \ { \ if (in_section != in_dtors) \ { \ fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \ in_section = in_dtors; \ } \ } /* This is machine-dependent because it needs to push something on the stack. */ #undef ASM_OUTPUT_CONSTRUCTOR /* A C statement (sans semicolon) to output an element in the table of global destructors. */ #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ do { \ fini_section (); \ fprintf (FILE, "%s\t ", ASM_LONG); \ assemble_name (FILE, NAME); \ fprintf (FILE, "\n"); \ } while (0) /* A C statement or statements to switch to the appropriate section for output of DECL. DECL is either a `VAR_DECL' node or a constant of some sort. RELOC indicates whether forming the initial value of DECL requires link-time relocations. */ #define SELECT_SECTION(DECL,RELOC) \ { \ if (TREE_CODE (DECL) == STRING_CST) \ { \ if (! flag_writable_strings) \ const_section (); \ else \ data_section (); \ } \ else if (TREE_CODE (DECL) == VAR_DECL) \ { \ if ((0 && RELOC) /* should be (flag_pic && RELOC) */ \ || !TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL)) \ data_section (); \ else \ const_section (); \ } \ else \ const_section (); \ } /* A C statement or statements to switch to the appropriate section for output of RTX in mode MODE. RTX is some kind of constant in RTL. The argument MODE is redundant except in the case of a `const_int' rtx. Currently, these always go into the const section. */ #define SELECT_RTX_SECTION(MODE,RTX) const_section() /* This is copied from i386/sysv3.h. */ /* Define a few machine-specific details of the implementation of constructors. The __CTORS_LIST__ goes in the .init section. Define CTOR_LIST_BEGIN and CTOR_LIST_END to contribute to the .init section an instruction to push a word containing 0 (or some equivalent of that). ASM_OUTPUT_CONSTRUCTOR should be defined to push the address of the constructor. */ #undef INIT_SECTION_ASM_OP #define INIT_SECTION_ASM_OP ".section .init,\"x\"" #define CTOR_LIST_BEGIN \ asm (INIT_SECTION_ASM_OP); \ asm ("pushl $0") #define CTOR_LIST_END CTOR_LIST_BEGIN #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ do { \ init_section (); \ fprintf (FILE, "\tpushl $"); \ assemble_name (FILE, NAME); \ fprintf (FILE, "\n"); \ } while (0) gcc-2.5.8/config/i386/svr3z.ifile100444 22011 13 2622 5450047074 15031 0ustar kenneruser/* * svr3z.ifile - for collectless G++ on i386 System V. * Leaves memory unconfigured at address 0. * * Install this file as $prefix/gcc-lib/TARGET/VERSION/gccz.ifile * * BLOCK to an offset that leaves room for many headers ( the value * here allows for a file header, an outheader, and up to 11 section * headers on most systems. * BIND to an address that excludes page 0 from being mapped. The value * used for BLOCK should be or'd into this value. Here I'm setting BLOCK * to 0x200 and BIND to ( 0x400000 | value_used_for(BLOCK) ) * If you are using shared libraries, watch that you don't overlap the * address ranges assigned for shared libs. * * GROUP BIND to a location in the next segment. Here, the only value * that you should change (I think) is that within NEXT, which I've set * to my hardware segment size. You can always use a larger size, but not * a smaller one. */ SECTIONS { .text BIND(0x400200) BLOCK (0x200) : { /* plenty for room for headers */ *(.init) *(.text) vfork = fork; /* I got tired of editing peoples sloppy code */ *(.fini) } GROUP BIND( NEXT(0x400000) + (ADDR(.text) + (SIZEOF(.text)) % 0x1000)): { .data : { __CTOR_LIST__ = . ; . += 4 ; /* leading NULL */ *(.ctor) . += 4 ; /* trailing NULL */ __DTOR_LIST__ = . ; . += 4 ; /* leading NULL */ *(.dtor) . += 4 ; /* trailing NULL */ } .bss : { } } } gcc-2.5.8/config/i386/sysv3.h100444 22011 13 7673 5453234566 14212 0ustar kenneruser/* Definitions for Intel 386 running system V. Copyright (C) 1988 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "i386/i386.h" /* Use default settings for system V.3. */ #include "svr3.h" /* Use the ATT assembler syntax. This overrides at least one macro (ASM_OUTPUT_LABELREF) from svr3.h. */ #include "i386/att.h" /* Use crt1.o as a startup file and crtn.o as a closing file. */ #define STARTFILE_SPEC \ "%{pg:gcrt1.o%s}%{!pg:%{posix:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}%{!posix:%{p:mcrt1.o%s}%{!p:crt1.o%s}}} crtbegin.o%s\ %{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp}" /* ??? There is a suggestion that -lg is needed here. Does anyone know whether this is right? */ #define LIB_SPEC "%{posix:-lcposix} %{shlib:-lc_s} -lc crtend.o%s crtn.o%s" /* Specify predefined symbols in preprocessor. */ #define CPP_PREDEFINES "-Dunix -Di386 -Asystem(unix) -Asystem(svr3) -Acpu(i386) -Amachine(i386)" #define CPP_SPEC "%{posix:-D_POSIX_SOURCE}" /* Writing `int' for a bitfield forces int alignment for the structure. */ #define PCC_BITFIELD_TYPE_MATTERS 1 /* Don't write a `.optim' pseudo; this assembler doesn't handle them. */ #undef ASM_FILE_START_1 #define ASM_FILE_START_1(FILE) /* longjmp may fail to restore the registers if called from the same function that called setjmp. To compensate, the compiler avoids putting variables in registers in functions that use both setjmp and longjmp. */ #define NON_SAVING_SETJMP \ (current_function_calls_setjmp && current_function_calls_longjmp) /* longjmp may fail to restore the stack pointer if the saved frame pointer is the same as the caller's frame pointer. Requiring a frame pointer in any function that calls setjmp or longjmp avoids this problem, unless setjmp and longjmp are called from the same function. Since a frame pointer will be required in such a function, it is OK that the stack pointer is not restored. */ #undef FRAME_POINTER_REQUIRED #define FRAME_POINTER_REQUIRED \ (current_function_calls_setjmp || current_function_calls_longjmp) /* Modify ASM_OUTPUT_LOCAL slightly to test -msvr3-shlib. */ #undef ASM_OUTPUT_LOCAL #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ do { \ int align = exact_log2 (ROUNDED); \ if (align > 2) align = 2; \ if (TARGET_SVR3_SHLIB) \ data_section (); \ else \ bss_section (); \ ASM_OUTPUT_ALIGN ((FILE), align == -1 ? 2 : align); \ ASM_OUTPUT_LABEL ((FILE), (NAME)); \ fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED)); \ } while (0) /* Define a few machine-specific details of the implementation of constructors. The __CTORS_LIST__ goes in the .init section. Define CTOR_LIST_BEGIN and CTOR_LIST_END to contribute to the .init section an instruction to push a word containing 0 (or some equivalent of that). ASM_OUTPUT_CONSTRUCTOR should be defined to push the address of the constructor. */ #undef INIT_SECTION_ASM_OP #define INIT_SECTION_ASM_OP ".section .init,\"x\"" #define CTOR_LIST_BEGIN \ asm (INIT_SECTION_ASM_OP); \ asm ("pushl $0") #define CTOR_LIST_END CTOR_LIST_BEGIN #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ do { \ init_section (); \ fprintf (FILE, "\tpushl $"); \ assemble_name (FILE, NAME); \ fprintf (FILE, "\n"); \ } while (0) gcc-2.5.8/config/i386/sysv4.h100444 22011 13 22106 5453662523 14215 0ustar kenneruser/* Target definitions for GNU compiler for Intel 80386 running System V.4 Copyright (C) 1991 Free Software Foundation, Inc. Written by Ron Guilmette (rfg@ncd.com). This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "i386/i386.h" /* Base i386 target machine definitions */ #include "i386/att.h" /* Use the i386 AT&T assembler syntax */ #include "svr4.h" /* Definitions common to all SVR4 targets */ #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (i386 System V Release 4)"); /* The svr4 ABI for the i386 says that records and unions are returned in memory. */ #undef RETURN_IN_MEMORY #define RETURN_IN_MEMORY(TYPE) \ (TYPE_MODE (TYPE) == BLKmode) /* Define which macros to predefine. __svr4__ is our extension. */ /* This used to define X86, but james@bigtex.cactus.org says that is supposed to be defined optionally by user programs--not by default. */ #define CPP_PREDEFINES \ "-Di386 -Dunix -D__svr4__ -Asystem(unix) -Asystem(svr4) -Acpu(i386) -Amachine(i386)" /* This is how to output assembly code to define a `float' constant. We always have to use a .long pseudo-op to do this because the native SVR4 ELF assembler is buggy and it generates incorrect values when we try to use the .float pseudo-op instead. */ #undef ASM_OUTPUT_FLOAT #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { long value; \ REAL_VALUE_TO_TARGET_SINGLE ((VALUE), value); \ if (sizeof (int) == sizeof (long)) \ fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value); \ else \ fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value); \ } while (0) /* This is how to output assembly code to define a `double' constant. We always have to use a pair of .long pseudo-ops to do this because the native SVR4 ELF assembler is buggy and it generates incorrect values when we try to use the the .double pseudo-op instead. */ #undef ASM_OUTPUT_DOUBLE #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { long value[2]; \ REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), value); \ if (sizeof (int) == sizeof (long)) \ { \ fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[0]); \ fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[1]); \ } \ else \ { \ fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[0]); \ fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[1]); \ } \ } while (0) #undef ASM_OUTPUT_LONG_DOUBLE #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ do { long value[3]; \ REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), value); \ if (sizeof (int) == sizeof (long)) \ { \ fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[0]); \ fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[1]); \ fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[2]); \ } \ else \ { \ fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[0]); \ fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[1]); \ fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[2]); \ } \ } while (0) /* Output at beginning of assembler file. */ /* The .file command should always begin the output. */ #undef ASM_FILE_START #define ASM_FILE_START(FILE) \ do { \ output_file_directive (FILE, main_input_filename); \ fprintf (FILE, "\t.version\t\"01.01\"\n"); \ } while (0) /* Define the register numbers to be used in Dwarf debugging information. The SVR4 reference port C compiler uses the following register numbers in its Dwarf output code: 0 for %eax (gnu regno = 0) 1 for %ecx (gnu regno = 2) 2 for %edx (gnu regno = 1) 3 for %ebx (gnu regno = 3) 4 for %esp (gnu regno = 7) 5 for %ebp (gnu regno = 6) 6 for %esi (gnu regno = 4) 7 for %edi (gnu regno = 5) The following three DWARF register numbers are never generated by the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4 believes these numbers have these meanings. 8 for %eip (no gnu equivalent) 9 for %eflags (no gnu equivalent) 10 for %trapno (no gnu equivalent) It is not at all clear how we should number the FP stack registers for the x86 architecture. If the version of SDB on x86/svr4 were a bit less brain dead with respect to floating-point then we would have a precedent to follow with respect to DWARF register numbers for x86 FP registers, but the SDB on x86/svr4 is so completely broken with respect to FP registers that it is hardly worth thinking of it as something to strive for compatibility with. The verison of x86/svr4 SDB I have at the moment does (partially) seem to believe that DWARF register number 11 is associated with the x86 register %st(0), but that's about all. Higher DWARF register numbers don't seem to be associated with anything in particular, and even for DWARF regno 11, SDB only seems to under- stand that it should say that a variable lives in %st(0) (when asked via an `=' command) if we said it was in DWARF regno 11, but SDB still prints garbage when asked for the value of the variable in question (via a `/' command). (Also note that the labels SDB prints for various FP stack regs when doing an `x' command are all wrong.) Note that these problems generally don't affect the native SVR4 C compiler because it doesn't allow the use of -O with -g and because when it is *not* optimizing, it allocates a memory location for each floating-point variable, and the memory location is what gets described in the DWARF AT_location attribute for the variable in question. Regardless of the severe mental illness of the x86/svr4 SDB, we do something sensible here and we use the following DWARF register numbers. Note that these are all stack-top-relative numbers. 11 for %st(0) (gnu regno = 8) 12 for %st(1) (gnu regno = 9) 13 for %st(2) (gnu regno = 10) 14 for %st(3) (gnu regno = 11) 15 for %st(4) (gnu regno = 12) 16 for %st(5) (gnu regno = 13) 17 for %st(6) (gnu regno = 14) 18 for %st(7) (gnu regno = 15) */ #undef DBX_REGISTER_NUMBER #define DBX_REGISTER_NUMBER(n) \ ((n) == 0 ? 0 \ : (n) == 1 ? 2 \ : (n) == 2 ? 1 \ : (n) == 3 ? 3 \ : (n) == 4 ? 6 \ : (n) == 5 ? 7 \ : (n) == 6 ? 5 \ : (n) == 7 ? 4 \ : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \ : (-1)) /* The routine used to output sequences of byte values. We use a special version of this for most svr4 targets because doing so makes the generated assembly code more compact (and thus faster to assemble) as well as more readable. Note that if we find subparts of the character sequence which end with NUL (and which are shorter than STRING_LIMIT) we output those using ASM_OUTPUT_LIMITED_STRING. */ #undef ASM_OUTPUT_ASCII #define ASM_OUTPUT_ASCII(FILE, STR, LENGTH) \ do \ { \ register unsigned char *_ascii_bytes = (unsigned char *) (STR); \ register unsigned char *limit = _ascii_bytes + (LENGTH); \ register unsigned bytes_in_chunk = 0; \ for (; _ascii_bytes < limit; _ascii_bytes++) \ { \ register unsigned char *p; \ if (bytes_in_chunk >= 64) \ { \ fputc ('\n', (FILE)); \ bytes_in_chunk = 0; \ } \ for (p = _ascii_bytes; p < limit && *p != '\0'; p++) \ continue; \ if (p < limit && (p - _ascii_bytes) <= STRING_LIMIT) \ { \ if (bytes_in_chunk > 0) \ { \ fputc ('\n', (FILE)); \ bytes_in_chunk = 0; \ } \ ASM_OUTPUT_LIMITED_STRING ((FILE), _ascii_bytes); \ _ascii_bytes = p; \ } \ else \ { \ if (bytes_in_chunk == 0) \ fprintf ((FILE), "\t.byte\t"); \ else \ fputc (',', (FILE)); \ fprintf ((FILE), "0x%02x", *_ascii_bytes); \ bytes_in_chunk += 5; \ } \ } \ if (bytes_in_chunk > 0) \ fprintf ((FILE), "\n"); \ } \ while (0) /* This is how to output an element of a case-vector that is relative. This is only used for PIC code. See comments by the `casesi' insn in i386.md for an explanation of the expression this outputs. */ #undef ASM_OUTPUT_ADDR_DIFF_ELT #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE) /* Indicate that jump tables go in the text section. This is necessary when compiling PIC code. */ #define JUMP_TABLES_IN_TEXT_SECTION gcc-2.5.8/config/i386/t-aix100444 22011 13 356 5455253135 13661 0ustar kenneruser# target: IBM AIX PS/2 1.3.0 with gas-2.x and gnu ld 2.x # For aix ps/2 we build crtbegin.o and crtend.o which serve to add begin and # end labels to the .ctors and .dtors section when we link using gcc. EXTRA_PARTS=crtbegin.o crtend.o gcc-2.5.8/config/i386/t-isc100444 22011 13 260 5455253140 13644 0ustar kenneruser# For svr3 we build crtbegin.o and crtend.o which serve to add begin and # end labels to the .ctors and .dtors section when we link using gcc. EXTRA_PARTS=crtbegin.o crtend.o gcc-2.5.8/config/i386/t-next100444 22011 13 345 5443705721 14054 0ustar kenneruser# libgcc1.c is not needed, since the standard library has these functions. LIBGCC1=libgcc1.null CROSS_LIBGCC1=libgcc1.null # Specify other dirs of system header files to be fixed. OTHER_FIXINCLUDES_DIRS= /LocalDeveloper/Headers gcc-2.5.8/config/i386/t-iscscodbx100444 22011 13 104 5450047170 15043 0ustar kenneruser# The one that comes with the system is POSIX-compliant. LIMITS_H = gcc-2.5.8/config/i386/t-osfrose100444 22011 13 131 5455253142 14545 0ustar kenneruserEXTRA_OBJS = halfpic.o halfpic.o: halfpic.c $(CONFIG_H) $(CONFIG2_H) $(RTL_H) $(TREE_H) gcc-2.5.8/config/i386/t-sco100444 22011 13 260 5455253145 13657 0ustar kenneruser# For svr3 we build crtbegin.o and crtend.o which serve to add begin and # end labels to the .ctors and .dtors section when we link using gcc. EXTRA_PARTS=crtbegin.o crtend.o gcc-2.5.8/config/i386/t-sol2100444 22011 13 2230 5443705722 13771 0ustar kenneruser# We need startup files for Solaris, since we don't get them with the system # FIXME: Should include "gmon.o" when it is ported. EXTRA_PARTS=crt1.o crti.o crtn.o crtbegin.o crtend.o # we need to supply our own assembly versions of libgcc1.c files, # since the user may not have native 'cc' available LIBGCC1 = libgcc1.null CROSS_LIBGCC1 = libgcc1.null # gmon build rule: gmon.o: $(srcdir)/config/i386/gmon-sol2.c $(GCC_PASSES) $(CONFIG_H) $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) \ -c $(srcdir)/config/i386/gmon-sol2.c -o gmon.o # Assemble startup files. # Apparently Sun believes that assembler files don't need comments, because no # single ASCII character is valid (tried them all). So we manually strip out # the comments with sed. This bug may only be in the Early Access releases. crt1.o: $(srcdir)/config/i386/sol2-c1.asm sed -e '/^!/d' <$(srcdir)/config/i386/sol2-c1.asm >crt1.s $(AS) -o crt1.o crt1.s crti.o: $(srcdir)/config/i386/sol2-ci.asm sed -e '/^!/d' <$(srcdir)/config/i386/sol2-ci.asm >crti.s $(AS) -o crti.o crti.s crtn.o: $(srcdir)/config/i386/sol2-cn.asm sed -e '/^!/d' <$(srcdir)/config/i386/sol2-cn.asm >crtn.s $(AS) -o crtn.o crtn.s gcc-2.5.8/config/i386/t-svr3dbx100444 22011 13 462 5450047246 14470 0ustar kenneruser# gas 1.38.1 supporting dbx-in-coff requires a link script. EXTRA_PARTS=svr3.ifile svr3z.ifile svr3.ifile: $(srcdir)/config/i386/svr3.ifile rm -f svr3.ifile; cp $(srcdir)/config/i386/svr3.ifile . svr3z.ifile: $(srcdir)/config/i386/svr3z.ifile rm -f svr3z.ifile; cp $(srcdir)/config/i386/svr3z.ifile . gcc-2.5.8/config/i386/unix.h100444 22011 13 11137 5317463223 14105 0ustar kenneruser/* Definitions for Unix assembler syntax for the Intel 80386. Copyright (C) 1988 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* This file defines the aspects of assembler syntax that are the same for all the i386 Unix systems (though they may differ in non-Unix systems). */ /* Define some concatenation macros to concatenate an opcode and one, two or three operands. In other assembler syntaxes they may alter the order of ther operands. */ /* Note that the other files fail to use these in some of the places where they should. */ #ifdef __STDC__ #define AS2(a,b,c) #a " " #b "," #c #define AS3(a,b,c,d) #a " " #b "," #c "," #d #define AS1(a,b) #a " " #b #else #define AS1(a,b) "a b" #define AS2(a,b,c) "a b,c" #define AS3(a,b,c,d) "a b,c,d" #endif /* Define macro used to output shift-double opcodes when the shift count is in %cl. Some assemblers require %cl as an argument; some don't. This macro controls what to do: by default, don't print %cl. */ #define AS3_SHIFT_DOUBLE(a,b,c,d) AS2 (a,c,d) /* Output the size-letter for an opcode. CODE is the letter used in an operand spec (L, B, W, S or Q). CH is the corresponding lower case letter (except if CODE is `Q' then CH is `l', unless GAS_MNEMONICS). */ #define PUT_OP_SIZE(CODE,CH,FILE) putc (CH,(FILE)) /* Opcode suffix for fullword insn. */ #define L_SIZE "l" /* Prefix for register names in this syntax. */ #define RP "%" /* Prefix for immediate operands in this syntax. */ #define IP "$" /* Indirect call instructions should use `*'. */ #define USE_STAR 1 /* Prefix for a memory-operand X. */ #define PRINT_PTR(X, FILE) /* Delimiters that surround base reg and index reg. */ #define ADDR_BEG(FILE) putc('(', (FILE)) #define ADDR_END(FILE) putc(')', (FILE)) /* Print an index register (whose rtx is IREG). */ #define PRINT_IREG(FILE,IREG) \ do \ { fputs (",", (FILE)); PRINT_REG ((IREG), 0, (FILE)); } \ while (0) /* Print an index scale factor SCALE. */ #define PRINT_SCALE(FILE,SCALE) \ if ((SCALE) != 1) fprintf ((FILE), ",%d", (SCALE)) /* Print a base/index combination. BREG is the base reg rtx, IREG is the index reg rtx, and SCALE is the index scale factor (an integer). */ #define PRINT_B_I_S(BREG,IREG,SCALE,FILE) \ { ADDR_BEG (FILE); \ if (BREG) PRINT_REG ((BREG), 0, (FILE)); \ if ((IREG) != 0) \ { PRINT_IREG ((FILE), (IREG)); \ PRINT_SCALE ((FILE), (SCALE)); } \ ADDR_END (FILE); } /* Define the syntax of pseudo-ops, labels and comments. */ /* String containing the assembler's comment-starter. */ #define ASM_COMMENT_START "/" #define COMMENT_BEGIN "/" /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ #define ASM_APP_ON "/APP\n" /* Output to assembler file text saying following lines no longer contain unusual constructs. */ #define ASM_APP_OFF "/NO_APP\n" /* Output before read-only data. */ #define TEXT_SECTION_ASM_OP ".text" /* Output before writable (initialized) data. */ #define DATA_SECTION_ASM_OP ".data" /* Output before writable (uninitialized) data. */ #define BSS_SECTION_ASM_OP ".bss" /* This is how to output a command to make the user-level label named NAME defined for reference from other files. */ #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ (fputs (".globl ", FILE), assemble_name (FILE, NAME), fputs ("\n", FILE)) /* By default, target has a 80387, uses IEEE compatible arithmetic, and returns float values in the 387, ie, (TARGET_80387 | TARGET_IEEE_FP | TARGET_FLOAT_RETURNS_IN_80387) */ #define TARGET_DEFAULT 0301 /* Floating-point return values come in the FP register. */ #define VALUE_REGNO(MODE) \ (GET_MODE_CLASS (MODE) == MODE_FLOAT \ && TARGET_FLOAT_RETURNS_IN_80387 ? FIRST_FLOAT_REG : 0) /* 1 if N is a possible register number for a function value. */ #define FUNCTION_VALUE_REGNO_P(N) \ ((N) == 0 || ((N)== FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387)) gcc-2.5.8/config/i386/v3gas.h100444 22011 13 5304 5450047302 14116 0ustar kenneruser/* Definitions for Intel 386 running system V, using gas. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "gas.h" /* Add stuff that normally comes from i386v.h */ /* longjmp may fail to restore the registers if called from the same function that called setjmp. To compensate, the compiler avoids putting variables in registers in functions that use both setjmp and longjmp. */ #define NON_SAVING_SETJMP \ (current_function_calls_setjmp && current_function_calls_longjmp) /* longjmp may fail to restore the stack pointer if the saved frame pointer is the same as the caller's frame pointer. Requiring a frame pointer in any function that calls setjmp or longjmp avoids this problem, unless setjmp and longjmp are called from the same function. Since a frame pointer will be required in such a function, it is OK that the stack pointer is not restored. */ #undef FRAME_POINTER_REQUIRED #define FRAME_POINTER_REQUIRED \ (current_function_calls_setjmp || current_function_calls_longjmp) /* Modify ASM_OUTPUT_LOCAL slightly to test -msvr3-shlib, adapted to gas */ #undef ASM_OUTPUT_LOCAL #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ do { \ int align = exact_log2 (ROUNDED); \ if (align > 2) align = 2; \ if (TARGET_SVR3_SHLIB) \ { \ data_section (); \ ASM_OUTPUT_ALIGN ((FILE), align == -1 ? 2 : align); \ ASM_OUTPUT_LABEL ((FILE), (NAME)); \ fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED)); \ } \ else \ { \ fputs (".lcomm ", (FILE)); \ assemble_name ((FILE), (NAME)); \ fprintf ((FILE), ",%u\n", (ROUNDED)); \ } \ } while (0) /* Add stuff that normally comes from i386v.h via svr3.h */ /* Define the actual types of some ANSI-mandated types. These definitions should work for most SVR3 systems. */ #undef SIZE_TYPE #define SIZE_TYPE "unsigned int" #undef PTRDIFF_TYPE #define PTRDIFF_TYPE "int" #undef WCHAR_TYPE #define WCHAR_TYPE "long int" #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE BITS_PER_WORD gcc-2.5.8/config/i386/x-aix100444 22011 13 765 5400067143 13661 0ustar kenneruser# There is an alloca in -lbsd, but it is limited to 32K ALLOCA = alloca.o # If you are running out of memory while compiling gcc, with the standard # /bin/cc uncomment MALLOCLIB line. That version of malloc is slower but # has less overhead than the one in libc. #MALLOCLIB = -lmalloc # Uncomment out the next line if you want to link with the shareable libc_s. #CLIB_S = -lc_s CLIB = -lld $(MALLOCLIB) $(CLIB_S) # Use a special fixincludes file to avoid munging types.h. FIXINCLUDES = fixinc.ps2 gcc-2.5.8/config/i386/x-isc100444 22011 13 124 5376470514 13657 0ustar kenneruserCLIB = -lPW -lcposix X_CFLAGS = -D_POSIX_SOURCE ENQUIRE_LDFLAGS = -posix $(LDFLAGS) gcc-2.5.8/config/i386/x-isc3100444 22011 13 251 5450047343 13734 0ustar kenneruserCLIB = -lPW # One person said it needs -DPOSIX_JC, but daa@CERF.NET says no. X_CFLAGS = -D_SYSV3 ENQUIRE_LDFLAGS = $(LDFLAGS) INSTALL_HEADERS_DIR = install-headers-cpio gcc-2.5.8/config/i386/x-linux100444 22011 13 1030 5463033117 14244 0ustar kenneruserX_CFLAGS = -DPOSIX # The following is needed when compiling stages 2 and 3 because gcc's # limits.h must be picked up before /usr/include/limits.h. This is because # each does an #include_next of the other if the other hasn't been included. # /usr/include/limits.h loses if it gets found first because /usr/include is # at the end of the search order. When a new version of gcc is released, # gcc's limits.h hasn't been installed yet and hence isn't found. BOOT_CFLAGS = -O $(CFLAGS) -Iinclude # Don't run fixproto STMP_FIXPROTO = gcc-2.5.8/config/i386/x-ncr3000100444 22011 13 2552 5426012070 14176 0ustar kenneruser# Makefile additions for the NCR3000 as host system. # Using -O with the AT&T compiler fails, with a message about a missing # /usr/ccs/lib/optim pass. So override the default in Makefile.in CCLIBFLAGS= ## Supposedly not needed now that xm-sysv4.h includes alloc.h for Metaware. ### NCR3000 ships with a MetaWare compiler installed as CC, which chokes and ### dies all over the place on GCC source. However, the AT&T compiler, ### crusty as it is, can be used to bootstrap GCC. It can be found in ### /usr/ccs/ATT/cc. It is also used to compile the things that should ### not be compiled with GCC. ## ##CC = /usr/ccs/ATT/cc ##OLDCC = /usr/ccs/ATT/cc # The rest is just x-i386v4. # Some versions of SVR4 have an alloca in /usr/ucblib/libucb.a, and if we are # careful to link that in after libc we can use it, but since newer versions of # SVR4 are dropping libucb, it is better to just use the portable C version for # bootstrapping. Do this by defining ALLOCA. ALLOCA = alloca.o # We used to build all stages *without* shared libraries because that may make # debugging the compiler easier (until there is a GDB which supports # both Dwarf *and* svr4 shared libraries). # But james@bigtex.cactus.org says that redefining GCC_CFLAGS causes trouble, # and that it is easy enough to debug using shared libraries. # CCLIBFLAGS=-Bstatic -dn -g # GCC_CFLAGS=-static -g -O2 -B./ gcc-2.5.8/config/i386/x-next100444 22011 13 272 5361400407 14047 0ustar kenneruser# Make assignments for compiling on NeXT with their compiler version. CC=cc -traditional-cpp OLDCC=cc -traditional-cpp libgcc2.a: stdarg.h stdarg.h: cp $(srcdir)/gstdarg.h ./stdarg.h gcc-2.5.8/config/i386/x-osfrose100444 22011 13 1663 5453107001 14572 0ustar kenneruser# Define CC and OLDCC as the same, so that the tests: # if [ x"$(OLDCC)" = x"$(CC)" ] ... # # will succeed (if OLDCC != CC, it is assumed that GCC is # being used in secondary stage builds). BUILD = CC = $(OLDCC) CLIB = -lld X_CFLAGS = $(DEB_OPT) $(MSTATS) $(SHLIB) $(X_DEFINES) X_CFLAGS_NODEBUG = $(NO_DEBUG) $(MSTATS) $(OPT) $(PROFILE) $(SHLIB) $(X_DEFINES) $(XCFLAGS) CPP_ABORT = # -Dabort=fancy_abort CPPFLAGS = $(CPP_ABORT) $(SYSTEM_INCLUDES) DEB_OPT = $(OPT) $(DEBUG) $(PROFILE) DEBUG = DEBUG_COLLECT = # -DDEBUG CCLIBFLAGS = -O -DNO_HALF_PIC GCC_CFLAGS = $(INTERNAL_CFLAGS) $(X_CFLAGS) $(T_CFLAGS) $(CFLAGS) -B./ -DPOSIX -DNO_HALF_PIC INSTALL = installbsd -c LDFLAGS = MSTATS = # -mstats OLDCC = /usr/ccs/gcc/gcc OPT = -O PROFILE = SHLIB = -pic-none SYSTEM_INCLUDES = # -I${BUILD}/usr/include X_DEFINES = -Dvfork=fork libdir = /usr/ccs mandir = /usr/ccs/gcc/$(target)/$(version) bindir = /usr/ccs/gcc/$(target)/$(version) gcc-2.5.8/config/i386/x-sco100444 22011 13 231 5317463236 13662 0ustar kenneruserRANLIB = : RANLIB_TEST = false CC = rcc $(RCCFLAGS) OLDCC = rcc $(RCCFLAGS) RCCFLAGS = -Dunix -Di386 -DM_UNIX -DM_I386 -DNULL=0 CCLIBFLAGS = CLIB = -lPW gcc-2.5.8/config/i386/x-sco4100444 22011 13 174 5317463240 13747 0ustar kenneruserRANLIB = : RANLIB_TEST = false CLIB = -lPW CC = cc -nointl # Seems to be needed with SCO DEV3.2v4. X_CFLAGS = -D__STDC__=0 gcc-2.5.8/config/i386/x-sysv3100444 22011 13 12 5317463244 14141 0ustar kenneruserCLIB=-lPW gcc-2.5.8/config/i386/xm-aix.h100444 22011 13 2117 5464510775 14313 0ustar kenneruser/* Configuration for GNU C-compiler for IBM PS/2 running AIX/386. Copyright (C) 1988, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define USG #undef TRUE #undef FALSE #include "i386/xm-i386.h" #define bcopy(a,b,c) memcpy (b,a,c) #define bzero(a,b) memset (a,0,b) #define bcmp(a,b,c) memcmp (a,b,c) /* If not compiled with GNU C, use the portable alloca. */ #ifndef __GNUC__ #define USE_C_ALLOCA #endif #define HAVE_PUTENV gcc-2.5.8/config/i386/xm-dos.h100444 22011 13 460 5361366550 14272 0ustar kenneruser#include "i386/xm-i386.h" /* Inhibit cccp.c's definition of putenv. */ #define HAVE_PUTENV /* Use semicolons to separate elements of a path. */ #define PATH_SEPARATOR ';' /* Suffix for executable file names. */ #define EXECUTABLE_SUFFIX ".exe" #define MKTEMP_EACH_FILE 1 #define NO_PRECOMPILES 1 gcc-2.5.8/config/i386/xm-i386.h100444 22011 13 2464 5413066534 14221 0ustar kenneruser/* Configuration for GNU C-compiler for Intel 80386. Copyright (C) 1988, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef i386 #define i386 #endif /* #defines that need visibility everywhere. */ #define FALSE 0 #define TRUE 1 /* This describes the machine the compiler is hosted on. */ #define HOST_BITS_PER_CHAR 8 #define HOST_BITS_PER_SHORT 16 #define HOST_BITS_PER_INT 32 #define HOST_BITS_PER_LONG 32 #define HOST_BITS_PER_LONGLONG 64 /* Arguments to use with `exit'. */ #define SUCCESS_EXIT_CODE 0 #define FATAL_EXIT_CODE 33 /* target machine dependencies. tm.h is a symbolic link to the actual target specific file. */ #include "tm.h" gcc-2.5.8/config/i386/xm-isc.h100444 22011 13 216 5363437640 14263 0ustar kenneruser#include "i386/xm-sysv3.h" #ifndef REAL_ARITHMETIC #define REAL_VALUE_ATOF(x, mode) strtod ((x), (char **)0) extern double strtod (); #endif gcc-2.5.8/config/i386/xm-linux.h100444 22011 13 1002 5317434602 14650 0ustar kenneruser/* Configuration for GCC for Intel i386 running Linux. * * Written by H.J. Lu (hlu@eecs.wsu.edu) */ #include "i386/xm-i386.h" #include "xm-svr3.h" #undef BSTRING #define BSTRING #undef bcmp #undef bcopy #undef bzero #undef index #undef rindex #if 0 /* These conflict with stdlib.h in protoize, it is said, and there's no evidence they are actually needed. */ #undef malloc(n) #define malloc(n) malloc ((n) ? (n) : 1) #undef calloc(n,e) #define calloc(n,e) calloc (((n) ? (n) : 1), ((e) ? (e) : 1)) #endif gcc-2.5.8/config/i386/xm-next.h100444 22011 13 203 5361400410 14436 0ustar kenneruser#include "i386/xm-i386.h" /* malloc does better with chunks the size of a page. */ #define OBSTACK_CHUNK_SIZE (getpagesize ()) gcc-2.5.8/config/i386/xm-os2.h100444 22011 13 2702 5466257442 14236 0ustar kenneruser/* Configuration for GNU compiler for an Intel i386 or later processor running OS/2 2.x. Copyright (C) 1993 Free Software Foundation, Inc. Contributed by Samuel Figueroa (figueroa@cs.nyu.edu) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef OS2 #define OS2 #endif #ifdef __IBMC__ #include /* this defines alloca */ #define USG #define ONLY_INT_FIELDS #define HAVE_PUTENV #define USE_PROTOTYPES 1 #define bcmp(a,b,c) memcmp (a,b,c) #define bcopy(a,b,c) memcpy (b,a,c) #define bzero(a,b) memset (a,0,b) #define index strchr #define rindex strrchr #define kill(a,b) raise(b) #define mktemp tmpnam #else #define ____386BSD____ int spawnv (int modeflag, char *path, char *argv[]); int spawnvp (int modeflag, char *path, char *argv[]); #endif /* __IBMC__ */ #define EXECUTABLE_SUFFIX ".exe" #include "i386/xm-i386.h" gcc-2.5.8/config/i386/xm-sco.h100444 22011 13 1044 5370042352 14277 0ustar kenneruser/* Configuration for GCC for Intel i386 running SCO. */ #include "i386/xm-sysv3.h" /* On SCO 3.2.1, ldexp rejects values outside [0.5, 1). */ #define BROKEN_LDEXP /* Big buffers improve performance. */ #define IO_BUFFER_SIZE (0x8000 - 1024) /* SCO has a very small ARG_MAX. */ #define SMALL_ARG_MAX #ifndef __GNUC__ /* The SCO compiler gets it wrong, and treats enumerated bitfields as signed quantities, making it impossible to use an 8-bit enum for compiling GNU C++. */ #define ONLY_INT_FIELDS 1 #define CODE_FIELD_BUG 1 #endif gcc-2.5.8/config/i386/xm-sun.h100444 22011 13 1665 5324156526 14341 0ustar kenneruser/* Configuration for GNU C-compiler for Intel 80386 running SunOS 4.0. Copyright (C) 1988 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define USG #include "i386/xm-i386.h" #define bcopy(a,b,c) memcpy (b,a,c) #define bzero(a,b) memset (a,0,b) #define bcmp(a,b,c) memcmp (a,b,c) gcc-2.5.8/config/i386/xm-sysv3.h100444 22011 13 170 5317435217 14570 0ustar kenneruser/* Configuration for GCC for Intel i386 running System V Release 3. */ #include "i386/xm-i386.h" #include "xm-svr3.h" gcc-2.5.8/config/i386/xm-sysv4.h100444 22011 13 732 5426011703 14564 0ustar kenneruser/* Configuration for GCC for Intel i386 running System V Release 4. */ #include "i386/xm-i386.h" #include "xm-svr4.h" /* If not compiled with GNU C, use the portable alloca. */ #ifndef __GNUC__ #define USE_C_ALLOCA #endif #ifdef __HIGHC__ #include /* for MetaWare High-C on NCR System 3000 */ #endif /* Univel, at least, has a small ARG_MAX. Defining this is harmless except for causing extra stat calls in the driver program. */ #define SMALL_ARG_MAX gcc-2.5.8/config/i860/ 40777 22011 13 0 5502603156 12631 5ustar kennerusergcc-2.5.8/config/i860/bsd-gas.h100444 22011 13 123 5322501177 14365 0ustar kenneruser#include "i860/bsd.h" #undef ASCII_DATA_ASM_OP #define ASCII_DATA_ASM_OP ".ascii" gcc-2.5.8/config/i860/bsd.h100444 22011 13 2056 5322502607 13643 0ustar kenneruser#include "i860/i860.h" #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (i860, BSD)") /* BSD UN*X systems use BSD STABS debugging info. */ #define DBX_DEBUGGING_INFO #define ASCII_DATA_ASM_OP ".byte" #define ASM_OUTPUT_ASCII(f, p, size) \ { register unsigned i; \ int inside; \ inside = FALSE; \ for (i = 0; i < (size); i++) { \ if (i % 64 == 0) { \ if (i != 0) { \ if (inside) \ putc('"', (f)); \ putc('\n', (f)); \ inside = FALSE; \ } \ fprintf((f), "\t%s ", ASCII_DATA_ASM_OP); \ } \ if ((p)[i] < 32 || (p)[i] == '\\' || (p)[i] == '"' || (p)[i] >= 127) { \ if (inside) { \ putc('"', (f)); \ inside = FALSE; \ } \ if (i % 64 != 0) \ putc(',', (f)); \ fprintf((f), "%d", (p)[i]); \ } else { \ if (!inside) { \ if (i % 64 != 0) \ putc(',', (f)); \ putc('"', (f)); \ inside = TRUE; \ } \ putc((p)[i], (f)); \ } \ } \ if (inside) \ putc('"', (f)); \ putc('\n', (f)); \ } gcc-2.5.8/config/i860/fx2800.h100444 22011 13 25702 5453234575 14060 0ustar kenneruser/* Target definitions for GNU compiler for Alliant FX/2800 running Concentrix 2.2 Copyright (C) 1991 Free Software Foundation, Inc. Written by Howard Chu (hyc@hanauma.jpl.nasa.gov). This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define OUTPUT_TDESC #include "i860/sysv4.h" /* The Alliant fx2800 running Concentrix 2.x is weird. This is basically a BSD 4.3 based operating system, but it uses svr4 ELF format object files and it somehow puts BSD stabs records into the ELF files for symbolic debug information. The assembler is "mostly an SVR4 assembler with some Alliant additions. We based it on the `Intel 80860 Assembly Language Specification' from AT&T." */ /* This file consists of three sections. The first section establishes definitions unique to the Alliant FX/2800. The next section reconciles differences between Alliant and i860v4.h, and the last overrides the remaining differences with svr4.h */ #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (i860 Alliant)"); /* atexit is not present prior to Concentrix 2.2. Uncomment the following if you're on 2.1 or older. */ /* #undef HAVE_ATEXIT */ #define I860_STRICT_ABI_PROLOGUES /* There is no avoiding this; -L does not exist at all (in Concentrix 2.2). */ #define LINK_LIBGCC_SPECIAL 1 /* Most of the Alliant-specific definitions here are to get stab info that Alliant's dbx can understand. */ #define DBX_DEBUGGING_INFO #define DEFAULT_GDB_EXTENSIONS 0 #define DBX_NO_XREFS #define DBX_NO_EXTRA_TAGS /* Alliant dbx also needs to see the function stab before anything else in the function. */ #define DBX_FUNCTION_FIRST #define DBX_LBRAC_FIRST /* Alliant dbx also needs to see the end of a function somewhere. */ #define DBX_OUTPUT_FUNCTION_END(file,decl) \ fprintf (file, ".stab \"\",.,0x%x,0,0\n", N_EFUN) /* Alliant dbx has predefined types, so they must be emitted with the proper type numbers. The defined types are: Type # C, Fortran, Pascal Types -- ------------------------ 1 char, integer*1 2 short, integer*2 3 int, long, integer*4, integer 4 logical*1, byte 5 logical*2 6 logical*4, logical 7 float, real*4, real 8 double, real*8, double 9 single complex, complex*8, complex 10 double complex, doublecomplex 11 character 12 void 13 nil 14 boolean 15 unsigned char, ubyte 16 unsigned short, uword 17 unsigned, unsigned int, unsigned long, ulong 18 quad, logical*8 19 long long, integer*8 20 unsigned long long, uquad*8 21-100 reserved for future predefined types 100 long redefine same as 3 101 unsigned long same as 17 -- -------------------- 102 First user program type Since long and unsigned long are int references, they must be handled as special cases. The Alliant compiler doesn't use types 18-20, so it sets long & unsigned long in 18 & 19, not in 100 & 101 as shown above. */ #define DBX_OUTPUT_STANDARD_TYPES(syms) \ { char *dtyps[]={"", "char", "short int", "int", "logical*1", \ "logical*2", "logical*4", "float", "double", "complex", \ "doublecomplex", "character", "void", "nil", "boolean", \ "unsigned char", "short unsigned int", "unsigned int", \ "logical*8", "long long int", "long long unsigned int",""}; \ \ tree decl; \ int i; \ \ for (i=1;*dtyps[i];i++) \ for (decl = syms; decl; decl = TREE_CHAIN(decl)) \ if ((TREE_CODE (decl) == TYPE_DECL) && DECL_NAME(decl) && \ !strcmp(IDENTIFIER_POINTER(DECL_NAME(decl)), dtyps[i])) { \ TYPE_SYMTAB_ADDRESS (TREE_TYPE (decl)) = i; \ typevec[i] = TYPE_DEFINED; \ dbxout_symbol (decl, 0); \ break; \ } \ \ for (decl = syms; decl; decl = TREE_CHAIN(decl)) \ if ((TREE_CODE (decl) == TYPE_DECL) && DECL_NAME(decl) && \ !strcmp(IDENTIFIER_POINTER(DECL_NAME(decl)),"long int")) { \ TYPE_SYMTAB_ADDRESS (TREE_TYPE (decl)) = i; \ typevec[i] = TYPE_DEFINED; \ fprintf(asmfile,".stab \"long int:t%d=3\",0,0x%x,0,0\n", \ i++,N_LSYM); \ TREE_ASM_WRITTEN (decl) = 1; \ break; \ } \ \ for (decl = syms; decl; decl = TREE_CHAIN(decl)) \ if ((TREE_CODE (decl) == TYPE_DECL) && DECL_NAME(decl) && !strcmp( \ IDENTIFIER_POINTER(DECL_NAME(decl)),"long unsigned int")) { \ TYPE_SYMTAB_ADDRESS (TREE_TYPE (decl)) = i; \ typevec[i] = TYPE_DEFINED; \ fprintf(asmfile,".stab \"long unsigned int:t%d=17\",0,0x%x,0,0\n",\ i++,N_LSYM); \ TREE_ASM_WRITTEN (decl) = 1; \ break; \ } \ next_type_number = i; }; /* Alliant dbx doesn't understand split names... */ #define DBX_CONTIN_LENGTH 0 /* The syntax for stabs records is also different; there is only a single ".stab" directive instead of the 3 directives in BSD, and the order of arguments is slightly changed. */ #define ASM_STABS_OP ".stab" #define ASM_STABN_OP ".stab" #define ASM_STABD_OP ".stab" #define DBX_MEMPARM_STABS_LETTER 'k' #define DBX_REGPARM_STABS_LETTER 'r' #define ASM_OUTPUT_SOURCE_LINE(file,num) \ fprintf (file, "\t.stab \"\",.,0x%x,0,%d\n", \ N_SLINE,num) #if 0 /* Alliant dbx only reads first N_SO, so it ignores the filename if dir is present. */ #define DBX_OUTPUT_MAIN_SOURCE_DIRECTORY(file,name) \ fprintf (file, ".stab \"%s/\",.Ltext0,0x%x,0,0\n", \ name, N_SO) #else #define DBX_OUTPUT_MAIN_SOURCE_DIRECTORY(file,name) #endif #define DBX_OUTPUT_MAIN_SOURCE_FILENAME(file,name) \ fprintf (file, ".stab "); \ output_quoted_string (file, name); \ fprintf (file, ",.Ltext0,0x%x,0,0\n", N_SO); \ text_section (); \ ASM_OUTPUT_INTERNAL_LABEL (file, "Ltext", 0) #define DBX_OUTPUT_SOURCE_FILENAME(file,name) \ do { fprintf (file, ".stab "); \ output_quoted_string (file, name); \ fprintf (file, ",.Ltext0,0x%x,0,0\n", N_SOL); \ } while (0) #define DBX_OUTPUT_CONSTANT_SYMBOL(file,name,ival) \ fprintf (file, ".stab \"%s:c=i%d\",0,0x%x,0,0\n", \ name, ival, N_LSYM) #define DBX_FINISH_SYMBOL(decl) \ int line = 0; \ fprintf (asmfile, "\","); \ if (current_sym_addr) \ output_addr_const (asmfile, current_sym_addr); \ else \ fprintf (asmfile, "%d", current_sym_value); \ if (decl != 0 && TREE_CODE(decl) == FUNCTION_DECL) \ line=DECL_SOURCE_LINE (decl); \ fprintf (asmfile, ",0x%x,%d,%d\n", current_sym_code, \ line!=0?64:0,line) #define DBX_OUTPUT_CATCH(file,decl,name) \ fprintf (file, ".stab \"%s:C1\",", \ IDENTIFIER_POINTER (DECL_NAME (decl))); \ assemble_name (file, name); \ fprintf (file, ",0x%x,0,0\n", N_CATCH) #define DBX_OUTPUT_LBRAC(file,name) \ if (depth > 1) { \ fprintf (file, ".stab \"\","); \ assemble_name (file, name); \ fprintf (file, ",0x%x,0,%d\n", N_LBRAC, depth); } #define DBX_OUTPUT_RBRAC(file,name) \ if (depth > 1) { \ fprintf (file, ".stab \"\","); \ assemble_name (file, name); \ fprintf (file, ",0x%x,0,%d\n", N_RBRAC, depth); } #define DBX_OUTPUT_ENUM(file,type) \ fprintf (file, "e3"); \ CHARS(2); \ for (tem = TYPE_VALUES (type); tem; tem = TREE_CHAIN (tem)) \ { \ fprintf (asmfile, "%s:%d,", \ IDENTIFIER_POINTER (TREE_PURPOSE (tem)), \ TREE_INT_CST_LOW (TREE_VALUE (tem))); \ CHARS (11 + IDENTIFIER_LENGTH (TREE_PURPOSE (tem))); \ if (TREE_CHAIN (tem) != 0) \ CONTIN; \ } \ putc (';', asmfile); \ CHARS (1); /* Undefine some things defined in i860.h because the native C compiler on the FX/2800 emits code to do these operations inline. For GCC, we will use the default implementation of these things... i.e. generating calls to libgcc1 routines. */ #undef DIVSI3_LIBCALL #undef UDIVSI3_LIBCALL #undef REMSI3_LIBCALL #undef UREMSI3_LIBCALL /* The Alliant compiler's mod function gives the wrong result after a shift operation. This bug typically hits in hash functions. */ #define perform_umodsi3(a, b) a %= b; if (a == b) a=0; return a #define perform_modsi3(a, b) a %= b; if (a == b) a=0; return a /* Global pointer needs to be 8 byte aligned? Link error if not... */ #define DATA_ALIGNMENT(dummy,align) \ ((TREE_PUBLIC (decl) && \ (TREE_CODE (TREE_TYPE (decl))==POINTER_TYPE)) ? 64:align) #undef FUNCTION_PROFILER #define FUNCTION_PROFILER(FILE, LABELNO) \ fprintf (FILE, "\tcall __mcount_\n\tnop\n") /* Overrides for i860v4.h begin here */ /* Provide a set of pre-definitions and pre-assertions appropriate for the i860 running Concentrix 2.x. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Di860 -Dunix -DBSD4_3 -Dalliant -Asystem(unix) -Asystem(bsd) -Acpu(i860) -Amachine(i860)" #undef I860_REG_PREFIX #undef ASM_COMMENT_START #define ASM_COMMENT_START "//" /* Use definitions of ASM_OUTPUT_{DOUBLE,FLOAT} as given in i860.h */ #undef ASM_OUTPUT_DOUBLE #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ fprintf(FILE, "\t.double %.20e\n", (VALUE)) #undef ASM_OUTPUT_FLOAT #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ fprintf(FILE, "\t.float %.12e\n", (VALUE)) #undef ASM_FILE_START #define ASM_FILE_START(FILE) #undef ASM_OUTPUT_FUNCTION_PREFIX #define ASM_OUTPUT_FUNCTION_PREFIX(FILE,NAME) \ fputs("\tnop\n", (FILE)); \ current_function_original_name = (NAME) #undef ASM_OUTPUT_PROLOGUE_SUFFIX /* Overrides for svr4.h begin here */ #undef SVR4 #undef SWITCH_TAKES_ARG #undef WORD_SWITCH_TAKES_ARG #undef ASM_SPEC #undef ASM_FINAL_SPEC #undef MD_STARTFILE_PREFIX #undef MD_EXEC_PREFIX /* Generate an error message if -p option is selected. Concentrix 2.x does not support prof format profiling, only gprof is supported. */ #define CPP_SPEC "%{p:%e-p option not supported: use -pg instead}" /* Provide an appropriate LIB_SPEC. The crtend.o file provides part of the support for getting C++ file-scope static objects constructed before entering `main'. */ #undef LIB_SPEC #define LIB_SPEC \ "%{g*:-lg} %{!pg:-lc}%{pg:-lc_p} crtend.o%s" /* Tell linker to strip local symbols, since assembler may not. */ #undef LINK_SPEC #define LINK_SPEC "-X" /* Get the correct startup file for regular or profiled code. Also use the crtbegin.o file for C++ ... */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{!pg:crt0.o%s}%{pg:gcrt0.o%s} crtbegin.o%s" #undef SCCS_DIRECTIVE #undef NO_DOLLAR_IN_LABEL #undef TARGET_MEM_FUNCTIONS #undef DWARF_DEBUGGING_INFO #undef ASM_OUTPUT_LABELREF #define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "_%s", NAME) #undef ASM_OUTPUT_EXTERNAL_LIBCALL #undef BSS_ASM_OP #define BSS_ASM_OP "\t.lcomm" gcc-2.5.8/config/i860/i860.c100444 22011 13 173653 5420114352 13623 0ustar kenneruser/* Subroutines for insn-output.c for Intel 860 Copyright (C) 1989, 1991 Free Software Foundation, Inc. Derived from sparc.c. Written by Richard Stallman (rms@ai.mit.edu). Hacked substantially by Ron Guilmette (rfg@ncd.com) to cater to the whims of the System V Release 4 assembler. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "config.h" #include "flags.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "output.h" #include "recog.h" #include "insn-attr.h" #include static rtx find_addr_reg (); #ifndef I860_REG_PREFIX #define I860_REG_PREFIX "" #endif char *i860_reg_prefix = I860_REG_PREFIX; /* Save information from a "cmpxx" operation until the branch is emitted. */ rtx i860_compare_op0, i860_compare_op1; /* Return non-zero if this pattern, can be evaluated safely, even if it was not asked for. */ int safe_insn_src_p (op, mode) rtx op; enum machine_mode mode; { /* Just experimenting. */ /* No floating point src is safe if it contains an arithmetic operation, since that operation may trap. */ switch (GET_CODE (op)) { case CONST_INT: case LABEL_REF: case SYMBOL_REF: case CONST: return 1; case REG: return 1; case MEM: return CONSTANT_ADDRESS_P (XEXP (op, 0)); /* We never need to negate or complement constants. */ case NEG: return (mode != SFmode && mode != DFmode); case NOT: case ZERO_EXTEND: return 1; case EQ: case NE: case LT: case GT: case LE: case GE: case LTU: case GTU: case LEU: case GEU: case MINUS: case PLUS: return (mode != SFmode && mode != DFmode); case AND: case IOR: case XOR: case LSHIFT: case ASHIFT: case ASHIFTRT: case LSHIFTRT: if ((GET_CODE (XEXP (op, 0)) == CONST_INT && ! SMALL_INT (XEXP (op, 0))) || (GET_CODE (XEXP (op, 1)) == CONST_INT && ! SMALL_INT (XEXP (op, 1)))) return 0; return 1; default: return 0; } } /* Return 1 if REG is clobbered in IN. Return 2 if REG is used in IN. Return 3 if REG is both used and clobbered in IN. Return 0 if neither. */ static int reg_clobbered_p (reg, in) rtx reg; rtx in; { register enum rtx_code code; if (in == 0) return 0; code = GET_CODE (in); if (code == SET || code == CLOBBER) { rtx dest = SET_DEST (in); int set = 0; int used = 0; while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG || GET_CODE (dest) == SIGN_EXTRACT || GET_CODE (dest) == ZERO_EXTRACT) dest = XEXP (dest, 0); if (dest == reg) set = 1; else if (GET_CODE (dest) == REG && refers_to_regno_p (REGNO (reg), REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)), SET_DEST (in), 0)) { set = 1; /* Anything that sets just part of the register is considered using as well as setting it. But note that a straight SUBREG of a single-word value clobbers the entire value. */ if (dest != SET_DEST (in) && ! (GET_CODE (SET_DEST (in)) == SUBREG || UNITS_PER_WORD >= GET_MODE_SIZE (GET_MODE (dest)))) used = 1; } if (code == SET) { if (set) used = refers_to_regno_p (REGNO (reg), REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)), SET_SRC (in), 0); else used = refers_to_regno_p (REGNO (reg), REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)), in, 0); } return set + used * 2; } if (refers_to_regno_p (REGNO (reg), REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)), in, 0)) return 2; return 0; } /* Return non-zero if OP can be written to without screwing up GCC's model of what's going on. It is assumed that this operand appears in the dest position of a SET insn in a conditional branch's delay slot. AFTER is the label to start looking from. */ int operand_clobbered_before_used_after (op, after) rtx op; rtx after; { /* Just experimenting. */ if (GET_CODE (op) == CC0) return 1; if (GET_CODE (op) == REG) { rtx insn; if (op == stack_pointer_rtx) return 0; /* Scan forward from the label, to see if the value of OP is clobbered before the first use. */ for (insn = NEXT_INSN (after); insn; insn = NEXT_INSN (insn)) { if (GET_CODE (insn) == NOTE) continue; if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN) { switch (reg_clobbered_p (op, PATTERN (insn))) { default: return 0; case 1: return 1; case 0: break; } } /* If we reach another label without clobbering OP, then we cannot safely write it here. */ else if (GET_CODE (insn) == CODE_LABEL) return 0; if (GET_CODE (insn) == JUMP_INSN) { if (condjump_p (insn)) return 0; /* This is a jump insn which has already been mangled. We can't tell what it does. */ if (GET_CODE (PATTERN (insn)) == PARALLEL) return 0; if (! JUMP_LABEL (insn)) return 0; /* Keep following jumps. */ insn = JUMP_LABEL (insn); } } return 1; } /* In both of these cases, the first insn executed for this op will be a orh whatever%h,%?r0,%?r31, which is tolerable. */ if (GET_CODE (op) == MEM) return (CONSTANT_ADDRESS_P (XEXP (op, 0))); return 0; } /* Return non-zero if this pattern, as a source to a "SET", is known to yield an instruction of unit size. */ int single_insn_src_p (op, mode) rtx op; enum machine_mode mode; { switch (GET_CODE (op)) { case CONST_INT: /* This is not always a single insn src, technically, but output_delayed_branch knows how to deal with it. */ return 1; case SYMBOL_REF: case CONST: /* This is not a single insn src, technically, but output_delayed_branch knows how to deal with it. */ return 1; case REG: return 1; case MEM: return 1; /* We never need to negate or complement constants. */ case NEG: return (mode != DFmode); case NOT: case ZERO_EXTEND: return 1; case PLUS: case MINUS: /* Detect cases that require multiple instructions. */ if (CONSTANT_P (XEXP (op, 1)) && !(GET_CODE (XEXP (op, 1)) == CONST_INT && SMALL_INT (XEXP (op, 1)))) return 0; case EQ: case NE: case LT: case GT: case LE: case GE: case LTU: case GTU: case LEU: case GEU: /* Not doing floating point, since they probably take longer than the branch slot they might fill. */ return (mode != SFmode && mode != DFmode); case AND: if (GET_CODE (XEXP (op, 1)) == NOT) { rtx arg = XEXP (XEXP (op, 1), 0); if (CONSTANT_P (arg) && !(GET_CODE (arg) == CONST_INT && (SMALL_INT (arg) || INTVAL (arg) & 0xffff == 0))) return 0; } case IOR: case XOR: /* Both small and round numbers take one instruction; others take two. */ if (CONSTANT_P (XEXP (op, 1)) && !(GET_CODE (XEXP (op, 1)) == CONST_INT && (SMALL_INT (XEXP (op, 1)) || INTVAL (XEXP (op, 1)) & 0xffff == 0))) return 0; case LSHIFT: case ASHIFT: case ASHIFTRT: case LSHIFTRT: return 1; case SUBREG: if (SUBREG_WORD (op) != 0) return 0; return single_insn_src_p (SUBREG_REG (op), mode); /* Not doing floating point, since they probably take longer than the branch slot they might fill. */ case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT: case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: return 0; default: return 0; } } /* Return non-zero only if OP is a register of mode MODE, or const0_rtx. */ int reg_or_0_operand (op, mode) rtx op; enum machine_mode mode; { return (op == const0_rtx || register_operand (op, mode) || op == CONST0_RTX (mode)); } /* Return truth value of whether OP can be used as an operands in a three address add/subtract insn (such as add %o1,7,%l2) of mode MODE. */ int arith_operand (op, mode) rtx op; enum machine_mode mode; { return (register_operand (op, mode) || (GET_CODE (op) == CONST_INT && SMALL_INT (op))); } /* Return 1 if OP is a valid first operand for a logical insn of mode MODE. */ int logic_operand (op, mode) rtx op; enum machine_mode mode; { return (register_operand (op, mode) || (GET_CODE (op) == CONST_INT && LOGIC_INT (op))); } /* Return 1 if OP is a valid first operand for a shift insn of mode MODE. */ int shift_operand (op, mode) rtx op; enum machine_mode mode; { return (register_operand (op, mode) || (GET_CODE (op) == CONST_INT)); } /* Return 1 if OP is a valid first operand for either a logical insn or an add insn of mode MODE. */ int compare_operand (op, mode) rtx op; enum machine_mode mode; { return (register_operand (op, mode) || (GET_CODE (op) == CONST_INT && SMALL_INT (op) && LOGIC_INT (op))); } /* Return truth value of whether OP can be used as the 5-bit immediate operand of a bte or btne insn. */ int bte_operand (op, mode) rtx op; enum machine_mode mode; { return (register_operand (op, mode) || (GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x20)); } /* Return 1 if OP is an indexed memory reference of mode MODE. */ int indexed_operand (op, mode) rtx op; enum machine_mode mode; { return (GET_CODE (op) == MEM && GET_MODE (op) == mode && GET_CODE (XEXP (op, 0)) == PLUS && GET_MODE (XEXP (op, 0)) == SImode && register_operand (XEXP (XEXP (op, 0), 0), SImode) && register_operand (XEXP (XEXP (op, 0), 1), SImode)); } /* Return 1 if OP is a suitable source operand for a load insn with mode MODE. */ int load_operand (op, mode) rtx op; enum machine_mode mode; { return (memory_operand (op, mode) || indexed_operand (op, mode)); } /* Return truth value of whether OP is a integer which fits the range constraining immediate operands in add/subtract insns. */ int small_int (op, mode) rtx op; enum machine_mode mode; { return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); } /* Return truth value of whether OP is a integer which fits the range constraining immediate operands in logic insns. */ int logic_int (op, mode) rtx op; enum machine_mode mode; { return (GET_CODE (op) == CONST_INT && LOGIC_INT (op)); } /* Test for a valid operand for a call instruction. Don't allow the arg pointer register or virtual regs since they may change into reg + const, which the patterns can't handle yet. */ int call_insn_operand (op, mode) rtx op; enum machine_mode mode; { if (GET_CODE (op) == MEM && (CONSTANT_ADDRESS_P (XEXP (op, 0)) || (GET_CODE (XEXP (op, 0)) == REG && XEXP (op, 0) != arg_pointer_rtx && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) return 1; return 0; } /* Return the best assembler insn template for moving operands[1] into operands[0] as a fullword. */ static char * singlemove_string (operands) rtx *operands; { if (GET_CODE (operands[0]) == MEM) { if (GET_CODE (operands[1]) != MEM) if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) { if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) && (cc_prev_status.flags & CC_HI_R31_ADJ) && cc_prev_status.mdep == XEXP (operands[0], 0))) { CC_STATUS_INIT; output_asm_insn ("orh %h0,%?r0,%?r31", operands); } cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; cc_status.mdep = XEXP (operands[0], 0); return "st.l %r1,%L0(%?r31)"; } else return "st.l %r1,%0"; else abort (); #if 0 { rtx xoperands[2]; cc_status.flags &= ~CC_F0_IS_0; xoperands[0] = gen_rtx (REG, SFmode, 32); xoperands[1] = operands[1]; output_asm_insn (singlemove_string (xoperands), xoperands); xoperands[1] = xoperands[0]; xoperands[0] = operands[0]; output_asm_insn (singlemove_string (xoperands), xoperands); return ""; } #endif } if (GET_CODE (operands[1]) == MEM) { if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) { if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) && (cc_prev_status.flags & CC_HI_R31_ADJ) && cc_prev_status.mdep == XEXP (operands[1], 0))) { CC_STATUS_INIT; output_asm_insn ("orh %h1,%?r0,%?r31", operands); } cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; cc_status.mdep = XEXP (operands[1], 0); return "ld.l %L1(%?r31),%0"; } return "ld.l %m1,%0"; } if (GET_CODE (operands[1]) == CONST_INT) { if (operands[1] == const0_rtx) return "mov %?r0,%0"; if((INTVAL (operands[1]) & 0xffff0000) == 0) return "or %L1,%?r0,%0"; if((INTVAL (operands[1]) & 0xffff8000) == 0xffff8000) return "adds %1,%?r0,%0"; if((INTVAL (operands[1]) & 0x0000ffff) == 0) return "orh %H1,%?r0,%0"; } return "mov %1,%0"; } /* Output assembler code to perform a doubleword move insn with operands OPERANDS. */ char * output_move_double (operands) rtx *operands; { enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1; rtx latehalf[2]; rtx addreg0 = 0, addreg1 = 0; int highest_first = 0; int no_addreg1_decrement = 0; /* First classify both operands. */ if (REG_P (operands[0])) optype0 = REGOP; else if (offsettable_memref_p (operands[0])) optype0 = OFFSOP; else if (GET_CODE (operands[0]) == MEM) optype0 = MEMOP; else optype0 = RNDOP; if (REG_P (operands[1])) optype1 = REGOP; else if (CONSTANT_P (operands[1])) optype1 = CNSTOP; else if (offsettable_memref_p (operands[1])) optype1 = OFFSOP; else if (GET_CODE (operands[1]) == MEM) optype1 = MEMOP; else optype1 = RNDOP; /* Check for the cases that the operand constraints are not supposed to allow to happen. Abort if we get one, because generating code for these cases is painful. */ if (optype0 == RNDOP || optype1 == RNDOP) abort (); /* If an operand is an unoffsettable memory ref, find a register we can increment temporarily to make it refer to the second word. */ if (optype0 == MEMOP) addreg0 = find_addr_reg (XEXP (operands[0], 0)); if (optype1 == MEMOP) addreg1 = find_addr_reg (XEXP (operands[1], 0)); /* ??? Perhaps in some cases move double words if there is a spare pair of floating regs. */ /* Ok, we can do one word at a time. Normally we do the low-numbered word first, but if either operand is autodecrementing then we do the high-numbered word first. In either case, set up in LATEHALF the operands to use for the high-numbered word and in some cases alter the operands in OPERANDS to be suitable for the low-numbered word. */ if (optype0 == REGOP) latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); else if (optype0 == OFFSOP) latehalf[0] = adj_offsettable_operand (operands[0], 4); else latehalf[0] = operands[0]; if (optype1 == REGOP) latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); else if (optype1 == OFFSOP) latehalf[1] = adj_offsettable_operand (operands[1], 4); else if (optype1 == CNSTOP) { if (GET_CODE (operands[1]) == CONST_DOUBLE) split_double (operands[1], &operands[1], &latehalf[1]); else if (CONSTANT_P (operands[1])) latehalf[1] = const0_rtx; } else latehalf[1] = operands[1]; /* If the first move would clobber the source of the second one, do them in the other order. RMS says "This happens only for registers; such overlap can't happen in memory unless the user explicitly sets it up, and that is an undefined circumstance." but it happens on the sparc when loading parameter registers, so I am going to define that circumstance, and make it work as expected. */ if (optype0 == REGOP && optype1 == REGOP && REGNO (operands[0]) == REGNO (latehalf[1])) { CC_STATUS_PARTIAL_INIT; /* Make any unoffsettable addresses point at high-numbered word. */ if (addreg0) output_asm_insn ("adds 0x4,%0,%0", &addreg0); if (addreg1) output_asm_insn ("adds 0x4,%0,%0", &addreg1); /* Do that word. */ output_asm_insn (singlemove_string (latehalf), latehalf); /* Undo the adds we just did. */ if (addreg0) output_asm_insn ("adds -0x4,%0,%0", &addreg0); if (addreg1) output_asm_insn ("adds -0x4,%0,%0", &addreg1); /* Do low-numbered word. */ return singlemove_string (operands); } else if (optype0 == REGOP && optype1 != REGOP && reg_overlap_mentioned_p (operands[0], operands[1])) { /* If both halves of dest are used in the src memory address, add the two regs and put them in the low reg (operands[0]). Then it works to load latehalf first. */ if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)) && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0))) { rtx xops[2]; xops[0] = latehalf[0]; xops[1] = operands[0]; output_asm_insn ("adds %1,%0,%1", xops); operands[1] = gen_rtx (MEM, DImode, operands[0]); latehalf[1] = adj_offsettable_operand (operands[1], 4); addreg1 = 0; highest_first = 1; } /* Only one register in the dest is used in the src memory address, and this is the first register of the dest, so we want to do the late half first here also. */ else if (! reg_mentioned_p (latehalf[0], XEXP (operands[1], 0))) highest_first = 1; /* Only one register in the dest is used in the src memory address, and this is the second register of the dest, so we want to do the late half last. If addreg1 is set, and addreg1 is the same register as latehalf, then we must suppress the trailing decrement, because it would clobber the value just loaded. */ else if (addreg1 && reg_mentioned_p (addreg1, latehalf[0])) no_addreg1_decrement = 1; } /* Normal case: do the two words, low-numbered first. Overlap case (highest_first set): do high-numbered word first. */ if (! highest_first) output_asm_insn (singlemove_string (operands), operands); CC_STATUS_PARTIAL_INIT; /* Make any unoffsettable addresses point at high-numbered word. */ if (addreg0) output_asm_insn ("adds 0x4,%0,%0", &addreg0); if (addreg1) output_asm_insn ("adds 0x4,%0,%0", &addreg1); /* Do that word. */ output_asm_insn (singlemove_string (latehalf), latehalf); /* Undo the adds we just did. */ if (addreg0) output_asm_insn ("adds -0x4,%0,%0", &addreg0); if (addreg1 && !no_addreg1_decrement) output_asm_insn ("adds -0x4,%0,%0", &addreg1); if (highest_first) output_asm_insn (singlemove_string (operands), operands); return ""; } char * output_fp_move_double (operands) rtx *operands; { /* If the source operand is any sort of zero, use f0 instead. */ if (operands[1] == CONST0_RTX (GET_MODE (operands[1]))) operands[1] = gen_rtx (REG, DFmode, F0_REGNUM); if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) return "fmov.dd %1,%0"; if (GET_CODE (operands[1]) == REG) { output_asm_insn ("ixfr %1,%0", operands); operands[0] = gen_rtx (REG, VOIDmode, REGNO (operands[0]) + 1); operands[1] = gen_rtx (REG, VOIDmode, REGNO (operands[1]) + 1); return "ixfr %1,%0"; } if (operands[1] == CONST0_RTX (DFmode)) return "fmov.dd f0,%0"; if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) { if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) && (cc_prev_status.flags & CC_HI_R31_ADJ) && cc_prev_status.mdep == XEXP (operands[1], 0))) { CC_STATUS_INIT; output_asm_insn ("orh %h1,%?r0,%?r31", operands); } cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; cc_status.mdep = XEXP (operands[1], 0); return "fld.d %L1(%?r31),%0"; } return "fld.d %1,%0"; } else if (FP_REG_P (operands[1])) { if (GET_CODE (operands[0]) == REG) { output_asm_insn ("fxfr %1,%0", operands); operands[0] = gen_rtx (REG, VOIDmode, REGNO (operands[0]) + 1); operands[1] = gen_rtx (REG, VOIDmode, REGNO (operands[1]) + 1); return "fxfr %1,%0"; } if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) { if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) && (cc_prev_status.flags & CC_HI_R31_ADJ) && cc_prev_status.mdep == XEXP (operands[0], 0))) { CC_STATUS_INIT; output_asm_insn ("orh %h0,%?r0,%?r31", operands); } cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; cc_status.mdep = XEXP (operands[0], 0); return "fst.d %1,%L0(%?r31)"; } return "fst.d %1,%0"; } else abort (); /* NOTREACHED */ return NULL; } /* Return a REG that occurs in ADDR with coefficient 1. ADDR can be effectively incremented by incrementing REG. */ static rtx find_addr_reg (addr) rtx addr; { while (GET_CODE (addr) == PLUS) { if (GET_CODE (XEXP (addr, 0)) == REG) addr = XEXP (addr, 0); else if (GET_CODE (XEXP (addr, 1)) == REG) addr = XEXP (addr, 1); else if (CONSTANT_P (XEXP (addr, 0))) addr = XEXP (addr, 1); else if (CONSTANT_P (XEXP (addr, 1))) addr = XEXP (addr, 0); else abort (); } if (GET_CODE (addr) == REG) return addr; abort (); /* NOTREACHED */ return NULL; } /* Return a template for a load instruction with mode MODE and arguments from the string ARGS. This string is in static storage. */ static char * load_opcode (mode, args, reg) enum machine_mode mode; char *args; rtx reg; { static char buf[30]; char *opcode; switch (mode) { case QImode: opcode = "ld.b"; break; case HImode: opcode = "ld.s"; break; case SImode: case SFmode: if (FP_REG_P (reg)) opcode = "fld.l"; else opcode = "ld.l"; break; case DImode: if (!FP_REG_P (reg)) abort (); case DFmode: opcode = "fld.d"; break; default: abort (); } sprintf (buf, "%s %s", opcode, args); return buf; } /* Return a template for a store instruction with mode MODE and arguments from the string ARGS. This string is in static storage. */ static char * store_opcode (mode, args, reg) enum machine_mode mode; char *args; rtx reg; { static char buf[30]; char *opcode; switch (mode) { case QImode: opcode = "st.b"; break; case HImode: opcode = "st.s"; break; case SImode: case SFmode: if (FP_REG_P (reg)) opcode = "fst.l"; else opcode = "st.l"; break; case DImode: if (!FP_REG_P (reg)) abort (); case DFmode: opcode = "fst.d"; break; default: abort (); } sprintf (buf, "%s %s", opcode, args); return buf; } /* Output a store-in-memory whose operands are OPERANDS[0,1]. OPERANDS[0] is a MEM, and OPERANDS[1] is a reg or zero. This function returns a template for an insn. This is in static storage. It may also output some insns directly. It may alter the values of operands[0] and operands[1]. */ char * output_store (operands) rtx *operands; { enum machine_mode mode = GET_MODE (operands[0]); rtx address = XEXP (operands[0], 0); char *string; cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; cc_status.mdep = address; if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) && (cc_prev_status.flags & CC_HI_R31_ADJ) && address == cc_prev_status.mdep)) { CC_STATUS_INIT; output_asm_insn ("orh %h0,%?r0,%?r31", operands); cc_prev_status.mdep = address; } /* Store zero in two parts when appropriate. */ if (mode == DFmode && operands[1] == CONST0_RTX (DFmode)) return store_opcode (DFmode, "%r1,%L0(%?r31)", operands[1]); /* Code below isn't smart enough to move a doubleword in two parts, so use output_move_double to do that in the cases that require it. */ if ((mode == DImode || mode == DFmode) && ! FP_REG_P (operands[1])) return output_move_double (operands); return store_opcode (mode, "%r1,%L0(%?r31)", operands[1]); } /* Output a load-from-memory whose operands are OPERANDS[0,1]. OPERANDS[0] is a reg, and OPERANDS[1] is a mem. This function returns a template for an insn. This is in static storage. It may also output some insns directly. It may alter the values of operands[0] and operands[1]. */ char * output_load (operands) rtx *operands; { enum machine_mode mode = GET_MODE (operands[0]); rtx address = XEXP (operands[1], 0); /* We don't bother trying to see if we know %hi(address). This is because we are doing a load, and if we know the %hi value, we probably also know that value in memory. */ cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; cc_status.mdep = address; if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) && (cc_prev_status.flags & CC_HI_R31_ADJ) && address == cc_prev_status.mdep && cc_prev_status.mdep == cc_status.mdep)) { CC_STATUS_INIT; output_asm_insn ("orh %h1,%?r0,%?r31", operands); cc_prev_status.mdep = address; } /* Code below isn't smart enough to move a doubleword in two parts, so use output_move_double to do that in the cases that require it. */ if ((mode == DImode || mode == DFmode) && ! FP_REG_P (operands[0])) return output_move_double (operands); return load_opcode (mode, "%L1(%?r31),%0", operands[0]); } #if 0 /* Load the address specified by OPERANDS[3] into the register specified by OPERANDS[0]. OPERANDS[3] may be the result of a sum, hence it could either be: (1) CONST (2) REG (2) REG + CONST_INT (3) REG + REG + CONST_INT (4) REG + REG (special case of 3). Note that (3) is not a legitimate address. All cases are handled here. */ void output_load_address (operands) rtx *operands; { rtx base, offset; if (CONSTANT_P (operands[3])) { output_asm_insn ("mov %3,%0", operands); return; } if (REG_P (operands[3])) { if (REGNO (operands[0]) != REGNO (operands[3])) output_asm_insn ("shl %?r0,%3,%0", operands); return; } if (GET_CODE (operands[3]) != PLUS) abort (); base = XEXP (operands[3], 0); offset = XEXP (operands[3], 1); if (GET_CODE (base) == CONST_INT) { rtx tmp = base; base = offset; offset = tmp; } if (GET_CODE (offset) != CONST_INT) { /* Operand is (PLUS (REG) (REG)). */ base = operands[3]; offset = const0_rtx; } if (REG_P (base)) { operands[6] = base; operands[7] = offset; CC_STATUS_PARTIAL_INIT; if (SMALL_INT (offset)) output_asm_insn ("adds %7,%6,%0", operands); else output_asm_insn ("mov %7,%0\n\tadds %0,%6,%0", operands); } else if (GET_CODE (base) == PLUS) { operands[6] = XEXP (base, 0); operands[7] = XEXP (base, 1); operands[8] = offset; CC_STATUS_PARTIAL_INIT; if (SMALL_INT (offset)) output_asm_insn ("adds %6,%7,%0\n\tadds %8,%0,%0", operands); else output_asm_insn ("mov %8,%0\n\tadds %0,%6,%0\n\tadds %0,%7,%0", operands); } else abort (); } #endif /* Output code to place a size count SIZE in register REG. Because block moves are pipelined, we don't include the first element in the transfer of SIZE to REG. For this, we subtract ALIGN. (Actually, I think it is not right to subtract on this machine, so right now we don't.) */ static void output_size_for_block_move (size, reg, align) rtx size, reg, align; { rtx xoperands[3]; xoperands[0] = reg; xoperands[1] = size; xoperands[2] = align; #if 1 cc_status.flags &= ~ CC_KNOW_HI_R31; output_asm_insn (singlemove_string (xoperands), xoperands); #else if (GET_CODE (size) == REG) output_asm_insn ("sub %2,%1,%0", xoperands); else { xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (size) - INTVAL (align)); cc_status.flags &= ~ CC_KNOW_HI_R31; output_asm_insn ("mov %1,%0", xoperands); } #endif } /* Emit code to perform a block move. OPERANDS[0] is the destination. OPERANDS[1] is the source. OPERANDS[2] is the size. OPERANDS[3] is the known safe alignment. OPERANDS[4..6] are pseudos we can safely clobber as temps. */ char * output_block_move (operands) rtx *operands; { /* A vector for our computed operands. Note that load_output_address makes use of (and can clobber) up to the 8th element of this vector. */ rtx xoperands[10]; rtx zoperands[10]; static int movstrsi_label = 0; int i, j; rtx temp1 = operands[4]; rtx alignrtx = operands[3]; int align = INTVAL (alignrtx); int chunk_size; xoperands[0] = operands[0]; xoperands[1] = operands[1]; xoperands[2] = temp1; /* We can't move more than four bytes at a time because we have only one register to move them through. */ if (align > 4) { align = 4; alignrtx = gen_rtx (CONST_INT, VOIDmode, 4); } /* Recognize special cases of block moves. These occur when GNU C++ is forced to treat something as BLKmode to keep it in memory, when its mode could be represented with something smaller. We cannot do this for global variables, since we don't know what pages they don't cross. Sigh. */ if (GET_CODE (operands[2]) == CONST_INT && ! CONSTANT_ADDRESS_P (operands[0]) && ! CONSTANT_ADDRESS_P (operands[1])) { int size = INTVAL (operands[2]); rtx op0 = xoperands[0]; rtx op1 = xoperands[1]; if ((align & 3) == 0 && (size & 3) == 0 && (size >> 2) <= 16) { if (memory_address_p (SImode, plus_constant (op0, size)) && memory_address_p (SImode, plus_constant (op1, size))) { cc_status.flags &= ~CC_KNOW_HI_R31; for (i = (size>>2)-1; i >= 0; i--) { xoperands[0] = plus_constant (op0, i * 4); xoperands[1] = plus_constant (op1, i * 4); output_asm_insn ("ld.l %a1,%?r31\n\tst.l %?r31,%a0", xoperands); } return ""; } } else if ((align & 1) == 0 && (size & 1) == 0 && (size >> 1) <= 16) { if (memory_address_p (HImode, plus_constant (op0, size)) && memory_address_p (HImode, plus_constant (op1, size))) { cc_status.flags &= ~CC_KNOW_HI_R31; for (i = (size>>1)-1; i >= 0; i--) { xoperands[0] = plus_constant (op0, i * 2); xoperands[1] = plus_constant (op1, i * 2); output_asm_insn ("ld.s %a1,%?r31\n\tst.s %?r31,%a0", xoperands); } return ""; } } else if (size <= 16) { if (memory_address_p (QImode, plus_constant (op0, size)) && memory_address_p (QImode, plus_constant (op1, size))) { cc_status.flags &= ~CC_KNOW_HI_R31; for (i = size-1; i >= 0; i--) { xoperands[0] = plus_constant (op0, i); xoperands[1] = plus_constant (op1, i); output_asm_insn ("ld.b %a1,%?r31\n\tst.b %?r31,%a0", xoperands); } return ""; } } } /* Since we clobber untold things, nix the condition codes. */ CC_STATUS_INIT; /* This is the size of the transfer. Either use the register which already contains the size, or use a free register (used by no operands). */ output_size_for_block_move (operands[2], operands[4], alignrtx); #if 0 /* Also emit code to decrement the size value by ALIGN. */ zoperands[0] = operands[0]; zoperands[3] = plus_constant (operands[0], align); output_load_address (zoperands); #endif /* Generate number for unique label. */ xoperands[3] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++); /* Calculate the size of the chunks we will be trying to move first. */ #if 0 if ((align & 3) == 0) chunk_size = 4; else if ((align & 1) == 0) chunk_size = 2; else #endif chunk_size = 1; /* Copy the increment (negative) to a register for bla insn. */ xoperands[4] = gen_rtx (CONST_INT, VOIDmode, - chunk_size); xoperands[5] = operands[5]; output_asm_insn ("adds %4,%?r0,%5", xoperands); /* Predecrement the loop counter. This happens again also in the `bla' instruction which precedes the loop, but we need to have it done two times before we enter the loop because of the bizarre semantics of the bla instruction. */ output_asm_insn ("adds %5,%2,%2", xoperands); /* Check for the case where the original count was less than or equal to zero. Avoid going through the loop at all if the original count was indeed less than or equal to zero. Note that we treat the count as if it were a signed 32-bit quantity here, rather than an unsigned one, even though we really shouldn't. We have to do this because of the semantics of the `ble' instruction, which assume that the count is a signed 32-bit value. Anyway, in practice it won't matter because nobody is going to try to do a memcpy() of more than half of the entire address space (i.e. 2 gigabytes) anyway. */ output_asm_insn ("bc .Le%3", xoperands); /* Make available a register which is a temporary. */ xoperands[6] = operands[6]; /* Now the actual loop. In xoperands, elements 1 and 0 are the input and output vectors. Element 2 is the loop index. Element 5 is the increment. */ output_asm_insn ("subs %1,%5,%1", xoperands); output_asm_insn ("bla %5,%2,.Lm%3", xoperands); output_asm_insn ("adds %0,%2,%6", xoperands); output_asm_insn ("\n.Lm%3:", xoperands); /* Label for bla above. */ output_asm_insn ("\n.Ls%3:", xoperands); /* Loop start label. */ output_asm_insn ("adds %5,%6,%6", xoperands); /* NOTE: The code here which is supposed to handle the cases where the sources and destinations are known to start on a 4 or 2 byte boundary are currently broken. They fail to do anything about the overflow bytes which might still need to be copied even after we have copied some number of words or halfwords. Thus, for now we use the lowest common denominator, i.e. the code which just copies some number of totally unaligned individual bytes. (See the calculation of chunk_size above. */ if (chunk_size == 4) { output_asm_insn ("ld.l %2(%1),%?r31", xoperands); output_asm_insn ("bla %5,%2,.Ls%3", xoperands); output_asm_insn ("st.l %?r31,8(%6)", xoperands); } else if (chunk_size == 2) { output_asm_insn ("ld.s %2(%1),%?r31", xoperands); output_asm_insn ("bla %5,%2,.Ls%3", xoperands); output_asm_insn ("st.s %?r31,4(%6)", xoperands); } else /* chunk_size == 1 */ { output_asm_insn ("ld.b %2(%1),%?r31", xoperands); output_asm_insn ("bla %5,%2,.Ls%3", xoperands); output_asm_insn ("st.b %?r31,2(%6)", xoperands); } output_asm_insn ("\n.Le%3:", xoperands); /* Here if count <= 0. */ return ""; } /* Output a delayed branch insn with the delay insn in its branch slot. The delayed branch insn template is in TEMPLATE, with operands OPERANDS. The insn in its delay slot is INSN. As a special case, since we know that all memory transfers are via ld/st insns, if we see a (MEM (SYMBOL_REF ...)) we divide the memory reference around the branch as orh ha%x,%?r0,%?r31 b ... ld/st l%x(%?r31),... As another special case, we handle loading (SYMBOL_REF ...) and other large constants around branches as well: orh h%x,%?r0,%0 b ... or l%x,%0,%1 */ char * output_delayed_branch (template, operands, insn) char *template; rtx *operands; rtx insn; { rtx src = XVECEXP (PATTERN (insn), 0, 1); rtx dest = XVECEXP (PATTERN (insn), 0, 0); /* See if we are doing some branch together with setting some register to some 32-bit value which does (or may) have some of the high-order 16 bits set. If so, we need to set the register in two stages. One stage must be done before the branch, and the other one can be done in the delay slot. */ if ( (GET_CODE (src) == CONST_INT && ((unsigned) INTVAL (src) & (unsigned) 0xffff0000) != (unsigned) 0) || (GET_CODE (src) == SYMBOL_REF) || (GET_CODE (src) == LABEL_REF) || (GET_CODE (src) == CONST)) { rtx xoperands[2]; xoperands[0] = dest; xoperands[1] = src; CC_STATUS_PARTIAL_INIT; /* Output the `orh' insn. */ output_asm_insn ("orh %H1,%?r0,%0", xoperands); /* Output the branch instruction next. */ output_asm_insn (template, operands); /* Now output the `or' insn. */ output_asm_insn ("or %L1,%0,%0", xoperands); } else if ((GET_CODE (src) == MEM && CONSTANT_ADDRESS_P (XEXP (src, 0))) || (GET_CODE (dest) == MEM && CONSTANT_ADDRESS_P (XEXP (dest, 0)))) { rtx xoperands[2]; char *split_template; xoperands[0] = dest; xoperands[1] = src; /* Output the `orh' insn. */ if (GET_CODE (src) == MEM) { if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) && (cc_prev_status.flags & CC_HI_R31_ADJ) && cc_prev_status.mdep == XEXP (operands[1], 0))) { CC_STATUS_INIT; output_asm_insn ("orh %h1,%?r0,%?r31", xoperands); } split_template = load_opcode (GET_MODE (dest), "%L1(%?r31),%0", dest); } else { if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) && (cc_prev_status.flags & CC_HI_R31_ADJ) && cc_prev_status.mdep == XEXP (operands[0], 0))) { CC_STATUS_INIT; output_asm_insn ("orh %h0,%?r0,%?r31", xoperands); } split_template = store_opcode (GET_MODE (dest), "%r1,%L0(%?r31)", src); } /* Output the branch instruction next. */ output_asm_insn (template, operands); /* Now output the load or store. No need to do a CC_STATUS_INIT, because we are branching anyway. */ output_asm_insn (split_template, xoperands); } else { int insn_code_number; rtx pat = gen_rtx (SET, VOIDmode, dest, src); rtx delay_insn = gen_rtx (INSN, VOIDmode, 0, 0, 0, pat, -1, 0, 0); int i; /* Output the branch instruction first. */ output_asm_insn (template, operands); /* Now recognize the insn which we put in its delay slot. We must do this after outputting the branch insn, since operands may just be a pointer to `recog_operand'. */ INSN_CODE (delay_insn) = insn_code_number = recog (pat, delay_insn); if (insn_code_number == -1) abort (); for (i = 0; i < insn_n_operands[insn_code_number]; i++) { if (GET_CODE (recog_operand[i]) == SUBREG) recog_operand[i] = alter_subreg (recog_operand[i]); } insn_extract (delay_insn); if (! constrain_operands (insn_code_number, 1)) fatal_insn_not_found (delay_insn); template = insn_template[insn_code_number]; if (template == 0) template = (*insn_outfun[insn_code_number]) (recog_operand, delay_insn); output_asm_insn (template, recog_operand); } CC_STATUS_INIT; return ""; } /* Output a newly constructed insn DELAY_INSN. */ char * output_delay_insn (delay_insn) rtx delay_insn; { char *template; int insn_code_number; int i; /* Now recognize the insn which we put in its delay slot. We must do this after outputting the branch insn, since operands may just be a pointer to `recog_operand'. */ insn_code_number = recog_memoized (delay_insn); if (insn_code_number == -1) abort (); /* Extract the operands of this delay insn. */ INSN_CODE (delay_insn) = insn_code_number; insn_extract (delay_insn); /* It is possible that this insn has not been properly scanned by final yet. If this insn's operands don't appear in the peephole's actual operands, then they won't be fixed up by final, so we make sure they get fixed up here. -- This is a kludge. */ for (i = 0; i < insn_n_operands[insn_code_number]; i++) { if (GET_CODE (recog_operand[i]) == SUBREG) recog_operand[i] = alter_subreg (recog_operand[i]); } #ifdef REGISTER_CONSTRAINTS if (! constrain_operands (insn_code_number)) abort (); #endif cc_prev_status = cc_status; /* Update `cc_status' for this instruction. The instruction's output routine may change it further. If the output routine for a jump insn needs to depend on the cc status, it should look at cc_prev_status. */ NOTICE_UPDATE_CC (PATTERN (delay_insn), delay_insn); /* Now get the template for what this insn would have been, without the branch. */ template = insn_template[insn_code_number]; if (template == 0) template = (*insn_outfun[insn_code_number]) (recog_operand, delay_insn); output_asm_insn (template, recog_operand); return ""; } /* Special routine to convert an SFmode value represented as a CONST_DOUBLE into its equivalent unsigned long bit pattern. We convert the value from a double precision floating-point value to single precision first, and thence to a bit-wise equivalent unsigned long value. This routine is used when generating an immediate move of an SFmode value directly into a general register because the svr4 assembler doesn't grok floating literals in instruction operand contexts. */ unsigned long sfmode_constant_to_ulong (x) rtx x; { REAL_VALUE_TYPE d; union { float f; unsigned long i; } u2; if (GET_CODE (x) != CONST_DOUBLE || GET_MODE (x) != SFmode) abort (); #if TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT error IEEE emulation needed #endif REAL_VALUE_FROM_CONST_DOUBLE (d, x); u2.f = d; return u2.i; } /* This function generates the assembly code for function entry. The macro FUNCTION_PROLOGUE in i860.h is defined to call this function. ASM_FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. Refer to the array `regs_ever_live' to determine which registers to save; `regs_ever_live[I]' is nonzero if register number I is ever used in the function. This macro is responsible for knowing which registers should not be saved even if used. NOTE: `frame_lower_bytes' is the count of bytes which will lie between the new `fp' value and the new `sp' value after the prologue is done. `frame_upper_bytes' is the count of bytes that will lie between the new `fp' and the *old* `sp' value after the new `fp' is setup (in the prologue). The upper part of each frame always includes at least 2 words (8 bytes) to hold the saved frame pointer and the saved return address. The svr4 ABI for the i860 now requires that the values of the stack pointer and frame pointer registers be kept aligned to 16-byte boundaries at all times. We obey that restriction here. The svr4 ABI for the i860 is entirely vague when it comes to specifying exactly where the "preserved" registers should be saved. The native svr4 C compiler I now have doesn't help to clarify the requirements very much because it is plainly out-of-date and non-ABI-compliant (in at least one important way, i.e. how it generates function epilogues). The native svr4 C compiler saves the "preserved" registers (i.e. r4-r15 and f2-f7) in the lower part of a frame (i.e. at negative offsets from the frame pointer). Previous versions of GCC also saved the "preserved" registers in the "negative" part of the frame, but they saved them using positive offsets from the (adjusted) stack pointer (after it had been adjusted to allocate space for the new frame). That's just plain wrong because if the current function calls alloca(), the stack pointer will get moved, and it will be impossible to restore the registers properly again after that. Both compilers handled parameter registers (i.e. r16-r27 and f8-f15) by copying their values either into various "preserved" registers or into stack slots in the lower part of the current frame (as seemed appropriate, depending upon subsequent usage of these values). Here we want to save the preserved registers at some offset from the frame pointer register so as to avoid any possible problems arising from calls to alloca(). We can either save them at small positive offsets from the frame pointer, or at small negative offsets from the frame pointer. If we save them at small negative offsets from the frame pointer (i.e. in the lower part of the frame) then we must tell the rest of GCC (via STARTING_FRAME_OFFSET) exactly how many bytes of space we plan to use in the lower part of the frame for this purpose. Since other parts of the compiler reference the value of STARTING_FRAME_OFFSET long before final() calls this function, we would have to go ahead and assume the worst-case storage requirements for saving all of the "preserved" registers (and use that number, i.e. `80', to define STARTING_FRAME_OFFSET) if we wanted to save them in the lower part of the frame. That could potentially be very wasteful, and that wastefulness could really hamper people compiling for embedded i860 targets with very tight limits on stack space. Thus, we choose here to save the preserved registers in the upper part of the frame, so that we can decide at the very last minute how much (or how little) space we must allocate for this purpose. To satisfy the needs of the svr4 ABI "tdesc" scheme, preserved registers must always be saved so that the saved values of registers with higher numbers are at higher addresses. We obey that restriction here. There are two somewhat different ways that you can generate prologues here... i.e. pedantically ABI-compliant, and the "other" way. The "other" way is more consistent with what is currently generated by the "native" svr4 C compiler for the i860. That's important if you want to use the current (as of 8/91) incarnation of svr4 SDB for the i860. The SVR4 SDB for the i860 insists on having function prologues be non-ABI-compliant! To get fully ABI-compliant prologues, define I860_STRICT_ABI_PROLOGUES in the i860svr4.h file. (By default this is *not* defined). The differences between the ABI-compliant and non-ABI-compliant prologues are that (a) the ABI version seems to require the use of *signed* (rather than unsigned) adds and subtracts, and (b) the ordering of the various steps (e.g. saving preserved registers, saving the return address, setting up the new frame pointer value) is different. For strict ABI compliance, it seems to be the case that the very last thing that is supposed to happen in the prologue is getting the frame pointer set to its new value (but only after everything else has already been properly setup). We do that here, but only if the symbol I860_STRICT_ABI_PROLOGUES is defined. */ #ifndef STACK_ALIGNMENT #define STACK_ALIGNMENT 16 #endif extern char call_used_regs[]; extern int leaf_function_p (); char *current_function_original_name; static int must_preserve_r1; static unsigned must_preserve_bytes; void function_prologue (asm_file, local_bytes) register FILE *asm_file; register unsigned local_bytes; { register unsigned frame_lower_bytes; register unsigned frame_upper_bytes; register unsigned total_fsize; register unsigned preserved_reg_bytes = 0; register unsigned i; register unsigned preserved_so_far = 0; must_preserve_r1 = (optimize < 2 || ! leaf_function_p ()); must_preserve_bytes = 4 + (must_preserve_r1 ? 4 : 0); /* Count registers that need preserving. Ignore r0. It never needs preserving. */ for (i = 1; i < FIRST_PSEUDO_REGISTER; i++) { if (regs_ever_live[i] && ! call_used_regs[i]) preserved_reg_bytes += 4; } /* Round-up the frame_lower_bytes so that it's a multiple of 16. */ frame_lower_bytes = (local_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT; /* The upper part of each frame will contain the saved fp, the saved r1, and stack slots for all of the other "preserved" registers that we find we will need to save & restore. */ frame_upper_bytes = must_preserve_bytes + preserved_reg_bytes; /* Round-up the frame_upper_bytes so that it's a multiple of 16. */ frame_upper_bytes = (frame_upper_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT; total_fsize = frame_upper_bytes + frame_lower_bytes; #ifndef I860_STRICT_ABI_PROLOGUES /* There are two kinds of function prologues. You use the "small" version if the total frame size is small enough so that it can fit into an immediate 16-bit value in one instruction. Otherwise, you use the "large" version of the function prologue. */ if (total_fsize > 0x7fff) { /* Adjust the stack pointer. The ABI sez to do this using `adds', but the native C compiler on svr4 uses `addu'. */ fprintf (asm_file, "\taddu -%d,%ssp,%ssp\n", frame_upper_bytes, i860_reg_prefix, i860_reg_prefix); /* Save the old frame pointer. */ fprintf (asm_file, "\tst.l %sfp,0(%ssp)\n", i860_reg_prefix, i860_reg_prefix); /* Setup the new frame pointer. The ABI sez to do this after preserving registers (using adds), but that's not what the native C compiler on svr4 does. */ fprintf (asm_file, "\taddu 0,%ssp,%sfp\n", i860_reg_prefix, i860_reg_prefix); /* Get the value of frame_lower_bytes into r31. */ fprintf (asm_file, "\torh %d,%sr0,%sr31\n", frame_lower_bytes >> 16, i860_reg_prefix, i860_reg_prefix); fprintf (asm_file, "\tor %d,%sr31,%sr31\n", frame_lower_bytes & 0xffff, i860_reg_prefix, i860_reg_prefix); /* Now re-adjust the stack pointer using the value in r31. The ABI sez to do this with `subs' but SDB may prefer `subu'. */ fprintf (asm_file, "\tsubu %ssp,%sr31,%ssp\n", i860_reg_prefix, i860_reg_prefix, i860_reg_prefix); /* Preserve registers. The ABI sez to do this before setting up the new frame pointer, but that's not what the native C compiler on svr4 does. */ for (i = 1; i < 32; i++) if (regs_ever_live[i] && ! call_used_regs[i]) fprintf (asm_file, "\tst.l %s%s,%d(%sfp)\n", i860_reg_prefix, reg_names[i], must_preserve_bytes + (4 * preserved_so_far++), i860_reg_prefix); for (i = 32; i < 64; i++) if (regs_ever_live[i] && ! call_used_regs[i]) fprintf (asm_file, "\tfst.l %s%s,%d(%sfp)\n", i860_reg_prefix, reg_names[i], must_preserve_bytes + (4 * preserved_so_far++), i860_reg_prefix); /* Save the return address. */ if (must_preserve_r1) fprintf (asm_file, "\tst.l %sr1,4(%sfp)\n", i860_reg_prefix, i860_reg_prefix); } else { /* Adjust the stack pointer. The ABI sez to do this using `adds', but the native C compiler on svr4 uses `addu'. */ fprintf (asm_file, "\taddu -%d,%ssp,%ssp\n", total_fsize, i860_reg_prefix, i860_reg_prefix); /* Save the old frame pointer. */ fprintf (asm_file, "\tst.l %sfp,%d(%ssp)\n", i860_reg_prefix, frame_lower_bytes, i860_reg_prefix); /* Setup the new frame pointer. The ABI sez to do this after preserving registers and after saving the return address, (and its saz to do this using adds), but that's not what the native C compiler on svr4 does. */ fprintf (asm_file, "\taddu %d,%ssp,%sfp\n", frame_lower_bytes, i860_reg_prefix, i860_reg_prefix); /* Preserve registers. The ABI sez to do this before setting up the new frame pointer, but that's not what the native compiler on svr4 does. */ for (i = 1; i < 32; i++) if (regs_ever_live[i] && ! call_used_regs[i]) fprintf (asm_file, "\tst.l %s%s,%d(%sfp)\n", i860_reg_prefix, reg_names[i], must_preserve_bytes + (4 * preserved_so_far++), i860_reg_prefix); for (i = 32; i < 64; i++) if (regs_ever_live[i] && ! call_used_regs[i]) fprintf (asm_file, "\tfst.l %s%s,%d(%sfp)\n", i860_reg_prefix, reg_names[i], must_preserve_bytes + (4 * preserved_so_far++), i860_reg_prefix); /* Save the return address. The ABI sez to do this earlier, and also via an offset from %sp, but the native C compiler on svr4 does it later (i.e. now) and uses an offset from %fp. */ if (must_preserve_r1) fprintf (asm_file, "\tst.l %sr1,4(%sfp)\n", i860_reg_prefix, i860_reg_prefix); } #else /* defined(I860_STRICT_ABI_PROLOGUES) */ /* There are two kinds of function prologues. You use the "small" version if the total frame size is small enough so that it can fit into an immediate 16-bit value in one instruction. Otherwise, you use the "large" version of the function prologue. */ if (total_fsize > 0x7fff) { /* Adjust the stack pointer (thereby allocating a new frame). */ fprintf (asm_file, "\tadds -%d,%ssp,%ssp\n", frame_upper_bytes, i860_reg_prefix, i860_reg_prefix); /* Save the caller's frame pointer. */ fprintf (asm_file, "\tst.l %sfp,0(%ssp)\n", i860_reg_prefix, i860_reg_prefix); /* Save return address. */ if (must_preserve_r1) fprintf (asm_file, "\tst.l %sr1,4(%ssp)\n", i860_reg_prefix, i860_reg_prefix); /* Get the value of frame_lower_bytes into r31 for later use. */ fprintf (asm_file, "\torh %d,%sr0,%sr31\n", frame_lower_bytes >> 16, i860_reg_prefix, i860_reg_prefix); fprintf (asm_file, "\tor %d,%sr31,%sr31\n", frame_lower_bytes & 0xffff, i860_reg_prefix, i860_reg_prefix); /* Now re-adjust the stack pointer using the value in r31. */ fprintf (asm_file, "\tsubs %ssp,%sr31,%ssp\n", i860_reg_prefix, i860_reg_prefix, i860_reg_prefix); /* Pre-compute value to be used as the new frame pointer. */ fprintf (asm_file, "\tadds %ssp,%sr31,%sr31\n", i860_reg_prefix, i860_reg_prefix, i860_reg_prefix); /* Preserve registers. */ for (i = 1; i < 32; i++) if (regs_ever_live[i] && ! call_used_regs[i]) fprintf (asm_file, "\tst.l %s%s,%d(%sr31)\n", i860_reg_prefix, reg_names[i], must_preserve_bytes + (4 * preserved_so_far++), i860_reg_prefix); for (i = 32; i < 64; i++) if (regs_ever_live[i] && ! call_used_regs[i]) fprintf (asm_file, "\tfst.l %s%s,%d(%sr31)\n", i860_reg_prefix, reg_names[i], must_preserve_bytes + (4 * preserved_so_far++), i860_reg_prefix); /* Actually set the new value of the frame pointer. */ fprintf (asm_file, "\tmov %sr31,%sfp\n", i860_reg_prefix, i860_reg_prefix); } else { /* Adjust the stack pointer. */ fprintf (asm_file, "\tadds -%d,%ssp,%ssp\n", total_fsize, i860_reg_prefix, i860_reg_prefix); /* Save the caller's frame pointer. */ fprintf (asm_file, "\tst.l %sfp,%d(%ssp)\n", i860_reg_prefix, frame_lower_bytes, i860_reg_prefix); /* Save the return address. */ if (must_preserve_r1) fprintf (asm_file, "\tst.l %sr1,%d(%ssp)\n", i860_reg_prefix, frame_lower_bytes + 4, i860_reg_prefix); /* Preserve registers. */ for (i = 1; i < 32; i++) if (regs_ever_live[i] && ! call_used_regs[i]) fprintf (asm_file, "\tst.l %s%s,%d(%ssp)\n", i860_reg_prefix, reg_names[i], frame_lower_bytes + must_preserve_bytes + (4 * preserved_so_far++), i860_reg_prefix); for (i = 32; i < 64; i++) if (regs_ever_live[i] && ! call_used_regs[i]) fprintf (asm_file, "\tfst.l %s%s,%d(%ssp)\n", i860_reg_prefix, reg_names[i], frame_lower_bytes + must_preserve_bytes + (4 * preserved_so_far++), i860_reg_prefix); /* Setup the new frame pointer. */ fprintf (asm_file, "\tadds %d,%ssp,%sfp\n", frame_lower_bytes, i860_reg_prefix, i860_reg_prefix); } #endif /* defined(I860_STRICT_ABI_PROLOGUES) */ #ifdef ASM_OUTPUT_PROLOGUE_SUFFIX ASM_OUTPUT_PROLOGUE_SUFFIX (asm_file); #endif /* defined(ASM_OUTPUT_PROLOGUE_SUFFIX) */ } /* This function generates the assembly code for function exit. The macro FUNCTION_EPILOGUE in i860.h is defined to call this function. ASM_FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. The function epilogue should not depend on the current stack pointer! It should use the frame pointer only. This is mandatory because of alloca; we also take advantage of it to omit stack adjustments before returning. Note that when we go to restore the preserved register values we must not try to address their slots by using offsets from the stack pointer. That's because the stack pointer may have been moved during the function execution due to a call to alloca(). Rather, we must restore all preserved registers via offsets from the frame pointer value. Note also that when the current frame is being "popped" (by adjusting the value of the stack pointer) on function exit, we must (for the sake of alloca) set the new value of the stack pointer based upon the current value of the frame pointer. We can't just add what we believe to be the (static) frame size to the stack pointer because if we did that, and alloca() had been called during this function, we would end up returning *without* having fully deallocated all of the space grabbed by alloca. If that happened, and a function containing one or more alloca() calls was called over and over again, then the stack would grow without limit! Finally note that the epilogues generated here are completely ABI compliant. They go out of their way to insure that the value in the frame pointer register is never less than the value in the stack pointer register. It's not clear why this relationship needs to be maintained at all times, but maintaining it only costs one extra instruction, so what the hell. */ /* This corresponds to a version 4 TDESC structure. Lower numbered versions successively omit the last word of the structure. We don't try to handle version 5 here. */ typedef struct TDESC_flags { int version:4; int reg_packing:1; int callable_block:1; int reserved:4; int fregs:6; /* fp regs 2-7 */ int iregs:16; /* regs 0-15 */ } TDESC_flags; typedef struct TDESC { TDESC_flags flags; int integer_reg_offset; /* same as must_preserve_bytes */ int floating_point_reg_offset; unsigned int positive_frame_size; /* same as frame_upper_bytes */ unsigned int negative_frame_size; /* same as frame_lower_bytes */ } TDESC; void function_epilogue (asm_file, local_bytes) register FILE *asm_file; register unsigned local_bytes; { register unsigned frame_upper_bytes; register unsigned frame_lower_bytes; register unsigned preserved_reg_bytes = 0; register unsigned i; register unsigned restored_so_far = 0; register unsigned int_restored; register unsigned mask; unsigned intflags=0; register TDESC_flags *flags = (TDESC_flags *) &intflags; flags->version = 4; flags->reg_packing = 1; flags->iregs = 8; /* old fp always gets saved */ /* Round-up the frame_lower_bytes so that it's a multiple of 16. */ frame_lower_bytes = (local_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT; /* Count the number of registers that were preserved in the prologue. Ignore r0. It is never preserved. */ for (i = 1; i < FIRST_PSEUDO_REGISTER; i++) { if (regs_ever_live[i] && ! call_used_regs[i]) preserved_reg_bytes += 4; } /* The upper part of each frame will contain only saved fp, the saved r1, and stack slots for all of the other "preserved" registers that we find we will need to save & restore. */ frame_upper_bytes = must_preserve_bytes + preserved_reg_bytes; /* Round-up frame_upper_bytes so that t is a multiple of 16. */ frame_upper_bytes = (frame_upper_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT; /* Restore all of the "preserved" registers that need restoring. */ mask = 2; for (i = 1; i < 32; i++, mask<<=1) if (regs_ever_live[i] && ! call_used_regs[i]) { fprintf (asm_file, "\tld.l %d(%sfp),%s%s\n", must_preserve_bytes + (4 * restored_so_far++), i860_reg_prefix, i860_reg_prefix, reg_names[i]); if (i > 3 && i < 16) flags->iregs |= mask; } int_restored = restored_so_far; mask = 1; for (i = 32; i < 64; i++) { if (regs_ever_live[i] && ! call_used_regs[i]) { fprintf (asm_file, "\tfld.l %d(%sfp),%s%s\n", must_preserve_bytes + (4 * restored_so_far++), i860_reg_prefix, i860_reg_prefix, reg_names[i]); if (i > 33 & i < 40) flags->fregs |= mask; } if (i > 33 && i < 40) mask<<=1; } /* Get the value we plan to use to restore the stack pointer into r31. */ fprintf (asm_file, "\tadds %d,%sfp,%sr31\n", frame_upper_bytes, i860_reg_prefix, i860_reg_prefix); /* Restore the return address and the old frame pointer. */ if (must_preserve_r1) { fprintf (asm_file, "\tld.l 4(%sfp),%sr1\n", i860_reg_prefix, i860_reg_prefix); flags->iregs |= 2; } fprintf (asm_file, "\tld.l 0(%sfp),%sfp\n", i860_reg_prefix, i860_reg_prefix); /* Return and restore the old stack pointer value. */ fprintf (asm_file, "\tbri %sr1\n\tmov %sr31,%ssp\n", i860_reg_prefix, i860_reg_prefix, i860_reg_prefix); #ifdef OUTPUT_TDESC /* Output an ABI-compliant TDESC entry */ if (! frame_lower_bytes) { flags->version--; if (! frame_upper_bytes) { flags->version--; if (restored_so_far == int_restored) /* No FP saves */ flags->version--; } } assemble_name(asm_file,current_function_original_name); fputs(".TDESC:\n", asm_file); fprintf(asm_file, "%s 0x%0x\n", ASM_LONG, intflags); fprintf(asm_file, "%s %d\n", ASM_LONG, int_restored ? must_preserve_bytes : 0); if (flags->version > 1) { fprintf(asm_file, "%s %d\n", ASM_LONG, (restored_so_far == int_restored) ? 0 : must_preserve_bytes + (4 * int_restored)); if (flags->version > 2) { fprintf(asm_file, "%s %d\n", ASM_LONG, frame_upper_bytes); if (flags->version > 3) fprintf(asm_file, "%s %d\n", ASM_LONG, frame_lower_bytes); } } tdesc_section(); fprintf(asm_file, "%s ", ASM_LONG); assemble_name(asm_file, current_function_original_name); fprintf(asm_file, "\n%s ", ASM_LONG); assemble_name(asm_file, current_function_original_name); fputs(".TDESC\n", asm_file); text_section(); #endif } gcc-2.5.8/config/i860/i860.h100444 22011 13 153027 5471401260 13624 0ustar kenneruser/* Definitions of target machine for GNU compiler, for Intel 860. Copyright (C) 1989, 1991, 1993 Free Software Foundation, Inc. Written by Richard Stallman (rms@ai.mit.edu). Hacked substantially by Ron Guilmette (rfg@ncd.com) to cater to the whims of the System V Release 4 assembler. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Note that some other tm.h files include this one and then override many of the definitions that relate to assembler syntax. */ /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Di860 -Dunix -Asystem(unix) -Asystem(svr4) -Acpu(i860) -Amachine(i860)" /* Print subsidiary information on the compiler version in use. */ #define TARGET_VERSION fprintf (stderr, " (i860)"); /* Run-time compilation parameters selecting different hardware subsets or supersets. On the i860, we have one: TARGET_XP. This option allows gcc to generate additional instructions available only on the newer i860 XP (but not on the older i860 XR). */ extern int target_flags; /* Nonzero if we should generate code to use the fpu. */ #define TARGET_XP (target_flags & 1) /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */ #define TARGET_SWITCHES \ { {"xp", 1}, \ {"noxp", -1}, \ {"xr", -1}, \ { "", TARGET_DEFAULT}} #define TARGET_DEFAULT 0 /* target machine storage layout */ /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. This is a moot question on the i860 due to the lack of bit-field insns. */ #define BITS_BIG_ENDIAN 0 /* Define this if most significant byte of a word is the lowest numbered. */ /* That is not true on i860 in the mode we will use. */ #define BYTES_BIG_ENDIAN 0 /* Define this if most significant word of a multiword number is the lowest numbered. */ /* For the i860 this goes with BYTES_BIG_ENDIAN. */ /* NOTE: GCC probably cannot support a big-endian i860 because GCC fundamentally assumes that the order of words in memory as the same as the order in registers. That's not true for the big-endian i860. The big-endian i860 isn't important enough to justify the trouble of changing this assumption. */ #define WORDS_BIG_ENDIAN 0 /* number of bits in an addressable storage unit */ #define BITS_PER_UNIT 8 /* Width in bits of a "word", which is the contents of a machine register. Note that this is not necessarily the width of data type `int'; if using 16-bit ints on a 68000, this would still be 32. But on a machine with 16-bit registers, this would be 16. */ #define BITS_PER_WORD 32 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 4 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ #define POINTER_SIZE 32 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ #define PARM_BOUNDARY 32 /* Boundary (in *bits*) on which stack pointer should be aligned. */ #define STACK_BOUNDARY 128 /* Allocation boundary (in *bits*) for the code of a function. */ #define FUNCTION_BOUNDARY 64 /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 32 /* Every structure's size must be a multiple of this. */ #define STRUCTURE_SIZE_BOUNDARY 8 /* Minimum size in bits of the largest boundary to which any and all fundamental data types supported by the hardware might need to be aligned. No data type wants to be aligned rounder than this. The i860 supports 128-bit (long double) floating point quantities, and the System V Release 4 i860 ABI requires these to be aligned to 16-byte (128-bit) boundaries. */ #define BIGGEST_ALIGNMENT 128 /* Set this nonzero if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 1 /* If bit field type is int, dont let it cross an int, and give entire struct the alignment of an int. */ #define PCC_BITFIELD_TYPE_MATTERS 1 /* Standard register usage. */ /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. i860 has 32 fullword registers and 32 floating point registers. */ #define FIRST_PSEUDO_REGISTER 64 /* 1 for registers that have pervasive standard uses and are not available for the register allocator. On the i860, this includes the always-0 registers and fp, sp, arg pointer, and the return address. Also r31, used for special purposes for constant addresses. */ #define FIXED_REGISTERS \ {1, 1, 1, 1, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 1, \ 1, 1, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0} /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. On the i860, these are r0-r3, r16-r31, f0, f1, and f16-f31. */ #define CALL_USED_REGISTERS \ {1, 1, 1, 1, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 0, 0, 0, 0, 0, 0, \ 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1} /* Try to get a non-preserved register before trying to get one we will have to preserve. Try to get an FP register only *after* trying to get a general register, because it is relatively expensive to move into or out of an FP register. */ #define REG_ALLOC_ORDER \ {31, 30, 29, 28, 27, 26, 25, 24, \ 23, 22, 21, 20, 19, 18, 17, 16, \ 15, 14, 13, 12, 11, 10, 9, 8, \ 7, 6, 5, 4, 3, 2, 1, 0, \ 63, 62, 61, 60, 59, 58, 57, 56, \ 55, 54, 53, 52, 51, 50, 49, 48, \ 47, 46, 45, 44, 43, 42, 41, 40, \ 39, 38, 37, 36, 35, 34, 33, 32} /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. On the i860, all registers hold 32 bits worth. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) #define REGNO_MODE_ALIGNED(REGNO, MODE) \ (((REGNO) % ((GET_MODE_UNIT_SIZE (MODE) + 3) / 4)) == 0) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On the i860, we allow anything to go into any registers, but we require any sort of value going into the FP registers to be properly aligned (based on its size) within the FP register set. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ (((REGNO) < 32) \ || (MODE) == VOIDmode || (MODE) == BLKmode \ || REGNO_MODE_ALIGNED (REGNO, MODE)) /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. */ /* I think that is not always true; alignment restrictions for doubles should not prevent tying them with singles. So try allowing that. On the other hand, don't let fixed and floating be tied; this restriction is not necessary, but may make better code. */ #define MODES_TIEABLE_P(MODE1, MODE2) \ ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ /* i860 pc isn't overloaded on a register that the compiler knows about. */ /* #define PC_REGNUM */ /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM 2 /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM 3 /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */ #define FRAME_POINTER_REQUIRED 1 /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM 28 /* Register in which static-chain is passed to a function. */ #define STATIC_CHAIN_REGNUM 29 /* Register in which address to store a structure value is passed to a function. */ #define STRUCT_VALUE_REGNUM 16 /* Register to use when a source of a floating-point zero is needed. */ #define F0_REGNUM 32 /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. One of the classes must always be named ALL_REGS and include all hard regs. If there is more than one class, another class must be named NO_REGS and contain no registers. The name GENERAL_REGS must be the name of a class (or an alias for another name such as ALL_REGS). This is the class of registers that is allowed by "g" or "r" in a register constraint. Also, registers outside this class are allocated only when instructions express preferences for them. The classes must be numbered in nondecreasing order; that is, a larger-numbered class must never be contained completely in a smaller-numbered class. For any two classes, it is very desirable that there be another class that represents their union. */ /* The i860 has two kinds of registers, hence four classes. */ enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" } /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS \ {{0, 0}, {0xffffffff, 0}, \ {0, 0xffffffff}, {0xffffffff, 0xffffffff}} /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ #define REGNO_REG_CLASS(REGNO) \ ((REGNO) >= 32 ? FP_REGS : GENERAL_REGS) /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS GENERAL_REGS #define BASE_REG_CLASS GENERAL_REGS /* Get reg_class from a letter such as appears in the machine description. */ #define REG_CLASS_FROM_LETTER(C) \ ((C) == 'f' ? FP_REGS : NO_REGS) /* The letters I, J, K, L and M in a register constraint string can be used to stand for particular ranges of immediate operands. This macro defines what the ranges are. C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. For the i860, `I' is used for the range of constants an add/subtract insn can actually contain. But not including -0x8000, since we need to negate the constant sometimes. `J' is used for the range which is just zero (since that is R0). `K' is used for the range allowed in bte. `L' is used for the range allowed in logical insns. */ #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x7fff) < 0xffff) #define LOGIC_INT(X) ((unsigned) INTVAL (X) < 0x10000) #define SMALL_INTVAL(X) ((unsigned) ((X) + 0x7fff) < 0xffff) #define LOGIC_INTVAL(X) ((unsigned) (X) < 0x10000) #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? ((unsigned) (VALUE) + 0x7fff) < 0xffff \ : (C) == 'J' ? (VALUE) == 0 \ : (C) == 'K' ? (unsigned) (VALUE) < 0x20 \ : (C) == 'L' ? (unsigned) (VALUE) < 0x10000 \ : 0) /* Return non-zero if the given VALUE is acceptable for the constraint letter C. For the i860, constraint letter 'G' permits only a floating-point zero value. */ #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'G' && CONST_DOUBLE_LOW ((VALUE)) == 0 \ && CONST_DOUBLE_HIGH ((VALUE)) == 0) /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. If we are trying to put an integer constant into some register, prefer an integer register to an FP register. If we are trying to put a non-zero floating-point constant into some register, use an integer register if the constant is SFmode and GENERAL_REGS is one of our options. Otherwise, put the constant into memory. When reloading something smaller than a word, use a general reg rather than an FP reg. */ #define PREFERRED_RELOAD_CLASS(X,CLASS) \ ((CLASS) == ALL_REGS && GET_CODE (X) == CONST_INT ? GENERAL_REGS \ : ((GET_MODE (X) == HImode || GET_MODE (X) == QImode) \ && (CLASS) == ALL_REGS) \ ? GENERAL_REGS \ : (GET_CODE (X) == CONST_DOUBLE \ && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ && ! CONST_DOUBLE_OK_FOR_LETTER_P (X, 'G')) \ ? ((CLASS) == ALL_REGS && GET_MODE (X) == SFmode ? GENERAL_REGS \ : (CLASS) == GENERAL_REGS && GET_MODE (X) == SFmode ? (CLASS) \ : NO_REGS) \ : (CLASS)) /* Return the register class of a scratch register needed to copy IN into a register in CLASS in MODE. If it can be done directly, NO_REGS is returned. */ #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \ ((CLASS) == FP_REGS && CONSTANT_P (IN) ? GENERAL_REGS : NO_REGS) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ /* On the i860, this is the size of MODE in words. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack makes the stack pointer a smaller address. */ #define STACK_GROWS_DOWNWARD /* Define this if the nominal address of the stack frame is at the high-address end of the local variables; that is, each additional local variable allocated goes at a more negative offset in the frame. */ #define FRAME_GROWS_DOWNWARD /* Offset within stack frame to start allocating local variables at. If FRAME_GROWS_DOWNWARD, this is the offset to the END of the first local allocated. Otherwise, it is the offset to the BEGINNING of the first local allocated. */ #define STARTING_FRAME_OFFSET 0 /* If we generate an insn to push BYTES bytes, this says how many the stack pointer really advances by. On the i860, don't define this because there are no push insns. */ /* #define PUSH_ROUNDING(BYTES) */ /* Offset of first parameter from the argument pointer register value. */ #define FIRST_PARM_OFFSET(FNDECL) 0 /* Value is the number of bytes of arguments automatically popped when returning from a subroutine call. FUNTYPE is the data type of the function (as a tree), or for a library call it is an identifier node for the subroutine name. SIZE is the number of bytes of arguments passed on the stack. */ #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0 /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */ /* On the i860, the value register depends on the mode. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ gen_rtx (REG, TYPE_MODE (VALTYPE), \ (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \ ? 40 : 16)) /* Define how to find the value returned by a library function assuming the value has mode MODE. */ #define LIBCALL_VALUE(MODE) \ gen_rtx (REG, MODE, \ (GET_MODE_CLASS ((MODE)) == MODE_FLOAT \ ? 40 : 16)) /* 1 if N is a possible register number for a function value as seen by the caller. */ #define FUNCTION_VALUE_REGNO_P(N) ((N) == 40 || (N) == 16) /* 1 if N is a possible register number for function argument passing. On the i860, these are r16-r27 and f8-f15. */ #define FUNCTION_ARG_REGNO_P(N) \ (((N) < 28 && (N) > 15) || ((N) < 48 && (N) >= 40)) /* Define a data type for recording info about an argument list during the scan of that argument list. This data type should hold all necessary information about the function itself and about the args processed so far, enough to enable macros such as FUNCTION_ARG to determine where the next arg should go. On the i860, we must count separately the number of general registers used and the number of float registers used. */ struct cumulative_args { int ints, floats; }; #define CUMULATIVE_ARGS struct cumulative_args /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. On the i860, the general-reg offset normally starts at 0, but starts at 4 bytes when the function gets a structure-value-address as an invisible first argument. */ #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ ((CUM).ints = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE ((FNTYPE))) \ ? 4 : 0), \ (CUM).floats = 0) /* Machine-specific subroutines of the following macros. */ #define CEILING(X,Y) (((X) + (Y) - 1) / (Y)) #define ROUNDUP(X,Y) (CEILING ((X), (Y)) * (Y)) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. (TYPE is null for libcalls where that information may not be available.) Floats, and doubleword ints, are returned in f regs; other ints, in r regs. Aggregates, even short ones, are passed in memory. */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE \ || TREE_CODE ((TYPE)) == UNION_TYPE) \ ? 0 \ : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode \ ? ((CUM).floats = (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) \ + ROUNDUP (GET_MODE_SIZE (MODE), 4))) \ : GET_MODE_CLASS ((MODE)) == MODE_INT \ ? ((CUM).ints = (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) \ + ROUNDUP (GET_MODE_SIZE (MODE), 4))) \ : 0) /* Determine where to put an argument to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. MODE is the argument's machine mode. TYPE is the data type of the argument (as a tree). This is null for libcalls where that information may not be available. CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called. NAMED is nonzero if this argument is a named parameter (otherwise it is an extra parameter matching an ellipsis). */ /* On the i860, the first 12 words of integer arguments go in r16-r27, and the first 8 words of floating arguments go in f8-f15. DImode values are treated as floats. */ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE \ || TREE_CODE ((TYPE)) == UNION_TYPE) \ ? 0 \ : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode \ ? (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) < 32 \ ? gen_rtx (REG, (MODE), \ 40+(ROUNDUP ((CUM).floats, \ GET_MODE_SIZE ((MODE))) \ / 4)) \ : 0) \ : GET_MODE_CLASS ((MODE)) == MODE_INT \ ? (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) < 48 \ ? gen_rtx (REG, (MODE), \ 16+(ROUNDUP ((CUM).ints, \ GET_MODE_SIZE ((MODE))) \ / 4)) \ : 0) \ : 0) /* For an arg passed partly in registers and partly in memory, this is the number of registers used. For args passed entirely in registers or entirely in memory, zero. */ #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 /* If defined, a C expression that gives the alignment boundary, in bits, of an argument with the specified mode and type. If it is not defined, `PARM_BOUNDARY' is used for all arguments. */ #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ (((TYPE) != 0) \ ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \ ? PARM_BOUNDARY \ : TYPE_ALIGN(TYPE)) \ : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \ ? PARM_BOUNDARY \ : GET_MODE_ALIGNMENT(MODE))) /* This macro generates the assembly code for function entry. FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. */ #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue ((FILE), (SIZE)) /* Output a no-op just before the beginning of the function, to ensure that there does not appear to be a delayed branch there. Such a thing would confuse interrupt recovery. */ #define ASM_OUTPUT_FUNCTION_PREFIX(FILE,NAME) \ fprintf (FILE, "\tnop\n") /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ #define FUNCTION_PROFILER(FILE, LABELNO) \ abort (); /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, the stack pointer does not matter. The value is tested only in functions that have frame pointers. No definition is equivalent to always zero. */ #define EXIT_IGNORE_STACK 1 /* This macro generates the assembly code for function exit. FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. The function epilogue should not depend on the current stack pointer! It should use the frame pointer only. This is mandatory because of alloca; we also take advantage of it to omit stack adjustments before returning. */ #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue ((FILE), (SIZE)) /* Store in the variable DEPTH the initial difference between the frame pointer reg contents and the stack pointer reg contents, as of the start of the function body. This depends on the layout of the fixed parts of the stack frame and on how registers are saved. On the i860, FRAME_POINTER_REQUIRED is always 1, so the definition of this macro doesn't matter. But it must be defined. */ #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ do { (DEPTH) = 0; } while (0) /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. */ /* On the i860, the trampoline contains five instructions: orh #TOP_OF_FUNCTION,r0,r31 or #BOTTOM_OF_FUNCTION,r31,r31 orh #TOP_OF_STATIC,r0,r29 bri r31 or #BOTTOM_OF_STATIC,r29,r29 */ #define TRAMPOLINE_TEMPLATE(FILE) \ { \ ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xec1f0000)); \ ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xe7ff0000)); \ ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xec1d0000)); \ ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4000f800)); \ ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xe7bd0000)); \ } /* Length in units of the trampoline for entering a nested function. */ #define TRAMPOLINE_SIZE 20 /* Emit RTL insns to initialize the variable parts of a trampoline. FNADDR is an RTX for the address of the function's pure code. CXT is an RTX for the static chain value for the function. Store hi function at +0, low function at +4, hi static at +8, low static at +16 */ #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ rtx cxt = force_reg (Pmode, CXT); \ rtx fn = force_reg (Pmode, FNADDR); \ rtx hi_cxt = expand_shift (RSHIFT_EXPR, SImode, cxt, \ size_int (16), 0, 0); \ rtx hi_fn = expand_shift (RSHIFT_EXPR, SImode, fn, \ size_int (16), 0, 0); \ emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 16)), \ gen_lowpart (HImode, cxt)); \ emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 4)), \ gen_lowpart (HImode, fn)); \ emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 8)), \ gen_lowpart (HImode, hi_cxt)); \ emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 0)), \ gen_lowpart (HImode, hi_fn)); \ } /* Addressing modes, and classification of registers for them. */ /* #define HAVE_POST_INCREMENT */ /* #define HAVE_POST_DECREMENT */ /* #define HAVE_PRE_DECREMENT */ /* #define HAVE_PRE_INCREMENT */ /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. */ #define REGNO_OK_FOR_INDEX_P(REGNO) \ ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) #define REGNO_OK_FOR_BASE_P(REGNO) \ ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) #define REGNO_OK_FOR_FP_P(REGNO) \ (((REGNO) ^ 0x20) < 32 || (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32) /* Now macros that check whether X is a register and also, strictly, whether it is in a specified class. These macros are specific to the i860, and may be used only in code for printing assembler insns and in conditions for define_optimization. */ /* 1 if X is an fp register. */ #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) /* Maximum number of registers that can appear in a valid memory address. */ #define MAX_REGS_PER_ADDRESS 2 /* Recognize any constant value that is a valid address. */ #define CONSTANT_ADDRESS_P(X) \ (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ || GET_CODE (X) == HIGH) /* Nonzero if the constant value X is a legitimate general operand. It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. On the Sparc, this is anything but a CONST_DOUBLE. Let's try permitting CONST_DOUBLEs and see what happens. */ #define LEGITIMATE_CONSTANT_P(X) 1 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. The usual definition accepts all pseudo regs; the other rejects them unless they have been allocated suitable hard regs. The symbol REG_OK_STRICT causes the latter definition to be used. Most source files want to accept pseudo regs in the hope that they will get allocated to the class that the insn wants them to be in. Source files for reload pass need to be strict. After reload, it makes no difference, since pseudo regs have been eliminated by then. */ #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 14) /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 14) #else /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) #endif /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. On the i860, the actual addresses must be REG+REG or REG+SMALLINT. But we can treat a SYMBOL_REF as legitimate if it is part of this function's constant-pool, because such addresses can actually be output as REG+SMALLINT. The displacement in an address must be a multiple of the alignment. Try making SYMBOL_REF (and other things which are CONSTANT_ADDRESS_P) a legitimate address, regardless. Because the only insns which can use memory are load or store insns, the added hair in the machine description is not that bad. It should also speed up the compiler by halving the number of insns it must manage for each (MEM (SYMBOL_REF ...)) involved. */ #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { if (GET_CODE (X) == REG) \ { if (REG_OK_FOR_BASE_P (X)) goto ADDR; } \ else if (GET_CODE (X) == PLUS) \ { \ if (GET_CODE (XEXP (X, 0)) == REG \ && REG_OK_FOR_BASE_P (XEXP (X, 0))) \ { \ if (GET_CODE (XEXP (X, 1)) == CONST_INT \ && INTVAL (XEXP (X, 1)) >= -0x8000 \ && INTVAL (XEXP (X, 1)) < 0x8000 \ && (INTVAL (XEXP (X, 1)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \ goto ADDR; \ } \ else if (GET_CODE (XEXP (X, 1)) == REG \ && REG_OK_FOR_BASE_P (XEXP (X, 1))) \ { \ if (GET_CODE (XEXP (X, 0)) == CONST_INT \ && INTVAL (XEXP (X, 0)) >= -0x8000 \ && INTVAL (XEXP (X, 0)) < 0x8000 \ && (INTVAL (XEXP (X, 0)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \ goto ADDR; \ } \ } \ else if (CONSTANT_ADDRESS_P (X)) \ goto ADDR; \ } /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. OLDX is the address as it was before break_out_memory_refs was called. In some cases it is useful to look at this to decide what needs to be done. MODE and WIN are passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. It is always safe for this macro to do nothing. It exists to recognize opportunities to optimize the output. */ /* On the i860, change COMPLICATED + CONSTANT to REG+CONSTANT. Also change a symbolic constant to a REG, though that may not be necessary. */ #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \ force_operand (XEXP (X, 0), 0)); \ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \ force_operand (XEXP (X, 1), 0)); \ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \ force_operand (XEXP (X, 0), 0)); \ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \ force_operand (XEXP (X, 1), 0)); \ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) != REG \ && GET_CODE (XEXP (X, 0)) != CONST_INT) \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \ copy_to_mode_reg (SImode, XEXP (X, 0))); \ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) != REG \ && GET_CODE (XEXP (X, 1)) != CONST_INT) \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \ copy_to_mode_reg (SImode, XEXP (X, 1))); \ if (GET_CODE (x) == SYMBOL_REF) \ (X) = copy_to_reg (X); \ if (GET_CODE (x) == CONST) \ (X) = copy_to_reg (X); \ if (memory_address_p (MODE, X)) \ goto WIN; } /* Go to LABEL if ADDR (a legitimate address expression) has an effect that depends on the machine mode it is used for. On the i860 this is never true. There are some addresses that are invalid in wide modes but valid for narrower modes, but they shouldn't affect the places that use this macro. */ #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE SImode /* Define this if the tablejump instruction expects the table to contain offsets from the address of the table. Do not define this if the table should contain absolute addresses. */ /* #define CASE_VECTOR_PC_RELATIVE */ /* Specify the tree operation to be used to convert reals to integers. */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR /* This is the kind of divide that is easiest to do in the general case. */ #define EASY_DIV_EXPR TRUNC_DIV_EXPR /* Must pass floats to libgcc functions as doubles. */ #define LIBGCC_NEEDS_DOUBLE 1 #define DIVSI3_LIBCALL "*.div" #define UDIVSI3_LIBCALL "*.udiv" #define REMSI3_LIBCALL "*.rem" #define UREMSI3_LIBCALL "*.urem" /* Define this as 1 if `char' should by default be signed; else as 0. */ #define DEFAULT_SIGNED_CHAR 1 /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ #define MOVE_MAX 16 /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS 0 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 /* Value is 1 if it generates better code to perform an unsigned comparison on the given literal integer value in the given mode when we are only looking for an equal/non-equal result. */ /* For the i860, if the immediate value has its high-order 27 bits zero, then we want to engineer an unsigned comparison for EQ/NE because such values can fit in the 5-bit immediate field of a bte or btne instruction (which gets zero extended before comparing). For all other immediate values on the i860, we will use signed compares because that avoids the need for doing explicit xor's to zero_extend the non-constant operand in cases where it was (mem:QI ...) or a (mem:HI ...) which always gets automatically sign-extended by the hardware upon loading. */ #define LITERAL_COMPARE_BETTER_UNSIGNED(intval, mode) \ (((unsigned) (intval) & 0x1f) == (unsigned) (intval)) /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ #define Pmode SImode /* A function address in a call instruction is a byte address (for indexing purposes) so give the MEM rtx a byte's mode. */ #define FUNCTION_MODE SImode /* Define this if addresses of constant functions shouldn't be put through pseudo regs where they can be cse'd. Desirable on machines where ordinary constants are expensive but a CALL with constant address is cheap. */ #define NO_FUNCTION_CSE /* Compute the cost of computing a constant rtl expression RTX whose rtx-code is CODE. The body of this macro is a portion of a switch statement. If the code is computed here, return it with a return statement. Otherwise, break from the switch. */ #define CONST_COSTS(RTX,CODE, OUTER_CODE) \ case CONST_INT: \ if (INTVAL (RTX) == 0) \ return 0; \ if (INTVAL (RTX) < 0x2000 && INTVAL (RTX) >= -0x2000) return 1; \ case CONST: \ case LABEL_REF: \ case SYMBOL_REF: \ return 4; \ case CONST_DOUBLE: \ return 6; /* Specify the cost of a branch insn; roughly the number of extra insns that should be added to avoid a branch. Set this to 3 on the i860 since branches may often take three cycles. */ #define BRANCH_COST 3 /* Tell final.c how to eliminate redundant test instructions. */ /* Here we define machine-dependent flags and fields in cc_status (see `conditions.h'). */ /* This holds the value sourcing h%r31. We keep this info around so that mem/mem ops, such as increment and decrement, etc, can be performed reasonably. */ #define CC_STATUS_MDEP rtx #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0) #define CC_NEGATED 01000 /* We use this macro in those places in the i860.md file where we would normally just do a CC_STATUS_INIT (for other machines). This macro differs from CC_STATUS_INIT in that it doesn't mess with the special bits or fields which describe what is currently in the special r31 scratch register, but it does clear out everything that actually relates to the condition code bit of the i860. */ #define CC_STATUS_PARTIAL_INIT \ (cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ), \ cc_status.value1 = 0, \ cc_status.value2 = 0) /* Nonzero if we know the value of h%r31. */ #define CC_KNOW_HI_R31 0100000 /* Nonzero if h%r31 is actually ha%something, rather than h%something. */ #define CC_HI_R31_ADJ 0200000 /* Store in cc_status the expressions that the condition codes will describe after execution of an instruction whose pattern is EXP. Do not alter them if the instruction would not alter the cc's. */ /* On the i860, only compare insns set a useful condition code. */ #define NOTICE_UPDATE_CC(EXP, INSN) \ { cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ); \ cc_status.value1 = 0; cc_status.value2 = 0; } /* Control the assembler format that we output. */ /* Assembler pseudos to introduce constants of various size. */ #define ASM_BYTE_OP "\t.byte" #define ASM_SHORT "\t.short" #define ASM_LONG "\t.long" #define ASM_DOUBLE "\t.double" /* Output at beginning of assembler file. */ /* The .file command should always begin the output. */ #define ASM_FILE_START(FILE) #if 0 #define ASM_FILE_START(FILE) \ do { output_file_directive ((FILE), main_input_filename); \ if (optimize) ASM_FILE_START_1 (FILE); \ } while (0) #endif #define ASM_FILE_START_1(FILE) /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ #define ASM_APP_ON "" /* Output to assembler file text saying following lines no longer contain unusual constructs. */ #define ASM_APP_OFF "" /* Output before read-only data. */ #define TEXT_SECTION_ASM_OP ".text" /* Output before writable data. */ #define DATA_SECTION_ASM_OP ".data" /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ #define REGISTER_NAMES \ {"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7", "r8", "r9", \ "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \ "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \ "r30", "r31", \ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \ "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \ "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \ "f30", "f31" } /* How to renumber registers for dbx and gdb. */ #define DBX_REGISTER_NUMBER(REGNO) (REGNO) /* This is how to output the definition of a user-level label named NAME, such as the label on a static function or variable NAME. */ #define ASM_OUTPUT_LABEL(FILE,NAME) \ do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) /* This is how to output a command to make the user-level label named NAME defined for reference from other files. */ #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ do { fputs (".globl ", FILE); \ assemble_name (FILE, NAME); \ fputs ("\n", FILE); \ } while (0) /* This is how to output a reference to a user-level label named NAME. `assemble_name' uses this. This definition is overridden in i860v4.h because under System V Release 4, user-level symbols are *not* prefixed with underscores in the generated assembly code. */ #define ASM_OUTPUT_LABELREF(FILE,NAME) \ fprintf (FILE, "_%s", NAME) /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, ".%s%d:\n", PREFIX, NUM) /* This is how to output an internal numbered label which labels a jump table. */ #undef ASM_OUTPUT_CASE_LABEL #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ do { ASM_OUTPUT_ALIGN ((FILE), 2); \ ASM_OUTPUT_INTERNAL_LABEL ((FILE), PREFIX, NUM); \ } while (0) /* Output at the end of a jump table. */ #define ASM_OUTPUT_CASE_END(FILE,NUM,INSN) \ fprintf (FILE, ".text\n") /* This is how to store into the string LABEL the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ sprintf (LABEL, "*.%s%d", PREFIX, NUM) /* This is how to output an assembler line defining a `double' constant. */ #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ fprintf (FILE, "\t.double %.20e\n", (VALUE)) /* This is how to output an assembler line defining a `float' constant. */ #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ fprintf (FILE, "\t.float %.12e\n", (VALUE)) /* This is how to output an assembler line defining an `int' constant. */ #define ASM_OUTPUT_INT(FILE,VALUE) \ ( fprintf (FILE, "\t.long "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* Likewise for `char' and `short' constants. */ #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "\t.short "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ( fprintf (FILE, "\t.byte "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* This is how to output an assembler line for a numeric constant byte. */ #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) /* This is how to output code to push a register on the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\taddu -16,%ssp,%ssp\n\t%sst.l %s%s,0(%ssp)\n", \ i860_reg_prefix, i860_reg_prefix, \ ((REGNO) < 32 ? "" : "f"), \ i860_reg_prefix, reg_names[REGNO], \ i860_reg_prefix) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\t%sld.l 0(%ssp),%s%s\n\taddu 16,%ssp,%ssp\n", \ ((REGNO) < 32 ? "" : "f"), \ i860_reg_prefix, \ i860_reg_prefix, reg_names[REGNO], \ i860_reg_prefix, i860_reg_prefix) /* This is how to output an element of a case-vector that is absolute. */ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "\t.long .L%d\n", VALUE) /* This is how to output an element of a case-vector that is relative. (The i860 does not use such vectors, but we must define this macro anyway.) */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL) /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG) != 0) \ fprintf (FILE, "\t.align %d\n", 1 << (LOG)) #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t.blkb %u\n", (SIZE)) /* This says how to output an assembler line to define a global common symbol. */ #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fputs (".comm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (ROUNDED))) /* This says how to output an assembler line to define a local common symbol. */ #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( fputs (".lcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (ROUNDED))) /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) /* Define the parentheses used to group arithmetic operations in assembler code. */ #define ASM_OPEN_PAREN "(" #define ASM_CLOSE_PAREN ")" /* Define results of standard character escape sequences. */ #define TARGET_BELL 007 #define TARGET_BS 010 #define TARGET_TAB 011 #define TARGET_NEWLINE 012 #define TARGET_VT 013 #define TARGET_FF 014 #define TARGET_CR 015 /* Print operand X (an rtx) in assembler syntax to file FILE. CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. For `%' followed by punctuation, CODE is the punctuation and X is null. In the following comments, the term "constant address" is used frequently. For an exact definition of what constitutes a "constant address" see the output_addr_const routine in final.c On the i860, the following target-specific special codes are recognized: `r' The operand can be anything, but if is is an immediate zero value (either integer or floating point) then it will be represented as `r0' or as `f0' (respectively). `m' The operand is a memory ref (to a constant address) but print its address as a constant. `L' The operand is a numeric constant, a constant address, or a memory ref to a constant address. Print the correct notation to yield the low part of the given value or address or the low part of the address of the referred to memory object. `H' The operand is a numeric constant, a constant address, or a memory ref to a constant address. Print the correct notation to yield the high part of the given value or address or the high part of the address of the referred to memory object. `h' The operand is a numeric constant, a constant address, or a memory ref to a constant address. Either print the correct notation to yield the plain high part of the given value or address (or the plain high part of the address of the memory object) or else print the correct notation to yield the "adjusted" high part of the given address (or of the address of the referred to memory object). The choice of what to print depends upon whether the address in question is relocatable or not. If it is relocatable, print the notation to get the adjusted high part. Otherwise just print the notation to get the plain high part. Note that "adjusted" high parts are generally used *only* when the next following instruction uses the low part of the address as an offset, as in `offset(reg)'. `R' The operand is a floating-pointer register. Print the name of the next following (32-bit) floating-point register. (This is used when moving a value into just the most significant part of a floating-point register pair.) `?' (takes no operand) Substitute the value of i860_reg_prefix at this point. The value of i860_reg_prefix is typically a null string for most i860 targets, but for System V Release 4 the i860 assembler syntax requires that all names of registers be prefixed with a percent-sign, so for SVR4, the value of i860_reg_prefix is initialized to "%" in i860.c. */ extern char *i860_reg_prefix; extern unsigned long sfmode_constant_to_ulong (); #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '?') /* The following macro definition is overridden in i860v4.h because the svr4 i860 assembler required a different syntax for getting parts of constant/relocatable values. */ #define PRINT_OPERAND_PART(FILE, X, PART_CODE) \ do { fprintf (FILE, "%s%%", PART_CODE); \ output_address (X); \ } while (0) #define OPERAND_LOW_PART "l" #define OPERAND_HIGH_PART "h" /* NOTE: All documentation available for the i860 sez that you must use "ha" to get the relocated high part of a relocatable, but reality sez different. */ #define OPERAND_HIGH_ADJ_PART "ha" #define PRINT_OPERAND(FILE, X, CODE) \ { if ((CODE) == '?') \ fprintf (FILE, "%s", i860_reg_prefix); \ else if (CODE == 'R') \ fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X) + 1]); \ else if (GET_CODE (X) == REG) \ fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X)]); \ else if ((CODE) == 'm') \ output_address (XEXP (X, 0)); \ else if ((CODE) == 'L') \ { \ if (GET_CODE (X) == MEM) \ PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_LOW_PART); \ else \ PRINT_OPERAND_PART (FILE, X, OPERAND_LOW_PART); \ } \ else if ((CODE) == 'H') \ { \ if (GET_CODE (X) == MEM) \ PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_PART); \ else \ PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_PART); \ } \ else if ((CODE) == 'h') \ { \ if (GET_CODE (X) == MEM) \ PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_ADJ_PART); \ else \ PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_ADJ_PART); \ } \ else if (GET_CODE (X) == MEM) \ output_address (XEXP (X, 0)); \ else if ((CODE) == 'r' && (X) == const0_rtx) \ fprintf (FILE, "%sr0", i860_reg_prefix); \ else if ((CODE) == 'r' && (X) == CONST0_RTX (GET_MODE (X))) \ fprintf (FILE, "%sf0", i860_reg_prefix); \ else if (GET_CODE (X) == CONST_DOUBLE) \ fprintf (FILE, "0x%x", sfmode_constant_to_ulong (X)); \ else \ output_addr_const (FILE, X); } /* Print a memory address as an operand to reference that memory location. */ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ { register rtx base, index = 0; \ int offset = 0; \ register rtx addr = ADDR; \ if (GET_CODE (addr) == REG) \ { \ fprintf (FILE, "0(%s%s)", \ i860_reg_prefix, reg_names[REGNO (addr)]); \ } \ else if (GET_CODE (addr) == CONST_DOUBLE \ && GET_MODE (addr) == SFmode) \ fprintf (FILE, "0x%x", sfmode_constant_to_ulong (addr)); \ else if (GET_CODE (addr) == PLUS) \ { \ if ((GET_CODE (XEXP (addr, 0)) == CONST_INT) \ && (GET_CODE (XEXP (addr, 1)) == REG)) \ fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 0)), \ i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\ else if ((GET_CODE (XEXP (addr, 1)) == CONST_INT) \ && (GET_CODE (XEXP (addr, 0)) == REG)) \ fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 1)), \ i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))]);\ else if ((GET_CODE (XEXP (addr, 0)) == REG) \ && (GET_CODE (XEXP (addr, 1)) == REG)) \ fprintf (FILE, "%s%s(%s%s)", \ i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))], \ i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\ else \ output_addr_const (FILE, addr); \ } \ else \ { \ output_addr_const (FILE, addr); \ } \ } /* The following #defines are used when compiling the routines in libgcc1.c. Since the i860 calling conventions require single precision floats to be passed in the floating-point registers (rather than in the general registers) we have to build the libgcc1.c routines in such a way that they know the actual types of their formal arguments and the actual types of their return values. Otherwise, gcc will generate calls to the libgcc1.c routines, passing arguments in the floating-point registers, but the libgcc1.c routines will expect their arguments on the stack (where the i860 calling conventions require structs & unions to be passed). */ #define FLOAT_TYPE_VALUE float #define INTIFY(FLOATVAL) (FLOATVAL) #define FLOATIFY(INTVAL) (INTVAL) #define FLOAT_ARG_TYPE float /* Optionally define this if you have added predicates to `MACHINE.c'. This macro is called within an initializer of an array of structures. The first field in the structure is the name of a predicate and the second field is an array of rtl codes. For each predicate, list all rtl codes that can be in expressions matched by the predicate. The list should have a trailing comma. Here is an example of two entries in the list for a typical RISC machine: #define PREDICATE_CODES \ {"gen_reg_rtx_operand", {SUBREG, REG}}, \ {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}}, Defining this macro does not affect the generated code (however, incorrect definitions that omit an rtl code that may be matched by the predicate can cause the compiler to malfunction). Instead, it allows the table built by `genrecog' to be more compact and efficient, thus speeding up the compiler. The most important predicates to include in the list specified by this macro are thoses used in the most insn patterns. */ #define PREDICATE_CODES \ {"reg_or_0_operand", {REG, SUBREG, CONST_INT}}, \ {"arith_operand", {REG, SUBREG, CONST_INT}}, \ {"logic_operand", {REG, SUBREG, CONST_INT}}, \ {"shift_operand", {REG, SUBREG, CONST_INT}}, \ {"compare_operand", {REG, SUBREG, CONST_INT}}, \ {"arith_const_operand", {CONST_INT}}, \ {"logic_const_operand", {CONST_INT}}, \ {"bte_operand", {REG, SUBREG, CONST_INT}}, \ {"indexed_operand", {MEM}}, \ {"load_operand", {MEM}}, \ {"small_int", {CONST_INT}}, \ {"logic_int", {CONST_INT}}, \ {"call_insn_operand", {MEM}}, /* Define the information needed to generate branch insns. This is stored from the compare operation. Note that we can't use "rtx" here since it hasn't been defined! */ extern struct rtx_def *i860_compare_op0, *i860_compare_op1; /* Declare things which are defined in i860.c but called from insn-output.c. */ extern unsigned long sfmode_constant_to_ulong (); extern char *output_load (); extern char *output_store (); extern char *output_move_double (); extern char *output_fp_move_double (); extern char *output_block_move (); extern char *output_delay_insn (); extern char *output_delayed_branch (); extern void output_load_address (); gcc-2.5.8/config/i860/i860.md100444 22011 13 177355 5413627056 14020 0ustar kenneruser;;- Machine description for Intel 860 chip for GNU C compiler ;; Copyright (C) 1989, 1990 Free Software Foundation, Inc. ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code ;;- updates for most instructions. ;;- Operand classes for the register allocator: /* Bit-test instructions. */ (define_insn "" [(set (cc0) (eq (and:SI (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "logic_operand" "rL")) (const_int 0)))] "" "* { CC_STATUS_PARTIAL_INIT; return \"and %1,%0,%?r0\"; }") (define_insn "" [(set (cc0) (ne (and:SI (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "logic_operand" "rL")) (const_int 0)))] "" "* { CC_STATUS_PARTIAL_INIT; cc_status.flags |= CC_NEGATED; return \"and %1,%0,%?r0\"; }") (define_insn "" [(set (cc0) (eq (and:SI (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "immediate_operand" "i")) (const_int 0)))] "GET_CODE (operands[1]) == CONST_INT && (INTVAL (operands[1]) & 0xffff) == 0" "* { CC_STATUS_PARTIAL_INIT; return \"andh %H1,%0,%?r0\"; }") (define_insn "" [(set (cc0) (ne (and:SI (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "immediate_operand" "i")) (const_int 0)))] "GET_CODE (operands[1]) == CONST_INT && (INTVAL (operands[1]) & 0xffff) == 0" "* { CC_STATUS_PARTIAL_INIT; cc_status.flags |= CC_NEGATED; return \"andh %H1,%0,%?r0\"; }") (define_insn "" [(set (cc0) (eq (ashiftrt:SI (sign_extend:SI (ashift:QI (match_operand:QI 0 "register_operand" "r") (match_operand:QI 1 "logic_int" "n"))) (match_operand:SI 2 "logic_int" "n")) (const_int 0)))] "" "* { int width = 8 - INTVAL (operands[2]); int pos = 8 - width - INTVAL (operands[1]); CC_STATUS_PARTIAL_INIT; operands[2] = gen_rtx (CONST_INT, VOIDmode, ~((-1) << width) << pos); return \"and %2,%0,%?r0\"; }") ;; ------------------------------------------------------------------------- ;; SImode signed integer comparisons ;; ------------------------------------------------------------------------- (define_insn "cmpeqsi" [(set (cc0) (eq (match_operand:SI 0 "logic_operand" "r,rL") (match_operand:SI 1 "logic_operand" "L,r")))] "" "* { CC_STATUS_PARTIAL_INIT; if (REG_P (operands[0])) return \"xor %1,%0,%?r0\"; else return \"xor %0,%1,%?r0\"; }") (define_insn "cmpnesi" [(set (cc0) (ne (match_operand:SI 0 "logic_operand" "r,rL") (match_operand:SI 1 "logic_operand" "L,r")))] "" "* { CC_STATUS_PARTIAL_INIT; cc_status.flags |= CC_NEGATED; if (REG_P (operands[0])) return \"xor %1,%0,%?r0\"; else return \"xor %0,%1,%?r0\"; }") (define_insn "cmpltsi" [(set (cc0) (lt (match_operand:SI 0 "arith_operand" "r,rI") (match_operand:SI 1 "arith_operand" "I,r")))] "" "* { CC_STATUS_PARTIAL_INIT; if (REG_P (operands[1])) return \"subs %0,%1,%?r0\"; else { cc_status.flags |= CC_REVERSED; operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); return \"adds %1,%0,%?r0\"; } }") (define_insn "cmpgtsi" [(set (cc0) (gt (match_operand:SI 0 "arith_operand" "r,rI") (match_operand:SI 1 "arith_operand" "I,r")))] "" "* { CC_STATUS_PARTIAL_INIT; if (REG_P (operands[0])) return \"subs %1,%0,%?r0\"; else { cc_status.flags |= CC_REVERSED; operands[0] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[0])); return \"adds %0,%1,%?r0\"; } }") (define_insn "cmplesi" [(set (cc0) (le (match_operand:SI 0 "arith_operand" "r,rI") (match_operand:SI 1 "arith_operand" "I,r")))] "" "* { CC_STATUS_PARTIAL_INIT; cc_status.flags |= CC_NEGATED; if (REG_P (operands[0])) return \"subs %1,%0,%?r0\"; else { cc_status.flags |= CC_REVERSED; operands[0] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[0])); return \"adds %0,%1,%?r0\"; } }") (define_insn "cmpgesi" [(set (cc0) (ge (match_operand:SI 0 "arith_operand" "r,rI") (match_operand:SI 1 "arith_operand" "I,r")))] "" "* { CC_STATUS_PARTIAL_INIT; cc_status.flags |= CC_NEGATED; if (REG_P (operands[1])) return \"subs %0,%1,%?r0\"; else { cc_status.flags |= CC_REVERSED; operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); return \"adds %1,%0,%?r0\"; } }") ;; ------------------------------------------------------------------------- ;; SImode unsigned integer comparisons ;; ------------------------------------------------------------------------- ;; WARNING! There is a small i860 hardware limitation (bug?) which we ;; may run up against (if we are not careful) when we are trying to do ;; unsigned comparisons like (x >= 0), (x < 0), (0 <= x), and (0 > x). ;; Specifically, we must avoid using an `addu' instruction to perform ;; such comparisons because the result (in the CC bit register) will ;; come out wrong. (This fact is documented in a footnote on page 7-10 ;; of the 1991 version of the i860 Microprocessor Family Programmer's ;; Reference Manual). Note that unsigned comparisons of this sort are ;; always redundant anyway, because an unsigned quantity can never be ;; less than zero. When we see cases like this, we generate an ;; `or K,%r0,%r0' instruction instead (where K is a constant 0 or -1) ;; so as to get the CC bit register set properly for any subsequent ;; conditional jump instruction. (define_insn "cmpgeusi" [(set (cc0) (geu (match_operand:SI 0 "arith_operand" "r,rI") (match_operand:SI 1 "arith_operand" "I,r")))] "" "* { CC_STATUS_PARTIAL_INIT; if (REG_P (operands[1])) return \"subu %0,%1,%?r0\"; else { if (INTVAL (operands[1]) == 0) return \"or 0,%?r0,%?r0\"; else { cc_status.flags |= CC_REVERSED; operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); return \"addu %1,%0,%?r0\"; } } }") (define_insn "cmpleusi" [(set (cc0) (leu (match_operand:SI 0 "arith_operand" "r,rI") (match_operand:SI 1 "arith_operand" "I,r")))] "" "* { CC_STATUS_PARTIAL_INIT; if (REG_P (operands[0])) return \"subu %1,%0,%?r0\"; else { if (INTVAL (operands[0]) == 0) return \"or 0,%?r0,%?r0\"; else { cc_status.flags |= CC_REVERSED; operands[0] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[0])); return \"addu %0,%1,%?r0\"; } } }") ;; ------------------------------------------------------------------------- ;; SFmode floating-point comparisons ;; ------------------------------------------------------------------------- (define_insn "cmpeqsf" [(set (cc0) (eq (match_operand:SF 0 "reg_or_0_operand" "fG") (match_operand:SF 1 "reg_or_0_operand" "fG")))] "" "* { CC_STATUS_PARTIAL_INIT; return \"pfeq.ss %r0,%r1,%?f0\"; }") (define_insn "cmpnesf" [(set (cc0) (ne (match_operand:SF 0 "reg_or_0_operand" "fG") (match_operand:SF 1 "reg_or_0_operand" "fG")))] "" "* { CC_STATUS_PARTIAL_INIT; cc_status.flags |= CC_NEGATED; return \"pfeq.ss %r1,%r0,%?f0\"; }") ;; NOTE: The i860 Programmer's Reference Manual says that when we are ;; doing (A < B) or (A > B) comparisons, we have to use pfgt for these ;; in order to be IEEE compliant (in case a trap occurs during these ;; operations). Conversely, for (A <= B) or (A >= B) comparisons, we ;; must use pfle to be IEEE compliant. (define_insn "cmpltsf" [(set (cc0) (lt (match_operand:SF 0 "reg_or_0_operand" "fG") (match_operand:SF 1 "reg_or_0_operand" "fG")))] "" "* { CC_STATUS_PARTIAL_INIT; return \"pfgt.ss %r1,%r0,%?f0\"; }") (define_insn "cmpgtsf" [(set (cc0) (gt (match_operand:SF 0 "reg_or_0_operand" "fG") (match_operand:SF 1 "reg_or_0_operand" "fG")))] "" "* { CC_STATUS_PARTIAL_INIT; return \"pfgt.ss %r0,%r1,%?f0\"; }") ;; NOTE: The pfle opcode doesn't do what you think it does. It is ;; bass-ackwards. It *clears* the CC flag if the first operand is ;; less than or equal to the second. Thus, we have to set CC_NEGATED ;; for the following two patterns. (define_insn "cmplesf" [(set (cc0) (le (match_operand:SF 0 "reg_or_0_operand" "fG") (match_operand:SF 1 "reg_or_0_operand" "fG")))] "" "* { CC_STATUS_PARTIAL_INIT; cc_status.flags |= CC_NEGATED; return \"pfle.ss %r0,%r1,%?f0\"; }") (define_insn "cmpgesf" [(set (cc0) (ge (match_operand:SF 0 "reg_or_0_operand" "fG") (match_operand:SF 1 "reg_or_0_operand" "fG")))] "" "* { CC_STATUS_PARTIAL_INIT; cc_status.flags |= CC_NEGATED; return \"pfle.ss %r1,%r0,%?f0\"; }") ;; ------------------------------------------------------------------------- ;; DFmode floating-point comparisons ;; ------------------------------------------------------------------------- (define_insn "cmpeqdf" [(set (cc0) (eq (match_operand:DF 0 "reg_or_0_operand" "fG") (match_operand:DF 1 "reg_or_0_operand" "fG")))] "" "* { CC_STATUS_PARTIAL_INIT; return \"pfeq.dd %r0,%r1,%?f0\"; }") (define_insn "cmpnedf" [(set (cc0) (ne (match_operand:DF 0 "reg_or_0_operand" "fG") (match_operand:DF 1 "reg_or_0_operand" "fG")))] "" "* { CC_STATUS_PARTIAL_INIT; cc_status.flags |= CC_NEGATED; return \"pfeq.dd %r1,%r0,%?f0\"; }") ;; NOTE: The i860 Programmer's Reference Manual says that when we are ;; doing (A < B) or (A > B) comparisons, we have to use pfgt for these ;; in order to be IEEE compliant (in case a trap occurs during these ;; operations). Conversely, for (A <= B) or (A >= B) comparisons, we ;; must use pfle to be IEEE compliant. (define_insn "cmpltdf" [(set (cc0) (lt (match_operand:DF 0 "reg_or_0_operand" "fG") (match_operand:DF 1 "reg_or_0_operand" "fG")))] "" "* { CC_STATUS_PARTIAL_INIT; return \"pfgt.dd %r1,%r0,%?f0\"; }") (define_insn "cmpgtdf" [(set (cc0) (gt (match_operand:DF 0 "reg_or_0_operand" "fG") (match_operand:DF 1 "reg_or_0_operand" "fG")))] "" "* { CC_STATUS_PARTIAL_INIT; return \"pfgt.dd %r0,%r1,%?f0\"; }") ;; NOTE: The pfle opcode doesn't do what you think it does. It is ;; bass-ackwards. It *clears* the CC flag if the first operand is ;; less than or equal to the second. Thus, we have to set CC_NEGATED ;; for the following two patterns. (define_insn "cmpledf" [(set (cc0) (le (match_operand:DF 0 "reg_or_0_operand" "fG") (match_operand:DF 1 "reg_or_0_operand" "fG")))] "" "* { CC_STATUS_PARTIAL_INIT; cc_status.flags |= CC_NEGATED; return \"pfle.dd %r0,%r1,%?f0\"; }") (define_insn "cmpgedf" [(set (cc0) (ge (match_operand:DF 0 "reg_or_0_operand" "fG") (match_operand:DF 1 "reg_or_0_operand" "fG")))] "" "* { CC_STATUS_PARTIAL_INIT; cc_status.flags |= CC_NEGATED; return \"pfle.dd %r1,%r0,%?f0\"; }") ;; ------------------------------------------------------------------------ ;; Integer EQ/NE comparisons against constant values which will fit in the ;; 16-bit immediate field of an instruction. These are made by combining. ;; ------------------------------------------------------------------------ (define_insn "" [(set (cc0) (eq (zero_extend:SI (match_operand:HI 0 "load_operand" "m")) (match_operand:SI 1 "small_int" "I")))] "INTVAL (operands[1]) >= 0" "* { CC_STATUS_PARTIAL_INIT; return \"ld.s %0,%?r31\;xor %1,%?r31,%?r0\"; }") (define_insn "" [(set (cc0) (eq (match_operand:SI 0 "small_int" "I") (zero_extend:SI (match_operand:HI 1 "load_operand" "m"))))] "INTVAL (operands[0]) >= 0" "* { CC_STATUS_PARTIAL_INIT; return \"ld.s %1,%?r31\;xor %0,%?r31,%?r0\"; }") ;; ------------------------------------------------------------------------ ;; Define the real conditional branch instructions. ;; ------------------------------------------------------------------------ (define_insn "cbranch" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { if ((cc_prev_status.flags & CC_NEGATED) == 0) return \"bnc %l0\"; else return \"bc %l0\"; }") (define_insn "flipped_cbranch" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { if ((cc_prev_status.flags & CC_NEGATED) == 0) return \"bnc %l0\"; else return \"bc %l0\"; }") (define_insn "inverse_cbranch" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { if ((cc_prev_status.flags & CC_NEGATED) == 0) return \"bc %l0\"; else return \"bnc %l0\"; }") (define_insn "flipped_inverse_cbranch" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { if ((cc_prev_status.flags & CC_NEGATED) == 0) return \"bc %l0\"; else return \"bnc %l0\"; }") ;; Simple BTE/BTNE compare-and-branch insns made by combining. ;; Note that it is wrong to add similar patterns for QI or HImode ;; because bte/btne always compare the whole register. (define_insn "" [(set (pc) (if_then_else (eq (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "bte_operand" "rK")) (label_ref (match_operand 2 "" "")) (pc)))] "" "bte %1,%0,%2") (define_insn "" [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "bte_operand" "rK")) (label_ref (match_operand 2 "" "")) (pc)))] "" "btne %1,%0,%2") (define_insn "" [(set (pc) (if_then_else (eq (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "bte_operand" "rK")) (pc) (label_ref (match_operand 2 "" ""))))] "" "btne %1,%0,%2") (define_insn "" [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "bte_operand" "rK")) (pc) (label_ref (match_operand 2 "" ""))))] "" "bte %1,%0,%2") ;; Load byte/halfword, zero-extend, & compare-and-branch insns. ;; These are made by combining. (define_insn "" [(set (pc) (if_then_else (eq (zero_extend:SI (match_operand:QI 0 "memory_operand" "m")) (match_operand:SI 1 "bte_operand" "K")) (label_ref (match_operand 2 "" "")) (pc))) (match_scratch:SI 3 "=r")] "" "ld.b %0,%3;bte %1,%3,%2") (define_insn "" [(set (pc) (if_then_else (ne (zero_extend:SI (match_operand:QI 0 "memory_operand" "m")) (match_operand:SI 1 "bte_operand" "K")) (label_ref (match_operand 2 "" "")) (pc))) (match_scratch:SI 3 "=r")] "" "ld.b %0,%3;btne %1,%3,%2") (define_insn "" [(set (pc) (if_then_else (eq (zero_extend:SI (match_operand:QI 0 "memory_operand" "m")) (match_operand:SI 1 "bte_operand" "K")) (pc) (label_ref (match_operand 2 "" "")))) (match_scratch:SI 3 "=r")] "" "ld.b %0,%3;btne %1,%3,%2") (define_insn "" [(set (pc) (if_then_else (ne (zero_extend:SI (match_operand:QI 0 "memory_operand" "m")) (match_operand:SI 1 "bte_operand" "K")) (pc) (label_ref (match_operand 2 "" "")))) (match_scratch:SI 3 "=r")] "" "ld.b %0,%3;bte %1,%3,%2") (define_insn "" [(set (pc) (if_then_else (eq (zero_extend:SI (match_operand:HI 0 "memory_operand" "m")) (match_operand:SI 1 "bte_operand" "K")) (label_ref (match_operand 2 "" "")) (pc))) (match_scratch:SI 3 "=r")] "" "ld.s %0,%3;bte %1,%3,%2") (define_insn "" [(set (pc) (if_then_else (ne (zero_extend:SI (match_operand:HI 0 "memory_operand" "m")) (match_operand:SI 1 "bte_operand" "K")) (label_ref (match_operand 2 "" "")) (pc))) (match_scratch:SI 3 "=r")] "" "ld.s %0,%3;btne %1,%3,%2") (define_insn "" [(set (pc) (if_then_else (eq (zero_extend:SI (match_operand:HI 0 "memory_operand" "m")) (match_operand:SI 1 "bte_operand" "K")) (pc) (label_ref (match_operand 2 "" "")))) (match_scratch:SI 3 "=r")] "" "ld.s %0,%3;btne %1,%3,%2") (define_insn "" [(set (pc) (if_then_else (ne (zero_extend:SI (match_operand:HI 0 "memory_operand" "m")) (match_operand:SI 1 "bte_operand" "K")) (pc) (label_ref (match_operand 2 "" "")))) (match_scratch:SI 3 "=r")] "" "ld.s %0,%3;bte %1,%3,%2") ;; Generation of conditionals. ;; We save the compare operands in the cmpxx patterns and use then when ;; we generate the branch. (define_expand "cmpsi" [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "compare_operand" "")))] "" " { i860_compare_op0 = operands[0]; i860_compare_op1 = operands[1]; DONE; }") (define_expand "cmpsf" [(set (cc0) (compare (match_operand:SF 0 "register_operand" "") (match_operand:SF 1 "register_operand" "")))] "" " { i860_compare_op0 = operands[0]; i860_compare_op1 = operands[1]; DONE; }") (define_expand "cmpdf" [(set (cc0) (compare (match_operand:DF 0 "register_operand" "") (match_operand:DF 1 "register_operand" "")))] "" " { i860_compare_op0 = operands[0]; i860_compare_op1 = operands[1]; DONE; }") ;; These are the standard-named conditional branch patterns. ;; Detailed comments are found in the first one only. (define_expand "beq" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { /* Emit a single-condition compare insn according to the type of operands and the condition to be tested. */ if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT) emit_insn (gen_cmpeqsi (i860_compare_op0, i860_compare_op1)); else if (GET_MODE (i860_compare_op0) == SFmode) emit_insn (gen_cmpeqsf (i860_compare_op0, i860_compare_op1)); else if (GET_MODE (i860_compare_op0) == DFmode) emit_insn (gen_cmpeqdf (i860_compare_op0, i860_compare_op1)); else abort (); /* Emit branch-if-true. */ emit_jump_insn (gen_flipped_inverse_cbranch (operands[0])); DONE; }") (define_expand "bne" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT) emit_insn (gen_cmpeqsi (i860_compare_op0, i860_compare_op1)); else if (GET_MODE (i860_compare_op0) == SFmode) emit_insn (gen_cmpeqsf (i860_compare_op0, i860_compare_op1)); else if (GET_MODE (i860_compare_op0) == DFmode) emit_insn (gen_cmpeqdf (i860_compare_op0, i860_compare_op1)); else abort (); emit_jump_insn (gen_flipped_cbranch (operands[0])); DONE; }") (define_expand "bgt" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT) emit_insn (gen_cmpgtsi (i860_compare_op0, i860_compare_op1)); else if (GET_MODE (i860_compare_op0) == SFmode) emit_insn (gen_cmpgtsf (i860_compare_op0, i860_compare_op1)); else if (GET_MODE (i860_compare_op0) == DFmode) emit_insn (gen_cmpgtdf (i860_compare_op0, i860_compare_op1)); else abort (); emit_jump_insn (gen_flipped_inverse_cbranch (operands[0])); DONE; }") (define_expand "blt" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT) emit_insn (gen_cmpltsi (i860_compare_op0, i860_compare_op1)); else if (GET_MODE (i860_compare_op0) == SFmode) emit_insn (gen_cmpltsf (i860_compare_op0, i860_compare_op1)); else if (GET_MODE (i860_compare_op0) == DFmode) emit_insn (gen_cmpltdf (i860_compare_op0, i860_compare_op1)); else abort (); emit_jump_insn (gen_flipped_inverse_cbranch (operands[0])); DONE; }") (define_expand "ble" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT) { emit_insn (gen_cmpgtsi (i860_compare_op0, i860_compare_op1)); emit_jump_insn (gen_flipped_cbranch (operands[0])); } else { if (GET_MODE (i860_compare_op0) == SFmode) emit_insn (gen_cmplesf (i860_compare_op0, i860_compare_op1)); else if (GET_MODE (i860_compare_op0) == DFmode) emit_insn (gen_cmpledf (i860_compare_op0, i860_compare_op1)); else abort (); emit_jump_insn (gen_flipped_inverse_cbranch (operands[0])); } DONE; }") (define_expand "bge" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT) { emit_insn (gen_cmpltsi (i860_compare_op0, i860_compare_op1)); emit_jump_insn (gen_flipped_cbranch (operands[0])); } else { if (GET_MODE (i860_compare_op0) == SFmode) emit_insn (gen_cmpgesf (i860_compare_op0, i860_compare_op1)); else if (GET_MODE (i860_compare_op0) == DFmode) emit_insn (gen_cmpgedf (i860_compare_op0, i860_compare_op1)); else abort (); emit_jump_insn (gen_flipped_inverse_cbranch (operands[0])); } DONE; }") (define_expand "bgtu" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT) abort (); emit_insn (gen_cmpleusi (i860_compare_op0, i860_compare_op1)); emit_jump_insn (gen_flipped_cbranch (operands[0])); DONE; }") (define_expand "bltu" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT) abort (); emit_insn (gen_cmpgeusi (i860_compare_op0, i860_compare_op1)); emit_jump_insn (gen_flipped_cbranch (operands[0])); DONE; }") (define_expand "bgeu" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT) abort (); emit_insn (gen_cmpgeusi (i860_compare_op0, i860_compare_op1)); emit_jump_insn (gen_flipped_inverse_cbranch (operands[0])); DONE; }") (define_expand "bleu" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT) abort (); emit_insn (gen_cmpleusi (i860_compare_op0, i860_compare_op1)); emit_jump_insn (gen_flipped_inverse_cbranch (operands[0])); DONE; }") ;; Move instructions ;; Note that source operands for `mov' pseudo-instructions are no longer ;; allowed (by the svr4 assembler) to be "big" things, i.e. constants that ;; won't fit in 16-bits. (This includes any sort of a relocatable address ;; also.) Thus, we must use an explicit orh/or pair of instructions if ;; the source operand is something "big". (define_insn "movsi" [(set (match_operand:SI 0 "general_operand" "=r,m,f") (match_operand:SI 1 "general_operand" "rmif,rfJ,rmfJ"))] "" "* { if (GET_CODE (operands[0]) == MEM) { if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) return output_store (operands); if (FP_REG_P (operands[1])) return \"fst.l %1,%0\"; return \"st.l %r1,%0\"; } if (GET_CODE (operands[1]) == MEM) { if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) return output_load (operands); if (FP_REG_P (operands[0])) return \"fld.l %1,%0\"; return \"ld.l %1,%0\"; } if (FP_REG_P (operands[1]) && FP_REG_P (operands[0])) return \"fmov.ss %1,%0\"; if (FP_REG_P (operands[1])) return \"fxfr %1,%0\"; if (FP_REG_P (operands[0]) && operands[1] == const0_rtx) return \"fmov.ss %?f0,%0\"; if (FP_REG_P (operands[0])) return \"ixfr %1,%0\"; if (GET_CODE (operands[1]) == REG) return \"shl %?r0,%1,%0\"; CC_STATUS_PARTIAL_INIT; if (GET_CODE (operands[1]) == CONST_INT) { if((INTVAL (operands[1]) & 0xffff0000) == 0) return \"or %L1,%?r0,%0\"; if((INTVAL (operands[1]) & 0x0000ffff) == 0) return \"orh %H1,%?r0,%0\"; } return \"orh %H1,%?r0,%0\;or %L1,%0,%0\"; }") (define_insn "movhi" [(set (match_operand:HI 0 "general_operand" "=r,m,!*f,!r") (match_operand:HI 1 "general_operand" "rmi,rJ,rJ*f,*f"))] "" "* { if (GET_CODE (operands[0]) == MEM) { if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) return output_store (operands); return \"st.s %r1,%0\"; } if (GET_CODE (operands[1]) == MEM) { if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) return output_load (operands); return \"ld.s %1,%0\"; } if (FP_REG_P (operands[1]) && FP_REG_P (operands[0])) return \"fmov.ss %1,%0\"; if (FP_REG_P (operands[1])) return \"fxfr %1,%0\"; if (FP_REG_P (operands[0]) && operands[1] == const0_rtx) return \"fmov.ss %?f0,%0\"; if (FP_REG_P (operands[0])) return \"ixfr %1,%0\"; if (GET_CODE (operands[1]) == REG) return \"shl %?r0,%1,%0\"; CC_STATUS_PARTIAL_INIT; return \"or %L1,%?r0,%0\"; }") (define_insn "movqi" [(set (match_operand:QI 0 "general_operand" "=r,m,!*f,!r") (match_operand:QI 1 "general_operand" "rmi,rJ,rJ*f,*f"))] "" "* { if (GET_CODE (operands[0]) == MEM) { if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) return output_store (operands); return \"st.b %r1,%0\"; } if (GET_CODE (operands[1]) == MEM) { if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) return output_load (operands); return \"ld.b %1,%0\"; } if (FP_REG_P (operands[1]) && FP_REG_P (operands[0])) return \"fmov.ss %1,%0\"; if (FP_REG_P (operands[1])) return \"fxfr %1,%0\"; if (FP_REG_P (operands[0]) && operands[1] == const0_rtx) return \"fmov.ss %?f0,%0\"; if (FP_REG_P (operands[0])) return \"ixfr %1,%0\"; if (GET_CODE (operands[1]) == REG) return \"shl %?r0,%1,%0\"; CC_STATUS_PARTIAL_INIT; return \"or %L1,%?r0,%0\"; }") ;; The definition of this insn does not really explain what it does, ;; but it should suffice ;; that anything generated as this insn will be recognized as one ;; and that it won't successfully combine with anything. (define_expand "movstrsi" [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" "")) (mem:BLK (match_operand:BLK 1 "general_operand" ""))) (use (match_operand:SI 2 "nonmemory_operand" "")) (use (match_operand:SI 3 "immediate_operand" "")) (clobber (match_dup 4)) (clobber (match_dup 5)) (clobber (match_dup 6)) (clobber (match_dup 0)) (clobber (match_dup 1))])] "" " { operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); operands[4] = gen_reg_rtx (SImode); operands[5] = gen_reg_rtx (SImode); operands[6] = gen_reg_rtx (SImode); }") (define_insn "" [(set (mem:BLK (match_operand:SI 0 "register_operand" "r")) (mem:BLK (match_operand:SI 1 "register_operand" "r"))) (use (match_operand:SI 2 "general_operand" "rn")) (use (match_operand:SI 3 "immediate_operand" "i")) (clobber (match_operand:SI 4 "register_operand" "=r")) (clobber (match_operand:SI 5 "register_operand" "=r")) (clobber (match_operand:SI 6 "register_operand" "=r")) (clobber (match_dup 0)) (clobber (match_dup 1))] "" "* return output_block_move (operands);") ;; Floating point move insns ;; This pattern forces (set (reg:DF ...) (const_double ...)) ;; to be reloaded by putting the constant into memory. ;; It must come before the more general movdf pattern. (define_insn "" [(set (match_operand:DF 0 "general_operand" "=r,f,o") (match_operand:DF 1 "" "mG,m,G"))] "GET_CODE (operands[1]) == CONST_DOUBLE" "* { if (FP_REG_P (operands[0]) || operands[1] == CONST0_RTX (DFmode)) return output_fp_move_double (operands); return output_move_double (operands); }") (define_insn "movdf" [(set (match_operand:DF 0 "general_operand" "=*rm,*r,?f,?*rm") (match_operand:DF 1 "general_operand" "*r,m,*rfmG,f"))] "" "* { if (GET_CODE (operands[0]) == MEM && CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) return output_store (operands); if (GET_CODE (operands[1]) == MEM && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) return output_load (operands); if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) return output_fp_move_double (operands); return output_move_double (operands); }") (define_insn "movdi" [(set (match_operand:DI 0 "general_operand" "=rm,r,?f,?rm") (match_operand:DI 1 "general_operand" "r,miF,rfmG,f"))] "" "* { if (GET_CODE (operands[0]) == MEM && CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) return output_store (operands); if (GET_CODE (operands[1]) == MEM && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) return output_load (operands); /* ??? How can we have a DFmode arg here with DImode above? */ if (FP_REG_P (operands[0]) && operands[1] == CONST0_RTX (DFmode)) return \"fmov.dd %?f0,%0\"; if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) return output_fp_move_double (operands); return output_move_double (operands); }") ;; The alternative m/r is separate from m/f ;; The first alternative is separate from the second for the same reason. (define_insn "movsf" [(set (match_operand:SF 0 "general_operand" "=*rf,*rf,*r,m,m") (match_operand:SF 1 "general_operand" "*r,fmG,F,*r,f"))] "" "* { if (GET_CODE (operands[0]) == MEM && CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) return output_store (operands); if (GET_CODE (operands[1]) == MEM && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) return output_load (operands); if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) return \"fmov.ss %1,%0\"; if (GET_CODE (operands[1]) == REG) return \"ixfr %1,%0\"; if (operands[1] == CONST0_RTX (SFmode)) return \"fmov.ss %?f0,%0\"; if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) { if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) && (cc_prev_status.flags & CC_HI_R31_ADJ) && cc_prev_status.mdep == XEXP(operands[1],0))) { CC_STATUS_INIT; cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; cc_status.mdep = XEXP (operands[1], 0); return \"orh %h1,%?r0,%?r31\;fld.l %L1(%?r31),%0\"; } return \"fld.l %L1(%?r31),%0\"; } return \"fld.l %1,%0\"; } if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE) { if (GET_CODE (operands[0]) == REG && FP_REG_P (operands[1])) return \"fxfr %1,%0\"; if (GET_CODE (operands[0]) == REG) { CC_STATUS_PARTIAL_INIT; if (GET_CODE (operands[1]) == CONST_DOUBLE) { register unsigned long ul; ul = sfmode_constant_to_ulong (operands[1]); if ((ul & 0x0000ffff) == 0) return \"orh %H1,%?r0,%0\"; if ((ul & 0xffff0000) == 0) return \"or %L1,%?r0,%0\"; } return \"orh %H1,%?r0,%0\;or %L1,%0,%0\"; } /* Now operand 0 must be memory. If operand 1 is CONST_DOUBLE, its value must be 0. */ if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) { if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) && (cc_prev_status.flags & CC_HI_R31_ADJ) && XEXP (operands[0], 0) == cc_prev_status.mdep)) { CC_STATUS_INIT; cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; cc_status.mdep = XEXP (operands[0], 0); output_asm_insn (\"orh %h0,%?r0,%?r31\", operands); } return \"fst.l %r1,%L0(%?r31)\"; } return \"fst.l %r1,%0\"; } if (GET_CODE (operands[0]) == MEM) return \"st.l %r1,%0\"; if (GET_CODE (operands[1]) == MEM) return \"ld.l %1,%0\"; if (operands[1] == CONST0_RTX (SFmode)) return \"shl %?r0,%?r0,%0\"; return \"mov %1,%0\"; }") ;; Special load insns for REG+REG addresses. ;; Such addresses are not "legitimate" because st rejects them. (define_insn "" [(set (match_operand:DF 0 "register_operand" "=rf") (match_operand:DF 1 "indexed_operand" "m"))] "" "* { if (FP_REG_P (operands[0])) return output_fp_move_double (operands); return output_move_double (operands); }") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=rf") (match_operand:SF 1 "indexed_operand" "m"))] "" "* { if (FP_REG_P (operands[0])) return \"fld.l %1,%0\"; return \"ld.l %1,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=rf") (match_operand:SI 1 "indexed_operand" "m"))] "" "* { if (FP_REG_P (operands[0])) return \"fld.l %1,%0\"; return \"ld.l %1,%0\"; }") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (match_operand:HI 1 "indexed_operand" "m"))] "" "ld.s %1,%0") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") (match_operand:QI 1 "indexed_operand" "m"))] "" "ld.b %1,%0") ;; Likewise for floating-point store insns. (define_insn "" [(set (match_operand:DF 0 "indexed_operand" "=m") (match_operand:DF 1 "register_operand" "f"))] "" "fst.d %1,%0") (define_insn "" [(set (match_operand:SF 0 "indexed_operand" "=m") (match_operand:SF 1 "register_operand" "f"))] "" "fst.l %1,%0") ;;- truncation instructions (define_insn "truncsiqi2" [(set (match_operand:QI 0 "general_operand" "=g") (truncate:QI (match_operand:SI 1 "register_operand" "r")))] "" "* { if (GET_CODE (operands[0]) == MEM) if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) { if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) && (cc_prev_status.flags & CC_HI_R31_ADJ) && XEXP (operands[0], 0) == cc_prev_status.mdep)) { CC_STATUS_INIT; cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; cc_status.mdep = XEXP (operands[0], 0); output_asm_insn (\"orh %h0,%?r0,%?r31\", operands); } return \"st.b %1,%L0(%?r31)\"; } else return \"st.b %1,%0\"; return \"shl %?r0,%1,%0\"; }") (define_insn "trunchiqi2" [(set (match_operand:QI 0 "general_operand" "=g") (truncate:QI (match_operand:HI 1 "register_operand" "r")))] "" "* { if (GET_CODE (operands[0]) == MEM) if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) { if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) && (cc_prev_status.flags & CC_HI_R31_ADJ) && XEXP (operands[0], 0) == cc_prev_status.mdep)) { CC_STATUS_INIT; cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; cc_status.mdep = XEXP (operands[0], 0); output_asm_insn (\"orh %h0,%?r0,%?r31\", operands); } return \"st.b %1,%L0(%?r31)\"; } else return \"st.b %1,%0\"; return \"shl %?r0,%1,%0\"; }") (define_insn "truncsihi2" [(set (match_operand:HI 0 "general_operand" "=g") (truncate:HI (match_operand:SI 1 "register_operand" "r")))] "" "* { if (GET_CODE (operands[0]) == MEM) if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) { if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) && (cc_prev_status.flags & CC_HI_R31_ADJ) && XEXP (operands[0], 0) == cc_prev_status.mdep)) { CC_STATUS_INIT; cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; cc_status.mdep = XEXP (operands[0], 0); output_asm_insn (\"orh %h0,%?r0,%?r31\", operands); } return \"st.s %1,%L0(%?r31)\"; } else return \"st.s %1,%0\"; return \"shl %?r0,%1,%0\"; }") ;;- zero extension instructions (define_insn "zero_extendhisi2" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))] "" "* { CC_STATUS_PARTIAL_INIT; return \"and 0xffff,%1,%0\"; }") (define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "=r") (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))] "" "* { CC_STATUS_PARTIAL_INIT; return \"and 0xff,%1,%0\"; }") (define_insn "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))] "" "* { CC_STATUS_PARTIAL_INIT; return \"and 0xff,%1,%0\"; }") ;; Sign extension instructions. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (sign_extend:SI (match_operand:HI 1 "indexed_operand" "m")))] "" "ld.s %1,%0") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (sign_extend:HI (match_operand:QI 1 "indexed_operand" "m")))] "" "ld.b %1,%0") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (sign_extend:SI (match_operand:QI 1 "indexed_operand" "m")))] "" "ld.b %1,%0") (define_insn "extendhisi2" [(set (match_operand:SI 0 "register_operand" "=r") (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "mr")))] "" "* { if (REG_P (operands[1])) return \"shl 16,%1,%0\;shra 16,%0,%0\"; if (GET_CODE (operands[1]) == CONST_INT) abort (); if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) { CC_STATUS_INIT; cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; cc_status.mdep = XEXP (operands[1], 0); return \"orh %h1,%?r0,%?r31\;ld.s %L1(%?r31),%0\"; } else return \"ld.s %1,%0\"; }") (define_insn "extendqihi2" [(set (match_operand:HI 0 "register_operand" "=r") (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "mr")))] "" "* { if (REG_P (operands[1])) return \"shl 24,%1,%0\;shra 24,%0,%0\"; if (GET_CODE (operands[1]) == CONST_INT) abort (); if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) { CC_STATUS_INIT; cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; cc_status.mdep = XEXP (operands[1], 0); return \"orh %h1,%?r0,%?r31\;ld.b %L1(%?r31),%0\"; } else return \"ld.b %1,%0\"; }") (define_insn "extendqisi2" [(set (match_operand:SI 0 "register_operand" "=r") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "mr")))] "" "* { if (REG_P (operands[1])) return \"shl 24,%1,%0\;shra 24,%0,%0\"; if (GET_CODE (operands[1]) == CONST_INT) abort (); if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) { CC_STATUS_INIT; cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; cc_status.mdep = XEXP (operands[1], 0); return \"orh %h1,%?r0,%?r31\;ld.b %L1(%?r31),%0\"; } else return \"ld.b %1,%0\"; }") ;; Signed bitfield extractions come out looking like ;; (shiftrt (sign_extend (shift )) ) ;; which we expand poorly as four shift insns. ;; These patters yeild two shifts: ;; (shiftrt (shift ) ) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "r")) (match_operand:SI 2 "logic_int" "n")))] "INTVAL (operands[2]) < 8" "* { return \"shl 24,%1,%0\;shra 24+%2,%0,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI (sign_extend:SI (subreg:QI (ashift:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "logic_int" "n")) 0)) (match_operand:SI 3 "logic_int" "n")))] "INTVAL (operands[3]) < 8" "* { return \"shl 0x18+%2,%1,%0\;shra 0x18+%3,%0,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI (sign_extend:SI (ashift:QI (match_operand:QI 1 "register_operand" "r") (match_operand:QI 2 "logic_int" "n"))) (match_operand:SI 3 "logic_int" "n")))] "INTVAL (operands[3]) < 8" "* { return \"shl 0x18+%2,%1,%0\;shra 0x18+%3,%0,%0\"; }") ;; Special patterns for optimizing bit-field instructions. ;; First two patterns are for bitfields that came from memory ;; testing only the high bit. They work with old combiner. (define_insn "" [(set (cc0) (eq (zero_extend:SI (subreg:QI (lshiftrt:SI (match_operand:SI 0 "register_operand" "r") (const_int 7)) 0)) (const_int 0)))] "" "* { CC_STATUS_PARTIAL_INIT; return \"and 128,%0,%?r0\"; }") (define_insn "" [(set (cc0) (eq (sign_extend:SI (subreg:QI (ashiftrt:SI (match_operand:SI 0 "register_operand" "r") (const_int 7)) 0)) (const_int 0)))] "" "* { CC_STATUS_PARTIAL_INIT; return \"and 128,%0,%?r0\"; }") ;; next two patterns are good for bitfields coming from memory ;; (via pseudo-register) or from a register, though this optimization ;; is only good for values contained wholly within the bottom 13 bits (define_insn "" [(set (cc0) (eq (and:SI (lshiftrt:SI (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "logic_int" "n")) (match_operand:SI 2 "logic_int" "n")) (const_int 0)))] "LOGIC_INTVAL (INTVAL (operands[2]) << INTVAL (operands[1]))" "* { CC_STATUS_PARTIAL_INIT; operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) << INTVAL (operands[1]))); return \"and %2,%0,%?r0\"; }") (define_insn "" [(set (cc0) (eq (and:SI (ashiftrt:SI (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "logic_int" "n")) (match_operand:SI 2 "logic_int" "n")) (const_int 0)))] "LOGIC_INTVAL (INTVAL (operands[2]) << INTVAL (operands[1]))" "* { CC_STATUS_PARTIAL_INIT; operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) << INTVAL (operands[1]))); return \"and %2,%0,%?r0\"; }") ;; Conversions between float and double. (define_insn "extendsfdf2" [(set (match_operand:DF 0 "register_operand" "=f") (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] "" "fmov.sd %1,%0") (define_insn "truncdfsf2" [(set (match_operand:SF 0 "register_operand" "=f") (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] "" "fmov.ds %1,%0") ;; Conversion between fixed point and floating point. ;; Note that among the fix-to-float insns ;; the ones that start with SImode come first. ;; That is so that an operand that is a CONST_INT ;; (and therefore lacks a specific machine mode). ;; will be recognized as SImode (which is always valid) ;; rather than as QImode or HImode. ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...))) ;; to be reloaded by putting the constant into memory. ;; It must come before the more general floatsisf2 pattern. (define_expand "floatsidf2" [(set (match_dup 2) (match_dup 3)) (set (match_dup 4) (xor:SI (match_operand:SI 1 "register_operand" "") (const_int -2147483648))) (set (match_dup 5) (match_dup 3)) (set (subreg:SI (match_dup 5) 0) (match_dup 4)) (set (match_operand:DF 0 "register_operand" "") (minus:DF (match_dup 5) (match_dup 2)))] "" " { REAL_VALUE_TYPE d; /* 4503601774854144 is (1 << 30) * ((1 << 22) + (1 << 1)). */ d = REAL_VALUE_ATOF (\"4503601774854144\", DFmode); operands[2] = gen_reg_rtx (DFmode); operands[3] = CONST_DOUBLE_FROM_REAL_VALUE (d, DFmode); operands[4] = gen_reg_rtx (SImode); operands[5] = gen_reg_rtx (DFmode); }") ;; Floating to fixed conversion. (define_expand "fix_truncdfsi2" ;; This first insn produces a double-word value ;; in which only the low word is valid. [(set (match_dup 2) (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f")))) (set (match_operand:SI 0 "register_operand" "=f") (subreg:SI (match_dup 2) 0))] "" " { operands[2] = gen_reg_rtx (DImode); }") ;; Recognize the first insn generated above. ;; This RTL looks like a fix_truncdfdi2 insn, ;; but we dont call it that, because only 32 bits ;; of the result are valid. ;; This pattern will work for the intended purposes ;; as long as we do not have any fixdfdi2 or fix_truncdfdi2. (define_insn "" [(set (match_operand:DI 0 "register_operand" "=f") (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))] "" "ftrunc.dd %1,%0") (define_expand "fix_truncsfsi2" ;; This first insn produces a double-word value ;; in which only the low word is valid. [(set (match_dup 2) (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f")))) (set (match_operand:SI 0 "register_operand" "=f") (subreg:SI (match_dup 2) 0))] "" " { operands[2] = gen_reg_rtx (DImode); }") ;; Recognize the first insn generated above. ;; This RTL looks like a fix_truncsfdi2 insn, ;; but we dont call it that, because only 32 bits ;; of the result are valid. ;; This pattern will work for the intended purposes ;; as long as we do not have any fixsfdi2 or fix_truncsfdi2. (define_insn "" [(set (match_operand:DI 0 "register_operand" "=f") (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))] "" "ftrunc.sd %1,%0") ;;- arithmetic instructions (define_insn "addsi3" [(set (match_operand:SI 0 "register_operand" "=r,*f") (plus:SI (match_operand:SI 1 "nonmemory_operand" "%r,*f") (match_operand:SI 2 "arith_operand" "rI,*f")))] "" "* { if (which_alternative == 1) return \"fiadd.ss %2,%1,%0\"; CC_STATUS_PARTIAL_INIT; return \"addu %2,%1,%0\"; }") (define_insn "adddi3" [(set (match_operand:DI 0 "register_operand" "=f") (plus:DI (match_operand:DI 1 "register_operand" "%f") (match_operand:DI 2 "register_operand" "f")))] "" "fiadd.dd %1,%2,%0") (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,*f") (minus:SI (match_operand:SI 1 "register_operand" "r,I,*f") (match_operand:SI 2 "arith_operand" "rI,r,*f")))] "" "* { if (which_alternative == 2) return \"fisub.ss %1,%2,%0\"; CC_STATUS_PARTIAL_INIT; if (REG_P (operands[2])) return \"subu %1,%2,%0\"; operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2])); return \"addu %2,%1,%0\"; }") (define_insn "subdi3" [(set (match_operand:DI 0 "register_operand" "=f") (minus:DI (match_operand:DI 1 "register_operand" "%f") (match_operand:DI 2 "register_operand" "f")))] "" "fisub.dd %1,%2,%0") (define_expand "mulsi3" [(set (subreg:SI (match_dup 4) 0) (match_operand:SI 1 "general_operand" "")) (set (subreg:SI (match_dup 5) 0) (match_operand:SI 2 "general_operand" "")) (clobber (match_dup 3)) (set (subreg:SI (match_dup 3) 0) (mult:SI (subreg:SI (match_dup 4) 0) (subreg:SI (match_dup 5) 0))) (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 0))] "" " { if (WORDS_BIG_ENDIAN) emit_insn (gen_mulsi3_big (operands[0], operands[1], operands[2])); else emit_insn (gen_mulsi3_little (operands[0], operands[1], operands[2])); DONE; }") (define_expand "mulsi3_little" [(set (subreg:SI (match_dup 4) 0) (match_operand:SI 1 "general_operand" "")) (set (subreg:SI (match_dup 5) 0) (match_operand:SI 2 "general_operand" "")) (clobber (match_dup 3)) (set (subreg:SI (match_dup 3) 0) (mult:SI (subreg:SI (match_dup 4) 0) (subreg:SI (match_dup 5) 0))) (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 0))] "! WORDS_BIG_ENDIAN" " { operands[3] = gen_reg_rtx (DImode); operands[4] = gen_reg_rtx (DImode); operands[5] = gen_reg_rtx (DImode); }") (define_expand "mulsi3_big" [(set (subreg:SI (match_dup 4) 1) (match_operand:SI 1 "general_operand" "")) (set (subreg:SI (match_dup 5) 1) (match_operand:SI 2 "general_operand" "")) (clobber (match_dup 3)) (set (subreg:SI (match_dup 3) 1) (mult:SI (subreg:SI (match_dup 4) 1) (subreg:SI (match_dup 5) 1))) (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 1))] "WORDS_BIG_ENDIAN" " { operands[3] = gen_reg_rtx (DImode); operands[4] = gen_reg_rtx (DImode); operands[5] = gen_reg_rtx (DImode); }") (define_insn "" [(set (subreg:SI (match_operand:DI 0 "register_operand" "=f") 0) (mult:SI (subreg:SI (match_operand:DI 1 "register_operand" "f") 0) (subreg:SI (match_operand:DI 2 "register_operand" "f") 0)))] "! WORDS_BIG_ENDIAN" "fmlow.dd %2,%1,%0") (define_insn "" [(set (subreg:SI (match_operand:DI 0 "register_operand" "=f") 1) (mult:SI (subreg:SI (match_operand:DI 1 "register_operand" "f") 1) (subreg:SI (match_operand:DI 2 "register_operand" "f") 1)))] "WORDS_BIG_ENDIAN" "fmlow.dd %2,%1,%0") ;;- and instructions (with compliment also) (define_insn "andsi3" [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (match_operand:SI 1 "nonmemory_operand" "%r") (match_operand:SI 2 "nonmemory_operand" "rL")))] "" "* { rtx xop[3]; CC_STATUS_PARTIAL_INIT; if (REG_P (operands[2]) || LOGIC_INT (operands[2])) return \"and %2,%1,%0\"; if ((INTVAL (operands[2]) & 0xffff) == 0) { operands[2] = gen_rtx (CONST_INT, VOIDmode, (unsigned) INTVAL (operands[2]) >> 16); return \"andh %2,%1,%0\"; } xop[0] = operands[0]; xop[1] = operands[1]; xop[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]) & 0xffff); output_asm_insn (\"andnot %2,%1,%0\", xop); operands[2] = gen_rtx (CONST_INT, VOIDmode, ~(unsigned) INTVAL (operands[2]) >> 16); return \"andnoth %2,%0,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (not:SI (match_operand:SI 1 "register_operand" "rn")) (match_operand:SI 2 "register_operand" "r")))] "" "* { rtx xop[3]; CC_STATUS_PARTIAL_INIT; if (REG_P (operands[1]) || LOGIC_INT (operands[1])) return \"andnot %1,%2,%0\"; if ((INTVAL (operands[1]) & 0xffff) == 0) { operands[1] = gen_rtx (CONST_INT, VOIDmode, (unsigned) INTVAL (operands[1]) >> 16); return \"andnoth %1,%2,%0\"; } xop[0] = operands[0]; xop[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) & 0xffff)); xop[2] = operands[2]; output_asm_insn (\"andnot %1,%2,%0\", xop); operands[1] = gen_rtx (CONST_INT, VOIDmode, (unsigned) INTVAL (operands[1]) >> 16); return \"andnoth %1,%0,%0\"; }") (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (match_operand:SI 1 "nonmemory_operand" "%r") (match_operand:SI 2 "nonmemory_operand" "rL")))] "" "* { rtx xop[3]; CC_STATUS_PARTIAL_INIT; if (REG_P (operands[2]) || LOGIC_INT (operands[2])) return \"or %2,%1,%0\"; if ((INTVAL (operands[2]) & 0xffff) == 0) { operands[2] = gen_rtx (CONST_INT, VOIDmode, (unsigned) INTVAL (operands[2]) >> 16); return \"orh %2,%1,%0\"; } xop[0] = operands[0]; xop[1] = operands[1]; xop[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) & 0xffff)); output_asm_insn (\"or %2,%1,%0\", xop); operands[2] = gen_rtx (CONST_INT, VOIDmode, (unsigned) INTVAL (operands[2]) >> 16); return \"orh %2,%0,%0\"; }") (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=r") (xor:SI (match_operand:SI 1 "nonmemory_operand" "%r") (match_operand:SI 2 "nonmemory_operand" "rL")))] "" "* { rtx xop[3]; CC_STATUS_PARTIAL_INIT; if (REG_P (operands[2]) || LOGIC_INT (operands[2])) return \"xor %2,%1,%0\"; if ((INTVAL (operands[2]) & 0xffff) == 0) { operands[2] = gen_rtx (CONST_INT, VOIDmode, (unsigned) INTVAL (operands[2]) >> 16); return \"xorh %2,%1,%0\"; } xop[0] = operands[0]; xop[1] = operands[1]; xop[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) & 0xffff)); output_asm_insn (\"xor %2,%1,%0\", xop); operands[2] = gen_rtx (CONST_INT, VOIDmode, (unsigned) INTVAL (operands[2]) >> 16); return \"xorh %2,%0,%0\"; }") ;(The i860 instruction set doesn't allow an immediate second operand in ; a subtraction.) (define_insn "negsi2" [(set (match_operand:SI 0 "general_operand" "=r") (neg:SI (match_operand:SI 1 "arith_operand" "r")))] "" "* { CC_STATUS_PARTIAL_INIT; return \"subu %?r0,%1,%0\"; }") (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "general_operand" "=r") (not:SI (match_operand:SI 1 "arith_operand" "r")))] "" "* { CC_STATUS_PARTIAL_INIT; return \"subu -1,%1,%0\"; }") ;; Floating point arithmetic instructions. (define_insn "adddf3" [(set (match_operand:DF 0 "register_operand" "=f") (plus:DF (match_operand:DF 1 "register_operand" "f") (match_operand:DF 2 "register_operand" "f")))] "" "fadd.dd %1,%2,%0") (define_insn "addsf3" [(set (match_operand:SF 0 "register_operand" "=f") (plus:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "" "fadd.ss %1,%2,%0") (define_insn "subdf3" [(set (match_operand:DF 0 "register_operand" "=f") (minus:DF (match_operand:DF 1 "register_operand" "f") (match_operand:DF 2 "register_operand" "f")))] "" "fsub.dd %1,%2,%0") (define_insn "subsf3" [(set (match_operand:SF 0 "register_operand" "=f") (minus:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "" "fsub.ss %1,%2,%0") (define_insn "muldf3" [(set (match_operand:DF 0 "register_operand" "=f") (mult:DF (match_operand:DF 1 "register_operand" "f") (match_operand:DF 2 "register_operand" "f")))] "" "fmul.dd %1,%2,%0") (define_insn "mulsf3" [(set (match_operand:SF 0 "register_operand" "=f") (mult:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "" "fmul.ss %1,%2,%0") (define_insn "negdf2" [(set (match_operand:DF 0 "register_operand" "=f") (neg:DF (match_operand:DF 1 "register_operand" "f")))] "" "fsub.dd %?f0,%1,%0") (define_insn "negsf2" [(set (match_operand:SF 0 "register_operand" "=f") (neg:SF (match_operand:SF 1 "register_operand" "f")))] "" "fsub.ss %?f0,%1,%0") (define_insn "divdf3" [(set (match_operand:DF 0 "register_operand" "=&f") (div:DF (match_operand:DF 1 "register_operand" "f") (match_operand:DF 2 "register_operand" "f"))) (clobber (match_scratch:DF 3 "=&f")) (clobber (match_scratch:DF 4 "=&f"))] "" "* { CC_STATUS_PARTIAL_INIT; if (((cc_prev_status.flags & CC_KNOW_HI_R31) == 0) || (cc_prev_status.flags & CC_HI_R31_ADJ) || (cc_prev_status.mdep != CONST2_RTX (SFmode))) { cc_status.flags |= CC_KNOW_HI_R31; cc_status.flags &= ~CC_HI_R31_ADJ; cc_status.mdep = CONST2_RTX (SFmode); return \"frcp.dd %2,%3\;fmul.dd %2,%3,%0\;fmov.dd %?f0,%4\;\\\ orh 0x4000,%?r0,%?r31\;ixfr %?r31,%R4\;fsub.dd %4,%0,%0\;\\\ fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\\ fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\\ fmul.dd %3,%1,%3\;fmul.dd %0,%3,%0\"; } else return \"frcp.dd %2,%3\;fmul.dd %2,%3,%0\;fmov.dd %?f0,%4\;\\\ ixfr %?r31,%R4\;fsub.dd %4,%0,%0\;\\\ fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\\ fmul.dd %3,%0,%3\;fmul.dd %2,%3,%0\;fsub.dd %4,%0,%0\;\\\ fmul.dd %3,%1,%3\;fmul.dd %0,%3,%0\"; }") (define_insn "divsf3" [(set (match_operand:SF 0 "register_operand" "=&f") (div:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f"))) (clobber (match_scratch:SF 3 "=&f")) (clobber (match_scratch:SF 4 "=&f"))] "" "* { CC_STATUS_PARTIAL_INIT; if (((cc_prev_status.flags & CC_KNOW_HI_R31) == 0) || (cc_prev_status.flags & CC_HI_R31_ADJ) || (cc_prev_status.mdep != CONST2_RTX (SFmode))) { cc_status.flags |= CC_KNOW_HI_R31; cc_status.flags &= ~CC_HI_R31_ADJ; cc_status.mdep = CONST2_RTX (SFmode); output_asm_insn (\"orh 0x4000,%?r0,%?r31\", operands); } return \"ixfr %?r31,%4\;frcp.ss %2,%0\;\\\ fmul.ss %2,%0,%3\;fsub.ss %4,%3,%3\;fmul.ss %0,%3,%0\;\\\ fmul.ss %2,%0,%3\;fsub.ss %4,%3,%3\;\\\ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\"; }") ;; Shift instructions ;; Optimized special case of shifting. ;; Must precede the general case. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m") (const_int 24)))] "" "* { if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) { CC_STATUS_INIT; cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; cc_status.mdep = XEXP (operands[1], 0); return \"orh %h1,%?r0,%?r31\;ld.b %L1(%?r31),%0\"; } return \"ld.b %1,%0\"; }") ;;- arithmetic shift instructions (define_insn "ashlsi3" [(set (match_operand:SI 0 "register_operand" "=r") (ashift:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "shift_operand" "rn")))] "" "* { return \"shl %2,%1,%0\"; }") (define_insn "ashlhi3" [(set (match_operand:HI 0 "register_operand" "=r") (ashift:HI (match_operand:HI 1 "register_operand" "r") (match_operand:HI 2 "shift_operand" "rn")))] "" "* { return \"shl %2,%1,%0\"; }") (define_insn "ashlqi3" [(set (match_operand:QI 0 "register_operand" "=r") (ashift:QI (match_operand:QI 1 "register_operand" "r") (match_operand:QI 2 "shift_operand" "rn")))] "" "* { return \"shl %2,%1,%0\"; }") (define_insn "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "shift_operand" "rn")))] "" "* { return \"shra %2,%1,%0\"; }") (define_insn "lshrsi3" [(set (match_operand:SI 0 "register_operand" "=r") (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "shift_operand" "rn")))] "" "* { return \"shr %2,%1,%0\"; }") ;; Unconditional and other jump instructions (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "* { return \"br %l0\;nop\"; }") ;; Here are two simple peepholes which fill the delay slot of ;; an unconditional branch. (define_peephole [(set (match_operand:SI 0 "register_operand" "=rf") (match_operand:SI 1 "single_insn_src_p" "gfG")) (set (pc) (label_ref (match_operand 2 "" "")))] "" "* return output_delayed_branch (\"br %l2\", operands, insn);") (define_peephole [(set (match_operand:SI 0 "memory_operand" "=m") (match_operand:SI 1 "reg_or_0_operand" "rfJ")) (set (pc) (label_ref (match_operand 2 "" "")))] "" "* return output_delayed_branch (\"br %l2\", operands, insn);") (define_insn "tablejump" [(set (pc) (match_operand:SI 0 "register_operand" "r")) (use (label_ref (match_operand 1 "" "")))] "" "bri %0\;nop") (define_peephole [(set (match_operand:SI 0 "memory_operand" "=m") (match_operand:SI 1 "reg_or_0_operand" "rfJ")) (set (pc) (match_operand:SI 2 "register_operand" "r")) (use (label_ref (match_operand 3 "" "")))] "" "* return output_delayed_branch (\"bri %2\", operands, insn);") ;;- jump to subroutine (define_expand "call" [(call (match_operand:SI 0 "memory_operand" "m") (match_operand 1 "" "i"))] ;; operand[2] is next_arg_register "" " { /* Make sure the address is just one reg and will stay that way. */ if (! call_insn_operand (operands[0], QImode)) operands[0] = change_address (operands[0], VOIDmode, copy_to_mode_reg (Pmode, XEXP (operands[0], 0))); if (INTVAL (operands[1]) > 0) { emit_move_insn (arg_pointer_rtx, stack_pointer_rtx); emit_insn (gen_rtx (USE, VOIDmode, arg_pointer_rtx)); } }") ;;- jump to subroutine (define_insn "" [(call (match_operand:SI 0 "call_insn_operand" "m") (match_operand 1 "" "i"))] ;; operand[2] is next_arg_register "" "* { /* strip the MEM. */ operands[0] = XEXP (operands[0], 0); CC_STATUS_INIT; if (GET_CODE (operands[0]) == REG) return \"calli %0\;nop\"; return \"call %0\;nop\"; }") (define_peephole [(set (match_operand:SI 0 "register_operand" "=rf") (match_operand:SI 1 "single_insn_src_p" "gfG")) (call (match_operand:SI 2 "memory_operand" "m") (match_operand 3 "" "i"))] ;;- Don't use operand 1 for most machines. "! reg_mentioned_p (operands[0], operands[2])" "* { /* strip the MEM. */ operands[2] = XEXP (operands[2], 0); if (GET_CODE (operands[2]) == REG) return output_delayed_branch (\"calli %2\", operands, insn); return output_delayed_branch (\"call %2\", operands, insn); }") (define_peephole [(set (match_operand:SI 0 "memory_operand" "=m") (match_operand:SI 1 "reg_or_0_operand" "rfJ")) (call (match_operand:SI 2 "call_insn_operand" "m") (match_operand 3 "" "i"))] ;;- Don't use operand 1 for most machines. "" "* { /* strip the MEM. */ operands[2] = XEXP (operands[2], 0); if (GET_CODE (operands[2]) == REG) return output_delayed_branch (\"calli %2\", operands, insn); return output_delayed_branch (\"call %2\", operands, insn); }") (define_expand "call_value" [(set (match_operand 0 "register_operand" "=rf") (call (match_operand:SI 1 "memory_operand" "m") (match_operand 2 "" "i")))] ;; operand 3 is next_arg_register "" " { /* Make sure the address is just one reg and will stay that way. */ if (! call_insn_operand (operands[1], QImode)) operands[1] = change_address (operands[1], VOIDmode, copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); if (INTVAL (operands[2]) > 0) { emit_move_insn (arg_pointer_rtx, stack_pointer_rtx); emit_insn (gen_rtx (USE, VOIDmode, arg_pointer_rtx)); } }") (define_insn "" [(set (match_operand 0 "register_operand" "=rf") (call (match_operand:SI 1 "call_insn_operand" "m") (match_operand 2 "" "i")))] ;; operand 3 is next_arg_register "" "* { /* strip the MEM. */ operands[1] = XEXP (operands[1], 0); CC_STATUS_INIT; if (GET_CODE (operands[1]) == REG) return \"calli %1\;nop\"; return \"call %1\;nop\"; }") (define_peephole [(set (match_operand:SI 0 "register_operand" "=rf") (match_operand:SI 1 "single_insn_src_p" "gfG")) (set (match_operand 2 "" "=rf") (call (match_operand:SI 3 "call_insn_operand" "m") (match_operand 4 "" "i")))] ;;- Don't use operand 4 for most machines. "! reg_mentioned_p (operands[0], operands[3])" "* { /* strip the MEM. */ operands[3] = XEXP (operands[3], 0); if (GET_CODE (operands[3]) == REG) return output_delayed_branch (\"calli %3\", operands, insn); return output_delayed_branch (\"call %3\", operands, insn); }") (define_peephole [(set (match_operand:SI 0 "memory_operand" "=m") (match_operand:SI 1 "reg_or_0_operand" "rJf")) (set (match_operand 2 "" "=rf") (call (match_operand:SI 3 "call_insn_operand" "m") (match_operand 4 "" "i")))] ;;- Don't use operand 4 for most machines. "" "* { /* strip the MEM. */ operands[3] = XEXP (operands[3], 0); if (GET_CODE (operands[3]) == REG) return output_delayed_branch (\"calli %3\", operands, insn); return output_delayed_branch (\"call %3\", operands, insn); }") ;; Call subroutine returning any type. (define_expand "untyped_call" [(parallel [(call (match_operand 0 "" "") (const_int 0)) (match_operand 1 "" "") (match_operand 2 "" "")])] "" " { int i; emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); for (i = 0; i < XVECLEN (operands[2], 0); i++) { rtx set = XVECEXP (operands[2], 0, i); emit_move_insn (SET_DEST (set), SET_SRC (set)); } /* The optimizer does not know that the call sets the function value registers we stored in the result block. We avoid problems by claiming that all hard registers are used and clobbered at this point. */ emit_insn (gen_blockage ()); DONE; }") ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and ;; all of memory. This blocks insns from being moved across this point. (define_insn "blockage" [(unspec_volatile [(const_int 0)] 0)] "" "") (define_insn "nop" [(const_int 0)] "" "nop") (define_insn "indirect_jump" [(set (pc) (match_operand:SI 0 "register_operand" "r"))] "" "bri %0") ;; ;; A special insn that does the work to get setup just ;; before a table jump. ;; (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") (label_ref (match_operand 2 "" "")))))] "" "* { CC_STATUS_INIT; return \"orh %H2,%?r0,%?r31\;or %L2,%?r31,%?r31\;ld.l %?r31(%1),%0\"; }") (define_peephole [(set (match_operand:SI 0 "register_operand" "=rf") (match_operand:SI 1 "single_insn_src_p" "gfG")) (set (pc) (match_operand:SI 2 "register_operand" "r")) (use (label_ref (match_operand 3 "" "")))] "REGNO (operands[0]) != REGNO (operands[2])" "* return output_delayed_branch (\"bri %2\", operands, insn);") gcc-2.5.8/config/i860/mach.h100444 22011 13 1107 5453234606 14005 0ustar kenneruser/* Configuration for an i860 running Mach as the target machine. */ #include "i860/i860.h" #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (i860 Mach3.x)"); #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dunix -Di860 -DMACH -Asystem(unix) -Asystem(mach) -Acpu(i860) -Amachine(i860)" /* Specify extra dir to search for include files. */ #define SYSTEM_INCLUDE_DIR "/usr/mach/include" /* Don't default to pcc-struct-return, because gcc is the only compiler, and we want to retain compatibility with older gcc versions. */ #define DEFAULT_PCC_STRUCT_RETURN 0 gcc-2.5.8/config/i860/paragon.h100444 22011 13 17037 5466476413 14565 0ustar kenneruser/* Target definitions for GNU compiler for Intel 80860 running OSF/1AD Copyright (C) 1991 Free Software Foundation, Inc. Based upon original work of Ron Guilmette (rfg@ncd.com). Whacked into submission by Andy Pfiffer (andyp@ssd.intel.com). Partially inspired by Pete Beckman @ Indiana University (beckman@cs.indiana.edu) Harry Dolan of Intel Corporation (dolan@ssd.intel.com) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "i860/i860.h" #include "svr3.h" /* For the sake of libgcc2.c, indicate target supports atexit. */ #define HAVE_ATEXIT #undef TARGET_SWITCHES #define TARGET_SWITCHES \ { {"xp", 1}, \ {"noxp", -1}, \ {"xr", -1}, \ {"noieee", -1}, \ {"nx", 2}, \ { "", TARGET_DEFAULT}} #undef TARGET_DEFAULT #define TARGET_DEFAULT 1 /* The Intel as860 assembler does not understand .stabs, must use COFF */ #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (i860 OSF/1AD)"); #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Di860 -D__i860 -D__i860__ -D__PARAGON__ -D__OSF1__ -D_COFF -Dunix -DMACH -DCMU" #define CPP_SPEC "%{mnx:-D__NODE}" /* autoinit.o autolaunches NX applications */ #define STARTFILE_SPEC "-ycrt0.o%s %{mnx:-yoptions/autoinit.o%s}" /* libic.a is the PGI intrisic library */ /* libpm.o and guard.o are for the performance monitoring modules (ignored) */ /* /usr/lib/noieee contains non-IEEE compliant (but faster) math routines */ #if HAVE_DASH_G #define LIB_SPEC "%{mnoieee:-L/usr/lib/noieee} -L/usr/lib %{mnx:-lnx -lmach} % {g*:-lg} -lc -lic" #else /* HAVE_DASH_G */ /* can't use -g for -lg; libg.a doesn't have a symbol table and ld complains */ #define LIB_SPEC "%{mnoieee:-L/usr/lib/noieee} -L/usr/lib %{mnx:-lnx -lmach} -lc -lic" #endif /* HAVE_DASH_G */ /* Get rid of definition from svr3.h. */ #undef SIZE_TYPE #undef I860_REG_PREFIX #undef ASM_COMMENT_START #define ASM_COMMENT_START "//" #undef TYPE_OPERAND_FMT #define TYPE_OPERAND_FMT "\"%s\"" #define DBX_REGISTER_NUMBER(REGNO) (REGNO) #undef ASCII_DATA_ASM_OP #define ASCII_DATA_ASM_OP ".byte" /* * the assembler we're using doesn't grok .ident... */ #undef ASM_OUTPUT_IDENT #define ASM_OUTPUT_IDENT(FILE, NAME) \ fprintf (FILE, "//\t.ident \"%s\"\n", NAME); /* * the assembler doesn't grok .double INF and the like * but does understand .long with hex numbers, so special * case the "symbolic" IEEE numbers. */ #undef ASM_OUTPUT_DOUBLE #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ { \ if (REAL_VALUE_ISINF (VALUE) \ || REAL_VALUE_ISNAN (VALUE) \ || REAL_VALUE_MINUS_ZERO (VALUE)) \ { \ long t[2]; \ REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n", t[0], t[1]); \ } \ else \ fprintf (FILE, "\t.double %.20e\n", VALUE); \ } #undef ASM_OUTPUT_FLOAT #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ { \ if (REAL_VALUE_ISINF (VALUE) \ || REAL_VALUE_ISNAN (VALUE) \ || REAL_VALUE_MINUS_ZERO (VALUE)) \ { \ long t; \ REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ fprintf (FILE, "\t.long 0x%lx\n", t); \ } \ else \ fprintf (FILE, "\t.float %.12e\n", VALUE); \ } #undef ASM_OUTPUT_ASCII #define ASM_OUTPUT_ASCII(FILE, STR, LENGTH) \ do \ { \ register unsigned char *str = (unsigned char *) (STR); \ register unsigned char *limit = str + (LENGTH); \ register unsigned bytes_in_chunk = 0; \ for (; str < limit; str++) \ { \ register unsigned ch = *str; \ if (ch < 32 || ch == '\\' || ch == '"' || ch >= 127) \ { \ if (bytes_in_chunk > 0) \ { \ fprintf ((FILE), "\"\n"); \ bytes_in_chunk = 0; \ } \ fprintf ((FILE), "\t%s\t%d\n", ASM_BYTE_OP, ch); \ } \ else \ { \ if (bytes_in_chunk >= 60) \ { \ fprintf ((FILE), "\"\n"); \ bytes_in_chunk = 0; \ } \ if (bytes_in_chunk == 0) \ fprintf ((FILE), "\t%s\t\"", ASCII_DATA_ASM_OP);\ putc (ch, (FILE)); \ bytes_in_chunk++; \ } \ } \ if (bytes_in_chunk > 0) \ fprintf ((FILE), "\"\n"); \ } \ while (0) /* This says how to output an assembler line to define a local common symbol. */ #undef ASM_OUTPUT_LOCAL #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( fputs (".lcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (ROUNDED))) /* * not defining ASM_STABS_OP yields .stabs in the .s file * when using g++ -- so, I'll define it. */ #define ASM_STABS_OP "//.stabs" /* Define this macro if an argument declared as `char' or `short' in a prototype should actually be passed as an `int'. In addition to avoiding errors in certain cases of mismatch, it also makes for better code on certain machines. */ /*#define PROMOTE_PROTOTYPES*/ /* Define this macro if an instruction to load a value narrower than a word from memory into a register also zero-extends the value to the whole register. */ /*#define BYTE_LOADS_ZERO_EXTEND*/ /* Define this macro as a C expression which is nonzero if accessing less than a word of memory (i.e. a `char' or a `short') is no faster than accessing a word of memory, i.e., if such access require more than one instruction or if there is no difference in cost between byte and (aligned) word loads. On RISC machines, it tends to generate better code to define this as 1, since it avoids making a QI or HI mode register. */ /* #undef SLOW_BYTE_ACCESS #define SLOW_BYTE_ACCESS 1 */ /* Define if shifts truncate the shift count which implies one can omit a sign-extension or zero-extension of a shift count. */ #define SHIFT_COUNT_TRUNCATED 1 #define FASTEST_ALIGNMENT 32 /* Make strings word-aligned so strcpy from constants will be faster. */ #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ (TREE_CODE (EXP) == STRING_CST \ && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) /* Make arrays of chars word-aligned for the same reasons. */ #define DATA_ALIGNMENT(TYPE, ALIGN) \ (TREE_CODE (TYPE) == ARRAY_TYPE \ && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) /* * disable a few things picked up from svr3.h */ #undef INIT_SECTION_ASM_OP #undef FINI_SECTION_ASM_OP #undef CONST_SECTION_ASM_OP #undef CTORS_SECTION_ASM_OP #undef DTORS_SECTION_ASM_OP #undef DO_GLOBAL_CTORS_BODY #undef ASM_OUTPUT_DESTRUCTOR #undef SELECT_SECTION #undef SELECT_RTX_SECTION #undef READONLY_DATA_SECTION #define BSS_SECTION_ASM_OP ".bss" /* XXX */ #undef EXTRA_SECTIONS #define EXTRA_SECTIONS in_bss #undef EXTRA_SECTION_FUNCTIONS #define EXTRA_SECTION_FUNCTIONS \ BSS_SECTION_FUNCTION gcc-2.5.8/config/i860/sysv3.h100444 22011 13 13323 5453234611 14203 0ustar kenneruser/* Target definitions for GNU compiler for Intel 80860 running System V.3 Copyright (C) 1991 Free Software Foundation, Inc. Written by Ron Guilmette (rfg@ncd.com). This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "i860/i860.h" #include "svr3.h" #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (i860, System V Release 3)") /* Provide a set of pre-definitions and pre-assertions appropriate for the i860 running svr3. */ #define CPP_PREDEFINES "-Di860 -Dunix -D__svr3__ -Asystem(unix) -Asystem(svr3) -Acpu(i860) -Amachine(i860)" /* Use crt1.o as a startup file and crtn.o as a closing file. */ #define STARTFILE_SPEC \ "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}" #define LIB_SPEC "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} -lc crtn.o%s" /* Special flags for the linker. I don't know what they do. */ #define LINK_SPEC "%{T*} %{z:-lm}" /* The prefix to be used in assembler output for all names of registers. None is needed in V.3. */ #define I860_REG_PREFIX "" /* Delimiter that starts comments in the assembler code. */ #define ASM_COMMENT_START "//" /* Don't renumber the regusters for debugger output. */ #define DBX_REGISTER_NUMBER(REGNO) (REGNO) /* Output the special word the System V SDB wants to see just before the first word of each function's prologue code. */ extern char *current_function_original_name; /* This special macro is used to output a magic word just before the first word of each function. On some versions of UNIX running on the i860, this word can be any word that looks like a NOP, however under svr4, this neds to be an `shr r0,r0,r0' instruction in which the normally unused low-order bits contain the length of the function prologue code (in bytes). This is needed to make the System V SDB debugger happy. */ #undef ASM_OUTPUT_FUNCTION_PREFIX #define ASM_OUTPUT_FUNCTION_PREFIX(FILE, FNNAME) \ do { ASM_OUTPUT_ALIGN (FILE, 2); \ fprintf ((FILE), "\t.long\t.ep."); \ assemble_name (FILE, FNNAME); \ fprintf (FILE, "-"); \ assemble_name (FILE, FNNAME); \ fprintf (FILE, "+0xc8000000\n"); \ current_function_original_name = (FNNAME); \ } while (0) /* Output the special label that must go just after each function's prologue code to support svr4 SDB. */ #define ASM_OUTPUT_PROLOGUE_SUFFIX(FILE) \ do { fprintf (FILE, ".ep."); \ assemble_name (FILE, current_function_original_name); \ fprintf (FILE, ":\n"); \ } while (0) /* This says how to output an assembler line to define a local common symbol. The difference from svr3.h is we don't limit align to 2. */ #undef ASM_OUTPUT_LOCAL #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ do { \ int align = exact_log2 (ROUNDED); \ data_section (); \ ASM_OUTPUT_ALIGN ((FILE), align == -1 ? 2 : align); \ ASM_OUTPUT_LABEL ((FILE), (NAME)); \ fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED)); \ } while (0) /* The routine used to output string literals. #define ASCII_DATA_ASM_OP ".byte" #define ASM_OUTPUT_ASCII(FILE, STR, LENGTH) \ do \ { \ register unsigned char *str = (unsigned char *) (STR); \ register unsigned char *limit = str + (LENGTH); \ register unsigned bytes_in_chunk = 0; \ for (; str < limit; str++) \ { \ register unsigned ch = *str; \ if (ch < 32 || ch == '\\' || ch == '"' || ch >= 127) \ { \ if (bytes_in_chunk > 0) \ { \ fprintf ((FILE), "\"\n"); \ bytes_in_chunk = 0; \ } \ fprintf ((FILE), "\t%s\t%d\n", ASM_BYTE_OP, ch); \ } \ else \ { \ if (bytes_in_chunk >= 60) \ { \ fprintf ((FILE), "\"\n"); \ bytes_in_chunk = 0; \ } \ if (bytes_in_chunk == 0) \ fprintf ((FILE), "\t%s\t\"", ASCII_DATA_ASM_OP); \ putc (ch, (FILE)); \ bytes_in_chunk++; \ } \ } \ if (bytes_in_chunk > 0) \ fprintf ((FILE), "\"\n"); \ } \ while (0) #undef CTORS_SECTION_ASM_OP #define CTORS_SECTION_ASM_OP ".section\t.ctors,\"x\"" #undef DTORS_SECTION_ASM_OP #define DTORS_SECTION_ASM_OP ".section\t.dtors,\"x\"" /* Add definitions to support the .tdesc section as specified in the svr4 ABI for the i860. */ #define TDESC_SECTION_ASM_OP ".section\t.tdesc" #undef EXTRA_SECTIONS #define EXTRA_SECTIONS in_const, in_ctors, in_dtors, in_tdesc #undef EXTRA_SECTION_FUNCTIONS #define EXTRA_SECTION_FUNCTIONS \ CONST_SECTION_FUNCTION \ CTORS_SECTION_FUNCTION \ DTORS_SECTION_FUNCTION \ TDESC_SECTION_FUNCTION #define TDESC_SECTION_FUNCTION \ void \ tdesc_section () \ { \ if (in_section != in_tdesc) \ { \ fprintf (asm_out_file, "%s\n", TDESC_SECTION_ASM_OP); \ in_section = in_tdesc; \ } \ } /* Enable the `const' section that svr3.h defines how to use. */ #undef USE_CONST_SECTION #define USE_CONST_SECTION 1 gcc-2.5.8/config/i860/sysv4.h100444 22011 13 15335 5453234615 14215 0ustar kenneruser/* Target definitions for GNU compiler for Intel 80860 running System V.4 Copyright (C) 1991 Free Software Foundation, Inc. Written by Ron Guilmette (rfg@ncd.com). This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "i860/i860.h" #include "svr4.h" #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (i860 System V Release 4)"); /* Provide a set of pre-definitions and pre-assertions appropriate for the i860 running svr4. Note that the symbol `__svr4__' MUST BE DEFINED! It is needed so that the va_list struct in va-i860.h will get correctly defined for the svr4 (ABI compliant) case rather than for the previous (svr3, svr2, ...) case. It also needs to be defined so that the correct (svr4) version of __builtin_saveregs will be selected when we are building gnulib2.c. __svr4__ is our extension. */ #define CPP_PREDEFINES \ "-Di860 -Dunix -DSVR4 -D__svr4__ -Asystem(unix) -Asystem(svr4) -Acpu(i860) -Amachine(i860)" /* The prefix to be used in assembler output for all names of registers. This string gets prepended to all i860 register names (svr4 only). */ #define I860_REG_PREFIX "%" #define ASM_COMMENT_START "#" #undef TYPE_OPERAND_FMT #define TYPE_OPERAND_FMT "\"%s\"" #define DBX_REGISTER_NUMBER(REGNO) (REGNO) /* The following macro definition overrides the one in i860.h because the svr4 i860 assembler requires a different syntax for getting parts of constant/relocatable values. */ #undef PRINT_OPERAND_PART #define PRINT_OPERAND_PART(FILE, X, PART_CODE) \ do { fprintf (FILE, "["); \ output_address (X); \ fprintf (FILE, "]@%s", PART_CODE); \ } while (0) /* If the host and target formats match, output the floats as hex. */ #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT #if defined (HOST_WORDS_BIG_ENDIAN) == WORDS_BIG_ENDIAN /* This is how to output an assembler line defining a `double' constant. Note that the native i860/svr4 ELF assembler can't properly handle infinity. It generates an incorrect (non-infinity) value when given `.double 99e9999' and it doesn't grok `inf' at all. It also mishandles NaNs and -0.0. */ #undef ASM_OUTPUT_DOUBLE #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ { \ if (REAL_VALUE_ISINF (VALUE) \ || REAL_VALUE_ISNAN (VALUE) \ || REAL_VALUE_MINUS_ZERO (VALUE)) \ { \ long t[2]; \ REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ fprintf (FILE, "\t.word 0x%lx\n\t.word 0x%lx\n", t[0], t[1]); \ } \ else \ fprintf (FILE, "\t.double %.20e\n", VALUE); \ } /* This is how to output an assembler line defining a `float' constant. Note that the native i860/svr4 ELF assembler can't properly handle infinity. It actually generates an assembly time error when given `.float 99e9999' and it doesn't grok `inf' at all. It also mishandles NaNs and -0.0. */ #undef ASM_OUTPUT_FLOAT #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ { \ if (REAL_VALUE_ISINF (VALUE) \ || REAL_VALUE_ISNAN (VALUE) \ || REAL_VALUE_MINUS_ZERO (VALUE)) \ { \ long t; \ REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ fprintf (FILE, "\t.word 0x%lx\n", t); \ } \ else \ fprintf (FILE, "\t.float %.12e\n", VALUE); \ } #endif /* word order matches */ #endif /* HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT */ #undef ASM_FILE_START #define ASM_FILE_START(FILE) \ do { output_file_directive (FILE, main_input_filename); \ fprintf (FILE, "\t.version\t\"01.01\"\n"); \ } while (0) /* Output the special word the svr4 SDB wants to see just before the first word of each function's prologue code. */ extern char *current_function_original_name; /* This special macro is used to output a magic word just before the first word of each function. On some versions of UNIX running on the i860, this word can be any word that looks like a NOP, however under svr4, this neds to be an `shr r0,r0,r0' instruction in which the normally unused low-order bits contain the length of the function prologue code (in bytes). This is needed to make the svr4 SDB debugger happy. */ #undef ASM_OUTPUT_FUNCTION_PREFIX #define ASM_OUTPUT_FUNCTION_PREFIX(FILE, FNNAME) \ do { ASM_OUTPUT_ALIGN (FILE, 2); \ fprintf ((FILE), "\t.long\t.ep."); \ assemble_name (FILE, FNNAME); \ fprintf (FILE, "-"); \ assemble_name (FILE, FNNAME); \ fprintf (FILE, "+0xc8000000\n"); \ current_function_original_name = (FNNAME); \ } while (0) /* Output the special label that must go just after each function's prologue code to support svr4 SDB. */ #define ASM_OUTPUT_PROLOGUE_SUFFIX(FILE) \ do { fprintf (FILE, ".ep."); \ assemble_name (FILE, current_function_original_name); \ fprintf (FILE, ":\n"); \ } while (0) #undef CTORS_SECTION_ASM_OP #define CTORS_SECTION_ASM_OP ".section\t.ctors,\"a\",\"progbits\"" #undef DTORS_SECTION_ASM_OP #define DTORS_SECTION_ASM_OP ".section\t.dtors,\"a\",\"progbits\"" /* Add definitions to support the .tdesc section as specified in the svr4 ABI for the i860. */ #define TDESC_SECTION_ASM_OP ".section\t.tdesc" #undef EXTRA_SECTIONS #define EXTRA_SECTIONS in_const, in_ctors, in_dtors, in_tdesc #undef EXTRA_SECTION_FUNCTIONS #define EXTRA_SECTION_FUNCTIONS \ CONST_SECTION_FUNCTION \ CTORS_SECTION_FUNCTION \ DTORS_SECTION_FUNCTION \ TDESC_SECTION_FUNCTION #define TDESC_SECTION_FUNCTION \ void \ tdesc_section () \ { \ if (in_section != in_tdesc) \ { \ fprintf (asm_out_file, "%s\n", TDESC_SECTION_ASM_OP); \ in_section = in_tdesc; \ } \ } #ifdef OUTPUT_TDESC #undef ASM_FILE_END #define ASM_FILE_END(FILE) \ do { \ if (current_function_original_name != NULL) { \ tdesc_section(); \ fprintf ((FILE), "%s __ETEXT\n", ASM_LONG); \ fprintf ((FILE), "%s 0\n", ASM_LONG); \ text_section(); \ fputs("__ETEXT:\n", (FILE)); \ } \ fprintf ((FILE), "\t.ident\t\"GCC: (GNU) %s\"\n", \ version_string); \ } while (0) #endif gcc-2.5.8/config/i860/t-fx2800100444 22011 13 465 5235133553 14022 0ustar kenneruser # The Alliant FX2800 uses ELF object files, so needs these two modules # just as SVR4 does. -- hyc@hanauma.jpl.nasa.gov EXTRA_PARTS=crtbegin.o crtend.o # Use ieee rounding rules for divide and square root operations. # /bin/cc is assumed to point to fxc version 1.3 or newer. CCLIBFLAGS=-O -ieee -uniproc gcc-2.5.8/config/i860/x-fx2800100444 22011 13 375 5235133650 14024 0ustar kenneruser # The Alliant FX2800 is supposed to conform to the SysV R4 i860 ABI, # but apparently the native compiler generates non ABI-compliant # function prologues and epilogues, so we need the alloca from emacs. # -- hyc@hanauma.jpl.nasa.gov ALLOCA=alloca.o gcc-2.5.8/config/i860/x-sysv3100444 22011 13 20 5235134036 14126 0ustar kenneruserALLOCA=alloca.o gcc-2.5.8/config/i860/x-sysv4100444 22011 13 4543 5376522715 14220 0ustar kenneruser# The svr4 reference port for the i860 contains an alloca.o routine # in /usr/ucblib/libucb.a, but we can't just try to get that by # setting CLIB to /usr/ucblib/libucb.a because (unfortunately) # there are a lot of other routines in libucb.a which are supposed # to be the Berkeley versions of library routines normally found in # libc.a and many of these Berkeley versions are badly broken. Thus, # if we try to link programs with libucb.a before libc.a, those # programs tend to crash. # Also, the alloca() routine supplied in early version of svr4 for # the i860 is non-ABI compliant. It doesn't keep the stack aligned # to a 16-byte boundary as the ABI requires. # More importantly however, even a fully ABI compliant alloca() routine # would fail to work correctly with some versions of the native svr4 C # compiler currently being distributed for the i860 (as of 1/29/92). # The problem is that the native C compiler generates non-ABI-compliant # function epilogues which cut back the stack (upon function exit) in # an incorrect manner. Specifically, they cut back the stack by adding # the nominal *static* frame size (determined statically at compile-time) # to the stack pointer rather than setting the stack pointer based upon # the current value of the frame pointer (as called for in the i860 ABI). # This can cause serious trouble in cases where you repeatedly call a # routine which itself calls alloca(). In such cases, the stack will # grow continuously until you finally run out of swap space or exceed # the system's process size limit. To avoid this problem (which can # arise when a stage1 gcc is being used to build a stage2 gcc) you # *must* link in the C language version of alloca() which is supplied # with gcc to your stage1 version of gcc. The following definition # forces that to happen. ALLOCA=alloca.o # We build all stages *without* shared libraries because that may make # debugging the compiler easier (until there is a GDB which supports # both Dwarf *and* svr4 shared libraries). # Note that the native C compiler for the svr4 reference port on the # i860 recognizes a special -gg option. Using that option causes *full* # Dwarf debugging information to be generated, whereas using only -g # causes only limited Dwarf debugging information to be generated. # (This is an undocumented feature of the native svr4 C compiler.) CCLIBFLAGS=-Bstatic -dn -gg gcc-2.5.8/config/i860/xm-fx2800.h100444 22011 13 504 5455115376 14432 0ustar kenneruser/* Alliant FX/2800 running Concentrix 2.x. */ #include "i860/xm-i860.h" /* * vfprintf is not present prior to Concentrix 2.2. Unfortunately, there * does not seem to be a cpp symbol that identifies OS revision. Undefine * the following if running 2.1 or older. * -- hyc@hanauma.jpl.nasa.gov */ #define HAVE_VPRINTF gcc-2.5.8/config/i860/xm-i860.h100444 22011 13 2463 5413066443 14211 0ustar kenneruser/* Configuration for GNU C-compiler for Intel i860. Copyright (C) 1988, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef i860 #define i860 #endif /* #defines that need visibility everywhere. */ #define FALSE 0 #define TRUE 1 /* This describes the machine the compiler is hosted on. */ #define HOST_BITS_PER_CHAR 8 #define HOST_BITS_PER_SHORT 16 #define HOST_BITS_PER_INT 32 #define HOST_BITS_PER_LONG 32 #define HOST_BITS_PER_LONGLONG 64 /* Arguments to use with `exit'. */ #define SUCCESS_EXIT_CODE 0 #define FATAL_EXIT_CODE 33 /* target machine dependencies. tm.h is a symbolic link to the actual target specific file. */ #include "tm.h" gcc-2.5.8/config/i860/xm-paragon.h100444 22011 13 155 5463331741 15127 0ustar kenneruser/* Configuration for GCC for Intel i860 running OSF/1AD. */ #include "i860/xm-i860.h" #include "xm-svr3.h" gcc-2.5.8/config/i860/xm-sysv3.h100444 22011 13 170 5322503300 14546 0ustar kenneruser/* Configuration for GCC for Intel i860 running System V Release 3. */ #include "i860/xm-i860.h" #include "xm-svr3.h" gcc-2.5.8/config/i860/xm-sysv4.h100444 22011 13 170 5322503270 14555 0ustar kenneruser/* Configuration for GCC for Intel i860 running System V Release 4. */ #include "i860/xm-i860.h" #include "xm-svr4.h" gcc-2.5.8/config/i960/ 40777 22011 13 0 5502603156 12632 5ustar kennerusergcc-2.5.8/config/i960/i960.c100444 22011 13 162011 5425531171 13616 0ustar kenneruser/* Subroutines used for code generation on intel 80960. Copyright (C) 1992 Free Software Foundation, Inc. Contributed by Steven McGeady, Intel Corp. Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include "config.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "output.h" #include "insn-attr.h" #include "flags.h" #include "tree.h" #include "insn-codes.h" #include "assert.h" #include "expr.h" #include "function.h" #include "recog.h" #include /* Save the operands last given to a compare for use when we generate a scc or bcc insn. */ rtx i960_compare_op0, i960_compare_op1; /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS macro in i960.h. */ static int i960_maxbitalignment; static int i960_last_maxbitalignment; /* Used to implement switching between MEM and ALU insn types, for better C series performance. */ enum insn_types i960_last_insn_type; /* The leaf-procedure return register. Set only if this is a leaf routine. */ static int i960_leaf_ret_reg; /* True if replacing tail calls with jumps is OK. */ static int tail_call_ok; /* A string containing a list of insns to emit in the epilogue so as to restore all registers saved by the prologue. Created by the prologue code as it saves registers away. */ char epilogue_string[1000]; /* A unique number (per function) for return labels. */ static int ret_label = 0; #if 0 /* Handle pragmas for compatibility with Intel's compilers. */ /* ??? This is incomplete, since it does not handle all pragmas that the intel compilers understand. Also, it needs to be rewritten to accept a stream instead of a string for GCC 2. */ void process_pragma(str) char *str; { int align; int i; if ((i = sscanf (str, " align %d", &align)) == 1) switch (align) { case 0: /* Return to last alignment. */ align = i960_last_maxbitalignment / 8; case 16: /* Byte alignments. */ case 8: case 4: case 2: case 1: i960_last_maxbitalignment = i960_maxbitalignment; i960_maxbitalignment = align * 8; break; default: /* Unknown, silently ignore. */ break; } /* NOTE: ic960 R3.0 pragma align definition: #pragma align [(size)] | (identifier=size[,...]) #pragma noalign [(identifier)[,...]] (all parens are optional) - size is [1,2,4,8,16] - noalign means size==1 - applies only to component elements of a struct (and union?) - identifier applies to structure tag (only) - missing identifier means next struct - alignment rules for bitfields need more investigation */ /* Should be pragma 'far' or equivalent for callx/balx here. */ } #endif /* Initialize variables before compiling any files. */ void i960_initialize () { if (TARGET_IC_COMPAT2_0) { i960_maxbitalignment = 8; i960_last_maxbitalignment = 128; } else { i960_maxbitalignment = 128; i960_last_maxbitalignment = 8; } } /* Return true if OP can be used as the source of an fp move insn. */ int fpmove_src_operand (op, mode) rtx op; enum machine_mode mode; { return (GET_CODE (op) == CONST_DOUBLE || general_operand (op, mode)); } #if 0 /* Return true if OP is a register or zero. */ int reg_or_zero_operand (op, mode) rtx op; enum machine_mode mode; { return register_operand (op, mode) || op == const0_rtx; } #endif /* Return truth value of whether OP can be used as an operands in a three address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */ int arith_operand (op, mode) rtx op; enum machine_mode mode; { return (register_operand (op, mode) || literal (op, mode)); } /* Return true if OP is a register or a valid floating point literal. */ int fp_arith_operand (op, mode) rtx op; enum machine_mode mode; { return (register_operand (op, mode) || fp_literal (op, mode)); } /* Return true is OP is a register or a valid signed integer literal. */ int signed_arith_operand (op, mode) rtx op; enum machine_mode mode; { return (register_operand (op, mode) || signed_literal (op, mode)); } /* Return truth value of whether OP is a integer which fits the range constraining immediate operands in three-address insns. */ int literal (op, mode) rtx op; enum machine_mode mode; { return ((GET_CODE (op) == CONST_INT) && INTVAL(op) >= 0 && INTVAL(op) < 32); } /* Return true if OP is a float constant of 1. */ int fp_literal_one (op, mode) rtx op; enum machine_mode mode; { return (TARGET_NUMERICS && (mode == VOIDmode || mode == GET_MODE (op)) && (op == CONST1_RTX (mode))); } /* Return true if OP is a float constant of 0. */ int fp_literal_zero (op, mode) rtx op; enum machine_mode mode; { return (TARGET_NUMERICS && (mode == VOIDmode || mode == GET_MODE (op)) && (op == CONST0_RTX (mode))); } /* Return true if OP is a valid floating point literal. */ int fp_literal(op, mode) rtx op; enum machine_mode mode; { return fp_literal_zero (op, mode) || fp_literal_one (op, mode); } /* Return true if OP is a valid signed immediate constant. */ int signed_literal(op, mode) rtx op; enum machine_mode mode; { return ((GET_CODE (op) == CONST_INT) && INTVAL(op) > -32 && INTVAL(op) < 32); } /* Return truth value of statement that OP is a symbolic memory operand of mode MODE. */ int symbolic_memory_operand (op, mode) rtx op; enum machine_mode mode; { if (GET_CODE (op) == SUBREG) op = SUBREG_REG (op); if (GET_CODE (op) != MEM) return 0; op = XEXP (op, 0); return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); } /* Return truth value of whether OP is EQ or NE. */ int eq_or_neq (op, mode) rtx op; enum machine_mode mode; { return (GET_CODE (op) == EQ || GET_CODE (op) == NE); } /* OP is an integer register or a constant. */ int arith32_operand (op, mode) rtx op; enum machine_mode mode; { if (register_operand (op, mode)) return 1; return (CONSTANT_P (op)); } /* Return true if OP is an integer constant which is a power of 2. */ int power2_operand (op,mode) rtx op; enum machine_mode mode; { if (GET_CODE (op) != CONST_INT) return 0; return exact_log2 (INTVAL (op)) >= 0; } /* Return true if OP is an integer constant which is the complement of a power of 2. */ int cmplpower2_operand (op, mode) rtx op; enum machine_mode mode; { if (GET_CODE (op) != CONST_INT) return 0; return exact_log2 (~ INTVAL (op)) >= 0; } /* If VAL has only one bit set, return the index of that bit. Otherwise return -1. */ int bitpos (val) unsigned int val; { register int i; for (i = 0; val != 0; i++, val >>= 1) { if (val & 1) { if (val != 1) return -1; return i; } } return -1; } /* Return non-zero if OP is a mask, i.e. all one bits are consecutive. The return value indicates how many consecutive non-zero bits exist if this is a mask. This is the same as the next function, except that it does not indicate what the start and stop bit positions are. */ int is_mask (val) unsigned int val; { register int start, end, i; start = -1; for (i = 0; val != 0; val >>= 1, i++) { if (val & 1) { if (start < 0) start = i; end = i; continue; } /* Still looking for the first bit. */ if (start < 0) continue; /* We've seen the start of a bit sequence, and now a zero. There must be more one bits, otherwise we would have exited the loop. Therefore, it is not a mask. */ if (val) return 0; } /* The bit string has ones from START to END bit positions only. */ return end - start + 1; } /* If VAL is a mask, then return nonzero, with S set to the starting bit position and E set to the ending bit position of the mask. The return value indicates how many consecutive bits exist in the mask. This is the same as the previous function, except that it also indicates the start and end bit positions of the mask. */ int bitstr (val, s, e) unsigned int val; int *s, *e; { register int start, end, i; start = -1; end = -1; for (i = 0; val != 0; val >>= 1, i++) { if (val & 1) { if (start < 0) start = i; end = i; continue; } /* Still looking for the first bit. */ if (start < 0) continue; /* We've seen the start of a bit sequence, and now a zero. There must be more one bits, otherwise we would have exited the loop. Therefor, it is not a mask. */ if (val) { start = -1; end = -1; break; } } /* The bit string has ones from START to END bit positions only. */ *s = start; *e = end; return ((start < 0) ? 0 : end - start + 1); } /* Return the machine mode to use for a comparison. */ enum machine_mode select_cc_mode (op, x) RTX_CODE op; rtx x; { if (op == GTU || op == LTU || op == GEU || op == LEU) return CC_UNSmode; return CCmode; } /* X and Y are two things to compare using CODE. Emit the compare insn and return the rtx for register 36 in the proper mode. */ rtx gen_compare_reg (code, x, y) enum rtx_code code; rtx x, y; { rtx cc_reg; enum machine_mode ccmode = SELECT_CC_MODE (code, x, y); enum machine_mode mode = GET_MODE (x) == VOIDmode ? GET_MODE (y) : GET_MODE (x); if (mode == SImode) { if (! arith_operand (x, mode)) x = force_reg (SImode, x); if (! arith_operand (y, mode)) y = force_reg (SImode, y); } cc_reg = gen_rtx (REG, ccmode, 36); emit_insn (gen_rtx (SET, VOIDmode, cc_reg, gen_rtx (COMPARE, ccmode, x, y))); return cc_reg; } /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2, REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar are 4. Indexed addresses are cost 6. */ /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */ int i960_address_cost (x) rtx x; { #if 0 /* Handled before calling here. */ if (GET_CODE (x) == REG) return 1; #endif if (GET_CODE (x) == PLUS) { rtx base = XEXP (x, 0); rtx offset = XEXP (x, 1); if (GET_CODE (base) == SUBREG) base = SUBREG_REG (base); if (GET_CODE (offset) == SUBREG) offset = SUBREG_REG (offset); if (GET_CODE (base) == REG) { if (GET_CODE (offset) == REG) return 2; if (GET_CODE (offset) == CONST_INT) { if ((unsigned)INTVAL (offset) < 2047) return 2; return 4; } if (CONSTANT_P (offset)) return 4; } if (GET_CODE (base) == PLUS || GET_CODE (base) == MULT) return 6; /* This is an invalid address. The return value doesn't matter, but for convenience we make this more expensive than anything else. */ return 12; } if (GET_CODE (x) == MULT) return 6; /* Symbol_refs and other unrecognized addresses are cost 4. */ return 4; } /* Emit insns to move operands[1] into operands[0]. Return 1 if we have written out everything that needs to be done to do the move. Otherwise, return 0 and the caller will emit the move normally. */ int emit_move_sequence (operands, mode) rtx *operands; enum machine_mode mode; { register rtx operand0 = operands[0]; register rtx operand1 = operands[1]; /* We can only store registers to memory. */ if (GET_CODE (operand0) == MEM && GET_CODE (operand1) != REG) operands[1] = force_reg (mode, operand1); return 0; } /* Emit insns to load a constant. Uses several strategies to try to use as few insns as possible. */ char * i960_output_ldconst (dst, src) register rtx dst, src; { register int rsrc1; register unsigned rsrc2; enum machine_mode mode = GET_MODE (dst); rtx operands[4]; union { long l[2]; double d; } x; operands[0] = operands[2] = dst; operands[1] = operands[3] = src; /* Anything that isn't a compile time constant, such as a SYMBOL_REF, must be a ldconst insn. */ if (GET_CODE (src) != CONST_INT && GET_CODE (src) != CONST_DOUBLE) { output_asm_insn ("ldconst %1,%0", operands); return ""; } else if (mode == DFmode) { rtx first, second; if (fp_literal_zero (src, VOIDmode)) { if (FP_REG_P (dst)) return "movrl %1,%0"; else return "movl 0,%0"; } #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT split_double (src, &first, &second); output_asm_insn ("# ldconst %1,%0",operands); operands[0] = gen_rtx (REG, SImode, REGNO (dst)); operands[1] = first; output_asm_insn (i960_output_ldconst (operands[0], operands[1]), operands); operands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1); operands[1] = second; output_asm_insn (i960_output_ldconst (operands[0], operands[1]), operands); return ""; #else if (fp_literal_one (src, VOIDmode)) return "movrl 0f1.0,%0"; fatal ("inline double constants not supported on this host"); #endif } else if (mode == TImode) { /* ??? This is currently not handled at all. */ abort (); /* Note: lowest order word goes in lowest numbered reg. */ rsrc1 = INTVAL (src); if (rsrc1 >= 0 && rsrc1 < 32) return "movq %1,%0"; else output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands); /* Go pick up the low-order word. */ } else if (mode == DImode) { rtx upperhalf, lowerhalf, xoperands[2]; char *string; if (GET_CODE (src) == CONST_DOUBLE) { upperhalf = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_HIGH (src)); lowerhalf = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (src)); } else if (GET_CODE (src) == CONST_INT) { lowerhalf = src; upperhalf = INTVAL (src) < 0 ? constm1_rtx : const0_rtx; } else abort (); /* Note: lowest order word goes in lowest numbered reg. */ /* Numbers from 0 to 31 can be handled with a single insn. */ rsrc1 = INTVAL (lowerhalf); if (upperhalf == const0_rtx && rsrc1 >= 0 && rsrc1 < 32) return "movl %1,%0"; /* Output the upper half with a recursive call. */ xoperands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1); xoperands[1] = upperhalf; output_asm_insn (i960_output_ldconst (xoperands[0], xoperands[1]), xoperands); /* The lower word is emitted as normally. */ } else if (mode == SFmode) { #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT REAL_VALUE_TYPE d; long value; REAL_VALUE_FROM_CONST_DOUBLE (d, src); REAL_VALUE_TO_TARGET_SINGLE (d, value); output_asm_insn ("# ldconst %1,%0",operands); operands[0] = gen_rtx (REG, SImode, REGNO (dst)); operands[1] = gen_rtx (CONST_INT, VOIDmode, value); output_asm_insn (i960_output_ldconst (operands[0], operands[1]), operands); #else if (fp_literal_zero (src, VOIDmode)) return "movr 0f0.0,%0"; if (fp_literal_one (src, VOIDmode)) return "movr 0f1.0,%0"; fatal ("inline float constants not supported on this host"); #endif return ""; } else { rsrc1 = INTVAL (src); if (mode == QImode) { if (rsrc1 > 0xff) rsrc1 &= 0xff; } else if (mode == HImode) { if (rsrc1 > 0xffff) rsrc1 &= 0xffff; } } if (rsrc1 >= 0) { /* ldconst 0..31,X -> mov 0..31,X */ if (rsrc1 < 32) { if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) return "lda %1,%0"; return "mov %1,%0"; } /* ldconst 32..63,X -> add 31,nn,X */ if (rsrc1 < 63) { if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) return "lda %1,%0"; operands[1] = gen_rtx (CONST_INT, VOIDmode, rsrc1 - 31); output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands); return ""; } } else if (rsrc1 < 0) { /* ldconst -1..-31 -> sub 0,0..31,X */ if (rsrc1 >= -31) { /* return 'sub -(%1),0,%0' */ operands[1] = gen_rtx (CONST_INT, VOIDmode, - rsrc1); output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands); return ""; } /* ldconst -32 -> not 31,X */ if (rsrc1 == -32) { operands[1] = gen_rtx (CONST_INT, VOIDmode, ~rsrc1); output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands); return ""; } } /* If const is a single bit. */ if (bitpos (rsrc1) >= 0) { operands[1] = gen_rtx (CONST_INT, VOIDmode, bitpos (rsrc1)); output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands); return ""; } /* If const is a bit string of less than 6 bits (1..31 shifted). */ if (is_mask (rsrc1)) { int s, e; if (bitstr (rsrc1, &s, &e) < 6) { rsrc2 = ((unsigned int) rsrc1) >> s; operands[1] = gen_rtx (CONST_INT, VOIDmode, rsrc2); operands[2] = gen_rtx (CONST_INT, VOIDmode, s); output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands); return ""; } } /* Unimplemented cases: const is in range 0..31 but rotated around end of word: ror 31,3,g0 -> ldconst 0xe0000003,g0 and any 2 instruction cases that might be worthwhile */ output_asm_insn ("ldconst %1,%0", operands); return ""; } /* Determine if there is an opportunity for a bypass optimization. Bypass succeeds on the 960K* if the destination of the previous instruction is the second operand of the current instruction. Bypass always succeeds on the C*. Return 1 if the pattern should interchange the operands. CMPBR_FLAG is true if this is for a compare-and-branch insn. OP1 and OP2 are the two source operands of a 3 operand insn. */ int i960_bypass (insn, op1, op2, cmpbr_flag) register rtx insn, op1, op2; int cmpbr_flag; { register rtx prev_insn, prev_dest; if (TARGET_C_SERIES) return 0; /* Can't do this if op1 isn't a register. */ if (! REG_P (op1)) return 0; /* Can't do this for a compare-and-branch if both ops aren't regs. */ if (cmpbr_flag && ! REG_P (op2)) return 0; prev_insn = prev_real_insn (insn); if (prev_insn && GET_CODE (prev_insn) == INSN && GET_CODE (PATTERN (prev_insn)) == SET) { prev_dest = SET_DEST (PATTERN (prev_insn)); if ((GET_CODE (prev_dest) == REG && REGNO (prev_dest) == REGNO (op1)) || (GET_CODE (prev_dest) == SUBREG && GET_CODE (SUBREG_REG (prev_dest)) == REG && REGNO (SUBREG_REG (prev_dest)) == REGNO (op1))) return 1; } return 0; } /* Output the code which declares the function name. This also handles leaf routines, which have special requirements, and initializes some global variables. */ void i960_function_name_declare (file, name, fndecl) FILE *file; char *name; tree fndecl; { register int i, j; int leaf_proc_ok; rtx insn; /* Increment global return label. */ ret_label++; /* Compute whether tail calls and leaf routine optimizations can be performed for this function. */ if (TARGET_TAILCALL) tail_call_ok = 1; else tail_call_ok = 0; if (TARGET_LEAFPROC) leaf_proc_ok = 1; else leaf_proc_ok = 0; /* Even if nobody uses extra parms, can't have leafroc or tail calls if argblock, because argblock uses g14 implicitly. */ if (current_function_args_size != 0) { tail_call_ok = 0; leaf_proc_ok = 0; } /* See if caller passes in an address to return value. */ if (aggregate_value_p (DECL_RESULT (fndecl))) { tail_call_ok = 0; leaf_proc_ok = 0; } /* Can not use tail calls or make this a leaf routine if there is a non zero frame size. */ if (get_frame_size () != 0) leaf_proc_ok = 0; /* I don't understand this condition, and do not think that it is correct. Apparently this is just checking whether the frame pointer is used, and we can't trust regs_ever_live[fp] since it is (almost?) always set. */ if (tail_call_ok) for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) if (GET_CODE (insn) == INSN && reg_mentioned_p (frame_pointer_rtx, insn)) { tail_call_ok = 0; break; } /* Check for CALL insns. Can not be a leaf routine if there are any. */ if (leaf_proc_ok) for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) if (GET_CODE (insn) == CALL_INSN) { leaf_proc_ok = 0; break; } /* Can not be a leaf routine if any non-call clobbered registers are used in this function. */ if (leaf_proc_ok) for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++) if (regs_ever_live[i] && ((! call_used_regs[i]) || (i > 7 && i < 12))) { /* Global registers. */ if (i < 16 && i > 7 && i != 13) leaf_proc_ok = 0; /* Local registers. */ else if (i < 32) leaf_proc_ok = 0; } /* Now choose a leaf return register, if we can find one, and if it is OK for this to be a leaf routine. */ i960_leaf_ret_reg = -1; if (optimize && leaf_proc_ok) { for (i960_leaf_ret_reg = -1, i = 0; i < 8; i++) if (regs_ever_live[i] == 0) { i960_leaf_ret_reg = i; regs_ever_live[i] = 1; break; } } /* Do this after choosing the leaf return register, so it will be listed if one was chosen. */ fprintf (file, "\t# Function '%s'\n", name); fprintf (file, "\t# Registers used: "); for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++) { if (regs_ever_live[i]) { fprintf (file, "%s%s ", reg_names[i], call_used_regs[i] ? "" : "*"); if (i > 15 && j == 0) { fprintf (file,"\n\t#\t\t "); j++; } } } fprintf (file, "\n"); if (i960_leaf_ret_reg >= 0) { /* Make it a leaf procedure. */ if (TREE_PUBLIC (fndecl)) fprintf (file,"\t.globl %s.lf\n", name); fprintf (file, "\t.leafproc\t_%s,%s.lf\n", name, name); fprintf (file, "_%s:\n", name); fprintf (file, "\tlda LR%d,g14\n", ret_label); fprintf (file, "%s.lf:\n", name); fprintf (file, "\tmov g14,g%d\n", i960_leaf_ret_reg); if (TARGET_C_SERIES) { fprintf (file, "\tlda 0,g14\n"); i960_last_insn_type = I_TYPE_MEM; } else { fprintf (file, "\tmov 0,g14\n"); i960_last_insn_type = I_TYPE_REG; } } else { ASM_OUTPUT_LABEL (file, name); i960_last_insn_type = I_TYPE_CTRL; } } /* Compute and return the frame size. */ int compute_frame_size (size) int size; { int actual_fsize; int outgoing_args_size = current_function_outgoing_args_size + current_function_pretend_args_size; /* The STARTING_FRAME_OFFSET is totally hidden to us as far as size is concerned. */ actual_fsize = (size + 15) & -16; actual_fsize += (outgoing_args_size + 15) & -16; return actual_fsize; } /* Output code for the function prologue. */ void i960_function_prologue (file, size) FILE *file; unsigned int size; { register int i, j, nr; int n_iregs = 0; int rsize = 0; int actual_fsize, offset; char tmpstr[1000]; /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved somewhere. */ int regs[FIRST_PSEUDO_REGISTER]; for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) if (regs_ever_live[i] && ((! call_used_regs[i]) || (i > 7 && i < 12))) { regs[i] = -1; /* Count global registers that need saving. */ if (i < 16) n_iregs++; } else regs[i] = 0; epilogue_string[0] = '\0'; if (profile_flag || profile_block_flag) { /* When profiling, we may use registers 20 to 27 to save arguments, so they can't be used here for saving globals. J is the number of argument registers the mcount call will save. */ for (j = 7; j >= 0 && ! regs_ever_live[j]; j--) ; for (i = 20; i <= j + 20; i++) regs[i] = -1; } /* First look for local registers to save globals in. */ for (i = 0; i < 16; i++) { if (regs[i] == 0) continue; /* Start at r4, not r3. */ for (j = 20; j < 32; j++) { if (regs[j] != 0) continue; regs[i] = 1; regs[j] = -1; regs_ever_live[j] = 1; nr = 1; if (i <= 14 && i % 2 == 0 && j <= 30 && j % 2 == 0 && regs[i+1] != 0 && regs[j+1] == 0) { nr = 2; regs[i+1] = 1; regs[j+1] = -1; regs_ever_live[j+1] = 1; } if (nr == 2 && i <= 12 && i % 4 == 0 && j <= 28 && j % 4 == 0 && regs[i+2] != 0 && regs[j+2] == 0) { nr = 3; regs[i+2] = 1; regs[j+2] = -1; regs_ever_live[j+2] = 1; } if (nr == 3 && regs[i+3] != 0 && regs[j+3] == 0) { nr = 4; regs[i+3] = 1; regs[j+3] = -1; regs_ever_live[j+3] = 1; } fprintf (file, "\tmov%s %s,%s\n", ((nr == 4) ? "q" : (nr == 3) ? "t" : (nr == 2) ? "l" : ""), reg_names[i], reg_names[j]); sprintf (tmpstr, "\tmov%s %s,%s\n", ((nr == 4) ? "q" : (nr == 3) ? "t" : (nr == 2) ? "l" : ""), reg_names[j], reg_names[i]); strcat (epilogue_string, tmpstr); n_iregs -= nr; i += nr-1; break; } } /* N_iregs is now the number of global registers that haven't been saved yet. */ rsize = (n_iregs * 4); actual_fsize = compute_frame_size (size) + rsize; #if 0 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame size up to the nearest multiple of 16. I don't know whether this is necessary, or even desirable. The frame pointer must be aligned, but the call instruction takes care of that. If we leave the stack pointer unaligned, we may save a little on dynamic stack allocation. And we don't lose, at least according to the i960CA manual. */ actual_fsize = (actual_fsize + 15) & ~0xF; #endif /* Allocate space for register save and locals. */ if (actual_fsize > 0) { if (actual_fsize < 32) fprintf (file, "\taddo %d,sp,sp\n", actual_fsize); else fprintf (file, "\tlda\t%d(sp),sp\n", actual_fsize); } /* Take hardware register save area created by the call instruction into account. */ offset = compute_frame_size (size) + 64; /* Save registers on stack if needed. */ for (i = 0, j = n_iregs; j > 0 && i < 16; i++) { if (regs[i] != -1) continue; nr = 1; if (i <= 14 && i % 2 == 0 && regs[i+1] == -1 && offset % 2 == 0) nr = 2; if (nr == 2 && i <= 12 && i % 4 == 0 && regs[i+2] == -1 && offset % 4 == 0) nr = 3; if (nr == 3 && regs[i+3] == -1) nr = 4; fprintf (file,"\tst%s %s,%d(fp)\n", ((nr == 4) ? "q" : (nr == 3) ? "t" : (nr == 2) ? "l" : ""), reg_names[i], offset); sprintf (tmpstr,"\tld%s %d(fp),%s\n", ((nr == 4) ? "q" : (nr == 3) ? "t" : (nr == 2) ? "l" : ""), offset, reg_names[i]); strcat (epilogue_string, tmpstr); i += nr-1; j -= nr; offset += nr * 4; } if (actual_fsize == 0 && size == 0 && rsize == 0) return; fprintf (file, "\t#Prologue stats:\n"); fprintf (file, "\t# Total Frame Size: %d bytes\n", actual_fsize); if (size) fprintf (file, "\t# Local Variable Size: %d bytes\n", size); if (rsize) fprintf (file, "\t# Register Save Size: %d regs, %d bytes\n", n_iregs, rsize); fprintf (file, "\t#End Prologue#\n"); } /* Output code for the function profiler. */ void output_function_profiler (file, labelno) FILE *file; int labelno; { /* The last used parameter register. */ int last_parm_reg; int i, j, increment; /* Figure out the last used parameter register. The proper thing to do is to walk incoming args of the function. A function might have live parameter registers even if it has no incoming args. Note that we don't have to save parameter registers g8 to g11 because they are call preserved. */ /* See also output_function_prologue, which tries to use local registers for preserved call-saved global registers. */ for (last_parm_reg = 7; last_parm_reg >= 0 && ! regs_ever_live[last_parm_reg]; last_parm_reg--) ; /* Save parameter registers in regs r4 (20) to r11 (27). */ for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment) { if (i % 4 == 0 && (last_parm_reg - i) >= 3) increment = 4; else if (i % 4 == 0 && (last_parm_reg - i) >= 2) increment = 3; else if (i % 2 == 0 && (last_parm_reg - i) >= 1) increment = 2; else increment = 1; fprintf (file, "\tmov%s g%d,r%d\n", (increment == 4 ? "q" : increment == 3 ? "t" : increment == 2 ? "l": ""), i, j); } /* If this function uses the arg pointer, then save it in r3 and then set it to zero. */ if (current_function_args_size != 0) fprintf (file, "\tmov g14,r3\n\tmov 0,g14\n"); /* Load location address into g0 and call mcount. */ fprintf (file, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno); /* If this function uses the arg pointer, restore it. */ if (current_function_args_size != 0) fprintf (file, "\tmov r3,g14\n"); /* Restore parameter registers. */ for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment) { if (i % 4 == 0 && (last_parm_reg - i) >= 3) increment = 4; else if (i % 4 == 0 && (last_parm_reg - i) >= 2) increment = 3; else if (i % 2 == 0 && (last_parm_reg - i) >= 1) increment = 2; else increment = 1; fprintf (file, "\tmov%s r%d,g%d\n", (increment == 4 ? "q" : increment == 3 ? "t" : increment == 2 ? "l": ""), j, i); } } /* Output code for the function epilogue. */ void i960_function_epilogue (file, size) FILE *file; unsigned int size; { if (i960_leaf_ret_reg >= 0) { fprintf (file, "LR%d: ret\n", ret_label); return; } if (*epilogue_string == 0) { register rtx tmp; /* Emit a return insn, but only if control can fall through to here. */ tmp = get_last_insn (); while (tmp) { if (GET_CODE (tmp) == BARRIER) return; if (GET_CODE (tmp) == CODE_LABEL) break; if (GET_CODE (tmp) == JUMP_INSN) { if (GET_CODE (PATTERN (tmp)) == RETURN) return; break; } if (GET_CODE (tmp) == NOTE) { tmp = PREV_INSN (tmp); continue; } break; } fprintf (file, "LR%d: ret\n", ret_label); return; } fprintf (file, "LR%d:\n", ret_label); fprintf (file, "\t#EPILOGUE#\n"); /* Output the string created by the prologue which will restore all registers saved by the prologue. */ if (epilogue_string[0] != '\0') fprintf (file, "%s", epilogue_string); /* Must clear g14 on return. */ if (current_function_args_size != 0) fprintf (file, "\tmov 0,g14\n"); fprintf (file, "\tret\n"); fprintf (file, "\t#End Epilogue#\n"); } /* Output code for a call insn. */ char * i960_output_call_insn (target, argsize_rtx, arg_pointer, insn) register rtx target, argsize_rtx, arg_pointer, insn; { int argsize = INTVAL (argsize_rtx); rtx nexti = next_real_insn (insn); rtx operands[2]; operands[0] = target; operands[1] = arg_pointer; if (current_function_args_size != 0) output_asm_insn ("mov g14,r3", operands); if (argsize > 48) output_asm_insn ("lda %a1,g14", operands); else if (current_function_args_size != 0) output_asm_insn ("mov 0,g14", operands); /* The code used to assume that calls to SYMBOL_REFs could not be more than 24 bits away (b vs bx, callj vs callx). This is not true. This feature is now implemented by relaxing in the GNU linker. It can convert bx to b if in range, and callx to calls/call/balx/bal as appropriate. */ /* Nexti could be zero if the called routine is volatile. */ if (optimize && (*epilogue_string == 0) && argsize == 0 && tail_call_ok && (nexti == 0 || GET_CODE (PATTERN (nexti)) == RETURN)) { /* Delete following return insn. */ if (nexti && no_labels_between_p (insn, nexti)) delete_insn (nexti); output_asm_insn ("bx %0", operands); return "# notreached"; } output_asm_insn ("callx %0", operands); if (current_function_args_size != 0) output_asm_insn ("mov r3,g14", operands); return ""; } /* Output code for a return insn. */ char * i960_output_ret_insn (insn) register rtx insn; { static char lbuf[20]; if (*epilogue_string != 0) { if (! TARGET_CODE_ALIGN && next_real_insn (insn) == 0) return ""; sprintf (lbuf, "b LR%d", ret_label); return lbuf; } if (current_function_args_size != 0) output_asm_insn ("mov 0,g14", 0); if (i960_leaf_ret_reg >= 0) { sprintf (lbuf, "bx (%s)", reg_names[i960_leaf_ret_reg]); return lbuf; } return "ret"; } #if 0 /* Return a character string representing the branch prediction opcode to be tacked on an instruction. This must at least return a null string. */ char * i960_br_predict_opcode (lab_ref, insn) rtx lab_ref, insn; { if (TARGET_BRANCH_PREDICT) { unsigned long label_uid; if (GET_CODE (lab_ref) == CODE_LABEL) label_uid = INSN_UID (lab_ref); else if (GET_CODE (lab_ref) == LABEL_REF) label_uid = INSN_UID (XEXP (lab_ref, 0)); else return ".f"; /* If not optimizing, then the insn_addresses array will not be valid. In this case, always return ".t" since most branches are taken. If optimizing, return .t for backward branches and .f for forward branches. */ if (! optimize || insn_addresses[label_uid] < insn_addresses[INSN_UID (insn)]) return ".t"; return ".f"; } return ""; } #endif /* Print the operand represented by rtx X formatted by code CODE. */ void i960_print_operand (file, x, code) FILE *file; rtx x; char code; { enum rtx_code rtxcode = GET_CODE (x); if (rtxcode == REG) { switch (code) { case 'D': /* Second reg of a double. */ fprintf (file, "%s", reg_names[REGNO (x)+1]); break; case 0: fprintf (file, "%s", reg_names[REGNO (x)]); break; default: abort (); } return; } else if (rtxcode == MEM) { output_address (XEXP (x, 0)); return; } else if (rtxcode == CONST_INT) { if (INTVAL (x) > 9999 || INTVAL (x) < -999) fprintf (file, "0x%x", INTVAL (x)); else fprintf (file, "%d", INTVAL (x)); return; } else if (rtxcode == CONST_DOUBLE) { double d; if (x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode)) { fprintf (file, "0f0.0"); return; } else if (x == CONST1_RTX (DFmode) || x == CONST1_RTX (SFmode)) { fprintf (file, "0f1.0"); return; } /* This better be a comment. */ REAL_VALUE_FROM_CONST_DOUBLE (d, x); fprintf (file, "%#g", d); return; } switch(code) { case 'B': /* Branch or jump, depending on assembler. */ if (TARGET_ASM_COMPAT) fputs ("j", file); else fputs ("b", file); break; case 'S': /* Sign of condition. */ if ((rtxcode == EQ) || (rtxcode == NE) || (rtxcode == GTU) || (rtxcode == LTU) || (rtxcode == GEU) || (rtxcode == LEU)) fputs ("o", file); else if ((rtxcode == GT) || (rtxcode == LT) || (rtxcode == GE) || (rtxcode == LE)) fputs ("i", file); else abort(); break; case 'I': /* Inverted condition. */ rtxcode = reverse_condition (rtxcode); goto normal; case 'X': /* Inverted condition w/ reversed operands. */ rtxcode = reverse_condition (rtxcode); /* Fallthrough. */ case 'R': /* Reversed operand condition. */ rtxcode = swap_condition (rtxcode); /* Fallthrough. */ case 'C': /* Normal condition. */ normal: if (rtxcode == EQ) { fputs ("e", file); return; } else if (rtxcode == NE) { fputs ("ne", file); return; } else if (rtxcode == GT) { fputs ("g", file); return; } else if (rtxcode == GTU) { fputs ("g", file); return; } else if (rtxcode == LT) { fputs ("l", file); return; } else if (rtxcode == LTU) { fputs ("l", file); return; } else if (rtxcode == GE) { fputs ("ge", file); return; } else if (rtxcode == GEU) { fputs ("ge", file); return; } else if (rtxcode == LE) { fputs ("le", file); return; } else if (rtxcode == LEU) { fputs ("le", file); return; } else abort (); break; case 0: output_addr_const (file, x); break; default: abort (); } return; } /* Print a memory address as an operand to reference that memory location. This is exactly the same as legitimate_address_p, except that it the prints addresses instead of recognizing them. */ void i960_print_operand_addr (file, addr) FILE *file; register rtx addr; { rtx breg, ireg; rtx scale, offset; ireg = 0; breg = 0; offset = 0; scale = const1_rtx; if (GET_CODE (addr) == REG) breg = addr; else if (CONSTANT_P (addr)) offset = addr; else if (GET_CODE (addr) == PLUS) { rtx op0, op1; op0 = XEXP (addr, 0); op1 = XEXP (addr, 1); if (GET_CODE (op0) == REG) { breg = op0; if (GET_CODE (op1) == REG) ireg = op1; else if (CONSTANT_P (op1)) offset = op1; else abort (); } else if (GET_CODE (op0) == PLUS) { if (GET_CODE (XEXP (op0, 0)) == MULT) { ireg = XEXP (XEXP (op0, 0), 0); scale = XEXP (XEXP (op0, 0), 1); if (GET_CODE (XEXP (op0, 1)) == REG) { breg = XEXP (op0, 1); offset = op1; } else abort (); } else if (GET_CODE (XEXP (op0, 0)) == REG) { breg = XEXP (op0, 0); if (GET_CODE (XEXP (op0, 1)) == REG) { ireg = XEXP (op0, 1); offset = op1; } else abort (); } else abort (); } else if (GET_CODE (op0) == MULT) { ireg = XEXP (op0, 0); scale = XEXP (op0, 1); if (GET_CODE (op1) == REG) breg = op1; else if (CONSTANT_P (op1)) offset = op1; else abort (); } else abort (); } else if (GET_CODE (addr) == MULT) { ireg = XEXP (addr, 0); scale = XEXP (addr, 1); } else abort (); if (offset) output_addr_const (file, offset); if (breg) fprintf (file, "(%s)", reg_names[REGNO (breg)]); if (ireg) fprintf (file, "[%s*%d]", reg_names[REGNO (ireg)], INTVAL (scale)); } /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. On 80960, legitimate addresses are: base ld (g0),r0 disp (12 or 32 bit) ld foo,r0 base + index ld (g0)[g1*1],r0 base + displ ld 0xf00(g0),r0 base + index*scale + displ ld 0xf00(g0)[g1*4],r0 index*scale + base ld (g0)[g1*4],r0 index*scale + displ ld 0xf00[g1*4],r0 index*scale ld [g1*4],r0 index + base + displ ld 0xf00(g0)[g1*1],r0 In each case, scale can be 1, 2, 4, 8, or 16. */ /* This is exactly the same as i960_print_operand_addr, except that it recognizes addresses instead of printing them. It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should convert common non-canonical forms to canonical form so that they will be recognized. */ /* These two macros allow us to accept either a REG or a SUBREG anyplace where a register is valid. */ #define RTX_OK_FOR_BASE_P(X, STRICT) \ ((GET_CODE (X) == REG \ && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \ || (GET_CODE (X) == SUBREG \ && GET_CODE (SUBREG_REG (X)) == REG \ && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \ : REG_OK_FOR_BASE_P (SUBREG_REG (X))))) #define RTX_OK_FOR_INDEX_P(X, STRICT) \ ((GET_CODE (X) == REG \ && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\ || (GET_CODE (X) == SUBREG \ && GET_CODE (SUBREG_REG (X)) == REG \ && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \ : REG_OK_FOR_INDEX_P (SUBREG_REG (X))))) int legitimate_address_p (mode, addr, strict) enum machine_mode mode; register rtx addr; int strict; { if (RTX_OK_FOR_BASE_P (addr, strict)) return 1; else if (CONSTANT_P (addr)) return 1; else if (GET_CODE (addr) == PLUS) { rtx op0, op1; if (! TARGET_COMPLEX_ADDR && ! reload_completed) return 0; op0 = XEXP (addr, 0); op1 = XEXP (addr, 1); if (RTX_OK_FOR_BASE_P (op0, strict)) { if (RTX_OK_FOR_INDEX_P (op1, strict)) return 1; else if (CONSTANT_P (op1)) return 1; else return 0; } else if (GET_CODE (op0) == PLUS) { if (GET_CODE (XEXP (op0, 0)) == MULT) { if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0, 0), 0), strict) && SCALE_TERM_P (XEXP (XEXP (op0, 0), 1)))) return 0; if (RTX_OK_FOR_BASE_P (XEXP (op0, 1), strict) && CONSTANT_P (op1)) return 1; else return 0; } else if (RTX_OK_FOR_BASE_P (XEXP (op0, 0), strict)) { if (RTX_OK_FOR_INDEX_P (XEXP (op0, 1), strict) && CONSTANT_P (op1)) return 1; else return 0; } else return 0; } else if (GET_CODE (op0) == MULT) { if (! (RTX_OK_FOR_INDEX_P (XEXP (op0, 0), strict) && SCALE_TERM_P (XEXP (op0, 1)))) return 0; if (RTX_OK_FOR_BASE_P (op1, strict)) return 1; else if (CONSTANT_P (op1)) return 1; else return 0; } else return 0; } else if (GET_CODE (addr) == MULT) { if (! TARGET_COMPLEX_ADDR && ! reload_completed) return 0; return (RTX_OK_FOR_INDEX_P (XEXP (addr, 0), strict) && SCALE_TERM_P (XEXP (addr, 1))); } else return 0; } /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. This converts some non-canonical addresses to canonical form so they can be recognized. */ rtx legitimize_address (x, oldx, mode) register rtx x; register rtx oldx; enum machine_mode mode; { if (GET_CODE (x) == SYMBOL_REF) { abort (); x = copy_to_reg (x); } if (! TARGET_COMPLEX_ADDR && ! reload_completed) return x; /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const))) into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be created by virtual register instantiation, register elimination, and similar optimizations. */ if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS) x = gen_rtx (PLUS, Pmode, gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)), XEXP (XEXP (x, 1), 1)); /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const) into (plus (plus (mult (reg) (const)) (reg)) (const)). */ else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS && CONSTANT_P (XEXP (x, 1))) { rtx constant, other; if (GET_CODE (XEXP (x, 1)) == CONST_INT) { constant = XEXP (x, 1); other = XEXP (XEXP (XEXP (x, 0), 1), 1); } else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT) { constant = XEXP (XEXP (XEXP (x, 0), 1), 1); other = XEXP (x, 1); } else constant = 0; if (constant) x = gen_rtx (PLUS, Pmode, gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0), XEXP (XEXP (XEXP (x, 0), 1), 0)), plus_constant (other, INTVAL (constant))); } return x; } #if 0 /* Return the most stringent alignment that we are willing to consider objects of size SIZE and known alignment ALIGN as having. */ int i960_alignment (size, align) int size; int align; { int i; if (! TARGET_STRICT_ALIGN) if (TARGET_IC_COMPAT2_0 || align >= 4) { i = i960_object_bytes_bitalign (size) / BITS_PER_UNIT; if (i > align) align = i; } return align; } #endif /* Modes for condition codes. */ #define C_MODES \ ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode)) /* Modes for single-word (and smaller) quantities. */ #define S_MODES \ (~C_MODES \ & ~ ((1 << (int) DImode) | (1 << (int) TImode) \ | (1 << (int) DFmode) | (1 << (int) TFmode))) /* Modes for double-word (and smaller) quantities. */ #define D_MODES \ (~C_MODES \ & ~ ((1 << (int) TImode) | (1 << (int) TFmode))) /* Modes for quad-word quantities. */ #define T_MODES (~C_MODES) /* Modes for single-float quantities. */ #define SF_MODES ((1 << (int) SFmode)) /* Modes for double-float quantities. */ #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode)) /* Modes for quad-float quantities. */ #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode)) unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] = { T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, TF_MODES, TF_MODES, TF_MODES, TF_MODES, C_MODES}; /* Return the minimum alignment of an expression rtx X in bytes. This takes advantage of machine specific facts, such as knowing that the frame pointer is always 16 byte aligned. */ int i960_expr_alignment (x, size) rtx x; int size; { int align = 1; if (x == 0) return 1; switch (GET_CODE(x)) { case CONST_INT: align = INTVAL(x); if ((align & 0xf) == 0) align = 16; else if ((align & 0x7) == 0) align = 8; else if ((align & 0x3) == 0) align = 4; else if ((align & 0x1) == 0) align = 2; else align = 1; break; case PLUS: align = MIN (i960_expr_alignment (XEXP (x, 0), size), i960_expr_alignment (XEXP (x, 1), size)); break; case SYMBOL_REF: /* If this is a valid program, objects are guaranteed to be correctly aligned for whatever size the reference actually is. */ align = i960_object_bytes_bitalign (size) / BITS_PER_UNIT; break; case REG: if (REGNO (x) == FRAME_POINTER_REGNUM) align = 16; break; case ASHIFT: case LSHIFT: align = i960_expr_alignment (XEXP (x, 0)); if (GET_CODE (XEXP (x, 1)) == CONST_INT) { align = align << INTVAL (XEXP (x, 1)); align = MIN (align, 16); } break; case MULT: align = (i960_expr_alignment (XEXP (x, 0), size) * i960_expr_alignment (XEXP (x, 1), size)); align = MIN (align, 16); break; } return align; } /* Return true if it is possible to reference both BASE and OFFSET, which have alignment at least as great as 4 byte, as if they had alignment valid for an object of size SIZE. */ int i960_improve_align (base, offset, size) rtx base; rtx offset; int size; { int i, j; /* We have at least a word reference to the object, so we know it has to be aligned at least to 4 bytes. */ i = MIN (i960_expr_alignment (base, 4), i960_expr_alignment (offset, 4)); i = MAX (i, 4); /* We know the size of the request. If strict align is not enabled, we can guess that the alignment is OK for the requested size. */ if (! TARGET_STRICT_ALIGN) if ((j = (i960_object_bytes_bitalign (size) / BITS_PER_UNIT)) > i) i = j; return (i >= size); } /* Return true if it is possible to access BASE and OFFSET, which have 4 byte (SImode) alignment as if they had 16 byte (TImode) alignment. */ int i960_si_ti (base, offset) rtx base; rtx offset; { return i960_improve_align (base, offset, 16); } /* Return true if it is possible to access BASE and OFFSET, which have 4 byte (SImode) alignment as if they had 8 byte (DImode) alignment. */ int i960_si_di (base, offset) rtx base; rtx offset; { return i960_improve_align (base, offset, 8); } /* Return raw values of size and alignment (in words) for the data type being accessed. These values will be rounded by the caller. */ static void i960_arg_size_and_align (mode, type, size_out, align_out) enum machine_mode mode; tree type; int *size_out; int *align_out; { int size, align; /* Use formal alignment requirements of type being passed, except make it at least a word. If we don't have a type, this is a library call, and the parm has to be of scalar type. In this case, consider its formal alignment requirement to be its size in words. */ if (mode == BLKmode) size = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; else if (mode == VOIDmode) { /* End of parm list. */ assert (type != 0 && TYPE_MODE (type) == VOIDmode); size = 1; } else size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; if (type == 0) align = size; else if (TYPE_ALIGN (type) >= BITS_PER_WORD) align = TYPE_ALIGN (type) / BITS_PER_WORD; else align = 1; *size_out = size; *align_out = align; } /* On the 80960 the first 12 args are in registers and the rest are pushed. Any arg that is bigger than 4 words is placed on the stack and all subsequent arguments are placed on the stack. Additionally, parameters with an alignment requirement stronger than a word must be be aligned appropriately. */ /* Update CUM to advance past an argument described by MODE and TYPE. */ void i960_function_arg_advance (cum, mode, type, named) CUMULATIVE_ARGS *cum; enum machine_mode mode; tree type; int named; { int size, align; i960_arg_size_and_align (mode, type, &size, &align); if (named == 0 || size > 4 || cum->ca_nstackparms != 0 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS || MUST_PASS_IN_STACK (mode, type)) cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align) + size; else cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align) + size; } /* Return the register that the argument described by MODE and TYPE is passed in, or else return 0 if it is passed on the stack. */ rtx i960_function_arg (cum, mode, type, named) CUMULATIVE_ARGS *cum; enum machine_mode mode; tree type; int named; { rtx ret; int size, align; i960_arg_size_and_align (mode, type, &size, &align); if (named == 0 || size > 4 || cum->ca_nstackparms != 0 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS || MUST_PASS_IN_STACK (mode, type)) { cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align); ret = 0; } else { cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align); ret = gen_rtx (REG, mode, cum->ca_nregparms); } return ret; } /* Floating-point support. */ void i960_output_double (file, value) FILE *file; double value; { if (REAL_VALUE_ISINF (value)) { fprintf (file, "\t.word 0\n"); fprintf (file, "\t.word 0x7ff00000 # Infinity\n"); } else fprintf (file, "\t.double 0d%.17e\n", (value)); } void i960_output_float (file, value) FILE *file; double value; { if (REAL_VALUE_ISINF (value)) fprintf (file, "\t.word 0x7f800000 # Infinity\n"); else fprintf (file, "\t.float 0f%.12e\n", (value)); } /* Return the number of bits that an object of size N bytes is aligned to. */ int i960_object_bytes_bitalign (n) int n; { if (n > 8) n = 128; else if (n > 4) n = 64; else if (n > 2) n = 32; else if (n > 1) n = 16; else n = 8; return n; } /* Compute the size of an aggregate type TSIZE. */ tree i960_round_size (tsize) tree tsize; { int size, byte_size, align; if (TREE_CODE (tsize) != INTEGER_CST) return tsize; size = TREE_INT_CST_LOW (tsize); byte_size = (size + BITS_PER_UNIT - 1) / BITS_PER_UNIT; align = i960_object_bytes_bitalign (byte_size); /* Handle #pragma align. */ if (align > i960_maxbitalignment) align = i960_maxbitalignment; if (size % align) size = ((size / align) + 1) * align; return size_int (size); } /* Compute the alignment for an aggregate type TSIZE. */ int i960_round_align (align, tsize) int align; tree tsize; { int byte_size; if (TREE_CODE (tsize) != INTEGER_CST) return align; byte_size = (TREE_INT_CST_LOW (tsize) + BITS_PER_UNIT - 1) / BITS_PER_UNIT; align = i960_object_bytes_bitalign (byte_size); return align; } /* Do any needed setup for a varargs function. For the i960, we must create a register parameter block if one doesn't exist, and then copy all register parameters to memory. */ void i960_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) CUMULATIVE_ARGS *cum; enum machine_mode mode; tree type; int *pretend_size; int no_rtl; { if (cum->ca_nregparms < NPARM_REGS) { int first_reg_offset = cum->ca_nregparms; if (first_reg_offset > NPARM_REGS) first_reg_offset = NPARM_REGS; if (! (no_rtl) && first_reg_offset != NPARM_REGS) { rtx label = gen_label_rtx (); emit_insn (gen_cmpsi (arg_pointer_rtx, const0_rtx)); emit_jump_insn (gen_bne (label)); emit_insn (gen_rtx (SET, VOIDmode, arg_pointer_rtx, stack_pointer_rtx)); emit_insn (gen_rtx (SET, VOIDmode, stack_pointer_rtx, memory_address (SImode, plus_constant (stack_pointer_rtx, 48)))); emit_label (label); move_block_from_reg (first_reg_offset, gen_rtx (MEM, BLKmode, virtual_incoming_args_rtx), NPARM_REGS - first_reg_offset, (NPARM_REGS - first_reg_offset) * UNITS_PER_WORD); } *pretend_size = (NPARM_REGS - first_reg_offset) * UNITS_PER_WORD; } } /* Calculate the final size of the reg parm stack space for the current function, based on how many bytes would be allocated on the stack. */ int i960_final_reg_parm_stack_space (const_size, var_size) int const_size; tree var_size; { if (var_size || const_size > 48) return 48; else return 0; } /* Calculate the size of the reg parm stack space. This is a bit complicated on the i960. */ int i960_reg_parm_stack_space (fndecl) tree fndecl; { /* In this case, we are called from emit_library_call, and we don't need to pretend we have more space for parameters than what's apparent. */ if (fndecl == 0) return 0; /* In this case, we are called from locate_and_pad_parms when we're not IN_REGS, so we have an arg block. */ if (fndecl != current_function_decl) return 48; /* Otherwise, we have an arg block if the current function has more than 48 bytes of parameters. */ if (current_function_args_size != 0) return 48; else return 0; } /* Return the register class of a scratch register needed to copy IN into or out of a register in CLASS in MODE. If it can be done directly, NO_REGS is returned. */ enum reg_class secondary_reload_class (class, mode, in) enum reg_class class; enum machine_mode mode; rtx in; { int regno = -1; if (GET_CODE (in) == REG || GET_CODE (in) == SUBREG) regno = true_regnum (in); /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put LOCAL_OR_GLOBAL_REGS into anything. */ if (class == LOCAL_OR_GLOBAL_REGS || class == LOCAL_REGS || class == GLOBAL_REGS || (regno >= 0 && regno < 32)) return NO_REGS; /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */ if (class == FP_REGS && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER) || in == CONST0_RTX (mode) || in == CONST1_RTX (mode))) return NO_REGS; return LOCAL_OR_GLOBAL_REGS; } /* Look at the opcode P, and set i96_last_insn_type to indicate which function unit it executed on. */ /* ??? This would make more sense as an attribute. */ void i960_scan_opcode (p) char *p; { switch (*p) { case 'a': case 'd': case 'e': case 'm': case 'n': case 'o': case 'r': /* Ret is not actually of type REG, but it won't matter, because no insn will ever follow it. */ case 'u': case 'x': i960_last_insn_type = I_TYPE_REG; break; case 'b': if (p[1] == 'x' || p[3] == 'x') i960_last_insn_type = I_TYPE_MEM; i960_last_insn_type = I_TYPE_CTRL; break; case 'f': case 't': i960_last_insn_type = I_TYPE_CTRL; break; case 'c': if (p[1] == 'a') { if (p[4] == 'x') i960_last_insn_type = I_TYPE_MEM; else i960_last_insn_type = I_TYPE_CTRL; } else if (p[1] == 'm') { if (p[3] == 'd') i960_last_insn_type = I_TYPE_REG; else if (p[4] == 'b' || p[4] == 'j') i960_last_insn_type = I_TYPE_CTRL; else i960_last_insn_type = I_TYPE_REG; } else i960_last_insn_type = I_TYPE_REG; break; case 'l': i960_last_insn_type = I_TYPE_MEM; break; case 's': if (p[1] == 't') i960_last_insn_type = I_TYPE_MEM; else i960_last_insn_type = I_TYPE_REG; break; } } gcc-2.5.8/config/i960/i960.h100444 22011 13 161042 5474511406 13631 0ustar kenneruser/* Definitions of target machine for GNU compiler, for Intel 80960 Copyright (C) 1992, 1993 Free Software Foundation, Inc. Contributed by Steven McGeady, Intel Corp. Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Note that some other tm.h files may include this one and then override many of the definitions that relate to assembler syntax. */ /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Acpu(i960) -Amachine(i960)" /* Name to predefine in the preprocessor for processor variations. */ #define CPP_SPEC "%{mic*:-D__i960\ %{mka:-D__i960KA}%{mkb:-D__i960KB}\ %{msa:-D__i960SA}%{msb:-D__i960SB}\ %{mmc:-D__i960MC}\ %{mca:-D__i960CA}%{mcc:-D__i960CC}\ %{mcf:-D__i960CF}}\ %{mka:-D__i960KA__ -D__i960_KA__}\ %{mkb:-D__i960KB__ -D__i960_KB__}\ %{msa:-D__i960SA__ -D__i960_SA__}\ %{msb:-D__i960SB__ -D__i960_SB__}\ %{mmc:-D__i960MC__ -D__i960_MC__}\ %{mca:-D__i960CA__ -D__i960_CA__}\ %{mcc:-D__i960CC__ -D__i960_CC__}\ %{mcf:-D__i960CF__ -D__i960_CF__}\ %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\ %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}" /* -mic* options make characters signed by default. */ #define SIGNED_CHAR_SPEC \ (DEFAULT_SIGNED_CHAR ? "%{funsigned-char:-D__CHAR_UNSIGNED__}" \ : "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}") /* Specs for the compiler, to handle processor variations. */ #define CC1_SPEC \ "%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-mkb}}}}}}}}\ %{mbout:%{g*:-gstabs}}\ %{mcoff:%{g*:-gcoff}}\ %{!mbout:%{!mcoff:%{g*:-gstabs}}}" /* Specs for the assembler, to handle processor variations. For compatibility with Intel's gnu960 tool chain, pass -A options to the assembler. */ #define ASM_SPEC \ "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\ %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\ %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-AKB}}}}}}}}\ %{mlink-relax:-linkrelax}" /* Specs for the linker, to handle processor variations. For compatibility with Intel's gnu960 tool chain, pass -F and -A options to the linker. */ #define LINK_SPEC \ "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\ %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\ %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-AKB}}}}}}}}\ %{mbout:-Fbout}%{mcoff:-Fcoff}\ %{mlink-relax:-relax}" /* Specs for the libraries to link with, to handle processor variations. Compatible with Intel's gnu960 tool chain. */ #define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\ %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}" /* Omit frame pointer at -O2. Inline functions at -O3. */ #define OPTIMIZATION_OPTIONS(LEVEL) \ { \ if ((LEVEL) >= 2) \ { \ flag_omit_frame_pointer = 1; \ target_flags |= TARGET_FLAG_LEAFPROC; \ target_flags |= TARGET_FLAG_TAILCALL; \ } \ } /* Print subsidiary information on the compiler version in use. */ #define TARGET_VERSION fprintf (stderr," (intel 80960)"); /* Generate DBX debugging information. */ #define DBX_DEBUGGING_INFO /* Generate SDB style debugging information. */ #define SDB_DEBUGGING_INFO /* Generate DBX_DEBUGGING_INFO by default. */ #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG /* Redefine this to print in hex like iC960. */ #define PUT_SDB_TYPE(A) fprintf (asm_out_file, "\t.type\t0x%x;", A) /* Run-time compilation parameters selecting different hardware subsets. */ /* 960 architecture with floating-point. */ #define TARGET_FLAG_NUMERICS 0x01 #define TARGET_NUMERICS (target_flags & TARGET_FLAG_NUMERICS) /* 960 architecture with memory management. */ /* ??? Not used currently. */ #define TARGET_FLAG_PROTECTED 0x02 #define TARGET_PROTECTED (target_flags & TARGET_FLAG_PROTECTED) /* The following three are mainly used to provide a little sanity checking against the -mARCH flags given. */ /* Nonzero if we should generate code for the KA and similar processors. No FPU, no microcode instructions. */ #define TARGET_FLAG_K_SERIES 0x04 #define TARGET_K_SERIES (target_flags & TARGET_FLAG_K_SERIES) /* Nonzero if we should generate code for the MC processor. Not really different from KB for our purposes. */ #define TARGET_FLAG_MC 0x08 #define TARGET_MC (target_flags & TARGET_FLAG_MC) /* Nonzero if we should generate code for the CA processor. Enables different optimization strategies. */ #define TARGET_FLAG_C_SERIES 0x10 #define TARGET_C_SERIES (target_flags & TARGET_FLAG_C_SERIES) /* Nonzero if we should generate leaf-procedures when we find them. You may not want to do this because leaf-proc entries are slower when not entered via BAL - this would be true when a linker not supporting the optimization is used. */ #define TARGET_FLAG_LEAFPROC 0x20 #define TARGET_LEAFPROC (target_flags & TARGET_FLAG_LEAFPROC) /* Nonzero if we should perform tail-call optimizations when we find them. You may not want to do this because the detection of cases where this is not valid is not totally complete. */ #define TARGET_FLAG_TAILCALL 0x40 #define TARGET_TAILCALL (target_flags & TARGET_FLAG_TAILCALL) /* Nonzero if use of a complex addressing mode is a win on this implementation. Complex addressing modes are probably not worthwhile on the K-series, but they definitely are on the C-series. */ #define TARGET_FLAG_COMPLEX_ADDR 0x80 #define TARGET_COMPLEX_ADDR (target_flags & TARGET_FLAG_COMPLEX_ADDR) /* Align code to 8 byte boundaries for faster fetching. */ #define TARGET_FLAG_CODE_ALIGN 0x100 #define TARGET_CODE_ALIGN (target_flags & TARGET_FLAG_CODE_ALIGN) /* Append branch prediction suffixes to branch opcodes. */ /* ??? Not used currently. */ #define TARGET_FLAG_BRANCH_PREDICT 0x200 #define TARGET_BRANCH_PREDICT (target_flags & TARGET_FLAG_BRANCH_PREDICT) /* Forces prototype and return promotions. */ /* ??? This does not work. */ #define TARGET_FLAG_CLEAN_LINKAGE 0x400 #define TARGET_CLEAN_LINKAGE (target_flags & TARGET_FLAG_CLEAN_LINKAGE) /* For compatibility with iC960 v3.0. */ #define TARGET_FLAG_IC_COMPAT3_0 0x800 #define TARGET_IC_COMPAT3_0 (target_flags & TARGET_FLAG_IC_COMPAT3_0) /* For compatibility with iC960 v2.0. */ #define TARGET_FLAG_IC_COMPAT2_0 0x1000 #define TARGET_IC_COMPAT2_0 (target_flags & TARGET_FLAG_IC_COMPAT2_0) /* If no unaligned accesses are to be permitted. */ #define TARGET_FLAG_STRICT_ALIGN 0x2000 #define TARGET_STRICT_ALIGN (target_flags & TARGET_FLAG_STRICT_ALIGN) /* For compatibility with iC960 assembler. */ #define TARGET_FLAG_ASM_COMPAT 0x4000 #define TARGET_ASM_COMPAT (target_flags & TARGET_FLAG_ASM_COMPAT) /* For compatibility with the gcc960 v1.2 compiler. Use the old structure alignment rules. Also, turns on STRICT_ALIGNMENT. */ #define TARGET_FLAG_OLD_ALIGN 0x8000 #define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN) extern int target_flags; /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */ /* ??? Not all ten of these architecture variations actually exist, but I am not sure which are real and which aren't. */ #define TARGET_SWITCHES \ { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\ {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \ TARGET_FLAG_COMPLEX_ADDR)},\ /* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \ {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\ {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \ TARGET_FLAG_COMPLEX_ADDR)},\ /* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \ {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\ {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\ TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\ /* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES|\ TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN)},\ {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\ TARGET_FLAG_CODE_ALIGN)}, */ \ {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\ TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\ {"numerics", (TARGET_FLAG_NUMERICS)}, \ {"soft-float", -(TARGET_FLAG_NUMERICS)}, \ {"leaf-procedures", TARGET_FLAG_LEAFPROC}, \ {"no-leaf-procedures",-(TARGET_FLAG_LEAFPROC)}, \ {"tail-call",TARGET_FLAG_TAILCALL}, \ {"no-tail-call",-(TARGET_FLAG_TAILCALL)}, \ {"complex-addr",TARGET_FLAG_COMPLEX_ADDR}, \ {"no-complex-addr",-(TARGET_FLAG_COMPLEX_ADDR)}, \ {"code-align",TARGET_FLAG_CODE_ALIGN}, \ {"no-code-align",-(TARGET_FLAG_CODE_ALIGN)}, \ {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE)}, \ {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE)}, \ {"ic-compat", TARGET_FLAG_IC_COMPAT2_0}, \ {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0}, \ {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0}, \ {"asm-compat",TARGET_FLAG_ASM_COMPAT}, \ {"intel-asm",TARGET_FLAG_ASM_COMPAT}, \ {"strict-align", TARGET_FLAG_STRICT_ALIGN}, \ {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN)}, \ {"old-align", TARGET_FLAG_OLD_ALIGN}, \ {"no-old-align", -(TARGET_FLAG_OLD_ALIGN)}, \ {"link-relax", 0}, \ {"no-link-relax", 0}, \ { "", TARGET_DEFAULT}} /* Override conflicting target switch options. Doesn't actually detect if more than one -mARCH option is given, but does handle the case of two blatantly conflicting -mARCH options. */ #define OVERRIDE_OPTIONS \ { \ if (TARGET_K_SERIES && TARGET_C_SERIES) \ { \ warning ("conflicting architectures defined - using C series", 0); \ target_flags &= ~TARGET_FLAG_K_SERIES; \ } \ if (TARGET_K_SERIES && TARGET_MC) \ { \ warning ("conflicting architectures defined - using K series", 0); \ target_flags &= ~TARGET_FLAG_MC; \ } \ if (TARGET_C_SERIES && TARGET_MC) \ { \ warning ("conflicting architectures defined - using C series", 0);\ target_flags &= ~TARGET_FLAG_MC; \ } \ if (TARGET_IC_COMPAT3_0) \ { \ flag_short_enums = 1; \ flag_signed_char = 1; \ target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \ if (TARGET_IC_COMPAT2_0) \ { \ warning ("iC2.0 and iC3.0 are incompatible - using iC3.0", 0); \ target_flags &= ~TARGET_FLAG_IC_COMPAT2_0; \ } \ } \ if (TARGET_IC_COMPAT2_0) \ { \ flag_signed_char = 1; \ target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \ } \ i960_initialize (); \ } /* Don't enable anything by default. The user is expected to supply a -mARCH option. If none is given, then -mkb is added by CC1_SPEC. */ #define TARGET_DEFAULT 0 /* Target machine storage layout. */ /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. */ #define BITS_BIG_ENDIAN 0 /* Define this if most significant byte of a word is the lowest numbered. The i960 case be either big endian or little endian. We only support little endian, which is the most common. */ #define BYTES_BIG_ENDIAN 0 /* Define this if most significant word of a multiword number is lowest numbered. */ #define WORDS_BIG_ENDIAN 0 /* Number of bits in an addressable storage unit. */ #define BITS_PER_UNIT 8 /* Bitfields cannot cross word boundaries. */ #define BITFIELD_NBYTES_LIMITED 1 /* Width in bits of a "word", which is the contents of a machine register. Note that this is not necessarily the width of data type `int'; if using 16-bit ints on a 68000, this would still be 32. But on a machine with 16-bit registers, this would be 16. */ #define BITS_PER_WORD 32 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 4 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ #define POINTER_SIZE 32 /* Width in bits of a long double. Identical to double for now. */ #define LONG_DOUBLE_TYPE_SIZE 64 /* Allocation boundary (in *bits*) for storing pointers in memory. */ #define POINTER_BOUNDARY 32 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ #define PARM_BOUNDARY 32 /* Boundary (in *bits*) on which stack pointer should be aligned. */ #define STACK_BOUNDARY 128 /* Allocation boundary (in *bits*) for the code of a function. */ #define FUNCTION_BOUNDARY 128 /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 32 /* This makes zero-length anonymous fields lay the next field at a word boundary. It also makes the whole struct have at least word alignment if there are any bitfields at all. */ #define PCC_BITFIELD_TYPE_MATTERS 1 /* Every structure's size must be a multiple of this. */ #define STRUCTURE_SIZE_BOUNDARY 8 /* No data type wants to be aligned rounder than this. Extended precision floats gets 4-word alignment. */ #define BIGGEST_ALIGNMENT 128 /* Define this if move instructions will actually fail to work when given unaligned data. 80960 will work even with unaligned data, but it is slow. */ #define STRICT_ALIGNMENT TARGET_OLD_ALIGN /* Specify alignment for string literals (which might be higher than the base type's minimal alignment requirement. This allows strings to be aligned on word boundaries, and optimizes calls to the str* and mem* library functions. */ #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ (TREE_CODE (EXP) == STRING_CST \ && i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \ ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \ : (ALIGN)) /* Macros to determine size of aggregates (structures and unions in C). Normally, these may be defined to simply return the maximum alignment and simple rounded-up size, but on some machines (like the i960), the total size of a structure is based on a non-trivial rounding method. */ #define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \ ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \ ? i960_round_align ((SPECIFIED), TYPE_SIZE (TYPE)) \ : MAX ((COMPUTED), (SPECIFIED))) #define ROUND_TYPE_SIZE(TYPE, SIZE, ALIGN) \ ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \ ? (tree) i960_round_size (SIZE) \ : round_up ((SIZE), (ALIGN))) /* Standard register usage. */ /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. Registers 0-15 are the global registers (g0-g15). Registers 16-31 are the local registers (r0-r15). Register 32-35 are the fp registers (fp0-fp3). Register 36 is the condition code register. Register 37 is unused. */ #define FIRST_PSEUDO_REGISTER 38 /* 1 for registers that have pervasive standard uses and are not available for the register allocator. On 80960, this includes the frame pointer (g15), the previous FP (r0), the stack pointer (r1), the return instruction pointer (r2), and the argument pointer (g14). */ #define FIXED_REGISTERS \ {0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 1, 1, \ 1, 1, 1, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 1, 1} /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. */ /* On the 80960, note that: g0..g3 are used for return values, g0..g7 may always be used for parameters, g8..g11 may be used for parameters, but are preserved if they aren't, g12 is always preserved, but otherwise unused, g13 is the struct return ptr if used, or temp, but may be trashed, g14 is the leaf return ptr or the arg block ptr otherwise zero, must be reset to zero before returning if it was used, g15 is the frame pointer, r0 is the previous FP, r1 is the stack pointer, r2 is the return instruction pointer, r3-r15 are always available, r3 is clobbered by calls in functions that use the arg pointer r4-r11 may be clobbered by the mcount call when profiling r4-r15 if otherwise unused may be used for preserving global registers fp0..fp3 are never available. */ #define CALL_USED_REGISTERS \ {1, 1, 1, 1, 1, 1, 1, 1, \ 0, 0, 0, 0, 0, 1, 1, 1, \ 1, 1, 1, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1, 1, 1, 1, 1} /* If no fp unit, make all of the fp registers fixed so that they can't be used. */ #define CONDITIONAL_REGISTER_USAGE \ if (! TARGET_NUMERICS) { \ fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\ } \ /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. On 80960, ordinary registers hold 32 bits worth, but can be ganged together to hold double or extended precision floating point numbers, and the floating point registers hold any size floating point number */ #define HARD_REGNO_NREGS(REGNO, MODE) \ ((REGNO) < 32 \ ? (((MODE) == VOIDmode) \ ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \ : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On 80960, the cpu registers can hold any mode but the float registers can only hold SFmode, DFmode, or TFmode. */ extern unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER]; #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ((hard_regno_mode_ok[REGNO] & (1 << (int) (MODE))) != 0) /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. */ #define MODES_TIEABLE_P(MODE1, MODE2) \ ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ /* 80960 pc isn't overloaded on a register that the compiler knows about. */ /* #define PC_REGNUM */ /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM 17 /* Actual top-of-stack address is same as the contents of the stack pointer register. */ #define STACK_POINTER_OFFSET (-current_function_outgoing_args_size) /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM 15 /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */ /* ??? It isn't clear to me why this is here. Perhaps because of a bug (since fixed) in the definition of INITIAL_FRAME_POINTER_OFFSET which would have caused this to fail. */ #define FRAME_POINTER_REQUIRED (! leaf_function_p ()) /* C statement to store the difference between the frame pointer and the stack pointer values immediately after the function prologue. Since the stack grows upward on the i960, this must be a negative number. This includes the 64 byte hardware register save area and the size of the frame. */ #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ do { (VAR) = - (64 + compute_frame_size (get_frame_size ())); } while (0) /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM 14 /* Register in which static-chain is passed to a function. On i960, we use r3. */ #define STATIC_CHAIN_REGNUM 19 /* Functions which return large structures get the address to place the wanted value at in g13. */ #define STRUCT_VALUE_REGNUM 13 /* The order in which to allocate registers. */ #define REG_ALLOC_ORDER \ { 4, 5, 6, 7, 0, 1, 2, 3, 13, /* g4, g5, g6, g7, g0, g1, g2, g3, g13 */ \ 20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11 */ \ 28, 29, 30, 31, 19, 8, 9, 10, /* r12, r13, r14, r15, r3, g8, g9, g10 */ \ 11, 12, /* g11, g12 */ \ 32, 33, 34, 35, /* fp0, fp1, fp2, fp3 */ \ /* We can't actually allocate these. */ \ 16, 17, 18, 14, 15, 36, 37} /* r0, r1, r2, g14, g15, cc */ /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. One of the classes must always be named ALL_REGS and include all hard regs. If there is more than one class, another class must be named NO_REGS and contain no registers. The name GENERAL_REGS must be the name of a class (or an alias for another name such as ALL_REGS). This is the class of registers that is allowed by "g" or "r" in a register constraint. Also, registers outside this class are allocated only when instructions express preferences for them. The classes must be numbered in nondecreasing order; that is, a larger-numbered class must never be contained completely in a smaller-numbered class. For any two classes, it is very desirable that there be another class that represents their union. */ /* The 80960 has four kinds of registers, global, local, floating point, and condition code. The cc register is never allocated, so no class needs to be defined for it. */ enum reg_class { NO_REGS, GLOBAL_REGS, LOCAL_REGS, LOCAL_OR_GLOBAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES }; /* 'r' includes floating point registers if TARGET_NUMERICS. 'd' never does. */ #define GENERAL_REGS ((TARGET_NUMERICS) ? ALL_REGS : LOCAL_OR_GLOBAL_REGS) #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ { "NO_REGS", "GLOBAL_REGS", "LOCAL_REGS", "LOCAL_OR_GLOBAL_REGS", \ "FP_REGS", "ALL_REGS" } /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS \ { {0, 0}, {0x0ffff, 0}, {0xffff0000, 0}, {-1,0}, {0, -1}, {-1,-1}} /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ #define REGNO_REG_CLASS(REGNO) \ ((REGNO) < 16 ? GLOBAL_REGS \ : (REGNO) < 32 ? LOCAL_REGS \ : (REGNO) < 36 ? FP_REGS \ : NO_REGS) /* The class value for index registers, and the one for base regs. There is currently no difference between base and index registers on the i960, but this distinction may one day be useful. */ #define INDEX_REG_CLASS LOCAL_OR_GLOBAL_REGS #define BASE_REG_CLASS LOCAL_OR_GLOBAL_REGS /* Get reg_class from a letter such as appears in the machine description. 'f' is a floating point register (fp0..fp3) 'l' is a local register (r0-r15) 'b' is a global register (g0-g15) 'd' is any local or global register 'r' or 'g' are pre-defined to the class GENERAL_REGS. */ /* 'l' and 'b' are probably never used. Note that 'd' and 'r' are *not* the same thing, since 'r' may include the fp registers. */ #define REG_CLASS_FROM_LETTER(C) \ (((C) == 'f') && (TARGET_NUMERICS) ? FP_REGS : ((C) == 'l' ? LOCAL_REGS : \ (C) == 'b' ? GLOBAL_REGS : ((C) == 'd' ? LOCAL_OR_GLOBAL_REGS : NO_REGS))) /* The letters I, J, K, L and M in a register constraint string can be used to stand for particular ranges of immediate operands. This macro defines what the ranges are. C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. For 80960: 'I' is used for literal values 0..31 'J' means literal 0 'K' means 0..-31. */ #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? (((unsigned) (VALUE)) <= 31) \ : (C) == 'J' ? ((VALUE) == 0) \ : (C) == 'K' ? ((VALUE) > -32 && (VALUE) <= 0) \ : 0) /* Similar, but for floating constants, and defining letters G and H. Here VALUE is the CONST_DOUBLE rtx itself. For the 80960, G is 0.0 and H is 1.0. */ #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ ((TARGET_NUMERICS) && \ (((C) == 'G' && ((VALUE) == CONST0_RTX (DFmode) \ || (VALUE) == CONST0_RTX (SFmode))) \ || ((C) == 'H' && ((VALUE) == CONST1_RTX (DFmode) \ || (VALUE) == CONST1_RTX (SFmode))))) /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. */ /* On 960, can't load constant into floating-point reg except 0.0 or 1.0. Any hard reg is ok as a src operand of a reload insn. */ #define PREFERRED_RELOAD_CLASS(X,CLASS) \ (GET_CODE (X) == REG && REGNO (X) < FIRST_PSEUDO_REGISTER \ ? (CLASS) \ : ((CLASS) == FP_REGS && CONSTANT_P (X) \ && (X) != CONST0_RTX (DFmode) && (X) != CONST1_RTX (DFmode)\ && (X) != CONST0_RTX (SFmode) && (X) != CONST1_RTX (SFmode)\ ? NO_REGS \ : (CLASS) == ALL_REGS ? LOCAL_OR_GLOBAL_REGS : (CLASS))) #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ secondary_reload_class (CLASS, MODE, IN) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ /* On 80960, this is the size of MODE in words, except in the FP regs, where a single reg is always enough. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ ((CLASS) == FP_REGS ? 1 : HARD_REGNO_NREGS (0, (MODE))) /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack makes the stack pointer a smaller address. */ /* #define STACK_GROWS_DOWNWARD */ /* Define this if the nominal address of the stack frame is at the high-address end of the local variables; that is, each additional local variable allocated goes at a more negative offset in the frame. */ /* #define FRAME_GROWS_DOWNWARD */ /* Offset within stack frame to start allocating local variables at. If FRAME_GROWS_DOWNWARD, this is the offset to the END of the first local allocated. Otherwise, it is the offset to the BEGINNING of the first local allocated. The i960 has a 64 byte register save area, plus possibly some extra bytes allocated for varargs functions. */ #define STARTING_FRAME_OFFSET 64 /* If we generate an insn to push BYTES bytes, this says how many the stack pointer really advances by. On 80960, don't define this because there are no push insns. */ /* #define PUSH_ROUNDING(BYTES) BYTES */ /* Offset of first parameter from the argument pointer register value. */ #define FIRST_PARM_OFFSET(FNDECL) 0 /* When a parameter is passed in a register, no stack space is allocated for it. However, when args are passed in the stack, space is allocated for every register parameter. */ #define MAYBE_REG_PARM_STACK_SPACE 48 #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) \ i960_final_reg_parm_stack_space (CONST_SIZE, VAR_SIZE); #define REG_PARM_STACK_SPACE(DECL) i960_reg_parm_stack_space (DECL) #define OUTGOING_REG_PARM_STACK_SPACE /* Keep the stack pointer constant throughout the function. */ #define ACCUMULATE_OUTGOING_ARGS /* Value is 1 if returning from a function call automatically pops the arguments described by the number-of-args field in the call. FUNTYPE is the data type of the function (as a tree), or for a library call it is an identifier node for the subroutine name. */ #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0 /* Define how to find the value returned by a library function assuming the value has mode MODE. */ #define LIBCALL_VALUE(MODE) gen_rtx ((REG), (MODE), 0) /* 1 if N is a possible register number for a function value as seen by the caller. On 80960, returns are in g0..g3 */ #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) /* 1 if N is a possible register number for function argument passing. On 80960, parameters are passed in g0..g11 */ #define FUNCTION_ARG_REGNO_P(N) ((N) < 12) /* Perform any needed actions needed for a function that is receiving a variable number of arguments. CUM is as above. MODE and TYPE are the mode and type of the current parameter. PRETEND_SIZE is a variable that should be set to the amount of stack that must be pushed by the prolog to pretend that our caller pushed it. Normally, this macro will push all remaining incoming registers on the stack and set PRETEND_SIZE to the length of the registers pushed. */ #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL) /* Define a data type for recording info about an argument list during the scan of that argument list. This data type should hold all necessary information about the function itself and about the args processed so far, enough to enable macros such as FUNCTION_ARG to determine where the next arg should go. On 80960, this is two integers, which count the number of register parameters and the number of stack parameters seen so far. */ struct cum_args { int ca_nregparms; int ca_nstackparms; }; #define CUMULATIVE_ARGS struct cum_args /* Define the number of registers that can hold parameters. This macro is used only in macro definitions below and/or i960.c. */ #define NPARM_REGS 12 /* Define how to round to the next parameter boundary. This macro is used only in macro definitions below and/or i960.c. */ #define ROUND_PARM(X, MULTIPLE_OF) \ ((((X) + (MULTIPLE_OF) - 1) / (MULTIPLE_OF)) * MULTIPLE_OF) /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. On 80960, the offset always starts at 0; the first parm reg is g0. */ #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ ((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. CUM should be advanced to align with the data type accessed and also the size of that data type in # of regs. (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ i960_function_arg_advance(&CUM, MODE, TYPE, NAMED) /* Indicate the alignment boundary for an argument of the specified mode and type. */ #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ (((TYPE) != 0) \ ? ((TYPE_ALIGN (TYPE) <= PARM_BOUNDARY) \ ? PARM_BOUNDARY \ : TYPE_ALIGN (TYPE)) \ : ((GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY) \ ? PARM_BOUNDARY \ : GET_MODE_ALIGNMENT (MODE))) /* Determine where to put an argument to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. MODE is the argument's machine mode. TYPE is the data type of the argument (as a tree). This is null for libcalls where that information may not be available. CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called. NAMED is nonzero if this argument is a named parameter (otherwise it is an extra parameter matching an ellipsis). */ extern struct rtx_def *i960_function_arg (); #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ i960_function_arg(&CUM, MODE, TYPE, NAMED) /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */ #define FUNCTION_VALUE(TYPE, FUNC) \ gen_rtx (REG, TYPE_MODE (TYPE), 0) /* Force aggregates and objects larger than 16 bytes to be returned in memory, since we only have 4 registers available for return values. */ #define RETURN_IN_MEMORY(TYPE) \ (TYPE_MODE (TYPE) == BLKmode || int_size_in_bytes (TYPE) > 16) /* Don't default to pcc-struct-return, because we have already specified exactly how to return structures in the RETURN_IN_MEMORY macro. */ #define DEFAULT_PCC_STRUCT_RETURN 0 /* For an arg passed partly in registers and partly in memory, this is the number of registers used. This never happens on 80960. */ #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 /* Output the label for a function definition. This handles leaf functions and a few other things for the i960. */ #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ i960_function_name_declare (FILE, NAME, DECL) /* This macro generates the assembly code for function entry. FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. Refer to the array `regs_ever_live' to determine which registers to save; `regs_ever_live[I]' is nonzero if register number I is ever used in the function. This macro is responsible for knowing which registers should not be saved even if used. */ #define FUNCTION_PROLOGUE(FILE, SIZE) i960_function_prologue ((FILE), (SIZE)) /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ #define FUNCTION_PROFILER(FILE, LABELNO) \ output_function_profiler ((FILE), (LABELNO)); /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, the stack pointer does not matter. The value is tested only in functions that have frame pointers. No definition is equivalent to always zero. */ #define EXIT_IGNORE_STACK 1 /* This macro generates the assembly code for function exit, on machines that need it. If FUNCTION_EPILOGUE is not defined then individual return instructions are generated for each return statement. Args are same as for FUNCTION_PROLOGUE. The function epilogue should not depend on the current stack pointer! It should use the frame pointer only. This is mandatory because of alloca; we also take advantage of it to omit stack adjustments before returning. */ #define FUNCTION_EPILOGUE(FILE, SIZE) i960_function_epilogue (FILE, SIZE) /* Addressing modes, and classification of registers for them. */ /* #define HAVE_POST_INCREMENT */ /* #define HAVE_POST_DECREMENT */ /* #define HAVE_PRE_DECREMENT */ /* #define HAVE_PRE_INCREMENT */ /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. */ #define REGNO_OK_FOR_INDEX_P(REGNO) \ ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) #define REGNO_OK_FOR_BASE_P(REGNO) \ ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) #define REGNO_OK_FOR_FP_P(REGNO) \ ((REGNO) < 36 || (unsigned) reg_renumber[REGNO] < 36) /* Now macros that check whether X is a register and also, strictly, whether it is in a specified class. These macros are specific to the 960, and may be used only in code for printing assembler insns and in conditions for define_optimization. */ /* 1 if X is an fp register. */ #define FP_REG_P(X) (REGNO (X) >= 32 && REGNO (X) < 36) /* Maximum number of registers that can appear in a valid memory address. */ #define MAX_REGS_PER_ADDRESS 2 #define CONSTANT_ADDRESS_P(X) \ (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ || GET_CODE (X) == HIGH) /* LEGITIMATE_CONSTANT_P is nonzero if the constant value X is a legitimate general operand. It is given that X satisfies CONSTANT_P. Anything but a CONST_DOUBLE can be made to work, excepting 0.0 and 1.0. */ #define LEGITIMATE_CONSTANT_P(X) \ ((GET_CODE (X) != CONST_DOUBLE) || fp_literal ((X), VOIDmode)) /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. The usual definition accepts all pseudo regs; the other rejects them unless they have been allocated suitable hard regs. The symbol REG_OK_STRICT causes the latter definition to be used. Most source files want to accept pseudo regs in the hope that they will get allocated to the class that the insn wants them to be in. Source files for reload pass need to be strict. After reload, it makes no difference, since pseudo regs have been eliminated by then. */ #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ #define REG_OK_FOR_INDEX_P(X) \ (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER) /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ #define REG_OK_FOR_BASE_P(X) \ (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER) #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X)) #else /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) #endif /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. On 80960, legitimate addresses are: base ld (g0),r0 disp (12 or 32 bit) ld foo,r0 base + index ld (g0)[g1*1],r0 base + displ ld 0xf00(g0),r0 base + index*scale + displ ld 0xf00(g0)[g1*4],r0 index*scale + base ld (g0)[g1*4],r0 index*scale + displ ld 0xf00[g1*4],r0 index*scale ld [g1*4],r0 index + base + displ ld 0xf00(g0)[g1*1],r0 In each case, scale can be 1, 2, 4, 8, or 16. */ /* Returns 1 if the scale factor of an index term is valid. */ #define SCALE_TERM_P(X) \ (GET_CODE (X) == CONST_INT \ && (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \ || INTVAL(X) == 8 || INTVAL (X) == 16)) #ifdef REG_OK_STRICT #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { if (legitimate_address_p (MODE, X, 1)) goto ADDR; } #else #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { if (legitimate_address_p (MODE, X, 0)) goto ADDR; } #endif /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. OLDX is the address as it was before break_out_memory_refs was called. In some cases it is useful to look at this to decide what needs to be done. MODE and WIN are passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. It is always safe for this macro to do nothing. It exists to recognize opportunities to optimize the output. */ /* On 80960, convert non-canonical addresses to canonical form. */ extern struct rtx_def *legitimize_address (); #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ { rtx orig_x = (X); \ (X) = legitimize_address (X, OLDX, MODE); \ if ((X) != orig_x && memory_address_p (MODE, X)) \ goto WIN; } /* Go to LABEL if ADDR (a legitimate address expression) has an effect that depends on the machine mode it is used for. On the 960 this is never true. */ #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE SImode /* Define this if the tablejump instruction expects the table to contain offsets from the address of the table. Do not define this if the table should contain absolute addresses. */ /* #define CASE_VECTOR_PC_RELATIVE */ /* Specify the tree operation to be used to convert reals to integers. */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR /* This is the kind of divide that is easiest to do in the general case. */ #define EASY_DIV_EXPR TRUNC_DIV_EXPR /* Define this as 1 if `char' should by default be signed; else as 0. */ #define DEFAULT_SIGNED_CHAR 0 /* Allow and ignore #sccs directives. */ #define SCCS_DIRECTIVE /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ #define MOVE_MAX 16 /* Define if operations between registers always perform the operation on the full register even if a narrower mode is specified. */ #define WORD_REGISTER_OPERATIONS /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly done, NIL if none. */ #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Nonzero if access to memory by bytes is no faster than for words. Defining this results in worse code on the i960. */ #define SLOW_BYTE_ACCESS 0 /* We assume that the store-condition-codes instructions store 0 for false and some other value for true. This is the value stored for true. */ #define STORE_FLAG_VALUE 1 /* Define this to be nonzero if shift instructions ignore all but the low-order few bits. */ #define SHIFT_COUNT_TRUNCATED 1 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ #define Pmode SImode /* Specify the widest mode that BLKmode objects can be promoted to */ #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) /* These global variables are used to pass information between cc setter and cc user at insn emit time. */ extern struct rtx_def *i960_compare_op0, *i960_compare_op1; /* Define the function that build the compare insn for scc and bcc. */ extern struct rtx_def *gen_compare_reg (); /* Add any extra modes needed to represent the condition code. Also, signed and unsigned comparisons are distinguished, as are operations which are compatible with chkbit insns. */ #define EXTRA_CC_MODES CC_UNSmode, CC_CHKmode /* Define the names for the modes specified above. */ #define EXTRA_CC_NAMES "CC_UNS", "CC_CHK" /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, return the mode to be used for the comparison. For floating-point, CCFPmode should be used. CC_NOOVmode should be used when the first operand is a PLUS, MINUS, or NEG. CCmode should be used when no special processing is needed. */ #define SELECT_CC_MODE(OP,X,Y) select_cc_mode (OP, X) /* A function address in a call instruction is a byte address (for indexing purposes) so give the MEM rtx a byte's mode. */ #define FUNCTION_MODE SImode /* Define this if addresses of constant functions shouldn't be put through pseudo regs where they can be cse'd. Desirable on machines where ordinary constants are expensive but a CALL with constant address is cheap. */ #define NO_FUNCTION_CSE /* Use memcpy, etc. instead of bcopy. */ #ifndef WIND_RIVER #define TARGET_MEM_FUNCTIONS 1 #endif /* Compute the cost of computing a constant rtl expression RTX whose rtx-code is CODE. The body of this macro is a portion of a switch statement. If the code is computed here, return it with a return statement. Otherwise, break from the switch. */ /* Constants that can be (non-ldconst) insn operands are cost 0. Constants that can be non-ldconst operands in rare cases are cost 1. Other constants have higher costs. */ #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ case CONST_INT: \ if ((INTVAL (RTX) >= 0 && INTVAL (RTX) < 32) \ || power2_operand (RTX, VOIDmode)) \ return 0; \ else if (INTVAL (RTX) >= -31 && INTVAL (RTX) < 0) \ return 1; \ case CONST: \ case LABEL_REF: \ case SYMBOL_REF: \ return (TARGET_FLAG_C_SERIES ? 6 : 8); \ case CONST_DOUBLE: \ if ((RTX) == CONST0_RTX (DFmode) || (RTX) == CONST0_RTX (SFmode) \ || (RTX) == CONST1_RTX (DFmode) || (RTX) == CONST1_RTX (SFmode))\ return 1; \ return 12; /* The i960 offers addressing modes which are "as cheap as a register". See i960.c (or gcc.texinfo) for details. */ #define ADDRESS_COST(RTX) \ (GET_CODE (RTX) == REG ? 1 : i960_address_cost (RTX)) /* Control the assembler format that we output. */ /* Output at beginning of assembler file. */ #define ASM_FILE_START(file) /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ #define ASM_APP_ON "" /* Output to assembler file text saying following lines no longer contain unusual constructs. */ #define ASM_APP_OFF "" /* Output before read-only data. */ #define TEXT_SECTION_ASM_OP ".text" /* Output before writable data. */ #define DATA_SECTION_ASM_OP ".data" /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ #define REGISTER_NAMES { \ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \ "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \ "pfp","sp", "rip", "r3", "r4", "r5", "r6", "r7", \ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ "fp0","fp1","fp2", "fp3", "cc", "fake" } /* How to renumber registers for dbx and gdb. In the 960 encoding, g0..g15 are registers 16..31. */ #define DBX_REGISTER_NUMBER(REGNO) \ (((REGNO) < 16) ? (REGNO) + 16 \ : (((REGNO) > 31) ? (REGNO) : (REGNO) - 16)) /* Don't emit dbx records longer than this. This is an arbitrary value. */ #define DBX_CONTIN_LENGTH 1500 /* This is how to output a note to DBX telling it the line number to which the following sequence of instructions corresponds. */ #define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \ { if (write_symbols == SDB_DEBUG) { \ fprintf ((FILE), "\t.ln %d\n", \ (sdb_begin_function_line \ ? (LINE) - sdb_begin_function_line : 1)); \ } else if (write_symbols == DBX_DEBUG) { \ fprintf((FILE),"\t.stabd 68,0,%d\n",(LINE)); \ } } /* This is how to output the definition of a user-level label named NAME, such as the label on a static function or variable NAME. */ #define ASM_OUTPUT_LABEL(FILE,NAME) \ do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) /* This is how to output a command to make the user-level label named NAME defined for reference from other files. */ #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ { fputs ("\t.globl ", FILE); \ assemble_name (FILE, NAME); \ fputs ("\n", FILE); } /* This is how to output a reference to a user-level label named NAME. `assemble_name' uses this. */ #define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "_%s", NAME) /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, "%s%d:\n", PREFIX, NUM) /* This is how to store into the string LABEL the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ sprintf (LABEL, "*%s%d", PREFIX, NUM) /* This is how to output an assembler line defining a `double' constant. */ #define ASM_OUTPUT_DOUBLE(FILE,VALUE) i960_output_double(FILE, VALUE) /* This is how to output an assembler line defining a `float' constant. */ #define ASM_OUTPUT_FLOAT(FILE,VALUE) i960_output_float(FILE, VALUE) /* This is how to output an assembler line defining an `int' constant. */ #define ASM_OUTPUT_INT(FILE,VALUE) \ ( fprintf (FILE, "\t.word "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* Likewise for `char' and `short' constants. */ #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "\t.short "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ( fprintf (FILE, "\t.byte "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* This is how to output an assembler line for a numeric constant byte. */ #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO]) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tsubo\t4,sp,sp\n\tld\t(sp),%s\n", reg_names[REGNO]) /* This is how to output an element of a case-vector that is absolute. */ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "\t.word L%d\n", VALUE) /* This is how to output an element of a case-vector that is relative. */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL) /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #define ASM_OUTPUT_ALIGN(FILE,LOG) \ fprintf (FILE, "\t.align %d\n", (LOG)) #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t.space %d\n", (SIZE)) /* This says how to output an assembler line to define a global common symbol. */ /* For common objects, output unpadded size... gld960 & lnk960 both have code to align each common object at link time. Also, if size is 0, treat this as a declaration, not a definition - i.e., do nothing at all. */ #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ { if ((SIZE) != 0) \ { \ fputs (".globl ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fputs ("\n.comm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%d\n", (SIZE)); \ } \ } /* This says how to output an assembler line to define a local common symbol. Output unpadded size, with request to linker to align as requested. 0 size should not be possible here. */ #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ ( fputs (".bss\t", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%d,%d\n", (SIZE), \ ((ALIGN) <= 8 ? 0 \ : ((ALIGN) <= 16 ? 1 \ : ((ALIGN) <= 32 ? 2 \ : ((ALIGN <= 64 ? 3 : 4))))))) /* Output text for an #ident directive. */ #define ASM_OUTPUT_IDENT(FILE, STR) fprintf(FILE, "\t# %s\n", STR); /* Align code to 8 byte boundary if TARGET_CODE_ALIGN is true. */ #define ASM_OUTPUT_ALIGN_CODE(FILE) \ { if (TARGET_CODE_ALIGN) fputs("\t.align 3\n",FILE); } /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) /* Define the parentheses used to group arithmetic operations in assembler code. */ #define ASM_OPEN_PAREN "(" #define ASM_CLOSE_PAREN ")" /* Define results of standard character escape sequences. */ #define TARGET_BELL 007 #define TARGET_BS 010 #define TARGET_TAB 011 #define TARGET_NEWLINE 012 #define TARGET_VT 013 #define TARGET_FF 014 #define TARGET_CR 015 /* Output assembler code to FILE to initialize this source file's basic block profiling info, if that has not already been done. */ #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ { fprintf (FILE, "\tld LPBX0,g12\n"); \ fprintf (FILE, "\tcmpobne 0,g12,LPY%d\n",LABELNO);\ fprintf (FILE, "\tlda LPBX0,g12\n"); \ fprintf (FILE, "\tcall ___bb_init_func\n"); \ fprintf (FILE, "LPY%d:\n",LABELNO); } /* Output assembler code to FILE to increment the entry-count for the BLOCKNO'th basic block in this source file. */ #define BLOCK_PROFILER(FILE, BLOCKNO) \ { int blockn = (BLOCKNO); \ fprintf (FILE, "\tld LPBX2+%d,g12\n", 4 * blockn); \ fprintf (FILE, "\taddo g12,1,g12\n"); \ fprintf (FILE, "\tst g12,LPBX2+%d\n", 4 * blockn); } /* Print operand X (an rtx) in assembler syntax to file FILE. CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. For `%' followed by punctuation, CODE is the punctuation and X is null. */ #define PRINT_OPERAND(FILE, X, CODE) \ i960_print_operand (FILE, X, CODE); /* Print a memory address as an operand to reference that memory location. */ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ i960_print_operand_addr (FILE, ADDR) /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. */ /* On the i960, the trampoline contains three instructions: ldconst _function, r4 ldconst static addr, r3 jump (r4) */ #define TRAMPOLINE_TEMPLATE(FILE) \ { \ ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C203000)); \ ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C183000)); \ ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x84212000)); \ } /* Length in units of the trampoline for entering a nested function. */ #define TRAMPOLINE_SIZE 20 /* Emit RTL insns to initialize the variable parts of a trampoline. FNADDR is an RTX for the address of the function's pure code. CXT is an RTX for the static chain value for the function. */ #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), \ FNADDR); \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), \ CXT); \ } #if 0 /* Promote char and short arguments to ints, when want compatibility with the iC960 compilers. */ /* ??? In order for this to work, all users would need to be changed to test the value of the macro at run time. */ #define PROMOTE_PROTOTYPES TARGET_CLEAN_LINKAGE /* ??? This does not exist. */ #define PROMOTE_RETURN TARGET_CLEAN_LINKAGE #endif /* Instruction type definitions. Used to alternate instructions types for better performance on the C series chips. */ enum insn_types { I_TYPE_REG, I_TYPE_MEM, I_TYPE_CTRL }; /* Holds the insn type of the last insn output to the assembly file. */ extern enum insn_types i960_last_insn_type; /* Parse opcodes, and set the insn last insn type based on them. */ #define ASM_OUTPUT_OPCODE(FILE, INSN) i960_scan_opcode (INSN) /* Table listing what rtl codes each predicate in i960.c will accept. */ #define PREDICATE_CODES \ {"fpmove_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ LABEL_REF, SUBREG, REG, MEM}}, \ {"arith_operand", {SUBREG, REG, CONST_INT}}, \ {"fp_arith_operand", {SUBREG, REG, CONST_DOUBLE}}, \ {"signed_arith_operand", {SUBREG, REG, CONST_INT}}, \ {"literal", {CONST_INT}}, \ {"fp_literal_one", {CONST_DOUBLE}}, \ {"fp_literal_double", {CONST_DOUBLE}}, \ {"fp_literal", {CONST_DOUBLE}}, \ {"signed_literal", {CONST_INT}}, \ {"symbolic_memory_operand", {SUBREG, MEM}}, \ {"eq_or_neq", {EQ, NE}}, \ {"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT, \ CONST_DOUBLE, CONST}}, \ {"power2_operand", {CONST_INT}}, \ {"cmplpower2_operand", {CONST_INT}}, /* Define functions in i960.c and used in insn-output.c. */ extern char *i960_output_ldconst (); extern char *i960_output_call_insn (); extern char *i960_output_ret_insn (); /* Defined in reload.c, and used in insn-recog.c. */ extern int rtx_equal_function_value_matters; gcc-2.5.8/config/i960/i960.md100444 22011 13 230252 5400770546 14003 0ustar kenneruser;;- Machine description for Intel 80960 chip for GNU C compiler ;; Copyright (C) 1992 Free Software Foundation, Inc. ;; Contributed by Steven McGeady, Intel Corp. ;; Additional work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson ;; Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support. ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ;; There are very few (4) 'f' registers, they can't be loaded/stored from/to ;; memory, and some instructions explicitly require them, so we get better ;; code by discouraging psuedo-registers from being allocated to them. ;; However, we do want to allow all patterns which can store to them to ;; include them in their constraints, so we always use '*f' in a destination ;; constraint except when 'f' is the only alternative. ;; Insn attributes which describe the i960. ;; Modscan is not used, since the compiler never emits any of these insns. (define_attr "type" "move,arith,alu2,mult,div,modscan,load,store,branch,call,address,compare,fpload,fpstore,fpmove,fpcvt,fpcc,fpadd,fpmul,fpdiv,multi,misc" (const_string "arith")) ;; Length (in # of insns). (define_attr "length" "" (cond [(eq_attr "type" "load,fpload") (if_then_else (match_operand 1 "symbolic_memory_operand" "") (const_int 2) (const_int 1)) (eq_attr "type" "store,fpstore") (if_then_else (match_operand 0 "symbolic_memory_operand" "") (const_int 2) (const_int 1)) (eq_attr "type" "address") (const_int 2)] (const_int 1))) (define_asm_attributes [(set_attr "length" "1") (set_attr "type" "multi")]) ;; (define_function_unit {name} {num-units} {n-users} {test} ;; {ready-delay} {issue-delay} [{conflict-list}]) ;; The integer ALU (define_function_unit "alu" 2 0 (eq_attr "type" "arith,compare,move,address") 1 0) (define_function_unit "alu" 2 0 (eq_attr "type" "alu2") 2 0) (define_function_unit "alu" 2 0 (eq_attr "type" "mult") 5 0) (define_function_unit "alu" 2 0 (eq_attr "type" "div") 35 0) (define_function_unit "alu" 2 0 (eq_attr "type" "modscan") 3 0) ;; Memory with load-delay of 1 (i.e., 2 cycle load). (define_function_unit "memory" 1 0 (eq_attr "type" "load,fpload") 2 0) ;; Floating point operations. (define_function_unit "fp" 1 2 (eq_attr "type" "fpmove") 5 0) (define_function_unit "fp" 1 2 (eq_attr "type" "fpcvt") 35 0) (define_function_unit "fp" 1 2 (eq_attr "type" "fpcc") 10 0) (define_function_unit "fp" 1 2 (eq_attr "type" "fpadd") 10 0) (define_function_unit "fp" 1 2 (eq_attr "type" "fpmul") 20 0) (define_function_unit "fp" 1 2 (eq_attr "type" "fpdiv") 35 0) ;; Compare instructions. ;; This controls RTL generation and register allocation. ;; We generate RTL for comparisons and branches by having the cmpxx ;; patterns store away the operands. Then, the scc and bcc patterns ;; emit RTL for both the compare and the branch. ;; ;; We start with the DEFINE_EXPANDs, then then DEFINE_INSNs to match ;; the patterns. Finally, we have the DEFINE_SPLITs for some of the scc ;; insns that actually require more than one machine instruction. ;; Put cmpsi first because it is expected to be the most common. (define_expand "cmpsi" [(set (reg:CC 36) (compare:CC (match_operand:SI 0 "nonimmediate_operand" "") (match_operand:SI 1 "general_operand" "")))] "" " { i960_compare_op0 = operands[0]; i960_compare_op1 = operands[1]; DONE; }") (define_expand "cmpdf" [(set (reg:CC 36) (compare:CC (match_operand:DF 0 "register_operand" "r") (match_operand:DF 1 "nonmemory_operand" "rGH")))] "TARGET_NUMERICS" " { i960_compare_op0 = operands[0]; i960_compare_op1 = operands[1]; DONE; }") (define_expand "cmpsf" [(set (reg:CC 36) (compare:CC (match_operand:SF 0 "register_operand" "r") (match_operand:SF 1 "nonmemory_operand" "rGH")))] "TARGET_NUMERICS" " { i960_compare_op0 = operands[0]; i960_compare_op1 = operands[1]; DONE; }") ;; Now the DEFINE_INSNs for the compare and scc cases. First the compares. (define_insn "" [(set (reg:CC 36) (compare:CC (match_operand:SI 0 "register_operand" "d") (match_operand:SI 1 "arith_operand" "dI")))] "" "cmpi %0,%1" [(set_attr "type" "compare")]) (define_insn "" [(set (reg:CC_UNS 36) (compare:CC_UNS (match_operand:SI 0 "register_operand" "d") (match_operand:SI 1 "arith_operand" "dI")))] "" "cmpo %0,%1" [(set_attr "type" "compare")]) (define_insn "" [(set (reg:CC 36) (compare:CC (match_operand:DF 0 "register_operand" "r") (match_operand:DF 1 "nonmemory_operand" "rGH")))] "TARGET_NUMERICS" "cmprl %0,%1" [(set_attr "type" "fpcc")]) (define_insn "" [(set (reg:CC 36) (compare:CC (match_operand:SF 0 "register_operand" "r") (match_operand:SF 1 "nonmemory_operand" "rGH")))] "TARGET_NUMERICS" "cmpr %0,%1" [(set_attr "type" "fpcc")]) ;; Instruction definitions for branch-on-bit-set and clear insns. (define_insn "" [(set (pc) (if_then_else (ne (sign_extract:SI (match_operand:SI 1 "register_operand" "d") (const_int 1) (match_operand:SI 2 "arith_operand" "dI")) (const_int 0)) (label_ref (match_operand 3 "" "")) (pc)))] "" "bbs %2,%1,%l3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (eq (sign_extract:SI (match_operand:SI 1 "register_operand" "d") (const_int 1) (match_operand:SI 2 "arith_operand" "dI")) (const_int 0)) (label_ref (match_operand 3 "" "")) (pc)))] "" "bbc %2,%1,%l3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (ne (zero_extract:SI (match_operand:SI 1 "register_operand" "d") (const_int 1) (match_operand:SI 2 "arith_operand" "dI")) (const_int 0)) (label_ref (match_operand 3 "" "")) (pc)))] "" "bbs %2,%1,%l3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (eq (zero_extract:SI (match_operand:SI 1 "register_operand" "d") (const_int 1) (match_operand:SI 2 "arith_operand" "dI")) (const_int 0)) (label_ref (match_operand 3 "" "")) (pc)))] "" "bbc %2,%1,%l3" [(set_attr "type" "branch")]) ;; ??? These will never match. The LOG_LINKs necessary to make these match ;; are not created by flow. These remain as a reminder to make this work ;; some day. (define_insn "" [(set (reg:CC 36) (compare (match_operand:SI 0 "arith_operand" "d") (match_operand:SI 1 "arith_operand" "d"))) (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))] "0" "cmpinci %0,%1" [(set_attr "type" "compare")]) (define_insn "" [(set (reg:CC_UNS 36) (compare (match_operand:SI 0 "arith_operand" "d") (match_operand:SI 1 "arith_operand" "d"))) (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))] "0" "cmpinco %0,%1" [(set_attr "type" "compare")]) (define_insn "" [(set (reg:CC 36) (compare (match_operand:SI 0 "arith_operand" "d") (match_operand:SI 1 "arith_operand" "d"))) (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))] "0" "cmpdeci %0,%1" [(set_attr "type" "compare")]) (define_insn "" [(set (reg:CC_UNS 36) (compare (match_operand:SI 0 "arith_operand" "d") (match_operand:SI 1 "arith_operand" "d"))) (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))] "0" "cmpdeco %0,%1" [(set_attr "type" "compare")]) ;; Templates to store result of condition. ;; '1' is stored if condition is true. ;; '0' is stored if condition is false. ;; These should use predicate "general_operand", since ;; gcc seems to be creating mem references which use these ;; templates. (define_expand "seq" [(set (match_operand:SI 0 "general_operand" "=d") (eq:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1); }") (define_expand "sne" [(set (match_operand:SI 0 "general_operand" "=d") (ne:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1); }") (define_expand "sgt" [(set (match_operand:SI 0 "general_operand" "=d") (gt:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1); }") (define_expand "sgtu" [(set (match_operand:SI 0 "general_operand" "=d") (gtu:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1); }") (define_expand "slt" [(set (match_operand:SI 0 "general_operand" "=d") (lt:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1); }") (define_expand "sltu" [(set (match_operand:SI 0 "general_operand" "=d") (ltu:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1); }") (define_expand "sge" [(set (match_operand:SI 0 "general_operand" "=d") (ge:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1); }") (define_expand "sgeu" [(set (match_operand:SI 0 "general_operand" "=d") (geu:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1); }") (define_expand "sle" [(set (match_operand:SI 0 "general_operand" "=d") (le:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1); }") (define_expand "sleu" [(set (match_operand:SI 0 "general_operand" "=d") (leu:SI (match_dup 1) (const_int 0)))] "" " { operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1); }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d") (match_operator:SI 1 "comparison_operator" [(reg:CC 36) (const_int 0)]))] "" "test%C1 %0" [(set_attr "type" "compare")]) (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d") (match_operator:SI 1 "comparison_operator" [(reg:CC_UNS 36) (const_int 0)]))] "" "test%C1 %0" [(set_attr "type" "compare")]) ;; These control RTL generation for conditional jump insns ;; and match them for register allocation. (define_expand "beq" [(set (pc) (if_then_else (eq (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1); }") (define_expand "bne" [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1); }") (define_expand "bgt" [(set (pc) (if_then_else (gt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1); }") (define_expand "bgtu" [(set (pc) (if_then_else (gtu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1); }") (define_expand "blt" [(set (pc) (if_then_else (lt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1); }") (define_expand "bltu" [(set (pc) (if_then_else (ltu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1); }") (define_expand "bge" [(set (pc) (if_then_else (ge (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1); }") (define_expand "bgeu" [(set (pc) (if_then_else (geu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1); }") (define_expand "ble" [(set (pc) (if_then_else (le (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1); }") (define_expand "bleu" [(set (pc) (if_then_else (leu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" " { operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1); }") ;; Now the normal branch insns (forward and reverse). (define_insn "" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(reg:CC 36) (const_int 0)]) (label_ref (match_operand 1 "" "")) (pc)))] "" "b%C0 %l1" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(reg:CC 36) (const_int 0)]) (pc) (label_ref (match_operand 1 "" ""))))] "" "b%I0 %l1" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(reg:CC_UNS 36) (const_int 0)]) (label_ref (match_operand 1 "" "")) (pc)))] "" "b%C0 %l1" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(reg:CC_UNS 36) (const_int 0)]) (pc) (label_ref (match_operand 1 "" ""))))] "" "b%I0 %l1" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(match_operand:SI 1 "arith_operand" "d") (match_operand:SI 2 "arith_operand" "dI")]) (label_ref (match_operand 3 "" "")) (pc)))] "" "cmp%S0%B0%R0 %2,%1,%l3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(match_operand:SI 1 "arith_operand" "d") (match_operand:SI 2 "arith_operand" "dI")]) (pc) (label_ref (match_operand 3 "" ""))))] "" "cmp%S0%B0%X0 %2,%1,%l3" [(set_attr "type" "branch")]) ;; Normal move instructions. ;; This code is based on the sparc machine description. (define_expand "movsi" [(set (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))] "" " { if (emit_move_sequence (operands, SImode)) DONE; }") ;; The store case can not be separate, because reload may convert a register ;; to register move insn to a store (or load) insn without rerecognizing ;; the insn. ;; The i960 does not have any store constant to memory instruction. However, ;; the calling convention is defined so that the arg pointer when it is not ;; overwise being used is zero. Thus, we can handle store zero to memory ;; by storing an unused arg pointer. The arg pointer will be unused if ;; current_function_args_size is zero. This value of this variable is not ;; valid until after all rtl generation is complete, including function ;; inlining (because a function that doesn't need an arg pointer may be ;; inlined into a function that does need an arg pointer), so we must also ;; check that rtx_equal_function_value_matters is zero. (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d,d,d,m") (match_operand:SI 1 "general_operand" "dI,i,m,dJ"))] "(current_function_args_size == 0 && rtx_equal_function_value_matters == 0) && (register_operand (operands[0], SImode) || register_operand (operands[1], SImode) || operands[1] == const0_rtx)" "* { switch (which_alternative) { case 0: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) { if (GET_CODE (operands[1]) == REG) return \"lda (%1),%0\"; else return \"lda %1,%0\"; } return \"mov %1,%0\"; case 1: return i960_output_ldconst (operands[0], operands[1]); case 2: return \"ld %1,%0\"; case 3: if (operands[1] == const0_rtx) return \"st g14,%0\"; return \"st %1,%0\"; } }" [(set_attr "type" "move,address,load,store") (set_attr "length" "*,3,*,*")]) (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d,d,d,m") (match_operand:SI 1 "general_operand" "dI,i,m,d"))] "(current_function_args_size != 0 || rtx_equal_function_value_matters != 0) && (register_operand (operands[0], SImode) || register_operand (operands[1], SImode))" "* { switch (which_alternative) { case 0: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) { if (GET_CODE (operands[1]) == REG) return \"lda (%1),%0\"; else return \"lda %1,%0\"; } return \"mov %1,%0\"; case 1: return i960_output_ldconst (operands[0], operands[1]); case 2: return \"ld %1,%0\"; case 3: return \"st %1,%0\"; } }" [(set_attr "type" "move,address,load,store") (set_attr "length" "*,3,*,*")]) (define_expand "movhi" [(set (match_operand:HI 0 "general_operand" "") (match_operand:HI 1 "general_operand" ""))] "" " { if (emit_move_sequence (operands, HImode)) DONE; }") ;; Special pattern for zero stores to memory for functions which don't use ;; the arg pointer. ;; The store case can not be separate. See above. (define_insn "" [(set (match_operand:HI 0 "general_operand" "=d,d,d,m") (match_operand:HI 1 "general_operand" "dI,i,m,dJ"))] "(current_function_args_size == 0 && rtx_equal_function_value_matters == 0) && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode) || operands[1] == const0_rtx)" "* { switch (which_alternative) { case 0: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) { if (GET_CODE (operands[1]) == REG) return \"lda (%1),%0\"; else return \"lda %1,%0\"; } return \"mov %1,%0\"; case 1: return i960_output_ldconst (operands[0], operands[1]); case 2: return \"ldos %1,%0\"; case 3: if (operands[1] == const0_rtx) return \"stos g14,%0\"; return \"stos %1,%0\"; } }" [(set_attr "type" "move,misc,load,store") (set_attr "length" "*,3,*,*")]) ;; The store case can not be separate. See above. (define_insn "" [(set (match_operand:HI 0 "general_operand" "=d,d,d,m") (match_operand:HI 1 "general_operand" "dI,i,m,d"))] "(current_function_args_size != 0 || rtx_equal_function_value_matters != 0) && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" "* { switch (which_alternative) { case 0: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) { if (GET_CODE (operands[1]) == REG) return \"lda (%1),%0\"; else return \"lda %1,%0\"; } return \"mov %1,%0\"; case 1: return i960_output_ldconst (operands[0], operands[1]); case 2: return \"ldos %1,%0\"; case 3: return \"stos %1,%0\"; } }" [(set_attr "type" "move,misc,load,store") (set_attr "length" "*,3,*,*")]) (define_expand "movqi" [(set (match_operand:QI 0 "general_operand" "") (match_operand:QI 1 "general_operand" ""))] "" " { if (emit_move_sequence (operands, QImode)) DONE; }") ;; The store case can not be separate. See comment above. (define_insn "" [(set (match_operand:QI 0 "general_operand" "=d,d,d,m") (match_operand:QI 1 "general_operand" "dI,i,m,dJ"))] "(current_function_args_size == 0 && rtx_equal_function_value_matters == 0) && (register_operand (operands[0], QImode) || register_operand (operands[1], QImode) || operands[1] == const0_rtx)" "* { switch (which_alternative) { case 0: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) { if (GET_CODE (operands[1]) == REG) return \"lda (%1),%0\"; else return \"lda %1,%0\"; } return \"mov %1,%0\"; case 1: return i960_output_ldconst (operands[0], operands[1]); case 2: return \"ldob %1,%0\"; case 3: if (operands[1] == const0_rtx) return \"stob g14,%0\"; return \"stob %1,%0\"; } }" [(set_attr "type" "move,misc,load,store") (set_attr "length" "*,3,*,*")]) ;; The store case can not be separate. See comment above. (define_insn "" [(set (match_operand:QI 0 "general_operand" "=d,d,d,m") (match_operand:QI 1 "general_operand" "dI,i,m,d"))] "(current_function_args_size != 0 || rtx_equal_function_value_matters != 0) && (register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" "* { switch (which_alternative) { case 0: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) { if (GET_CODE (operands[1]) == REG) return \"lda (%1),%0\"; else return \"lda %1,%0\"; } return \"mov %1,%0\"; case 1: return i960_output_ldconst (operands[0], operands[1]); case 2: return \"ldob %1,%0\"; case 3: return \"stob %1,%0\"; } }" [(set_attr "type" "move,misc,load,store") (set_attr "length" "*,3,*,*")]) (define_expand "movdi" [(set (match_operand:DI 0 "general_operand" "") (match_operand:DI 1 "general_operand" ""))] "" " { if (emit_move_sequence (operands, DImode)) DONE; }") ;; The store case can not be separate. See comment above. (define_insn "" [(set (match_operand:DI 0 "general_operand" "=d,d,d,m,o") (match_operand:DI 1 "general_operand" "dI,i,m,d,J"))] "(current_function_args_size == 0 && rtx_equal_function_value_matters == 0) && (register_operand (operands[0], DImode) || register_operand (operands[1], DImode) || operands[1] == const0_rtx)" "* { switch (which_alternative) { case 0: return \"movl %1,%0\"; case 1: return i960_output_ldconst (operands[0], operands[1]); case 2: return \"ldl %1,%0\"; case 3: return \"stl %1,%0\"; case 4: operands[1] = adj_offsettable_operand (operands[0], 4); return \"st g14,%0\;st g14,%1\"; } }" [(set_attr "type" "move,load,load,store,store")]) ;; The store case can not be separate. See comment above. (define_insn "" [(set (match_operand:DI 0 "general_operand" "=d,d,d,m") (match_operand:DI 1 "general_operand" "dI,i,m,d"))] "(current_function_args_size != 0 || rtx_equal_function_value_matters != 0) && (register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" "* { switch (which_alternative) { case 0: return \"movl %1,%0\"; case 1: return i960_output_ldconst (operands[0], operands[1]); case 2: return \"ldl %1,%0\"; case 3: return \"stl %1,%0\"; } }" [(set_attr "type" "move,load,load,store")]) (define_expand "movti" [(set (match_operand:TI 0 "general_operand" "") (match_operand:TI 1 "general_operand" ""))] "" " { if (emit_move_sequence (operands, TImode)) DONE; }") ;; The store case can not be separate. See comment above. (define_insn "" [(set (match_operand:TI 0 "general_operand" "=d,d,d,m,o") (match_operand:TI 1 "general_operand" "dI,i,m,d,J"))] "(current_function_args_size == 0 && rtx_equal_function_value_matters == 0) && (register_operand (operands[0], TImode) || register_operand (operands[1], TImode) || operands[1] == const0_rtx)" "* { switch (which_alternative) { case 0: return \"movq %1,%0\"; case 1: return i960_output_ldconst (operands[0], operands[1]); case 2: return \"ldq %1,%0\"; case 3: return \"stq %1,%0\"; case 4: operands[1] = adj_offsettable_operand (operands[0], 4); operands[2] = adj_offsettable_operand (operands[0], 8); operands[3] = adj_offsettable_operand (operands[0], 12); return \"st g14,%0\;st g14,%1\;st g14,%2\;st g14,%3\"; } }" [(set_attr "type" "move,load,load,store,store")]) ;; The store case can not be separate. See comment above. (define_insn "" [(set (match_operand:TI 0 "general_operand" "=d,d,d,m") (match_operand:TI 1 "general_operand" "dI,i,m,d"))] "(current_function_args_size != 0 || rtx_equal_function_value_matters != 0) && (register_operand (operands[0], TImode) || register_operand (operands[1], TImode))" "* { switch (which_alternative) { case 0: return \"movq %1,%0\"; case 1: return i960_output_ldconst (operands[0], operands[1]); case 2: return \"ldq %1,%0\"; case 3: return \"stq %1,%0\"; } }" [(set_attr "type" "move,load,load,store")]) (define_expand "store_multiple" [(set (match_operand:SI 0 "" "") ;;- dest (match_operand:SI 1 "" "")) ;;- src (use (match_operand:SI 2 "" ""))] ;;- nregs "" " { int regno; int count; rtx from; int i; if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != CONST_INT) FAIL; count = INTVAL (operands[2]); if (count > 12) FAIL; regno = REGNO (operands[1]); from = memory_address (SImode, XEXP (operands[0], 0)); while (count >= 4 && ((regno & 3) == 0)) { emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (MEM, TImode, from), gen_rtx (REG, TImode, regno))); count -= 4; regno += 4; from = memory_address (TImode, plus_constant (from, 16)); } while (count >= 2 && ((regno & 1) == 0)) { emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (MEM, DImode, from), gen_rtx (REG, DImode, regno))); count -= 2; regno += 2; from = memory_address (DImode, plus_constant (from, 8)); } while (count > 0) { emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, from), gen_rtx (REG, SImode, regno))); count -= 1; regno += 1; from = memory_address (SImode, plus_constant (from, 4)); } DONE; }") ;; Floating point move insns (define_expand "movdf" [(set (match_operand:DF 0 "general_operand" "") (match_operand:DF 1 "fpmove_src_operand" ""))] "" " { if (emit_move_sequence (operands, DFmode)) DONE; }") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=r,*f,d,d,m,o") (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d,G"))] "(current_function_args_size == 0 && rtx_equal_function_value_matters == 0) && (register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode) || operands[1] == CONST0_RTX (DFmode))" "* { switch (which_alternative) { case 0: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) return \"movrl %1,%0\"; else return \"movl %1,%0\"; case 1: return \"movrl %1,%0\"; case 2: return i960_output_ldconst (operands[0], operands[1]); case 3: return \"ldl %1,%0\"; case 4: return \"stl %1,%0\"; case 5: operands[1] = adj_offsettable_operand (operands[0], 4); return \"st g14,%0\;st g14,%1\"; } }" [(set_attr "type" "move,move,load,fpload,fpstore,fpstore")]) (define_insn "" [(set (match_operand:DF 0 "general_operand" "=r,*f,d,d,m") (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d"))] "(current_function_args_size != 0 || rtx_equal_function_value_matters != 0) && (register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode))" "* { switch (which_alternative) { case 0: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) return \"movrl %1,%0\"; else return \"movl %1,%0\"; case 1: return \"movrl %1,%0\"; case 2: return i960_output_ldconst (operands[0], operands[1]); case 3: return \"ldl %1,%0\"; case 4: return \"stl %1,%0\"; } }" [(set_attr "type" "move,move,load,fpload,fpstore")]) (define_expand "movsf" [(set (match_operand:SF 0 "general_operand" "") (match_operand:SF 1 "fpmove_src_operand" ""))] "" " { if (emit_move_sequence (operands, SFmode)) DONE; }") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=r,*f,d,d,m") (match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,dG"))] "(current_function_args_size == 0 && rtx_equal_function_value_matters == 0) && (register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode) || operands[1] == CONST0_RTX (SFmode))" "* { switch (which_alternative) { case 0: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) return \"movr %1,%0\"; else return \"mov %1,%0\"; case 1: return \"movr %1,%0\"; case 2: return i960_output_ldconst (operands[0], operands[1]); case 3: return \"ld %1,%0\"; case 4: if (operands[1] == CONST0_RTX (SFmode)) return \"st g14,%0\"; return \"st %1,%0\"; } }" [(set_attr "type" "move,move,load,fpload,fpstore")]) (define_insn "" [(set (match_operand:SF 0 "general_operand" "=r,*f,d,d,m") (match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,d"))] "(current_function_args_size != 0 || rtx_equal_function_value_matters != 0) && (register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode))" "* { switch (which_alternative) { case 0: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) return \"movr %1,%0\"; else return \"mov %1,%0\"; case 1: return \"movr %1,%0\"; case 2: return i960_output_ldconst (operands[0], operands[1]); case 3: return \"ld %1,%0\"; case 4: return \"st %1,%0\"; } }" [(set_attr "type" "move,move,load,fpload,fpstore")]) ;; Mixed-mode moves with sign and zero-extension. ;; Note that the one starting from HImode comes before those for QImode ;; so that a constant operand will match HImode, not QImode. (define_expand "extendhisi2" [(set (match_operand:SI 0 "register_operand" "") (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] "" " { if (GET_CODE (operand1) == REG || (GET_CODE (operand1) == SUBREG && GET_CODE (XEXP (operand1, 0)) == REG)) { rtx temp = gen_reg_rtx (SImode); rtx shift_16 = gen_rtx (CONST_INT, VOIDmode, 16); int op1_subreg_word = 0; if (GET_CODE (operand1) == SUBREG) { op1_subreg_word = SUBREG_WORD (operand1); operand1 = SUBREG_REG (operand1); } operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); emit_insn (gen_ashlsi3 (temp, operand1, shift_16)); emit_insn (gen_ashrsi3 (operand0, temp, shift_16)); DONE; } }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] "" "ldis %1,%0" [(set_attr "type" "load")]) (define_expand "extendqisi2" [(set (match_operand:SI 0 "register_operand" "") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] "" " { if (GET_CODE (operand1) == REG || (GET_CODE (operand1) == SUBREG && GET_CODE (XEXP (operand1, 0)) == REG)) { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); int op1_subreg_word = 0; if (GET_CODE (operand1) == SUBREG) { op1_subreg_word = SUBREG_WORD (operand1); operand1 = SUBREG_REG (operand1); } operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word), emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); DONE; } }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] "" "ldib %1,%0" [(set_attr "type" "load")]) (define_expand "extendqihi2" [(set (match_operand:HI 0 "register_operand" "") (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] "" " { if (GET_CODE (operand1) == REG || (GET_CODE (operand1) == SUBREG && GET_CODE (XEXP (operand1, 0)) == REG)) { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); int op0_subreg_word = 0; int op1_subreg_word = 0; if (GET_CODE (operand1) == SUBREG) { op1_subreg_word = SUBREG_WORD (operand1); operand1 = SUBREG_REG (operand1); } operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); if (GET_CODE (operand0) == SUBREG) { op0_subreg_word = SUBREG_WORD (operand0); operand0 = SUBREG_REG (operand0); } if (GET_MODE (operand0) != SImode) operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subreg_word); emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); DONE; } }") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=d") (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))] "" "ldib %1,%0" [(set_attr "type" "load")]) (define_expand "zero_extendhisi2" [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] "" " { if (GET_CODE (operand1) == REG || (GET_CODE (operand1) == SUBREG && GET_CODE (XEXP (operand1, 0)) == REG)) { rtx temp = gen_reg_rtx (SImode); rtx shift_16 = gen_rtx (CONST_INT, VOIDmode, 16); int op1_subreg_word = 0; if (GET_CODE (operand1) == SUBREG) { op1_subreg_word = SUBREG_WORD (operand1); operand1 = SUBREG_REG (operand1); } operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); emit_insn (gen_ashlsi3 (temp, operand1, shift_16)); emit_insn (gen_lshrsi3 (operand0, temp, shift_16)); DONE; } }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] "" "ldos %1,%0" [(set_attr "type" "load")]) ;; Using shifts here generates much better code than doing an `and 255'. ;; This is mainly because the `and' requires loading the constant separately, ;; the constant is likely to get optimized, and then the compiler can't ;; optimize the `and' because it doesn't know that one operand is a constant. (define_expand "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] "" " { if (GET_CODE (operand1) == REG || (GET_CODE (operand1) == SUBREG && GET_CODE (XEXP (operand1, 0)) == REG)) { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); int op1_subreg_word = 0; if (GET_CODE (operand1) == SUBREG) { op1_subreg_word = SUBREG_WORD (operand1); operand1 = SUBREG_REG (operand1); } operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); emit_insn (gen_lshrsi3 (operand0, temp, shift_24)); DONE; } }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] "" "ldob %1,%0" [(set_attr "type" "load")]) (define_expand "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] "" " { if (GET_CODE (operand1) == REG || (GET_CODE (operand1) == SUBREG && GET_CODE (XEXP (operand1, 0)) == REG)) { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); int op0_subreg_word = 0; int op1_subreg_word = 0; if (GET_CODE (operand1) == SUBREG) { op1_subreg_word = SUBREG_WORD (operand1); operand1 = SUBREG_REG (operand1); } operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); if (GET_CODE (operand0) == SUBREG) { op0_subreg_word = SUBREG_WORD (operand0); operand0 = SUBREG_REG (operand0); } if (GET_MODE (operand0) != SImode) operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subreg_word); emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); emit_insn (gen_lshrsi3 (operand0, temp, shift_24)); DONE; } }") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=d") (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] "" "ldob %1,%0" [(set_attr "type" "load")]) ;; Conversions between float and double. (define_insn "extendsfdf2" [(set (match_operand:DF 0 "register_operand" "=*f,d") (float_extend:DF (match_operand:SF 1 "fp_arith_operand" "dGH,fGH")))] "TARGET_NUMERICS" "@ movr %1,%0 movrl %1,%0" [(set_attr "type" "fpmove")]) (define_insn "truncdfsf2" [(set (match_operand:SF 0 "register_operand" "=d") (float_truncate:SF (match_operand:DF 1 "fp_arith_operand" "fGH")))] "TARGET_NUMERICS" "movr %1,%0" [(set_attr "type" "fpmove")]) ;; Conversion between fixed point and floating point. (define_insn "floatsidf2" [(set (match_operand:DF 0 "register_operand" "=f") (float:DF (match_operand:SI 1 "register_operand" "d")))] "TARGET_NUMERICS" "cvtir %1,%0" [(set_attr "type" "fpcvt")]) (define_insn "floatsisf2" [(set (match_operand:SF 0 "register_operand" "=d*f") (float:SF (match_operand:SI 1 "register_operand" "d")))] "TARGET_NUMERICS" "cvtir %1,%0" [(set_attr "type" "fpcvt")]) ;; Convert a float to an actual integer. ;; Truncation is performed as part of the conversion. ;; The i960 requires conversion from DFmode to DImode to make ;; unsigned conversions work properly. (define_insn "fixuns_truncdfdi2" [(set (match_operand:DI 0 "register_operand" "=d") (unsigned_fix:DI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))] "TARGET_NUMERICS" "cvtzril %1,%0" [(set_attr "type" "fpcvt")]) (define_insn "fixuns_truncsfdi2" [(set (match_operand:DI 0 "register_operand" "=d") (unsigned_fix:DI (fix:SF (match_operand:SF 1 "fp_arith_operand" "fGH"))))] "TARGET_NUMERICS" "cvtzril %1,%0" [(set_attr "type" "fpcvt")]) (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "register_operand" "=d") (fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))] "TARGET_NUMERICS" "cvtzri %1,%0" [(set_attr "type" "fpcvt")]) (define_expand "fixuns_truncdfsi2" [(set (match_operand:SI 0 "register_operand" "") (unsigned_fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" ""))))] "TARGET_NUMERICS" " { rtx temp = gen_reg_rtx (DImode); emit_insn (gen_rtx (SET, VOIDmode, temp, gen_rtx (UNSIGNED_FIX, DImode, gen_rtx (FIX, DFmode, operands[1])))); emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (SUBREG, SImode, temp, 0))); DONE; }") (define_insn "fix_truncsfsi2" [(set (match_operand:SI 0 "register_operand" "=d") (fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" "dfGH"))))] "TARGET_NUMERICS" "cvtzri %1,%0" [(set_attr "type" "fpcvt")]) (define_expand "fixuns_truncsfsi2" [(set (match_operand:SI 0 "register_operand" "") (unsigned_fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" ""))))] "TARGET_NUMERICS" " { rtx temp = gen_reg_rtx (DImode); emit_insn (gen_rtx (SET, VOIDmode, temp, gen_rtx (UNSIGNED_FIX, DImode, gen_rtx (FIX, SFmode, operands[1])))); emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (SUBREG, SImode, temp, 0))); DONE; }") ;; Arithmetic instructions. (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=d") (minus:SI (match_operand:SI 1 "arith_operand" "dI") (match_operand:SI 2 "arith_operand" "dI")))] "" "subo %2,%1,%0") ;; Try to generate an lda instruction when it would be faster than an ;; add instruction. ;; Some assemblers apparently won't accept two addresses added together. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d,d,d") (plus:SI (match_operand:SI 1 "arith32_operand" "%dn,i,dn") (match_operand:SI 2 "arith32_operand" "dn,dn,i")))] "(TARGET_C_SERIES) && (CONSTANT_P (operands[1]) || CONSTANT_P (operands[2]))" "* { if (GET_CODE (operands[1]) == CONST_INT) { rtx tmp = operands[1]; operands[1] = operands[2]; operands[2] = tmp; } if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (operands[1]) == REG && i960_last_insn_type != I_TYPE_REG) { if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) > -32) return \"subo %n2,%1,%0\"; else if (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32) return \"addo %1,%2,%0\"; } if (CONSTANT_P (operands[1])) return \"lda %1+%2,%0\"; return \"lda %2(%1),%0\"; }") (define_insn "addsi3" [(set (match_operand:SI 0 "register_operand" "=d") (plus:SI (match_operand:SI 1 "signed_arith_operand" "%dI") (match_operand:SI 2 "signed_arith_operand" "dIK")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) return \"subo %n2,%1,%0\"; if (i960_bypass (insn, operands[1], operands[2], 0)) return \"addo %2,%1,%0\"; return \"addo %1,%2,%0\"; }") (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=d") (mult:SI (match_operand:SI 1 "arith_operand" "%dI") (match_operand:SI 2 "arith_operand" "dI")))] "" "* { if (i960_bypass (insn, operands[1], operands[2], 0)) return \"mulo %2,%1,%0\"; return \"mulo %1,%2,%0\"; }" [(set_attr "type" "mult")]) (define_insn "umulsidi3" [(set (match_operand:DI 0 "register_operand" "=d") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] "" "* { if (i960_bypass (insn, operands[1], operands[2], 0)) return \"emul %2,%1,%0\"; return \"emul %1,%2,%0\"; }" [(set_attr "type" "mult")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=d") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%d")) (match_operand:SI 2 "literal" "I")))] "" "* { if (i960_bypass (insn, operands[1], operands[2], 0)) return \"emul %2,%1,%0\"; return \"emul %1,%2,%0\"; }" [(set_attr "type" "mult")]) ;; This goes after the move/add/sub/mul instructions ;; because those instructions are better when they apply. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (match_operand:SI 1 "address_operand" "p"))] "" "lda %a1,%0" [(set_attr "type" "load")]) ;; This will never be selected because of an "optimization" that GCC does. ;; It always converts divides by a power of 2 into a sequence of instructions ;; that does a right shift, and then corrects the result if it was negative. ;; (define_insn "" ;; [(set (match_operand:SI 0 "register_operand" "=d") ;; (div:SI (match_operand:SI 1 "arith_operand" "dI") ;; (match_operand:SI 2 "power2_operand" "nI")))] ;; "" ;; "*{ ;; operands[2] = gen_rtx(CONST_INT, VOIDmode,bitpos (INTVAL (operands[2]))); ;; return \"shrdi %2,%1,%0\"; ;; }" (define_insn "divsi3" [(set (match_operand:SI 0 "register_operand" "=d") (div:SI (match_operand:SI 1 "arith_operand" "dI") (match_operand:SI 2 "arith_operand" "dI")))] "" "divi %2,%1,%0" [(set_attr "type" "div")]) (define_insn "udivsi3" [(set (match_operand:SI 0 "register_operand" "=d") (udiv:SI (match_operand:SI 1 "arith_operand" "dI") (match_operand:SI 2 "arith_operand" "dI")))] "" "divo %2,%1,%0" [(set_attr "type" "div")]) ;; We must use `remi' not `modi' here, to ensure that `%' has the effects ;; specified by the ANSI C standard. (define_insn "modsi3" [(set (match_operand:SI 0 "register_operand" "=d") (mod:SI (match_operand:SI 1 "arith_operand" "dI") (match_operand:SI 2 "arith_operand" "dI")))] "" "remi %2,%1,%0" [(set_attr "type" "div")]) (define_insn "umodsi3" [(set (match_operand:SI 0 "register_operand" "=d") (umod:SI (match_operand:SI 1 "arith_operand" "dI") (match_operand:SI 2 "arith_operand" "dI")))] "" "remo %2,%1,%0" [(set_attr "type" "div")]) ;; And instructions (with complement also). (define_insn "andsi3" [(set (match_operand:SI 0 "register_operand" "=d") (and:SI (match_operand:SI 1 "arith_operand" "%dI") (match_operand:SI 2 "arith_operand" "dI")))] "" "* { if (i960_bypass (insn, operands[1], operands[2], 0)) return \"and %2,%1,%0\"; return \"and %1,%2,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (and:SI (not:SI (match_operand:SI 1 "arith_operand" "dI")) (match_operand:SI 2 "arith_operand" "dI")))] "" "* { if (i960_bypass (insn, operands[1], operands[2], 0)) return \"notand %2,%1,%0\"; return \"andnot %1,%2,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (ior:SI (not:SI (match_operand:SI 1 "arith_operand" "%dI")) (not:SI (match_operand:SI 2 "arith_operand" "dI"))))] "" "* { if (i960_bypass (insn, operands[1], operands[2], 0)) return \"nand %2,%1,%0\"; return \"nand %1,%2,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (ior:SI (match_operand:SI 1 "arith_operand" "dI") (match_operand:SI 2 "power2_operand" "n")))] "" "* { operands[2] = gen_rtx (CONST_INT, VOIDmode, bitpos (INTVAL (operands[2]))); return \"setbit %2,%1,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (ior:SI (ashift:SI (const_int 1) (match_operand:SI 1 "register_operand" "d")) (match_operand:SI 2 "arith_operand" "dI")))] "" "setbit %1,%2,%0") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (and:SI (match_operand:SI 1 "arith_operand" "dI") (match_operand:SI 2 "cmplpower2_operand" "n")))] "" "* { operands[2] = gen_rtx (CONST_INT, VOIDmode, bitpos (~INTVAL (operands[2]))); return \"clrbit %2,%1,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (and:SI (ashift:SI (const_int 1) (match_operand:SI 1 "register_operand" "d")) (match_operand:SI 2 "arith_operand" "dI")))] "" "clrbit %1,%2,%0") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (xor:SI (match_operand:SI 1 "arith_operand" "dI") (match_operand:SI 2 "power2_operand" "n")))] "" "* { operands[2] = gen_rtx (CONST_INT, VOIDmode, bitpos (INTVAL (operands[2]))); return \"notbit %2,%1,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (xor:SI (ashift:SI (const_int 1) (match_operand:SI 1 "register_operand" "d")) (match_operand:SI 2 "arith_operand" "dI")))] "" "notbit %1,%2,%0") (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=d") (ior:SI (match_operand:SI 1 "arith_operand" "%dI") (match_operand:SI 2 "arith_operand" "dI")))] "" "* { if (i960_bypass (insn, operands[1], operands[2], 0)) return \"or %2,%1,%0\"; return \"or %1,%2,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (ior:SI (not:SI (match_operand:SI 1 "arith_operand" "dI")) (match_operand:SI 2 "arith_operand" "dI")))] "" "* { if (i960_bypass (insn, operands[1], operands[2], 0)) return \"notor %2,%1,%0\"; return \"ornot %1,%2,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (and:SI (not:SI (match_operand:SI 1 "arith_operand" "%dI")) (not:SI (match_operand:SI 2 "arith_operand" "dI"))))] "" "* { if (i960_bypass (insn, operands[1], operands[2], 0)) return \"nor %2,%1,%0\"; return \"nor %1,%2,%0\"; }") (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=d") (xor:SI (match_operand:SI 1 "arith_operand" "%dI") (match_operand:SI 2 "arith_operand" "dI")))] "" "* { if (i960_bypass (insn, operands[1], operands[2], 0)) return \"xor %2,%1,%0\"; return \"xor %1,%2,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (not:SI (xor:SI (match_operand:SI 1 "arith_operand" "%dI") (match_operand:SI 2 "arith_operand" "dI"))))] "" "* { if (i960_bypass (insn, operands[1], operands[2], 0)) return \"xnor %2,%1,%0\"; return \"xnor %2,%1,%0\"; }") (define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=d") (neg:SI (match_operand:SI 1 "arith_operand" "dI")))] "" "subo %1,0,%0" [(set_attr "length" "1")]) (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "=d") (not:SI (match_operand:SI 1 "arith_operand" "dI")))] "" "not %1,%0" [(set_attr "length" "1")]) ;; Floating point arithmetic instructions. (define_insn "adddf3" [(set (match_operand:DF 0 "register_operand" "=d*f") (plus:DF (match_operand:DF 1 "fp_arith_operand" "%rGH") (match_operand:DF 2 "fp_arith_operand" "rGH")))] "TARGET_NUMERICS" "addrl %1,%2,%0" [(set_attr "type" "fpadd")]) (define_insn "addsf3" [(set (match_operand:SF 0 "register_operand" "=d*f") (plus:SF (match_operand:SF 1 "fp_arith_operand" "%rGH") (match_operand:SF 2 "fp_arith_operand" "rGH")))] "TARGET_NUMERICS" "addr %1,%2,%0" [(set_attr "type" "fpadd")]) (define_insn "subdf3" [(set (match_operand:DF 0 "register_operand" "=d*f") (minus:DF (match_operand:DF 1 "fp_arith_operand" "rGH") (match_operand:DF 2 "fp_arith_operand" "rGH")))] "TARGET_NUMERICS" "subrl %2,%1,%0" [(set_attr "type" "fpadd")]) (define_insn "subsf3" [(set (match_operand:SF 0 "register_operand" "=d*f") (minus:SF (match_operand:SF 1 "fp_arith_operand" "rGH") (match_operand:SF 2 "fp_arith_operand" "rGH")))] "TARGET_NUMERICS" "subr %2,%1,%0" [(set_attr "type" "fpadd")]) (define_insn "muldf3" [(set (match_operand:DF 0 "register_operand" "=d*f") (mult:DF (match_operand:DF 1 "fp_arith_operand" "%rGH") (match_operand:DF 2 "fp_arith_operand" "rGH")))] "TARGET_NUMERICS" "mulrl %1,%2,%0" [(set_attr "type" "fpmul")]) (define_insn "mulsf3" [(set (match_operand:SF 0 "register_operand" "=d*f") (mult:SF (match_operand:SF 1 "fp_arith_operand" "%rGH") (match_operand:SF 2 "fp_arith_operand" "rGH")))] "TARGET_NUMERICS" "mulr %1,%2,%0" [(set_attr "type" "fpmul")]) (define_insn "divdf3" [(set (match_operand:DF 0 "register_operand" "=d*f") (div:DF (match_operand:DF 1 "fp_arith_operand" "rGH") (match_operand:DF 2 "fp_arith_operand" "rGH")))] "TARGET_NUMERICS" "divrl %2,%1,%0" [(set_attr "type" "fpdiv")]) (define_insn "divsf3" [(set (match_operand:SF 0 "register_operand" "=d*f") (div:SF (match_operand:SF 1 "fp_arith_operand" "rGH") (match_operand:SF 2 "fp_arith_operand" "rGH")))] "TARGET_NUMERICS" "divr %2,%1,%0" [(set_attr "type" "fpdiv")]) (define_insn "negdf2" [(set (match_operand:DF 0 "register_operand" "=d,d*f") (neg:DF (match_operand:DF 1 "register_operand" "d,r")))] "" "* { if (which_alternative == 0) { if (REGNO (operands[0]) == REGNO (operands[1])) return \"notbit 31,%D1,%D0\"; return \"mov %1,%0\;notbit 31,%D1,%D0\"; } return \"subrl %1,0f0.0,%0\"; }" [(set_attr "type" "fpadd")]) (define_insn "negsf2" [(set (match_operand:SF 0 "register_operand" "=d,d*f") (neg:SF (match_operand:SF 1 "register_operand" "d,r")))] "" "@ notbit 31,%1,%0 subr %1,0f0.0,%0" [(set_attr "type" "fpadd")]) ;;; The abs patterns also work even if the target machine doesn't have ;;; floating point, because in that case dstreg and srcreg will always be ;;; less than 32. (define_insn "absdf2" [(set (match_operand:DF 0 "register_operand" "=d*f") (abs:DF (match_operand:DF 1 "register_operand" "df")))] "" "* { int dstreg = REGNO (operands[0]); int srcreg = REGNO (operands[1]); if (dstreg < 32) { if (srcreg < 32) { if (dstreg != srcreg) output_asm_insn (\"mov %1,%0\", operands); return \"clrbit 31,%D1,%D0\"; } /* Src is an fp reg. */ return \"movrl %1,%0\;clrbit 31,%D1,%D0\"; } if (srcreg >= 32) return \"cpysre %1,0f0.0,%0\"; return \"movrl %1,%0\;cpysre %0,0f0.0,%0\"; }" [(set_attr "type" "multi")]) (define_insn "abssf2" [(set (match_operand:SF 0 "register_operand" "=d*f") (abs:SF (match_operand:SF 1 "register_operand" "df")))] "" "* { int dstreg = REGNO (operands[0]); int srcreg = REGNO (operands[1]); if (dstreg < 32 && srcreg < 32) return \"clrbit 31,%1,%0\"; if (dstreg >= 32 && srcreg >= 32) return \"cpysre %1,0f0.0,%0\"; if (dstreg < 32) return \"movr %1,%0\;clrbit 31,%0,%0\"; return \"movr %1,%0\;cpysre %0,0f0.0,%0\"; }" [(set_attr "type" "multi")]) ;; Tetra (16 byte) float support. (define_insn "cmptf" [(set (reg:CC 36) (compare:CC (match_operand:TF 0 "register_operand" "f") (match_operand:TF 1 "nonmemory_operand" "fG")))] "TARGET_NUMERICS" "cmpr %0,%1" [(set_attr "type" "fpcc")]) (define_expand "movtf" [(set (match_operand:TF 0 "general_operand" "") (match_operand:TF 1 "fpmove_src_operand" ""))] "" " { if (emit_move_sequence (operands, TFmode)) DONE; }") (define_insn "" [(set (match_operand:TF 0 "general_operand" "=r,*f,d,d,m,o") (match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,d,G"))] "(current_function_args_size == 0 && rtx_equal_function_value_matters == 0) && (register_operand (operands[0], TFmode) || register_operand (operands[1], TFmode) || operands[1] == CONST0_RTX (TFmode))" "* { switch (which_alternative) { case 0: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) return \"movre %1,%0\"; else return \"movq %1,%0\"; case 1: return \"movre %1,%0\"; case 2: return i960_output_ldconst (operands[0], operands[1]); case 3: return \"ldq %1,%0\"; case 4: return \"stq %1,%0\"; case 5: operands[1] = adj_offsettable_operand (operands[0], 4); operands[2] = adj_offsettable_operand (operands[0], 8); operands[3] = adj_offsettable_operand (operands[0], 12); return \"st g14,%0\;st g14,%1\;st g14,%2\;st g14,%3\"; } }" [(set_attr "type" "move,move,load,fpload,fpstore,fpstore")]) (define_insn "" [(set (match_operand:TF 0 "general_operand" "=r,*f,d,d,m") (match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,d"))] "(current_function_args_size != 0 || rtx_equal_function_value_matters != 0) && (register_operand (operands[0], TFmode) || register_operand (operands[1], TFmode))" "* { switch (which_alternative) { case 0: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) return \"movre %1,%0\"; else return \"movq %1,%0\"; case 1: return \"movre %1,%0\"; case 2: return i960_output_ldconst (operands[0], operands[1]); case 3: return \"ldq %1,%0\"; case 4: return \"stq %1,%0\"; } }" [(set_attr "type" "move,move,load,fpload,fpstore")]) (define_insn "extendsftf2" [(set (match_operand:TF 0 "register_operand" "=*f,d") (float_extend:TF (match_operand:SF 1 "register_operand" "d,f")))] "TARGET_NUMERICS" "@ movr %1,%0 movre %1,%0" [(set_attr "type" "fpmove")]) (define_insn "extenddftf2" [(set (match_operand:TF 0 "register_operand" "=*f,d") (float_extend:TF (match_operand:DF 1 "register_operand" "d,f")))] "TARGET_NUMERICS" "@ movrl %1,%0 movre %1,%0" [(set_attr "type" "fpmove")]) (define_insn "trunctfdf2" [(set (match_operand:DF 0 "register_operand" "=d") (float_truncate:DF (match_operand:TF 1 "register_operand" "f")))] "TARGET_NUMERICS" "movrl %1,%0" [(set_attr "type" "fpmove")]) (define_insn "trunctfsf2" [(set (match_operand:SF 0 "register_operand" "=d") (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))] "TARGET_NUMERICS" "movr %1,%0" [(set_attr "type" "fpmove")]) (define_insn "floatsitf2" [(set (match_operand:TF 0 "register_operand" "=f") (float:TF (match_operand:SI 1 "register_operand" "d")))] "TARGET_NUMERICS" "cvtir %1,%0" [(set_attr "type" "fpcvt")]) (define_insn "fix_trunctfsi2" [(set (match_operand:SI 0 "register_operand" "=d") (fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))] "TARGET_NUMERICS" "cvtzri %1,%0" [(set_attr "type" "fpcvt")]) (define_insn "fixuns_trunctfsi2" [(set (match_operand:SI 0 "register_operand" "=d") (unsigned_fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))] "TARGET_NUMERICS" "cvtzri %1,%0" [(set_attr "type" "fpcvt")]) (define_insn "addtf3" [(set (match_operand:TF 0 "register_operand" "=f") (plus:TF (match_operand:TF 1 "nonmemory_operand" "%fG") (match_operand:TF 2 "nonmemory_operand" "fG")))] "TARGET_NUMERICS" "addr %1,%2,%0" [(set_attr "type" "fpadd")]) (define_insn "subtf3" [(set (match_operand:TF 0 "register_operand" "=f") (minus:TF (match_operand:TF 1 "nonmemory_operand" "fG") (match_operand:TF 2 "nonmemory_operand" "fG")))] "TARGET_NUMERICS" "subr %2,%1,%0" [(set_attr "type" "fpadd")]) (define_insn "multf3" [(set (match_operand:TF 0 "register_operand" "=f") (mult:TF (match_operand:TF 1 "nonmemory_operand" "%fG") (match_operand:TF 2 "nonmemory_operand" "fG")))] "TARGET_NUMERICS" "mulr %1,%2,%0" [(set_attr "type" "fpmul")]) (define_insn "divtf3" [(set (match_operand:TF 0 "register_operand" "=f") (div:TF (match_operand:TF 1 "nonmemory_operand" "fG") (match_operand:TF 2 "nonmemory_operand" "fG")))] "TARGET_NUMERICS" "divr %2,%1,%0" [(set_attr "type" "fpdiv")]) (define_insn "negtf2" [(set (match_operand:TF 0 "register_operand" "=f") (neg:TF (match_operand:TF 1 "register_operand" "f")))] "TARGET_NUMERICS" "subr %1,0f0.0,%0" [(set_attr "type" "fpadd")]) (define_insn "abstf2" [(set (match_operand:TF 0 "register_operand" "=f") (abs:TF (match_operand:TF 1 "register_operand" "f")))] "(TARGET_NUMERICS)" "cpysre %1,0f0.0,%0" [(set_attr "type" "fpmove")]) ;; Arithmetic shift instructions. ;; The shli instruction generates an overflow fault if the sign changes. ;; In the case of overflow, it does not give the natural result, it instead ;; gives the last shift value before the overflow. We can not use this ;; instruction because gcc thinks that arithmetic left shift and logical ;; left shift are identical, and sometimes canonicalizes the logical left ;; shift to an arithmetic left shift. Therefore we must always use the ;; logical left shift instruction. (define_insn "ashlsi3" [(set (match_operand:SI 0 "register_operand" "=d") (ashift:SI (match_operand:SI 1 "arith_operand" "dI") (match_operand:SI 2 "arith_operand" "dI")))] "" "shlo %2,%1,%0" [(set_attr "type" "alu2")]) (define_insn "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=d") (ashiftrt:SI (match_operand:SI 1 "arith_operand" "dI") (match_operand:SI 2 "arith_operand" "dI")))] "" "shri %2,%1,%0" [(set_attr "type" "alu2")]) (define_insn "lshrsi3" [(set (match_operand:SI 0 "register_operand" "=d") (lshiftrt:SI (match_operand:SI 1 "arith_operand" "dI") (match_operand:SI 2 "arith_operand" "dI")))] "" "shro %2,%1,%0" [(set_attr "type" "alu2")]) ;; Unconditional and other jump instructions. (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "b %l0" [(set_attr "type" "branch")]) (define_insn "indirect_jump" [(set (pc) (match_operand:SI 0 "address_operand" "p"))] "" "bx %a0" [(set_attr "type" "branch")]) (define_insn "tablejump" [(set (pc) (match_operand:SI 0 "register_operand" "d")) (use (label_ref (match_operand 1 "" "")))] "" "bx (%0)" [(set_attr "type" "branch")]) ;;- jump to subroutine (define_expand "call" [(call (match_operand:SI 0 "general_operand" "g") (match_operand:SI 1 "immediate_operand" "i"))] "" " { emit_insn (gen_call_internal (operands[0], operands[1], virtual_outgoing_args_rtx)); DONE; }") ;; We need a call saved register allocated for the match_scratch, so we use ;; 'l' because all local registers are call saved. ;; ??? I would prefer to use a match_scratch here, but match_scratch allocated ;; registers can't be used for spills. In a function with lots of calls, ;; local-alloc may allocate all local registers to a match_scratch, leaving ;; no local registers available for spills. (define_insn "call_internal" [(call (match_operand:SI 0 "general_operand" "g") (match_operand:SI 1 "immediate_operand" "i")) (use (match_operand:SI 2 "address_operand" "p")) (clobber (reg:SI 19))] "" "* return i960_output_call_insn (operands[0], operands[1], operands[2], insn);" [(set_attr "type" "call")]) (define_expand "call_value" [(set (match_operand 0 "register_operand" "=d") (call (match_operand:SI 1 "general_operand" "g") (match_operand:SI 2 "immediate_operand" "i")))] "" " { emit_insn (gen_call_value_internal (operands[0], operands[1], operands[2], virtual_outgoing_args_rtx)); DONE; }") ;; We need a call saved register allocated for the match_scratch, so we use ;; 'l' because all local registers are call saved. (define_insn "call_value_internal" [(set (match_operand 0 "register_operand" "=d") (call (match_operand:SI 1 "general_operand" "g") (match_operand:SI 2 "immediate_operand" "i"))) (use (match_operand:SI 3 "address_operand" "p")) (clobber (reg:SI 19))] "" "* return i960_output_call_insn (operands[1], operands[2], operands[3], insn);" [(set_attr "type" "call")]) (define_insn "return" [(return)] "" "* return i960_output_ret_insn (insn);" [(set_attr "type" "branch")]) (define_insn "nop" [(const_int 0)] "" "") ;; Various peephole optimizations for multiple-word moves, loads, and stores. ;; Multiple register moves. ;; Matched 5/28/91 (define_peephole [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "register_operand" "r")) (set (match_operand:SI 2 "register_operand" "=r") (match_operand:SI 3 "register_operand" "r")) (set (match_operand:SI 4 "register_operand" "=r") (match_operand:SI 5 "register_operand" "r")) (set (match_operand:SI 6 "register_operand" "=r") (match_operand:SI 7 "register_operand" "r"))] "((REGNO (operands[0]) & 3) == 0) && ((REGNO (operands[1]) & 3) == 0) && (REGNO (operands[0]) + 1 == REGNO (operands[2])) && (REGNO (operands[1]) + 1 == REGNO (operands[3])) && (REGNO (operands[0]) + 2 == REGNO (operands[4])) && (REGNO (operands[1]) + 2 == REGNO (operands[5])) && (REGNO (operands[0]) + 3 == REGNO (operands[6])) && (REGNO (operands[1]) + 3 == REGNO (operands[7]))" "movq %1,%0") ;; Matched 4/17/92 (define_peephole [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "register_operand" "r")) (set (match_operand:DI 2 "register_operand" "=r") (match_operand:DI 3 "register_operand" "r"))] "((REGNO (operands[0]) & 3) == 0) && ((REGNO (operands[1]) & 3) == 0) && (REGNO (operands[0]) + 2 == REGNO (operands[2])) && (REGNO (operands[1]) + 2 == REGNO (operands[3]))" "movq %1,%0") ;; Matched 4/17/92 (define_peephole [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "register_operand" "r")) (set (match_operand:SI 2 "register_operand" "=r") (match_operand:SI 3 "register_operand" "r")) (set (match_operand:SI 4 "register_operand" "=r") (match_operand:SI 5 "register_operand" "r"))] "((REGNO (operands[0]) & 3) == 0) && ((REGNO (operands[1]) & 3) == 0) && (REGNO (operands[0]) + 2 == REGNO (operands[2])) && (REGNO (operands[1]) + 2 == REGNO (operands[3])) && (REGNO (operands[0]) + 3 == REGNO (operands[4])) && (REGNO (operands[1]) + 3 == REGNO (operands[5]))" "movq %1,%0") ;; Matched 4/17/92 (define_peephole [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "register_operand" "r")) (set (match_operand:SI 2 "register_operand" "=r") (match_operand:SI 3 "register_operand" "r")) (set (match_operand:DI 4 "register_operand" "=r") (match_operand:DI 5 "register_operand" "r"))] "((REGNO (operands[0]) & 3) == 0) && ((REGNO (operands[1]) & 3) == 0) && (REGNO (operands[0]) + 1 == REGNO (operands[2])) && (REGNO (operands[1]) + 1 == REGNO (operands[3])) && (REGNO (operands[0]) + 2 == REGNO (operands[4])) && (REGNO (operands[1]) + 2 == REGNO (operands[5]))" "movq %1,%0") ;; Matched 4/17/92 (define_peephole [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "register_operand" "r")) (set (match_operand:SI 2 "register_operand" "=r") (match_operand:SI 3 "register_operand" "r"))] "((REGNO (operands[0]) & 3) == 0) && ((REGNO (operands[1]) & 3) == 0) && (REGNO (operands[0]) + 2 == REGNO (operands[2])) && (REGNO (operands[1]) + 2 == REGNO (operands[3]))" "movt %1,%0") ;; Matched 5/28/91 (define_peephole [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "register_operand" "r")) (set (match_operand:SI 2 "register_operand" "=r") (match_operand:SI 3 "register_operand" "r")) (set (match_operand:SI 4 "register_operand" "=r") (match_operand:SI 5 "register_operand" "r"))] "((REGNO (operands[0]) & 3) == 0) && ((REGNO (operands[1]) & 3) == 0) && (REGNO (operands[0]) + 1 == REGNO (operands[2])) && (REGNO (operands[1]) + 1 == REGNO (operands[3])) && (REGNO (operands[0]) + 2 == REGNO (operands[4])) && (REGNO (operands[1]) + 2 == REGNO (operands[5]))" "movt %1,%0") ;; Matched 5/28/91 (define_peephole [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "register_operand" "r")) (set (match_operand:SI 2 "register_operand" "=r") (match_operand:SI 3 "register_operand" "r"))] "((REGNO (operands[0]) & 1) == 0) && ((REGNO (operands[1]) & 1) == 0) && (REGNO (operands[0]) + 1 == REGNO (operands[2])) && (REGNO (operands[1]) + 1 == REGNO (operands[3]))" "movl %1,%0") ; Multiple register loads. ;; Matched 6/15/91 (define_peephole [(set (match_operand:SI 0 "register_operand" "=r") (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "n")))) (set (match_operand:SI 3 "register_operand" "=r") (mem:SI (plus:SI (match_dup 1) (match_operand:SI 4 "immediate_operand" "n")))) (set (match_operand:SI 5 "register_operand" "=r") (mem:SI (plus:SI (match_dup 1) (match_operand:SI 6 "immediate_operand" "n")))) (set (match_operand:SI 7 "register_operand" "=r") (mem:SI (plus:SI (match_dup 1) (match_operand:SI 8 "immediate_operand" "n"))))] "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) && (REGNO (operands[1]) != REGNO (operands[0])) && (REGNO (operands[0]) + 1 == REGNO (operands[3])) && (REGNO (operands[1]) != REGNO (operands[3])) && (REGNO (operands[0]) + 2 == REGNO (operands[5])) && (REGNO (operands[1]) != REGNO (operands[5])) && (REGNO (operands[0]) + 3 == REGNO (operands[7])) && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])) && (INTVAL (operands[2]) + 8 == INTVAL (operands[6])) && (INTVAL (operands[2]) + 12 == INTVAL (operands[8])))" "ldq %2(%1),%0") ;; Matched 5/28/91 (define_peephole [(set (match_operand:DF 0 "register_operand" "=d") (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "immediate_operand" "n")))) (set (match_operand:DF 3 "register_operand" "=d") (mem:DF (plus:SI (match_dup 1) (match_operand:SI 4 "immediate_operand" "n"))))] "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) && (REGNO (operands[1]) != REGNO (operands[0])) && (REGNO (operands[0]) + 2 == REGNO (operands[3])) && (REGNO (operands[1]) != REGNO (operands[3])) && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))" "ldq %2(%1),%0") ;; Matched 1/24/92 (define_peephole [(set (match_operand:DI 0 "register_operand" "=d") (mem:DI (plus:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "immediate_operand" "n")))) (set (match_operand:DI 3 "register_operand" "=d") (mem:DI (plus:SI (match_dup 1) (match_operand:SI 4 "immediate_operand" "n"))))] "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) && (REGNO (operands[1]) != REGNO (operands[0])) && (REGNO (operands[0]) + 2 == REGNO (operands[3])) && (REGNO (operands[1]) != REGNO (operands[3])) && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))" "ldq %2(%1),%0") ;; Matched 4/17/92 (define_peephole [(set (match_operand:SI 0 "register_operand" "=d") (mem:SI (match_operand:SI 1 "register_operand" "d"))) (set (match_operand:SI 2 "register_operand" "=d") (mem:SI (plus:SI (match_dup 1) (match_operand:SI 3 "immediate_operand" "n")))) (set (match_operand:SI 4 "register_operand" "=d") (mem:SI (plus:SI (match_dup 1) (match_operand:SI 5 "immediate_operand" "n")))) (set (match_operand:SI 6 "register_operand" "=d") (mem:SI (plus:SI (match_dup 1) (match_operand:SI 7 "immediate_operand" "n"))))] "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0) && (REGNO (operands[1]) != REGNO (operands[0])) && (REGNO (operands[0]) + 1 == REGNO (operands[2])) && (REGNO (operands[1]) != REGNO (operands[2])) && (REGNO (operands[0]) + 2 == REGNO (operands[4])) && (REGNO (operands[1]) != REGNO (operands[4])) && (REGNO (operands[0]) + 3 == REGNO (operands[6])) && (INTVAL (operands[3]) == 4) && (INTVAL (operands[5]) == 8) && (INTVAL (operands[7]) == 12))" "ldq (%1),%0") ;; Matched 5/28/91 (define_peephole [(set (match_operand:SI 0 "register_operand" "=d") (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "immediate_operand" "n")))) (set (match_operand:SI 3 "register_operand" "=d") (mem:SI (plus:SI (match_dup 1) (match_operand:SI 4 "immediate_operand" "n")))) (set (match_operand:SI 5 "register_operand" "=d") (mem:SI (plus:SI (match_dup 1) (match_operand:SI 6 "immediate_operand" "n"))))] "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) && (REGNO (operands[1]) != REGNO (operands[0])) && (REGNO (operands[0]) + 1 == REGNO (operands[3])) && (REGNO (operands[1]) != REGNO (operands[3])) && (REGNO (operands[0]) + 2 == REGNO (operands[5])) && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])) && (INTVAL (operands[2]) + 8 == INTVAL (operands[6])))" "ldt %2(%1),%0") ;; Matched 6/15/91 (define_peephole [(set (match_operand:SI 0 "register_operand" "=d") (mem:SI (match_operand:SI 1 "register_operand" "d"))) (set (match_operand:SI 2 "register_operand" "=d") (mem:SI (plus:SI (match_dup 1) (match_operand:SI 3 "immediate_operand" "n")))) (set (match_operand:SI 4 "register_operand" "=d") (mem:SI (plus:SI (match_dup 1) (match_operand:SI 5 "immediate_operand" "n"))))] "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0) && (REGNO (operands[1]) != REGNO (operands[0])) && (REGNO (operands[0]) + 1 == REGNO (operands[2])) && (REGNO (operands[1]) != REGNO (operands[2])) && (REGNO (operands[0]) + 2 == REGNO (operands[4])) && (INTVAL (operands[3]) == 4) && (INTVAL (operands[5]) == 8))" "ldt (%1),%0") ;; Matched 5/28/91 (define_peephole [(set (match_operand:SI 0 "register_operand" "=d") (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "immediate_operand" "n")))) (set (match_operand:SI 3 "register_operand" "=d") (mem:SI (plus:SI (match_dup 1) (match_operand:SI 4 "immediate_operand" "n"))))] "(i960_si_di (operands[1], operands[2]) && ((REGNO (operands[0]) & 1) == 0) && (REGNO (operands[1]) != REGNO (operands[0])) && (REGNO (operands[0]) + 1 == REGNO (operands[3])) && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])))" "ldl %2(%1),%0") ;; Matched 5/28/91 (define_peephole [(set (match_operand:SI 0 "register_operand" "=d") (mem:SI (match_operand:SI 1 "register_operand" "d"))) (set (match_operand:SI 2 "register_operand" "=d") (mem:SI (plus:SI (match_dup 1) (match_operand:SI 3 "immediate_operand" "n"))))] "(i960_si_di (operands[1], 0) && ((REGNO (operands[0]) & 1) == 0) && (REGNO (operands[1]) != REGNO (operands[0])) && (REGNO (operands[0]) + 1 == REGNO (operands[2])) && (INTVAL (operands[3]) == 4))" "ldl (%1),%0") ; Multiple register stores. ;; Matched 5/28/91 (define_peephole [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d") (match_operand:SI 1 "immediate_operand" "n"))) (match_operand:SI 2 "register_operand" "d")) (set (mem:SI (plus:SI (match_dup 0) (match_operand:SI 3 "immediate_operand" "n"))) (match_operand:SI 4 "register_operand" "d")) (set (mem:SI (plus:SI (match_dup 0) (match_operand:SI 5 "immediate_operand" "n"))) (match_operand:SI 6 "register_operand" "d")) (set (mem:SI (plus:SI (match_dup 0) (match_operand:SI 7 "immediate_operand" "n"))) (match_operand:SI 8 "register_operand" "d"))] "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) && (REGNO (operands[2]) + 1 == REGNO (operands[4])) && (REGNO (operands[2]) + 2 == REGNO (operands[6])) && (REGNO (operands[2]) + 3 == REGNO (operands[8])) && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])) && (INTVAL (operands[1]) + 8 == INTVAL (operands[5])) && (INTVAL (operands[1]) + 12 == INTVAL (operands[7])))" "stq %2,%1(%0)") ;; Matched 6/16/91 (define_peephole [(set (mem:DF (plus:SI (match_operand:SI 0 "register_operand" "d") (match_operand:SI 1 "immediate_operand" "n"))) (match_operand:DF 2 "register_operand" "d")) (set (mem:DF (plus:SI (match_dup 0) (match_operand:SI 3 "immediate_operand" "n"))) (match_operand:DF 4 "register_operand" "d"))] "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) && (REGNO (operands[2]) + 2 == REGNO (operands[4])) && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))" "stq %2,%1(%0)") ;; Matched 4/17/92 (define_peephole [(set (mem:DI (plus:SI (match_operand:SI 0 "register_operand" "d") (match_operand:SI 1 "immediate_operand" "n"))) (match_operand:DI 2 "register_operand" "d")) (set (mem:DI (plus:SI (match_dup 0) (match_operand:SI 3 "immediate_operand" "n"))) (match_operand:DI 4 "register_operand" "d"))] "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) && (REGNO (operands[2]) + 2 == REGNO (operands[4])) && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))" "stq %2,%1(%0)") ;; Matched 1/23/92 (define_peephole [(set (mem:SI (match_operand:SI 0 "register_operand" "d")) (match_operand:SI 1 "register_operand" "d")) (set (mem:SI (plus:SI (match_dup 0) (match_operand:SI 2 "immediate_operand" "n"))) (match_operand:SI 3 "register_operand" "d")) (set (mem:SI (plus:SI (match_dup 0) (match_operand:SI 4 "immediate_operand" "n"))) (match_operand:SI 5 "register_operand" "d")) (set (mem:SI (plus:SI (match_dup 0) (match_operand:SI 6 "immediate_operand" "n"))) (match_operand:SI 7 "register_operand" "d"))] "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0) && (REGNO (operands[1]) + 1 == REGNO (operands[3])) && (REGNO (operands[1]) + 2 == REGNO (operands[5])) && (REGNO (operands[1]) + 3 == REGNO (operands[7])) && (INTVAL (operands[2]) == 4) && (INTVAL (operands[4]) == 8) && (INTVAL (operands[6]) == 12))" "stq %1,(%0)") ;; Matched 5/29/91 (define_peephole [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d") (match_operand:SI 1 "immediate_operand" "n"))) (match_operand:SI 2 "register_operand" "d")) (set (mem:SI (plus:SI (match_dup 0) (match_operand:SI 3 "immediate_operand" "n"))) (match_operand:SI 4 "register_operand" "d")) (set (mem:SI (plus:SI (match_dup 0) (match_operand:SI 5 "immediate_operand" "n"))) (match_operand:SI 6 "register_operand" "d"))] "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) && (REGNO (operands[2]) + 1 == REGNO (operands[4])) && (REGNO (operands[2]) + 2 == REGNO (operands[6])) && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])) && (INTVAL (operands[1]) + 8 == INTVAL (operands[5])))" "stt %2,%1(%0)") ;; Matched 5/29/91 (define_peephole [(set (mem:SI (match_operand:SI 0 "register_operand" "d")) (match_operand:SI 1 "register_operand" "d")) (set (mem:SI (plus:SI (match_dup 0) (match_operand:SI 2 "immediate_operand" "n"))) (match_operand:SI 3 "register_operand" "d")) (set (mem:SI (plus:SI (match_dup 0) (match_operand:SI 4 "immediate_operand" "n"))) (match_operand:SI 5 "register_operand" "d"))] "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0) && (REGNO (operands[1]) + 1 == REGNO (operands[3])) && (REGNO (operands[1]) + 2 == REGNO (operands[5])) && (INTVAL (operands[2]) == 4) && (INTVAL (operands[4]) == 8))" "stt %1,(%0)") ;; Matched 5/28/91 (define_peephole [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d") (match_operand:SI 1 "immediate_operand" "n"))) (match_operand:SI 2 "register_operand" "d")) (set (mem:SI (plus:SI (match_dup 0) (match_operand:SI 3 "immediate_operand" "n"))) (match_operand:SI 4 "register_operand" "d"))] "(i960_si_di (operands[0], operands[1]) && ((REGNO (operands[2]) & 1) == 0) && (REGNO (operands[2]) + 1 == REGNO (operands[4])) && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])))" "stl %2,%1(%0)") ;; Matched 5/28/91 (define_peephole [(set (mem:SI (match_operand:SI 0 "register_operand" "d")) (match_operand:SI 1 "register_operand" "d")) (set (mem:SI (plus:SI (match_dup 0) (match_operand:SI 2 "immediate_operand" "n"))) (match_operand:SI 3 "register_operand" "d"))] "(i960_si_di (operands[0], 0) && ((REGNO (operands[1]) & 1) == 0) && (REGNO (operands[1]) + 1 == REGNO (operands[3])) && (INTVAL (operands[2]) == 4))" "stl %1,(%0)") gcc-2.5.8/config/i960/xm-i960.h100444 22011 13 2566 5413066403 14213 0ustar kenneruser/* Configuration for GNU C-compiler for Intel 960 family Copyright (C) 1987, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* #defines that need visibility everywhere. */ #define FALSE 0 #define TRUE 1 /* This describes the machine the compiler is hosted on. */ #define HOST_BITS_PER_CHAR 8 #define HOST_BITS_PER_SHORT 16 #define HOST_BITS_PER_INT 32 #define HOST_BITS_PER_LONG 32 #define HOST_BITS_PER_LONGLONG 64 /* Arguments to use with `exit'. */ #define SUCCESS_EXIT_CODE 0 #define FATAL_EXIT_CODE 33 /* If not compiled with GNU C, use the C alloca */ #ifndef __GNUC__ #define USE_C_ALLOCA #endif /* target machine dependencies. tm.h is a symbolic link to the actual target specific file. */ #include "tm.h" gcc-2.5.8/config/lynx.h100444 22011 13 6033 5437727575 13422 0ustar kenneruser/* Target independent definitions for LynxOS. */ /* ??? The -C option may need to change to whatever option the GNU assembler actually accepts. */ #undef ASM_SPEC #define ASM_SPEC "%{mcoff:-C}" #undef CPP_SPEC #define CPP_SPEC "%{mthreads:-D_MULTITHREADED} %{mposix:-D_POSIX_SOURCE} %{msystem-v:-I/usr/include_v}" /* Provide required defaults for linker switches. */ /* ??? The -k option may need to change to whatever option the GNU linker actually accepts. This is to produce COFF output. */ /* ??? The -V option may need to change to whatever option the GNU linker actually accepts. This is to produce System-V magic numbers. */ #undef LINK_SPEC #define LINK_SPEC "-P1000 %{msystem-v:-V} %{mcoff:-k}" #undef LIB_SPEC #define LIB_SPEC "%{mthreads:-L/lib/thread/}%{msystem-v:-lc_v}%{!msystem-v:%{mposix:-lc_p} -lc}" #undef STARTFILE_SPEC #define STARTFILE_SPEC "%{p:%{mcoff:pinit1.o%s}%{!mcoff:pinit.o%s}}%{!p:%{msystem-v:%{mcoff:vinit1.o%s}%{!mcoff:vinit.o%s}}%{!msystem-v:%{mcoff:init1.o%s}%{!mcoff:init.o%s}}}" #undef ENDFILE_SPEC #define ENDFILE_SPEC "%{mcoff:initn.o%s} %{p:_etext.o%s}" #undef SIZE_TYPE #define SIZE_TYPE "unsigned int" #undef WCHAR_TYPE #define WCHAR_TYPE "int" #undef PTRDIFF_TYPE #define PTRDIFF_TYPE "long int" /* We want to output DBX debugging information. */ #define DBX_DEBUGGING_INFO #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG /* We optionally want to be able to produce SDB debugging output so that we can create debuggable SDB/coff files. This won't be needed when stabs-in-coff works. */ #define SDB_DEBUGGING_INFO /* Generate calls to memcpy, memcmp and memset. */ #define TARGET_MEM_FUNCTIONS /* Handle #pragma pack and sometimes #pragma weak. */ #define HANDLE_SYSV_PRAGMA #define TARGET_THREADS (target_flags & MASK_THREADS) #define MASK_THREADS 0x40000000 #define TARGET_POSIX (target_flags & MASK_POSIX) #define MASK_POSIX 0x20000000 #define TARGET_SYSTEM_V (target_flags & MASK_SYSTEM_V) #define MASK_SYSTEM_V 0x10000000 #define TARGET_COFF (target_flags & MASK_COFF) #define MASK_COFF 0x08000000 #undef SUBTARGET_SWITCHES #define SUBTARGET_SWITCHES \ {"threads", MASK_THREADS}, \ {"posix", MASK_POSIX}, \ {"system-v", MASK_SYSTEM_V}, \ {"coff", MASK_COFF}, #undef SUBTARGET_OVERRIDE_OPTIONS #define SUBTARGET_OVERRIDE_OPTIONS \ { if (TARGET_SYSTEM_V && profile_flag) \ warning ("-msystem-v and -p are incompatible"); \ if (TARGET_SYSTEM_V && TARGET_THREADS) \ warning ("-msystem-v and -mthreads are incompatible"); } /* Define this so that C++ destructors will use atexit. */ #define HAVE_ATEXIT /* This is defined only so that we can find the assembler. Everything else is in /bin. */ #define MD_EXEC_PREFIX "/usr/local/lib/gcc-" /* ??? This is needed because /bin/ld does not handle -L options correctly. This can be deleted if GNU ld is being used. */ #define LINK_LIBGCC_SPECIAL_1 /* The Lynx linker considers __main to be a possible entry point, so we must use a different name. */ #define NAME__MAIN "____main" #define SYMBOL__MAIN ____main gcc-2.5.8/config/m68k/ 40777 22011 13 0 5502603156 12730 5ustar kennerusergcc-2.5.8/config/m68k/3b1.h100444 22011 13 42422 5453234627 13611 0ustar kenneruser/* Definitions of target machine for GNU compiler. AT&T UNIX PC version (pc7300, 3b1) Written by Alex Crain bug reports to alex@umbc3.umd.edu Copyright (C) 1987 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define SGS_SWITCH_TABLES /* Different switch table handling */ #include "m68k/hp320.h" /* See m68k.h. 0 means 680[01]0 with no 68881. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT 0 /* Don't try using XFmode. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 /* -m68020 requires special flags to the assembler. */ #undef ASM_SPEC #define ASM_SPEC "%{m68020:-68020}%{!m68020:-68010} %{m68881:-68881}" /* we use /lib/libp/lib* when profiling */ #undef LIB_SPEC #define LIB_SPEC "%{!shlib:%{p:-L/lib/libp} %{pg:-L/lib/libp} -lc}" /* shared libraries need to use crt0s.o */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{!shlib:%{pg:mcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}\ %{shlib:crt0s.o%s shlib.ifile%s} " /* cpp has to support a #sccs directive for the /usr/include files */ #define SCCS_DIRECTIVE /* Make output for SDB. */ #define SDB_DEBUGGING_INFO /* The .file command should always begin the output. */ #undef ASM_FILE_START #define ASM_FILE_START(FILE) \ output_file_directive ((FILE), main_input_filename) /* Don't try to define `gcc_compiled.' since the assembler might not accept symbols with periods and GDB doesn't run on this machine anyway. */ #define ASM_IDENTIFY_GCC(FILE) /* Define __HAVE_68881__ in preprocessor if -m68881 is specified. This will control the use of inline 68881 insns in certain macros. */ #undef CPP_SPEC #define CPP_SPEC "%{m68881:-D__HAVE_68881__}" /* Names to predefine in the preprocessor for this target machine. */ /* ihnp4!lmayk!lgm@eddie.mit.edu says mc68000 and m68k should not be here. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dmc68k -Dunix -Dunixpc -D__motorola__ -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)" #undef REGISTER_NAMES #define REGISTER_NAMES \ {"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \ "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", \ "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7"} /* Specify how to pad function arguments. Value should be `upward', `downward' or `none'. Same as the default, except no padding for large or variable-size args. */ #define FUNCTION_ARG_PADDING(MODE, TYPE) \ (((MODE) == BLKmode \ ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ && int_size_in_bytes (TYPE) < PARM_BOUNDARY / BITS_PER_UNIT) \ : GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY) \ ? downward : none) /* Override part of the obstack macros. */ #define __PTR_TO_INT(P) ((int)(P)) #define __INT_TO_PTR(P) ((char *)(P)) /* The 3b1 does not have `atexit'. */ #undef HAVE_ATEXIT /* Override parts of m68k.h to fit the SGS-3b1 assembler. */ #undef TARGET_VERSION #undef ASM_FORMAT_PRIVATE_NAME #undef ASM_OUTPUT_DOUBLE #undef ASM_OUTPUT_FLOAT #undef ASM_OUTPUT_ALIGN #undef ASM_OUTPUT_SOURCE_FILENAME #undef ASM_OUTPUT_SOURCE_LINE #undef PRINT_OPERAND_ADDRESS #undef ASM_GENERATE_INTERNAL_LABEL #undef FUNCTION_PROFILER #undef ASM_OUTPUT_ADDR_VEC_ELT #undef ASM_OUTPUT_ADDR_DIFF_ELT #undef ASM_OUTPUT_INTERNAL_LABEL #undef ASM_OUTPUT_OPCODE #undef ASM_OUTPUT_LOCAL #undef ASM_OUTPUT_LABELREF #undef ASM_OUTPUT_ASCII #define TARGET_VERSION fprintf (stderr, " (68k, SGS/AT&T unixpc syntax)"); /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12), \ sprintf ((OUTPUT), "%s_%%%d", (NAME), (LABELNO))) /* The unixpc doesn't know about double's and float's */ #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { long l[2]; \ REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ fprintf (FILE, "\tlong 0x%x,0x%x\n", l[0], l[1]); \ } while (0) #undef ASM_OUTPUT_LONG_DOUBLE #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ do { long l[3]; \ REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ fprintf (FILE, "\tlong 0x%x,0x%x,0x%x\n", l[0], l[1], l[2]); \ } while (0) /* This is how to output an assembler line defining a `float' constant. */ #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { long l; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ fprintf ((FILE), "\tlong 0x%x\n", l); \ } while (0) #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG) == 1) \ fprintf (FILE, "\teven\n"); \ else if ((LOG) != 0) \ abort (); /* This is how to output an assembler line that says to advance the location counter by SIZE bytes. */ #undef ASM_OUTPUT_SKIP #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\tspace %d\n", (SIZE)) /* Can't use ASM_OUTPUT_SKIP in text section; it doesn't leave 0s. */ #define ASM_NO_SKIP_IN_TEXT 1 /* The beginnings of sdb support... */ #define ASM_OUTPUT_SOURCE_FILENAME(FILE, FILENAME) \ do { fprintf (FILE, "\tfile\t"); \ output_quoted_string (FILE, FILENAME); \ fprintf (FILE, "\n"); \ } while (0) #define ASM_OUTPUT_SOURCE_LINE(FILE, LINENO) \ fprintf (FILE, "\tln\t%d\n", \ (sdb_begin_function_line \ ? last_linenum - sdb_begin_function_line : 1)) /* Yet another null terminated string format. */ #define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ { register int sp = 0, lp = 0; \ fprintf ((FILE), "\tbyte\t"); \ loop: \ if ((PTR)[sp] > ' ' && ! ((PTR)[sp] & 0x80) && (PTR)[sp] != '\\') \ { lp += 3; \ fprintf ((FILE), "'%c", (PTR)[sp]); } \ else \ { lp += 5; \ fprintf ((FILE), "0x%x", (PTR)[sp]); } \ if (++sp < (LEN)) \ { if (lp > 60) \ { lp = 0; \ fprintf ((FILE), "\n\t%s ", ASCII_DATA_ASM_OP); } \ else \ putc (',', (FILE)); \ goto loop; } \ putc ('\n', (FILE)); } /* Note that in the case of the movhi which fetches an element of an ADDR_DIFF_VEC the offset output is too large by 2. This is because the 3b1 assembler refuses to subtract 2. ASM_OUTPUT_CASE_LABEL, below, compensates for this. */ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ { register rtx reg1, reg2, breg, ireg; \ register rtx addr = ADDR; \ rtx offset; \ switch (GET_CODE (addr)) \ { \ case REG: \ fprintf (FILE, "(%s)", reg_names[REGNO (addr)]); \ break; \ case PRE_DEC: \ fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case POST_INC: \ fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case PLUS: \ reg1 = 0; reg2 = 0; \ ireg = 0; breg = 0; \ offset = 0; \ if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \ { \ offset = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \ { \ offset = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) != PLUS) ; \ else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == MULT) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == MULT) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == REG) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == REG) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \ || GET_CODE (addr) == SIGN_EXTEND) \ { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \ /* for OLD_INDEXING \ else if (GET_CODE (addr) == PLUS) \ { \ if (GET_CODE (XEXP (addr, 0)) == REG) \ { \ reg2 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == REG) \ { \ reg2 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ } \ */ \ if (offset != 0) { if (addr != 0) abort (); addr = offset; } \ if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \ || GET_CODE (reg1) == MULT)) \ || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \ { breg = reg2; ireg = reg1; } \ else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \ { breg = reg1; ireg = reg2; } \ if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \ { int scale = 1; \ if (GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "LD%%%d(%%pc,%s.w", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (XEXP (ireg, 0))]); \ else \ fprintf (FILE, "LD%%%d(%%pc,%s.l", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (ireg)]); \ if (scale != 1) fprintf (FILE, "*%d", scale); \ fprintf (FILE, ")"); \ break; } \ if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF) \ { fprintf (FILE, "LD%%%d(%%pc,%s.l", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (breg)]); \ putc (')', FILE); \ break; } \ if (ireg != 0 || breg != 0) \ { int scale = 1; \ if (breg == 0) \ abort (); \ if (addr != 0) \ output_addr_const (FILE, addr); \ fprintf (FILE, "(%s", reg_names[REGNO (breg)]); \ if (ireg != 0) \ putc (',', FILE); \ if (ireg != 0 && GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]); \ else if (ireg != 0) \ fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]); \ if (scale != 1) fprintf (FILE, "*%d", scale); \ putc (')', FILE); \ break; \ } \ else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \ { fprintf (FILE, "LD%%%d(%%pc,%s.w)", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (reg1)]); \ break; } \ default: \ if (GET_CODE (addr) == CONST_INT \ && INTVAL (addr) < 0x8000 \ && INTVAL (addr) >= -0x8000) \ fprintf (FILE, "%d", INTVAL (addr)); \ else \ output_addr_const (FILE, addr); \ }} #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ sprintf ((LABEL), "%s%%%d", (PREFIX), (NUM)) #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, "%s%%%d:\n", PREFIX, NUM) /* Must put address in %a0 , not %d0 . -- LGM, 7/15/88 */ #define FUNCTION_PROFILER(FILE, LABEL_NO) \ fprintf (FILE, "\tmov.l &LP%%%d,%%a0\n\tjsr mcount\n", (LABEL_NO)) #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "\tlong L%%%d\n", (VALUE)) #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\tshort L%%%d-L%%%d\n", (VALUE), (REL)) /* ihnp4!lmayk!lgm says that `short 0' triggers assembler bug; `short L%nn-L%nn' supposedly works. */ #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \ if (! RTX_INTEGRATED_P (TABLE)) \ fprintf (FILE, "\tswbeg &%d\n%s%%%d:\n", \ XVECLEN (PATTERN (TABLE), 1), (PREFIX), (NUM)); \ else \ fprintf (FILE, "\tswbeg &%d\n%s%%%d:\n\tshort %s%%%d-%s%%%d\n", \ XVECLEN (PATTERN (TABLE), 1) + 1, (PREFIX), (NUM), \ (PREFIX), (NUM), (PREFIX), (NUM)) /* At end of a switch table, define LDnnn iff the symbol LInnn was defined. Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" fails to assemble. Luckily "LDnnn(pc,d0.l*2)" produces the results we want. This difference can be accommodated by making the assembler define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END macro. */ #define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \ { if (switch_table_difference_label_flag) \ fprintf (FILE, "\tset LD%%%d,L%%%d-LI%%%d\n", (NUM), (NUM), (NUM)); \ switch_table_difference_label_flag = 0; } int switch_table_difference_label_flag; #define ASM_OUTPUT_OPCODE(FILE, PTR) \ { if ((PTR)[0] == 'j' && (PTR)[1] == 'b') \ { ++(PTR); \ while (*(PTR) != ' ') \ { putc (*(PTR), (FILE)); ++(PTR); } \ fprintf ((FILE), ".w"); } \ else if ((PTR)[0] == 's') \ { \ if (!strncmp ((PTR), "swap", 4)) \ { fprintf ((FILE), "swap.w"); (PTR) += 4; } \ } \ else if ((PTR)[0] == 'f') \ { \ if (!strncmp ((PTR), "fmove", 5)) \ { fprintf ((FILE), "fmov"); (PTR) += 5; } \ else if (!strncmp ((PTR), "fbne", 4)) \ { fprintf ((FILE), "fbneq"); (PTR) += 4; } \ } \ /* MOVE, MOVEA, MOVEQ, MOVEC ==> MOV */ \ else if ((PTR)[0] == 'm' && (PTR)[1] == 'o' \ && (PTR)[2] == 'v' && (PTR)[3] == 'e') \ { fprintf ((FILE), "mov"); (PTR) += 4; \ if ((PTR)[0] == 'q' || (PTR)[0] == 'a' \ || (PTR)[0] == 'c') (PTR)++; } \ /* SUB, SUBQ, SUBA, SUBI ==> SUB */ \ else if ((PTR)[0] == 's' && (PTR)[1] == 'u' \ && (PTR)[2] == 'b') \ { fprintf ((FILE), "sub"); (PTR) += 3; \ if ((PTR)[0] == 'q' || (PTR)[0] == 'i' \ || (PTR)[0] == 'a') (PTR)++; } \ /* CMP, CMPA, CMPI, CMPM ==> CMP */ \ else if ((PTR)[0] == 'c' && (PTR)[1] == 'm' \ && (PTR)[2] == 'p') \ { fprintf ((FILE), "cmp"); (PTR) += 3; \ if ((PTR)[0] == 'a' || (PTR)[0] == 'i' \ || (PTR)[0] == 'm') (PTR)++; } \ } #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( fputs ("\tlcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (ROUNDED))) #define ASM_OUTPUT_LABELREF(FILE,NAME) \ fprintf (FILE, "%s", NAME) /* Override usual definitions of SDB output macros. These definitions differ only in the absence of the period at the beginning of the name of the directive and in the use of `~' as the symbol for the current location. */ #define PUT_SDB_SCL(a) fprintf(asm_out_file, "\tscl\t%d;", (a)) #define PUT_SDB_INT_VAL(a) fprintf (asm_out_file, "\tval\t%d;", (a)) #define PUT_SDB_VAL(a) \ ( fputs ("\tval\t", asm_out_file), \ output_addr_const (asm_out_file, (a)), \ fputc (';', asm_out_file)) #define PUT_SDB_DEF(a) \ do { fprintf (asm_out_file, "\tdef\t"); \ ASM_OUTPUT_LABELREF (asm_out_file, a); \ fprintf (asm_out_file, ";"); } while (0) #define PUT_SDB_PLAIN_DEF(a) fprintf(asm_out_file,"\tdef\t~%s;",a) #define PUT_SDB_ENDEF fputs("\tendef\n", asm_out_file) #define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\ttype\t0%o;", a) #define PUT_SDB_SIZE(a) fprintf(asm_out_file, "\tsize\t%d;", a) #define PUT_SDB_START_DIM fprintf(asm_out_file, "\tdim\t") #define PUT_SDB_TAG(a) \ do { fprintf (asm_out_file, "\ttag\t"); \ ASM_OUTPUT_LABELREF (asm_out_file, a); \ fprintf (asm_out_file, ";"); } while (0) #define PUT_SDB_BLOCK_START(LINE) \ fprintf (asm_out_file, \ "\tdef\t~bb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n", \ (LINE)) #define PUT_SDB_BLOCK_END(LINE) \ fprintf (asm_out_file, \ "\tdef\t~eb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n", \ (LINE)) #define PUT_SDB_FUNCTION_START(LINE) \ fprintf (asm_out_file, \ "\tdef\t~bf;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n", \ (LINE)) #define PUT_SDB_FUNCTION_END(LINE) \ fprintf (asm_out_file, \ "\tdef\t~ef;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n", \ (LINE)) #define PUT_SDB_EPILOGUE_END(NAME) \ fprintf (asm_out_file, \ "\tdef\t%s;\tval\t~;\tscl\t-1;\tendef\n", \ (NAME)) #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \ sprintf ((BUFFER), "~%dfake", (NUMBER)); /* Define subroutines to call to handle multiply, divide, and remainder. Use the subroutines that the 3b1's library provides. The `*' prevents an underscore from being prepended by the compiler. */ #define DIVSI3_LIBCALL "*ldiv" #define UDIVSI3_LIBCALL "*uldiv" #define MODSI3_LIBCALL "*lrem" #define UMODSI3_LIBCALL "*ulrem" #define MULSI3_LIBCALL "*lmul" #define UMULSI3_LIBCALL "*ulmul" /* Definitions for collect2. */ #define OBJECT_FORMAT_COFF #define NO_SYS_SIGLIST #define MY_ISCOFF(magic) \ ((magic) == MC68KWRMAGIC || (magic) == MC68KROMAGIC || (magic) == MC68KPGMAGIC) gcc-2.5.8/config/m68k/3b1g.h100444 22011 13 5003 5453234631 13725 0ustar kenneruser/* Definitions of target machine for GNU compiler, for a 3b1 using GAS. Copyright (C) 1987, 1988 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/m68k.h" /* See m68k.h. 0 means 68000 with no 68881. */ #define TARGET_DEFAULT 0 /* Don't try using XFmode. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 /* Define __HAVE_68881 in preprocessor only if -m68881 is specified. This will control the use of inline 68881 insns in certain macros. Also inform the program which CPU this is for. */ #define CPP_SPEC "%{m68881:-D__HAVE_68881__} \ %{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}" /* -m68020 requires special flags to the assembler. */ #define ASM_SPEC \ "%{m68020:-mc68020}%{mc68020:-mc68020}%{!mc68020:%{!m68020:-mc68010}}" /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Dmc68000 -Dmc68k -Dunix -Dunixpc -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)" /* This is (not really) BSD, so (but) it wants DBX format. */ #define DBX_DEBUGGING_INFO /* Brain damage. */ #define SCCS_DIRECTIVE /* Specify how to pad function arguments. Value should be `upward', `downward' or `none'. Same as the default, except no padding for large or variable-size args. */ #define FUNCTION_ARG_PADDING(MODE, TYPE) \ (((MODE) == BLKmode \ ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ && int_size_in_bytes (TYPE) < PARM_BOUNDARY / BITS_PER_UNIT) \ : GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY) \ ? downward : none) /* Override part of the obstack macros. */ #define __PTR_TO_INT(P) ((int)(P)) #define __INT_TO_PTR(P) ((char *)(P)) /* Every structure or union's size must be a multiple of 2 bytes. */ #define STRUCTURE_SIZE_BOUNDARY 16 /* Generate calls to memcpy, memcmp and memset. */ #define TARGET_MEM_FUNCTIONS gcc-2.5.8/config/m68k/altos3068.h100444 22011 13 10257 5453234634 14666 0ustar kenneruser/* Definitions of target machine for GNU compiler. Altos 3068 68020 version. Copyright (C) 1988, 1989, 1993 Free Software Foundation, Inc. Written by Jyrki Kuoppala Last modified: Mon Mar 6 22:47:58 1989 This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/m68k.h" /* See m68k.h. 7 means 68020 with 68881. */ /* 5 is without 68881. Change to 7 if you have 68881 */ #ifndef TARGET_DEFAULT #define TARGET_DEFAULT 5 /* Don't try using XFmode. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 #endif /* Define __HAVE_68881__ in preprocessor, according to the -m flags. This will control the use of inline 68881 insns in certain macros. Also inform the program which CPU this is for. */ #if TARGET_DEFAULT & 02 /* -m68881 is the default */ #define CPP_SPEC \ "%{!msoft-float:-D__HAVE_68881__ }\ %{!ansi:%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}}" #else /* -msoft-float is the default */ #define CPP_SPEC \ "%{m68881:-D__HAVE_68881__ }\ %{!ansi:%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}}" #endif /* -m68000 requires special flags to the assembler. */ #define ASM_SPEC \ "%{m68000:-mc68010}%{mc68000:-mc68010}%{!mc68000:%{!m68000:-mc68020}}" /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Dmc68000 -DPORTAR -Dmc68k32 -Uvax -Dm68k -Dunix -Asystem(unix) -Acpu(m68k) -Amachine(m68k)" /* Every structure or union's size must be a multiple of 2 bytes. */ #define STRUCTURE_SIZE_BOUNDARY 16 /* Generate calls to memcpy, memcmp and memset. */ #define TARGET_MEM_FUNCTIONS /* We use gnu assembler, linker and gdb, so we want DBX format. */ #define DBX_DEBUGGING_INFO /* Tell some conditionals we will use GAS. Is this really used? */ #define USE_GAS /* This is how to output an assembler line defining a `double' constant. */ #undef ASM_OUTPUT_DOUBLE #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { char dstr[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", dstr); \ fprintf (FILE, "\t.double 0r%s\n", dstr); \ } while (0) /* This is how to output an assembler line defining a `float' constant. */ #undef ASM_OUTPUT_FLOAT #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { char dstr[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", dstr); \ fprintf (FILE, "\t.single 0r%s\n", dstr); \ } while (0) #undef ASM_OUTPUT_FLOAT_OPERAND #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ do { \ if (CODE == 'f') \ { \ char dstr[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \ fprintf (FILE, "#0r%s", dstr); \ } \ else \ { \ long l; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ if (sizeof (int) == sizeof (long)) \ asm_fprintf ((FILE), "%I0x%x", l); \ else \ asm_fprintf ((FILE), "%I0x%lx", l); \ } \ } while (0) #undef ASM_OUTPUT_DOUBLE_OPERAND #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ do { char dstr[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ fprintf (FILE, "#0r%s", dstr); \ } while (0) /* Return pointer values in both d0 and a0. */ #undef FUNCTION_EXTRA_EPILOGUE #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) \ { \ extern int current_function_returns_pointer; \ if ((current_function_returns_pointer) && \ ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode))\ fprintf (FILE, "\tmovel d0,a0\n"); \ } gcc-2.5.8/config/m68k/amix.h100444 22011 13 13127 5463602666 14165 0ustar kenneruser/* Definitions of target machine for GNU compiler. Commodore Amiga A3000UX version. Copyright (C) 1991 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 1, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/m68kv4.h" /* rhealey@aggregate.com says dots are no good either. */ #define NO_DOT_IN_LABEL /* Alter assembler syntax for fsgldiv and fsglmul. It is highly likely that this is a generic SGS m68k assembler dependency. If so, it should eventually be handled in the m68k/sgs.h ASM_OUTPUT_OPCODE macro, like the other SGS assembler quirks. -fnf */ #define FSGLDIV_USE_S /* Use fsgldiv.s, not fsgldiv.x */ #define FSGLMUL_USE_S /* Use fsglmul.s, not fsglmul.x */ /* Names to predefine in the preprocessor for this target machine. For the Amiga, these definitions match those of the native AT&T compiler. Note that we override the definition in m68kv4.h, where SVR4 is defined and AMIX isn't. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES \ "-Dm68k -Dunix -DAMIX -D__svr4__ -D__motorola__ \ -Amachine(m68k) -Acpu(m68k) -Asystem(unix) -Alint(off)" /* At end of a switch table, define LDnnn iff the symbol LInnn was defined. Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results we want. This difference can be accommodated by making the assembler define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END macro. (the Amiga assembler has this bug) */ #undef ASM_OUTPUT_CASE_END #define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \ do { \ if (switch_table_difference_label_flag) \ asm_fprintf ((FILE), "\t%s %LLD%d,%LL%d\n", SET_ASM_OP, (NUM), (NUM));\ switch_table_difference_label_flag = 0; \ } while (0) int switch_table_difference_label_flag; /* This says how to output assembler code to declare an uninitialized external linkage data object. Under SVR4, the linker seems to want the alignment of data objects to depend on their types. We do exactly that here. [This macro overrides the one in svr4.h because the amix assembler has a minimum default alignment of 4, and will not accept any explicit alignment smaller than this. -fnf] */ #undef ASM_OUTPUT_ALIGNED_COMMON #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ do { \ fputs ("\t.comm\t", (FILE)); \ assemble_name ((FILE), (NAME)); \ fprintf ((FILE), ",%u,%u\n", (SIZE), MAX ((ALIGN) / BITS_PER_UNIT, 4)); \ } while (0) /* This says how to output assembler code to declare an uninitialized internal linkage data object. Under SVR4, the linker seems to want the alignment of data objects to depend on their types. We do exactly that here. [This macro overrides the one in svr4.h because the amix assembler has a minimum default alignment of 4, and will not accept any explicit alignment smaller than this. -fnf] */ #undef ASM_OUTPUT_ALIGNED_LOCAL #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ do { \ fprintf ((FILE), "\t%s\t%s,%u,%u\n", \ BSS_ASM_OP, (NAME), (SIZE), MAX ((ALIGN) / BITS_PER_UNIT, 4)); \ } while (0) /* This definition of ASM_OUTPUT_ASCII is the same as the one in m68k/sgs.h, which has been overridden by the one in svr4.h. However, we can't use the one in svr4.h because the amix assembler croaks on some of the strings that it emits (such as .string "\"%s\"\n"). */ #undef ASM_OUTPUT_ASCII #define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ { \ register int sp = 0, lp = 0, ch; \ fprintf ((FILE), "\t%s ", BYTE_ASM_OP); \ do { \ ch = (PTR)[sp]; \ if (ch > ' ' && ! (ch & 0x80) && ch != '\\') \ { \ fprintf ((FILE), "'%c", ch); \ } \ else \ { \ fprintf ((FILE), "0x%x", ch); \ } \ if (++sp < (LEN)) \ { \ if ((sp % 10) == 0) \ { \ fprintf ((FILE), "\n\t%s ", BYTE_ASM_OP); \ } \ else \ { \ putc (',', (FILE)); \ } \ } \ } while (sp < (LEN)); \ putc ('\n', (FILE)); \ } /* The following should be unnecessary as a result of PIC_CASE_VECTOR_ADDRESS. But rhealey@aggregate.com says they are still needed. */ /* Override these for the sake of an assembler bug: the Amix assembler can't handle .LC0@GOT syntax. This pollutes the final table for shared librarys but what's a poor soul to do; sigh... RFH */ #undef ASM_GENERATE_INTERNAL_LABEL #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ if (flag_pic && !strcmp(PREFIX,"LC")) \ sprintf (LABEL, "*%s%%%d", PREFIX, NUM); \ else \ sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM) #undef ASM_OUTPUT_INTERNAL_LABEL #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ if (flag_pic && !strcmp(PREFIX,"LC")) \ asm_fprintf (FILE, "%s%%%d:\n", PREFIX, NUM); \ else \ asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM) gcc-2.5.8/config/m68k/apollo68.h100444 22011 13 15024 5453234640 14661 0ustar kenneruser/* Definitions of target machine for GNU compiler. Apollo 680X0 version. Copyright (C) 1989,1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/m68k.h" /* This symbol may be tested in other files for special Apollo handling */ #define TM_APOLLO /* See m68k.h. 7 means 68020 with 68881. */ #ifndef TARGET_DEFAULT #define TARGET_DEFAULT 7 #endif /* Target switches for the Apollo is the same as in m68k.h, except there is no Sun FPA. */ #undef TARGET_SWITCHES #define TARGET_SWITCHES \ { { "68020", 5}, \ { "c68020", 5}, \ { "68881", 2}, \ { "bitfield", 4}, \ { "68000", -5}, \ { "c68000", -5}, \ { "soft-float", -0102}, \ { "nobitfield", -4}, \ { "rtd", 8}, \ { "nortd", -8}, \ { "short", 040}, \ { "noshort", -040}, \ { "", TARGET_DEFAULT}} /* Define __HAVE_68881__ in preprocessor, according to the -m flags. This will control the use of inline 68881 insns in certain macros. Also inform the program which CPU this is for. */ #if TARGET_DEFAULT & 02 /* -m68881 is the default */ #define CPP_SPEC \ "%{!msoft-float:%{mfpa:-D__HAVE_FPA__ }%{!mfpa:-D__HAVE_68881__ }}\ %{!ansi:%{m68000:-Dmc68010 }%{mc68000:-Dmc68010 }%{!mc68000:%{!m68000:-Dmc68020 }}\ %{!ansi:-D_APOLLO_SOURCE}}" #else /* -msoft-float is the default */ #define CPP_SPEC \ "%{m68881:-D__HAVE_68881__ }%{mfpa:-D__HAVE_FPA__ }\ %{!ansi:%{m68000:-Dmc68010 }%{mc68000:-Dmc68010 }%{!mc68000:%{!m68000:-Dmc68020 }}\ %{!ansi:-D_APOLLO_SOURCE}}" #endif /* Names to predefine in the preprocessor for this target machine. */ /* These are the ones defined by Apollo, plus mc68000 for uniformity with GCC on other 68000 systems. */ #define CPP_PREDEFINES "-Dapollo -Daegis -Dunix -Asystem(unix) -Acpu(m68k) -Amachine(m68k)" /* cpp has to support a #sccs directive for the /usr/include files */ #define SCCS_DIRECTIVE /* Allow #ident but output nothing for it. */ #define IDENT_DIRECTIVE #define ASM_OUTPUT_IDENT(FILE, NAME) /* Allow dollarsigns in identifiers */ #define DOLLARS_IN_IDENTIFIERS 2 /* -m68000 requires special flags to the assembler. */ #define ASM_SPEC \ "%{m68000:-mc68010}%{mc68000:-mc68010}%{!mc68000:%{!m68000:-mc68020}}" /* STARTFILE_SPEC Note that includes knowledge of the default specs for gcc, ie. no args translates to the same effect as -m68881 */ #if TARGET_DEFAULT & 2 /* -m68881 is the default */ #define STARTFILE_SPEC \ "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}" #else /* -msoft-float is the default */ #define STARTFILE_SPEC \ "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}" #endif /* Specify library to handle `-a' basic block profiling. */ #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \ %{a:/usr/lib/bb_link.o} " /* Debugging is not supported yet */ #undef DBX_DEBUGGING_INFO #undef SDB_DEBUGGING_INFO /* We have atexit(2). So C++ can use it for global destructors. */ #if 0 /* troy@cbme.unsw.edu.au says people are still using sr10.2 and it does not support atexit. */ #define HAVE_ATEXIT #endif /* Every structure or union's size must be a multiple of 2 bytes. */ #define STRUCTURE_SIZE_BOUNDARY 16 /* Boundary (in *bits*) on which stack pointer should be aligned. */ #undef STACK_BOUNDARY #define STACK_BOUNDARY 32 /* Functions which return large structures get the address to place the wanted value from a hidden parameter. */ #undef PCC_STATIC_STRUCT_RETURN #undef STRUCT_VALUE_REGNUM #define STRUCT_VALUE 0 #define STRUCT_VALUE_INCOMING 0 /* Specify how to pad function arguments. Arguments are not padded at all; the stack is kept aligned on long boundaries. */ #define FUNCTION_ARG_PADDING(mode, size) none /* The definition of this macro imposes a limit on the size of an aggregate object which can be treated as if it were a scalar object. */ #define MAX_FIXED_MODE_SIZE BITS_PER_WORD /* The definition of this macro implies that there are cases where a scalar value cannot be returned in registers. For Apollo, anything larger than one integer register is returned using the structure-value mechanism, i.e. objects of DFmode are returned that way. */ #define RETURN_IN_MEMORY(type) \ (TYPE_MODE (type) == BLKmode \ || GET_MODE_SIZE (TYPE_MODE (type)) > UNITS_PER_WORD) /* In order to link with Apollo libraries, we can't prefix external symbols with an underscore. */ #undef USER_LABEL_PREFIX /* Use a prefix for local labels, just to be on the save side. */ #undef LOCAL_LABEL_PREFIX #define LOCAL_LABEL_PREFIX "." /* Use a register prefix to avoid clashes with external symbols (classic example: `extern char PC;' in termcap). */ #undef REGISTER_PREFIX #define REGISTER_PREFIX "%" /* In the machine description we can't use %R, because it will not be seen by ASM_FPRINTF. (Isn't that a design bug?). */ #undef REGISTER_PREFIX_MD #define REGISTER_PREFIX_MD "%%" /* config/m68k.md has an explicit reference to the program counter, prefix this by the register prefix. */ #define ASM_RETURN_CASE_JUMP return "jmp %%pc@(2,%0:w)" /* Here are the new register names. */ #undef REGISTER_NAMES #ifndef SUPPORT_SUN_FPA #define REGISTER_NAMES \ {"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \ "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp", \ "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7" } #else /* SUPPORTED_SUN_FPA */ #define REGISTER_NAMES \ {"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \ "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp", \ "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7", \ "%fpa0", "%fpa1", "%fpa2", "%fpa3", "%fpa4", "%fpa5", "%fpa6", "%fpa7", \ "%fpa8", "%fpa9", "%fpa10", "%fpa11", "%fpa12", "%fpa13", "%fpa14", "%fpa15", \ "%fpa16", "%fpa17", "%fpa18", "%fpa19", "%fpa20", "%fpa21", "%fpa22", "%fpa23", \ "%fpa24", "%fpa25", "%fpa26", "%fpa27", "%fpa28", "%fpa29", "%fpa30", "%fpa31" } #endif /* defined SUPPORT_SUN_FPA */ gcc-2.5.8/config/m68k/crds.h100444 22011 13 53701 5453234644 14160 0ustar kenneruser/* Definitions of target machine for GNU compiler. Charles River Data Systems UNiverse/32 Written by Gary E. Miller bug reports to Gary_Edmunds_Miller@cup.portal.com Copyright (C) 1987, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define MOTOROLA /* Use Motorola syntax rather than "MIT" */ #define SGS /* Uses SGS assembler */ #define SGS_SWITCH_TABLES /* Different switch table handling */ #define CRDS /* Charles River Data Systems assembler */ #include "m68k/m68k.h" /* Without STRUCTURE_SIZE_BOUNDARY, we can't ensure that structures are aligned such that we can correctly extract bitfields from them. Someone should check whether the usual compiler on the crds machine provides the equivalent behavior of STRUCTURE_SIZE_BOUNDARY. */ #error This does not define STRUCTURE_SIZE_BOUNDARY /* See m68k.h. 0 means 680[01]0 with no 68881. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT 0 /* Don't try using XFmode. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 /* special flags to the unos assembler. */ #undef ASM_SPEC #define ASM_SPEC "-g" #undef LIB_SPEC #define LIB_SPEC "%{!p:%{!pg:-lunos}}%{p:-lc_p}%{pg:-lc_p}" #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{pg:gcrt0.o%s}%{!pg:%{p:mc68rt0.o%s}%{!p:c68rt0.o%s}}" /* CC1 spec */ #if 0 /* c.sac only used in _s_call_r() in libunos.a and malloc() in libmalloc.a */ /* so we do not need to bother ! */ #define CC1_SPEC "-fpcc-struct-return" #endif /* -O2 for MAX optimization */ #undef CC1_SPEC #define CC1_SPEC "%{O2:-fstrength-reduce}" /* cpp has to support a #sccs directive for the /usr/include files */ #define SCCS_DIRECTIVE /* Make output for SDB. */ /* #define SDB_DEBUGGING_INFO UNOS casm has no debugging :-( */ /* UNOS has vprintf() */ #define HAVE_VPRINTF /* UNOS need stack probe :-( */ #define HAVE_probe 1 #define gen_probe() gen_rtx(ASM_INPUT, VOIDmode, "tstb -2048(sp)\t;probe\n") /* use memcpy, memset instead of bcopy, etc. */ #define TARGET_MEM_FUNCTIONS /* Don't try to define `gcc_compiled.' since the assembler might not accept symbols with periods and GDB doesn't run on this machine anyway. */ #define ASM_IDENTIFY_GCC(FILE) /* Define __HAVE_68881__ in preprocessor if -m68881 is specified. This will control the use of inline 68881 insns in certain macros. */ #undef CPP_SPEC #define CPP_SPEC "%{m68881:-D__HAVE_68881__}" /* Names to predefine in the preprocessor for this target machine. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dmc68k -DM68000 -Dmc68000 -Dunos -Dunix -D__motorola__ -Asystem(unix) -Acpu(m68k) -Amachine(m68k)" /* Register in which address to store a structure value is passed to a function. */ /* unos uses ".comm c.sac" returns &c.sac in d0 */ /* make pointer to c.sac ? #undef STRUCT_VALUE_REGNUM #define STRUCT_VALUE gen_rtx(MEM, Pmode, gen_rtx( , , ) ) */ #define EXTRA_SECTIONS in_bss #define EXTRA_SECTION_FUNCTIONS \ void \ bss_section () \ { \ if (in_section != in_bss) \ { \ fprintf (asm_out_file, ".bss\n"); \ in_section = in_bss; \ } \ } /* Specify how to pad function arguments. Value should be `upward', `downward' or `none'. Same as the default, except no padding for large or variable-size args. */ #define FUNCTION_ARG_PADDING(MODE, TYPE) \ (((MODE) == BLKmode \ ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ && int_size_in_bytes (TYPE) < PARM_BOUNDARY / BITS_PER_UNIT) \ : GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY) \ ? downward : none) /* Override part of the obstack macros. */ #define __PTR_TO_INT(P) ((int)(P)) #define __INT_TO_PTR(P) ((char *)(P)) /* Override parts of m68k.h to fit the CRuDS assembler. */ #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (68k, CRDS/UNOS)"); /* Specify extra dir to search for include files. */ #define SYSTEM_INCLUDE_DIR "/include" /* Control the assembler format that we output. */ /* Output at beginning of assembler file. */ #undef ASM_FILE_START #define ASM_FILE_START(FILE) \ fprintf (FILE, ";#NO_APP\n"); /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ #undef ASM_APP_ON #define ASM_APP_ON ";#APP\n" /* Output to assembler file text saying following lines no longer contain unusual constructs. */ #undef ASM_APP_OFF #define ASM_APP_OFF ";#NO_APP\n" /* This is how to output an assembler line defining a `double' constant. */ #undef ASM_OUTPUT_DOUBLE #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { long l[2]; \ REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ fprintf (FILE, "\t.long 0x%x, 0x%x\n", l[0], l[1]); \ } while (0) /*unos has no .skip :-( */ #undef ASM_OUTPUT_SKIP #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t. = . + %u\n", (SIZE)); /* This says how to output an assembler line to define a local common symbol. */ /* should use bss_section instead of data_section but this makes casm die ? */ #undef ASM_OUTPUT_LOCAL #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ { data_section (); \ if ((SIZE) > 1) fprintf (FILE, "\t.even\n"); \ assemble_name ((FILE), (NAME)); \ fprintf ((FILE), ":\t. = . + %u\n", (ROUNDED));} /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #undef ASM_OUTPUT_REG_PUSH #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tmovel %s,-(sp)\n", reg_names[REGNO]) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #undef ASM_OUTPUT_REG_POP #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tmovel (sp)+,%s\n", reg_names[REGNO]) #undef ASM_OUTPUT_ASCII #define ASM_OUTPUT_ASCII(FILE, P , SIZE) \ { int i; \ fprintf ((FILE), "\t.ascii \""); \ for (i = 0; i < (SIZE); i++) \ { \ register int c = (P)[i]; \ if (i != 0 && (i / 200) * 200 == i) \ fprintf ((FILE), "\"\n\t.ascii \""); \ if (c >= ' ' && c < 0177) { \ if (c != '\"' && c != '\\') { \ putc (c, (FILE)); \ continue; \ } \ } \ /* brain dead asm doesn't understand char escapes */ \ fprintf ((FILE), "\"\n\t.byte\t%d\n\t.ascii \"", c); \ } \ fprintf ((FILE), "\"\n"); \ } /* Change all JBxx to Bxx. Also change all DBRA to DBF. Also change divs.l, etc., to divs, etc. But don't change divsl.l. */ #define ASM_OUTPUT_OPCODE(FILE, PTR) \ { if ((PTR)[0] == 'j' && (PTR)[1] == 'b') \ { ++(PTR); } \ else if ((PTR)[0] == 'd') \ { \ if (!strncmp ((PTR), "dbra", 4)) \ { fprintf ((FILE), "dbf"); (PTR) += 4; } \ else if (!strncmp ((PTR), "div", 3) && (PTR)[5] == ' ') \ { fprintf ((FILE), "div%c", (PTR)[3]); (PTR) += 6; } \ } \ } /* Print operand X (an rtx) in assembler syntax to file FILE. CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. For `%' followed by punctuation, CODE is the punctuation and X is null. On the 68000, we use several CODE characters: '.' for dot needed in Motorola-style opcode names. '-' for an operand pushing on the stack: sp@-, -(sp) or -(%sp) depending on the style of syntax. '+' for an operand pushing on the stack: sp@+, (sp)+ or (%sp)+ depending on the style of syntax. '@' for a reference to the top word on the stack: sp@, (sp) or (%sp) depending on the style of syntax. '#' for an immediate operand prefix (# in MIT and Motorola syntax but & in SGS syntax, $ in unos syntax). '!' for the fpcr register (used in some float-to-fixed conversions). 'b' for byte insn (no effect, on the Sun; this is for the ISI). 'd' to force memory addressing to be absolute, not relative. 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather than directly). Second part of 'y' below. 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), or print pair of registers as rx:ry. 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs CONST_DOUBLE's as SunFPA constant RAM registers if possible, so it should not be used except for the SunFPA. */ #undef PRINT_OPERAND_PUNCT_VALID_P #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ || (CODE) == '+' || (CODE) == '@' || (CODE) == '!') #undef PRINT_OPERAND #define PRINT_OPERAND(FILE, X, CODE) \ { int i; \ if (CODE == '.') ; \ else if (CODE == '#') fprintf (FILE, "$"); \ else if (CODE == '-') fprintf (FILE, "-(sp)"); \ else if (CODE == '+') fprintf (FILE, "(sp)+"); \ else if (CODE == '@') fprintf (FILE, "(sp)"); \ else if (CODE == '!') fprintf (FILE, "fpcr"); \ else if (CODE == '/') \ ; \ else if (GET_CODE (X) == REG) \ { if (REGNO (X) < 16 && (CODE == 'y' || CODE == 'x') && GET_MODE (X) == DFmode) \ fprintf (FILE, "%s:%s", reg_names[REGNO (X)], reg_names[REGNO (X)+1]); \ else \ fprintf (FILE, "%s", reg_names[REGNO (X)]); \ } \ else if (GET_CODE (X) == MEM) \ { \ output_address (XEXP (X, 0)); \ if (CODE == 'd' && ! TARGET_68020 \ && CONSTANT_ADDRESS_P (XEXP (X, 0))) \ /* fprintf (FILE, ".l") */; \ } \ else if ((CODE == 'y' || CODE == 'w') \ && GET_CODE(X) == CONST_DOUBLE \ && (i = standard_sun_fpa_constant_p (X))) \ fprintf (FILE, "%%%d", i & 0x1ff); \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \ { REAL_VALUE_TYPE r; long l; \ REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ if (CODE == 'f') \ ASM_OUTPUT_FLOAT_OPERAND (CODE, FILE, r); \ else \ { REAL_VALUE_TO_TARGET_SINGLE (r, l); \ fprintf (FILE, "$0x%x", l); } } \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == XFmode) \ { REAL_VALUE_TYPE r; \ REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ ASM_OUTPUT_LONG_DOUBLE_OPERAND (FILE, r); } \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != DImode) \ { REAL_VALUE_TYPE r; \ REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ ASM_OUTPUT_DOUBLE_OPERAND (FILE, r); } \ else { putc ('$', FILE); output_addr_const (FILE, X); }} /* Note that this contains a kludge that knows that the only reason we have an address (plus (label_ref...) (reg...)) is in the insn before a tablejump, and we know that m68k.md generates a label LInnn: on such an insn. */ #undef PRINT_OPERAND_ADDRESS #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ { register rtx reg1, reg2, breg, ireg; \ register rtx addr = ADDR; \ rtx offset; \ switch (GET_CODE (addr)) \ { \ case REG: \ fprintf (FILE, "(%s)", reg_names[REGNO (addr)]); \ break; \ case PRE_DEC: \ fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case POST_INC: \ fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case PLUS: \ reg1 = 0; reg2 = 0; \ ireg = 0; breg = 0; \ offset = 0; \ if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \ { \ offset = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \ { \ offset = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) != PLUS) ; \ else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == MULT) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == MULT) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == REG) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == REG) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \ || GET_CODE (addr) == SIGN_EXTEND) \ { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \ if (offset != 0) { if (addr != 0) abort (); addr = offset; } \ if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \ || GET_CODE (reg1) == MULT)) \ || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \ { breg = reg2; ireg = reg1; } \ else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \ { breg = reg1; ireg = reg2; } \ if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \ { int scale = 1; \ if (GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "L%d-LI%d-2(pc,%s.w", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (XEXP (ireg, 0))]); \ else \ fprintf (FILE, "L%d-LI%d-2(pc,%s.l", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (ireg)]); \ if (scale != 1) fprintf (FILE, ":%d", scale); \ putc (')', FILE); \ break; } \ if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF) \ { fprintf (FILE, "L%d-LI%d-2(pc,%s.l", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (breg)]); \ putc (')', FILE); \ break; } \ if (ireg != 0 || breg != 0) \ { int scale = 1; \ if (breg == 0) \ abort (); \ if (addr && GET_CODE (addr) == LABEL_REF) abort (); \ if (addr != 0) \ output_addr_const (FILE, addr); \ fprintf (FILE, "(%s", reg_names[REGNO (breg)]); \ if (breg != 0 && ireg != 0) \ putc (',', FILE); \ if (ireg != 0 && GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]); \ else if (ireg != 0) \ fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]); \ if (scale != 1) fprintf (FILE, ":%d", scale); \ putc (')', FILE); \ break; \ } \ else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \ { fprintf (FILE, "L%d-LI%d-2(pc,%s.l)", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (reg1)]); \ break; } \ default: \ if (GET_CODE (addr) == CONST_INT \ && INTVAL (addr) < 0x8000 \ && INTVAL (addr) >= -0x8000) \ fprintf (FILE, "%d", INTVAL (addr)); \ else \ output_addr_const (FILE, addr); \ }} #define ASM_OUTPUT_SOURCE_FILENAME(FILE, FILENAME) \ do { fprintf (FILE, "\t; file\t"); \ output_quoted_string (FILE, FILENAME); \ fprintf (FILE, "\n"); \ } while (0) #define ASM_OUTPUT_SOURCE_LINE(FILE, LINENO) \ fprintf (FILE, "\t; ln\t%d\n", \ (sdb_begin_function_line \ ? last_linenum - sdb_begin_function_line : 1)) /* This macro generates the assembly code for function entry. FILE is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. Refer to the array `regs_ever_live' to determine which registers to save; `regs_ever_live[I]' is nonzero if register number I is ever used in the function. This macro is responsible for knowing which registers should not be saved even if used. */ /* Note that the order of the bit mask for fmovem is the opposite of the order for movem! */ #undef FUNCTION_PROLOGUE #define FUNCTION_PROLOGUE(FILE, SIZE) \ { register int regno; \ register int mask = 0; \ extern char call_used_regs[]; \ int fsize = ((SIZE) + 3) & -4; \ /* unos stack probe */ \ if ( fsize > 30000 ) { \ fprintf (FILE, "\tmovel sp,a0\n"); \ fprintf (FILE, "\taddl $-%d,a0\n", 2048 + fsize); \ fprintf (FILE, "\ttstb (a0)\n"); \ } else { \ fprintf (FILE, "\ttstb -%d(sp)\n", 2048 + fsize); \ } \ if (frame_pointer_needed) \ { if (TARGET_68020 || fsize < 0x8000) \ fprintf (FILE, "\tlink a6,$%d\n", -fsize); \ else \ fprintf (FILE, "\tlink a6,$0\n\tsubl $%d,sp\n", fsize); } \ for (regno = 24; regno < 56; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ fprintf(FILE, "\tfpmoved %s, sp@-\n", \ reg_names[regno]); \ for (regno = 16; regno < 24; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ mask |= 1 << (regno - 16); \ if ((mask & 0xff) != 0) \ fprintf (FILE, "\tfmovem $0x%x,-(sp)\n", mask & 0xff); \ mask = 0; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ mask |= 1 << (15 - regno); \ if (frame_pointer_needed) \ mask &= ~ (1 << (15-FRAME_POINTER_REGNUM)); \ if (exact_log2 (mask) >= 0) \ fprintf (FILE, "\tmovel %s,-(sp)\n", reg_names[15 - exact_log2 (mask)]); \ else if (mask) fprintf (FILE, "\tmovem $0x%x,-(sp)\n", mask); } /* Must put address in %a0 , not %d0 . -- LGM, 7/15/88 */ /* UNOS ?? */ #undef FUNCTION_PROFILER #define FUNCTION_PROFILER(FILE, LABEL_NO) \ fprintf (FILE, "\tmovl &LP%%%d,%%a0\n\tjsr mcount\n", (LABEL_NO)) /* This macro generates the assembly code for function exit, on machines that need it. If FUNCTION_EPILOGUE is not defined then individual return instructions are generated for each return statement. Args are same as for FUNCTION_PROLOGUE. The function epilogue should not depend on the current stack pointer! It should use the frame pointer only. This is mandatory because of alloca; we also take advantage of it to omit stack adjustments before returning. */ #undef FUNCTION_EPILOGUE #define FUNCTION_EPILOGUE(FILE, SIZE) \ { register int regno; \ register int mask, fmask; \ register int nregs; \ int offset, foffset, fpoffset; \ extern char call_used_regs[]; \ int fsize = ((SIZE) + 3) & -4; \ int big = 0; \ nregs = 0; fmask = 0; fpoffset = 0; \ for (regno = 24 ; regno < 56 ; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ nregs++; \ fpoffset = nregs*8; \ nregs = 0; \ for (regno = 16; regno < 24; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ { nregs++; fmask |= 1 << (23 - regno); } \ foffset = fpoffset + nregs * 12; \ nregs = 0; mask = 0; \ if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ { nregs++; mask |= 1 << regno; } \ offset = foffset + nregs * 4; \ if (offset + fsize >= 0x8000 \ && frame_pointer_needed \ && (mask || fmask || fpoffset)) \ { fprintf (FILE, "\tmovel $%d,a0\n", -fsize); \ fsize = 0, big = 1; } \ if (exact_log2 (mask) >= 0) { \ if (big) \ fprintf (FILE, "\tmovel -%d(a6,a0.l),%s\n", \ offset + fsize, reg_names[exact_log2 (mask)]); \ else if (! frame_pointer_needed) \ fprintf (FILE, "\tmovel (sp)+,%s\n", \ reg_names[exact_log2 (mask)]); \ else \ fprintf (FILE, "\tmovel -%d(a6),%s\n", \ offset + fsize, reg_names[exact_log2 (mask)]); } \ else if (mask) { \ if (big) \ fprintf (FILE, "\tmovem -%d(a6,a0.l),$0x%x\n", \ offset + fsize, mask); \ else if (! frame_pointer_needed) \ fprintf (FILE, "\tmovem (sp)+,$0x%x\n", mask); \ else \ fprintf (FILE, "\tmovem -%d(a6),$0x%x\n", \ offset + fsize, mask); } \ if (fmask) { \ if (big) \ fprintf (FILE, "\tfmovem -%d(a6,a0.l),$0x%x\n", \ foffset + fsize, fmask); \ else if (! frame_pointer_needed) \ fprintf (FILE, "\tfmovem (sp)+,$0x%x\n", fmask); \ else \ fprintf (FILE, "\tfmovem -%d(a6),$0x%x\n", \ foffset + fsize, fmask); } \ if (fpoffset != 0) \ for (regno = 55; regno >= 24; regno--) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) { \ if (big) \ fprintf(FILE, "\tfpmoved -%d(a6,a0.l), %s\n", \ fpoffset + fsize, reg_names[regno]); \ else if (! frame_pointer_needed) \ fprintf(FILE, "\tfpmoved (sp)+, %s\n", \ reg_names[regno]); \ else \ fprintf(FILE, "\tfpmoved -%d(a6), %s\n", \ fpoffset + fsize, reg_names[regno]); \ fpoffset -= 8; \ } \ if (frame_pointer_needed) \ fprintf (FILE, "\tunlk a6\n"); \ if (current_function_pops_args) \ fprintf (FILE, "\trtd $%d\n", current_function_pops_args); \ else fprintf (FILE, "\trts\n"); } gcc-2.5.8/config/m68k/ctix.h100444 22011 13 3316 5453234646 14153 0ustar kenneruser/* Definitions of target machine for GNU compiler. Convergent Technologies MiniFrame version, using GAS and binutils with COFF encapsulation. Written by Ronald Cole Because the MiniFrame's C compiler is so completely lobotomized, bootstrapping this is damn near impossible! Write to me for information on obtaining the binaries... bug reports to csusac!unify!rjc@ucdavis.edu Copyright (C) 1990 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/3b1g.h" /* Names to predefine in the preprocessor for this target machine. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dmc68000 -Dmc68k -Dunix -Dctix -Asystem(unix) -Acpu(m68k) -Amachine(m68k)" /* Where to look for robotussinized startfiles. */ #undef STANDARD_STARTFILE_PREFIX #define STANDARD_STARTFILE_PREFIX "/usr/local/lib/gnu/" /* Generate calls to the MiniFrame's library (for speed). */ #define DIVSI3_LIBCALL "ldiv" #define UDIVSI3_LIBCALL "uldiv" #define MODSI3_LIBCALL "lrem" #define UMODSI3_LIBCALL "ulrem" #define MULSI3_LIBCALL "lmul" #define UMULSI3_LIBCALL "ulmul" gcc-2.5.8/config/m68k/dpx2.h100444 22011 13 102670 5453234654 14123 0ustar kenneruser/* dpx2.h - Bull DPX/2 200 and 300 systems (m68k, SysVr3). Contributed by Frederic Pierresteguy. Bug reports to F.Pierresteguy@frcl.bull.fr. */ #ifndef USE_GAS #define MOTOROLA /* Use Motorola syntax rather than "MIT" */ #define SGS_NO_LI /* Suppress jump table label usage */ #define VERSADOS /* This is the name of the assembler we have */ #define USG #endif #include "m68k/m68k.h" #undef SELECT_RTX_SECTION #include "svr3.h" /* See m68k.h. 7 means 68020 with 68881. * We really have 68030 and 68882, * but this will get us going. */ #ifndef TARGET_DEFAULT #define TARGET_DEFAULT 7 #endif #define OBJECT_FORMAT_COFF #define NO_SYS_SIGLIST #ifdef CPP_PREDEFINES #undef CPP_PREDEFINES #endif /* * define all the things the compiler should */ #ifdef ncl_mr # define CPP_PREDEFINES "-Dunix -Dbull -DDPX2 -DSVR3 -Dmc68000 -Dmc68020 -Dncl_mr=1 -D_BULL_SOURCE -D_POSIX_SOURCE -D_XOPEN_SOURCE -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)" #else # ifdef ncl_el # define CPP_PREDEFINES "-Dunix -Dbull -DDPX2 -DSVR3 -Dmc68000 -Dmc68020 -Dncl_el-D_BULL_SOURCE -D_POSIX_SOURCE -D_XOPEN_SOURCE -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)" # else # define CPP_PREDEFINES "-Dunix -Dbull -DDPX2 -DSVR3 -Dmc68000 -Dmc68020 -D_BULL_SOURCE -D_POSIX_SOURCE -D_XOPEN_SOURCE -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)" # endif #endif #undef CPP_SPEC /* * you can't get a DPX/2 without a 68882 but allow it * to be ignored... */ # define __HAVE_68881__ 1 # define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__ }" #define HAVE_ATEXIT #undef DO_GLOBAL_CTORS_BODY /* don't use svr3.h version */ #undef DO_GLOBAL_DTORS_BODY #ifndef USE_GAS /* * handle the native MOTOROLA VERSAdos assembler. */ /* See m68k.h. 3 means 68020 with 68881 and no bitfiled * bitfield instructions do not seem to work a clean way. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT 3 #undef EXTRA_SECTIONS #undef EXTRA_SECTION_FUNCTIONS #undef READONLY_DATA_SECTION #define READONLY_DATA_SECTION data_section #undef SELECT_SECTION #undef SELECT_RTX_SECTION #define fini_section() while (0) #undef CTORS_SECTION_ASM_OP #define CTORS_SECTION_ASM_OP "\tsection 15" #undef DTORS_SECTION_ASM_OP #define DTORS_SECTION_ASM_OP "\tsection 15" #undef INIT_SECTION_ASM_OP #define BSS_SECTION_ASM_OP "\tsection 14" #undef TEXT_SECTION_ASM_OP #define TEXT_SECTION_ASM_OP "\tsection 10" #undef DATA_SECTION_ASM_OP #define DATA_SECTION_ASM_OP "\tsection 15" /* Don't try using XFmode. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 /* Define if you don't want extended real, but do want to use the software floating point emulator for REAL_ARITHMETIC and decimal <-> binary conversion. */ #define REAL_ARITHMETIC #undef ASM_OUTPUT_SOURCE_FILENAME #define ASM_OUTPUT_SOURCE_FILENAME(FILE, NA) \ do { fprintf ((FILE), "\t.file\t'%s'\n", (NA)); } while (0) /* Assembler pseudos to introduce constants of various size. */ #undef ASM_BYTE_OP #define ASM_BYTE_OP "\tdc.b" #undef ASM_LONG #define ASM_LONG "\tdc.l" /* * we don't seem to support any of: * .globl * .even * .align * .ascii */ #undef ASM_OUTPUT_SKIP #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\tdcb.b %u,0\n", (SIZE)) #undef GLOBAL_ASM_OP #define GLOBAL_ASM_OP "\txdef" #undef ASM_OUTPUT_ALIGN #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG) >= 1) \ fprintf (FILE, "\tds.w 0\n"); #define STRING_LIMIT (0) #undef ASM_APP_ON #define ASM_APP_ON "" #undef ASM_APP_OFF #define ASM_APP_OFF "" /* * dc.b 'hello, world!' * dc.b 10,0 * is how we have to output "hello, world!\n" */ #undef ASM_OUTPUT_ASCII #define ASM_OUTPUT_ASCII(asm_out_file, p, thissize) \ do { register int i, c, f=0, len=0; \ for (i = 0; i < thissize; i++) { \ c = p[i]; \ if (c == '\'' || c < ' ' || c > 127) { \ switch(f) { \ case 0: /* need to output dc.b etc */ \ fprintf(asm_out_file, "\tdc.b %d", c); \ f=1; \ break; \ case 1: \ fprintf(asm_out_file, ",%d", c); \ break; \ default: \ /* close a string */ \ fprintf(asm_out_file, "'\n\tdc.b %d", c); \ f=1; \ break; \ } \ } else { \ switch(f) { \ case 0: \ fprintf(asm_out_file, "\tdc.b '%c", c); \ f=2; \ break; \ case 2: \ if (len >= 79) { \ fprintf(asm_out_file, "'\n\tdc.b '%c", c); \ len = 0; } \ else \ fprintf(asm_out_file, "%c", c); \ break; \ default: \ len = 0; \ fprintf(asm_out_file, "\n\tdc.b '%c", c); \ f=2; \ break; \ } \ } \ len++; \ } \ if (f==2) \ putc('\'', asm_out_file); \ putc('\n', asm_out_file); } while (0) /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #undef ASM_OUTPUT_REG_PUSH #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tmove.l %s,-(sp)\n", reg_names[REGNO]) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #undef ASM_OUTPUT_REG_POP #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tmove.l (sp)+,%s\n", reg_names[REGNO]) #define PUT_SDB_FUNCTION_START(LINE) \ fprintf (asm_out_file, \ "\t.def\t.bf%s\t.val\t*%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \ SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM) #define PUT_SDB_FUNCTION_END(LINE) \ fprintf (asm_out_file, \ "\t.def\t.ef%s\t.val\t*%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \ SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM) #define PUT_SDB_BLOCK_START(LINE) \ fprintf (asm_out_file, \ "\t.def\t.bb%s\t.val\t*%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \ SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM) #define PUT_SDB_BLOCK_END(LINE) \ fprintf (asm_out_file, \ "\t.def\t.eb%s\t.val\t*%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \ SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM) #define PUT_SDB_EPILOGUE_END(NAME) /* Output type in decimal not in octal as done in sdbout.c */ #define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0%d%s", a, SDB_DELIM) #undef FUNCTION_PROLOGUE #define FUNCTION_PROLOGUE(FILE, SIZE) \ { \ register int regno; \ register int mask = 0; \ int num_saved_regs = 0, first = 1; \ extern char call_used_regs[]; \ int fsize = ((SIZE) + 3) & -4; \ \ \ if (frame_pointer_needed) \ { \ /* Adding negative number is faster on the 68040. */ \ if (fsize < 0x8000 && !TARGET_68040) \ { \ fprintf (FILE, "\tlink %s,#%d\n", \ reg_names[FRAME_POINTER_REGNUM], -fsize); \ } \ else if (TARGET_68020) \ { \ fprintf (FILE, "\tlink %s,#%d\n", \ reg_names[FRAME_POINTER_REGNUM], -fsize); \ } \ else \ { \ fprintf (FILE, "\tlink %s,#0\n\tadd.l #%d,sp\n", \ reg_names[FRAME_POINTER_REGNUM], -fsize); \ } \ } \ else if (fsize) \ { \ /* Adding negative number is faster on the 68040. */ \ if (fsize + 4 < 0x8000) \ { \ fprintf (FILE, "\tadd.w #%d,sp\n", - (fsize + 4)); \ } \ else \ { \ fprintf (FILE, "\tadd.l #%d,sp\n", - (fsize + 4)); \ } \ } \ for (regno = 23; regno >= 16; regno--) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ if (first) { \ fprintf (FILE, "\tfmovem.x %s", reg_names[regno]); \ first = 0; \ } \ else fprintf (FILE, "/%s", reg_names[regno]); \ if (!first) fprintf (FILE, ",-(sp)\n"); \ \ mask = 0; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ { \ mask |= 1 << (15 - regno); \ num_saved_regs++; \ } \ if (frame_pointer_needed) \ { \ mask &= ~ (1 << (15 - FRAME_POINTER_REGNUM)); \ num_saved_regs--; \ } \ \ \ if (num_saved_regs <= 2) \ { \ /* Store each separately in the same order moveml uses. \ Using two movel instructions instead of a single moveml \ is about 15% faster for the 68020 and 68030 at no expense \ in code size */ \ \ int i; \ \ /* Undo the work from above. */ \ for (i = 0; i< 16; i++) \ if (mask & (1 << i)) \ fprintf (FILE, "\tmove.l %s,-(sp)\n", reg_names[15 - i]); \ } \ else if (mask) \ { \ first = 1; \ for (regno = 0; regno < 16; regno++) \ if (mask & (1 << regno)) \ if (first) { \ fprintf (FILE, "\tmovem.l %s", reg_names[15 - regno]); \ first = 0; \ } \ else fprintf (FILE, "/%s", reg_names[15 - regno]); \ fprintf (FILE, ",-(sp)\n"); \ } \ if (flag_pic && current_function_uses_pic_offset_table) \ { \ fprintf (FILE, "\tmove.l #__GLOBAL_OFFSET_TABLE_, %s\n", \ reg_names[PIC_OFFSET_TABLE_REGNUM]); \ fprintf (FILE, "\tlea.l (pc,%s.l),%s\n", \ reg_names[PIC_OFFSET_TABLE_REGNUM], \ reg_names[PIC_OFFSET_TABLE_REGNUM]); \ } \ } #undef FUNCTION_EPILOGUE #define FUNCTION_EPILOGUE(FILE, SIZE) \ { \ register int regno; \ register int mask, fmask; \ register int nregs; \ int offset, foffset, fpoffset, first = 1; \ extern char call_used_regs[]; \ int fsize = ((SIZE) + 3) & -4; \ int big = 0; \ rtx insn = get_last_insn (); \ \ /* If the last insn was a BARRIER, we don't have to write any code. */ \ if (GET_CODE (insn) == NOTE) \ insn = prev_nonnote_insn (insn); \ if (insn && GET_CODE (insn) == BARRIER) \ { \ /* Output just a no-op so that debuggers don't get confused \ about which function the pc is in at this address. */ \ fprintf (FILE, "\tnop\n"); \ return; \ } \ \ nregs = 0; fmask = 0; fpoffset = 0; \ for (regno = 16; regno < 24; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ { \ nregs++; \ fmask |= 1 << (23 - regno); \ } \ foffset = fpoffset + nregs * 12; \ nregs = 0; mask = 0; \ if (frame_pointer_needed) \ regs_ever_live[FRAME_POINTER_REGNUM] = 0; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ { \ nregs++; \ mask |= 1 << regno; \ } \ offset = foffset + nregs * 4; \ if (offset + fsize >= 0x8000 \ && frame_pointer_needed \ && (mask || fmask || fpoffset)) \ { \ fprintf (FILE, "\tmove.l #%d,a0\n", -fsize); \ fsize = 0, big = 1; \ } \ if (nregs <= 2) \ { \ /* Restore each separately in the same order moveml does. \ Using two movel instructions instead of a single moveml \ is about 15% faster for the 68020 and 68030 at no expense \ in code size. */ \ \ int i; \ \ /* Undo the work from above. */ \ for (i = 0; i< 16; i++) \ if (mask & (1 << i)) \ { \ if (big) \ { \ fprintf (FILE, "\tmove.l -%d(%s,a0.l),%s\n", \ offset + fsize, \ reg_names[FRAME_POINTER_REGNUM], \ reg_names[i]); \ } \ else if (! frame_pointer_needed) \ { \ fprintf (FILE, "\tmove.l (sp)+,%s\n", \ reg_names[i]); \ } \ else \ { \ fprintf (FILE, "\tmove.l -%d(%s),%s\n", \ offset + fsize, \ reg_names[FRAME_POINTER_REGNUM], \ reg_names[i]); \ } \ offset = offset - 4; \ } \ } \ else if (mask) \ { \ first = 1; \ for (regno = 0; regno < 16; regno++) \ if (mask & (1 << regno)) \ if (first && big) { \ fprintf (FILE, "\tmovem.l -%d(%s,a0.l),%s", \ offset + fsize, \ reg_names[FRAME_POINTER_REGNUM], \ reg_names[regno]); \ first = 0; \ } \ else if (first && ! frame_pointer_needed) { \ fprintf (FILE, "\tmovem.l (sp)+,%s", \ offset + fsize, \ reg_names[FRAME_POINTER_REGNUM], \ reg_names[regno]); \ first = 0; \ } \ else if (first) { \ fprintf (FILE, "\tmovem.l -%d(%s),%s", \ offset + fsize, \ reg_names[FRAME_POINTER_REGNUM], \ reg_names[regno]); \ first = 0; \ } \ else \ fprintf (FILE, "/%s", reg_names[regno]); \ fprintf (FILE, "\n"); \ } \ if (fmask) \ { \ first = 1; \ for (regno = 16; regno < 24; regno++) \ if (fmask & (1 << (23 - regno))) \ if (first && big) { \ fprintf (FILE, "\tfmovem.x -%d(%s,a0.l),%s", \ foffset + fsize, \ reg_names[FRAME_POINTER_REGNUM], \ reg_names[regno]); \ first = 0; \ } \ else if (first && ! frame_pointer_needed) { \ fprintf (FILE, "\tfmovem.x (sp)+,%s", \ foffset + fsize, \ reg_names[FRAME_POINTER_REGNUM], \ reg_names[regno]); \ first = 0; \ } \ else if (first) { \ fprintf (FILE, "\tfmovem.x -%d(%s),%s", \ foffset + fsize, \ reg_names[FRAME_POINTER_REGNUM], \ reg_names[regno]); \ first = 0; \ } \ else fprintf (FILE, "/%s", reg_names[regno]); \ fprintf (FILE, "\n"); \ } \ if (frame_pointer_needed) \ fprintf (FILE, "\tunlk %s\n", \ reg_names[FRAME_POINTER_REGNUM]); \ else if (fsize) \ { \ if (fsize + 4 < 0x8000) \ { \ fprintf (FILE, "\tadd.w #%d,sp\n", fsize + 4); \ } \ else \ { \ fprintf (FILE, "\tadd.l #%d,sp\n", fsize + 4); \ } \ } \ if (current_function_pops_args) \ fprintf (FILE, "\trtd #%d\n", current_function_pops_args); \ else \ fprintf (FILE, "\trts\n"); \ } /* Translate Motorola opcodes such as `jbeq' into VERSAdos opcodes such as `beq'. Change `fbeq' to `fbseq', `fbne' to `fbsneq'. */ #undef ASM_OUTPUT_OPCODE #define ASM_OUTPUT_OPCODE(FILE, PTR) \ { if ((PTR)[0] == 'j' && (PTR)[1] == 'b') \ { ++(PTR); \ while (*(PTR) != ' ') \ { putc (*(PTR), (FILE)); ++(PTR); } \ } \ else if ((PTR)[0] == 'f') \ { \ if (!strncmp ((PTR), "fbeq", 4)) \ { fprintf ((FILE), "fbseq"); (PTR) += 4; } \ else if (!strncmp ((PTR), "fbne", 4)) \ { fprintf ((FILE), "fbsneq"); (PTR) += 4; } \ } \ else if ((PTR)[0] == 'b' && (PTR)[1] == 'f') \ { \ char *s; \ if ((s = (char*)strchr ((PTR), '{'))) \ while (*s != '}') { \ if (*s == 'b') \ /* hack, I replace it with R ie nothing */ \ *s = '0'; \ s++; } \ } \ } /* This is how to output a `long double' extended real constant. */ #undef ASM_OUTPUT_LONG_DOUBLE #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ do { long l[3]; \ REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ if (sizeof (int) == sizeof (long)) \ fprintf (FILE, "\tdc.l $%x,$%x,$%x\n", l[0], l[1], l[2]); \ else \ fprintf (FILE, "\tdc.l $%lx,$%lx,$%lx\n", l[0], l[1], l[2]); \ } while (0) #undef ASM_OUTPUT_DOUBLE #if 0 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { char dstr[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ fprintf (FILE, "\tdc.d %s\n", dstr); \ } while (0) #endif #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { long l[2]; \ REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ fprintf (FILE, "\tdc.l $%x,$%x\n", l[0], l[1]); \ } while (0) /* This is how to output an assembler line defining a `float' constant. */ #undef ASM_OUTPUT_FLOAT #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { long l; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ if (sizeof (int) == sizeof (long)) \ fprintf (FILE, "\tdc.l $%x\n", l); \ else \ fprintf (FILE, "\tdc.l $%lx\n", l); \ } while (0) /* This is how to output an assembler line defining an `int' constant. */ #undef ASM_OUTPUT_INT #define ASM_OUTPUT_INT(FILE,VALUE) \ ( fprintf (FILE, "\tdc.l "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* Likewise for `char' and `short' constants. */ #undef ASM_OUTPUT_SHORT #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "\tdc.w "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #undef ASM_OUTPUT_CHAR #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ( fprintf (FILE, "\tdc.b "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* This is how to output an assembler line for a numeric constant byte. */ #undef ASM_OUTPUT_BYTE #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf (FILE, "\tdc.b $%x\n", (VALUE)) /* This is how to output an element of a case-vector that is absolute. (The 68000 does not use such vectors, but we must define this macro anyway.) */ #undef ASM_OUTPUT_ADDR_VEC_ELT #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ asm_fprintf (FILE, "\tdc.l %LL%d\n", VALUE) /* This is how to output an element of a case-vector that is relative. */ #undef ASM_OUTPUT_ADDR_DIFF_ELT #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ asm_fprintf (FILE, "\tdc.w %LL%d-%LL%d\n", VALUE, REL) /* Currently, JUMP_TABLES_IN_TEXT_SECTION must be defined in order to keep switch tables in the text section. */ #define JUMP_TABLES_IN_TEXT_SECTION 1 /* Output a float value (represented as a C double) as an immediate operand. This macro is a 68k-specific macro. */ #undef ASM_OUTPUT_FLOAT_OPERAND #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ do { \ if (CODE == 'f') \ { \ char dstr[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \ asm_fprintf ((FILE), "%I%s", dstr); \ } \ else \ { \ long l; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ if (sizeof (int) == sizeof (long)) \ asm_fprintf ((FILE), "%I$%x", l); \ else \ asm_fprintf ((FILE), "%I$%lx", l); \ } \ } while (0) /* Output a double value (represented as a C double) as an immediate operand. This macro is a 68k-specific macro. */ #undef ASM_OUTPUT_DOUBLE_OPERAND #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ do { char dstr[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ asm_fprintf (FILE, "%I%s", dstr); \ } while (0) /* Note, long double immediate operands are not actually generated by m68k.md. */ #undef ASM_OUTPUT_LONG_DOUBLE_OPERAND #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \ do { char dstr[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ asm_fprintf (FILE, "%I%s", dstr); \ } while (0) #undef ASM_OUTPUT_COMMON #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fputs ("\t.comm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (ROUNDED))) #undef ASM_OUTPUT_LOCAL #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ do { \ int align = exact_log2 (ROUNDED); \ /*fprintf ((FILE), "\tsection 14\n"); */ \ data_section (); \ ASM_OUTPUT_ALIGN ((FILE), align) \ ASM_OUTPUT_LABEL ((FILE), (NAME)); \ fprintf ((FILE), "\tdcb.b %u,0\n", (ROUNDED)); \ /* fprintf ((FILE), "\tsection 10\n"); */ \ } while (0) #undef PRINT_OPERAND_ADDRESS #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ { register rtx reg1, reg2, breg, ireg; \ register rtx addr = ADDR; \ rtx offset; \ switch (GET_CODE (addr)) \ { \ case REG: \ fprintf (FILE, "(%s)", reg_names[REGNO (addr)]); \ break; \ case PRE_DEC: \ fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case POST_INC: \ fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case PLUS: \ reg1 = 0; reg2 = 0; \ ireg = 0; breg = 0; \ offset = 0; \ if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \ { \ offset = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \ { \ offset = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) != PLUS) ; \ else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == MULT) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == MULT) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == REG) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == REG) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \ || GET_CODE (addr) == SIGN_EXTEND) \ { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \ /* for OLD_INDEXING \ else if (GET_CODE (addr) == PLUS) \ { \ if (GET_CODE (XEXP (addr, 0)) == REG) \ { \ reg2 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == REG) \ { \ reg2 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ } \ */ \ if (offset != 0) { if (addr != 0) abort (); addr = offset; } \ if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \ || GET_CODE (reg1) == MULT)) \ || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \ { breg = reg2; ireg = reg1; } \ else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \ { breg = reg1; ireg = reg2; } \ if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \ { int scale = 1; \ if (GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "(.L%d,pc,%s.w", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (XEXP (ireg, 0))]); \ else \ fprintf (FILE, "(.L%d,pc,%s.l", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (ireg)]); \ if (scale != 1) fprintf (FILE, "*%d", scale); \ putc (')', FILE); \ break; } \ if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF \ && ! (flag_pic && breg == pic_offset_table_rtx)) \ { \ fprintf (FILE, "(.L%d,pc,%s.l", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (breg)]); \ putc (')', FILE); \ break; } \ if (ireg != 0 || breg != 0) \ { int scale = 1; \ if (breg == 0) \ abort (); \ putc ('(', FILE); \ if (addr != 0) \ { \ output_addr_const (FILE, addr); \ putc (',', FILE); \ } \ fprintf (FILE, "%s", reg_names[REGNO (breg)]); \ if (ireg != 0) \ putc (',', FILE); \ if (ireg != 0 && GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]); \ else if (ireg != 0) \ fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]); \ if (scale != 1) fprintf (FILE, "*%d", scale); \ putc (')', FILE); \ break; \ } \ else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \ { fprintf (FILE, "(.L%d,pc,%s.w)", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (reg1)]); \ break; } \ default: \ if (GET_CODE (addr) == CONST_INT \ && INTVAL (addr) < 0x8000 \ && INTVAL (addr) >= -0x8000) \ fprintf (FILE, "%d.w", INTVAL (addr)); \ else \ output_addr_const (FILE, addr); \ }} #endif /* ! use gas */ gcc-2.5.8/config/m68k/dpx2.ifile100444 22011 13 3350 5324070055 14705 0ustar kenneruser/* * dpx2.ifile - for collectless G++ on Bull DPX/2 * * Peter Schauer * * Install this file as $prefix/gcc-lib/dpx2/VERSION/gcc.ifile * and comment out the lines referring to COLLECT at the top * of Makefile before building GCC. * * This file has been tested with gcc-2.2.2 on a DPX/2 340 * running BOS 2.00.45, if it doesn't work for you, stick * with collect. * --sjg */ /* * Ifile to link with memory configured at 0. * BLOCK to an offset that leaves room for many headers ( the value * here allows for a file header, an outheader, and up to 11 section * headers on most systems. * BIND to an address that excludes page 0 from being mapped. The value * used for BLOCK should be or'd into this value. Here I'm setting BLOCK * to 0x200 and BIND to ( 0x100000 | value_used_for(BLOCK) ) * If you are using shared libraries, watch that you don't overlap the * address ranges assigned for shared libs. * * GROUP BIND to a location in the next segment. Here, the only value * that you should change (I think) is that within NEXT, which I've set * to my hardware segment size. You can always use a larger size, but not * a smaller one. */ SECTIONS { .text BIND(0x100200) BLOCK (0x200) : { /* plenty of room for headers */ *(.init) *(.text) _vfork = _fork; /* I got tired of editing peoples sloppy code */ *(.fini) } GROUP BIND( NEXT(0x100000) + (ADDR(.text) + (SIZEOF(.text)) % 0x1000)): { .data : { ___CTOR_LIST__ = . ; . += 4 ; /* leading NULL */ *(.ctor) . += 4 ; /* trailing NULL */ ___DTOR_LIST__ = . ; . += 4 ; /* leading NULL */ *(.dtor) . += 4 ; /* trailing NULL */ } .bss : { } } } gcc-2.5.8/config/m68k/dpx2cdbx.h100444 22011 13 1732 5425152152 14710 0ustar kenneruser/* Definitions for Bull dpx/2 200 and 300 with gas using dbx-in-coff encapsulation. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/dpx2g.h" /* Use STABS debugging information inside COFF. */ #undef SDB_DEBUGGING_INFO #ifndef DBX_DEBUGGING_INFO #define DBX_DEBUGGING_INFO #endif gcc-2.5.8/config/m68k/dpx2g.h100444 22011 13 3653 5436243644 14233 0ustar kenneruser/* * dpx2g.h - Bull DPX/2 200 and 300 systems (m68k, SysVr3) with gas */ #define USE_GAS #include "m68k/dpx2.h" #ifndef USE_COLLECT2 /* We use set vectors for the constructors/destructors. */ #undef ASM_OUTPUT_CONSTRUCTOR #undef ASM_OUTPUT_DESTRUCTOR /* Although the gas we use can create .ctor and .dtor sections from N_SETT stabs, it does not support section directives, so we need to have the loader define the lists. */ #define CTOR_LISTS_DEFINED_EXTERNALLY /* similar to default, but allows for the table defined by ld with gcc.ifile. nptrs is always 0. So we need to instead check that __DTOR_LIST__[1] != 0. The old check is left in so that the same macro can be used if and when a future version of gas does support section directives. */ #define DO_GLOBAL_DTORS_BODY {int nptrs = *(int *)__DTOR_LIST__; int i; \ if (nptrs == -1 || (__DTOR_LIST__[0] == 0 && __DTOR_LIST__[1] != 0)) \ for (nptrs = 0; __DTOR_LIST__[nptrs + 1] != 0; nptrs++); \ for (i = nptrs; i >= 1; i--) \ __DTOR_LIST__[i] (); } #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{!r:gcc.ifile%s}\ %{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}\ huge.o%s" #else /* !USE_COLLECT2 */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}\ huge.o%s" #endif /* !USE_COLLECT2 */ /* * we are using GAS */ #undef EXTRA_SECTION_FUNCTIONS #undef EXTRA_SECTIONS /* Gas understands dollars in labels. */ #undef NO_DOLLAR_IN_LABEL /* GAS does not understand .ident so don't output anything for #ident. */ #undef ASM_OUTPUT_IDENT #undef ASM_LONG #define ASM_LONG "\t.long" /* * put const's in the text section */ #define const_section() text_section() #define fini_section() while (0) #undef CTORS_SECTION_ASM_OP #define CTORS_SECTION_ASM_OP "\t.data" #undef DTORS_SECTION_ASM_OP #define DTORS_SECTION_ASM_OP "\t.data" #undef INIT_SECTION_ASM_OP /* end of dpx2g.h */ gcc-2.5.8/config/m68k/hp2bsd.h100444 22011 13 5265 5453234657 14375 0ustar kenneruser/* Definitions of target machine for GNU compiler. HP 9000/200 68000 version. Copyright (C) 1987, 1991 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/m68k.h" /* See m68k.h. 0 means 68000 with no 68881. */ #define TARGET_DEFAULT 0 /* Don't try using XFmode. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 /* Define __HAVE_68881 in preprocessor only if -m68881 is specified. This will control the use of inline 68881 insns in certain macros. Also inform the program which CPU this is for. */ #define CPP_SPEC "%{m68881:-D__HAVE_68881__} \ %{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}" /* -m68020 requires special flags to the assembler. */ #define ASM_SPEC \ "%{m68020:-mc68020}%{mc68020:-mc68020}%{!mc68020:%{!m68020:-mc68010}}" /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Dmc68000 -Dmc68010 -Dhp200 -Dunix -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)" /* Link with libg.a when debugging, for dbx's sake. */ #define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} " /* Alignment of field after `int : 0' in a structure. */ #undef EMPTY_FIELD_BOUNDARY #define EMPTY_FIELD_BOUNDARY 16 /* Every structure or union's size must be a multiple of 2 bytes. */ #define STRUCTURE_SIZE_BOUNDARY 16 /* This is BSD, so it wants DBX format. */ #define DBX_DEBUGGING_INFO /* Define subroutines to call to handle multiply, divide, and remainder. These routines are built into the c-library on the hp200. XXX What other routines from the c-library could we use? The `*' prevents an underscore from being prepended by the compiler. */ #define DIVSI3_LIBCALL "*ldiv" #define UDIVSI3_LIBCALL "*uldiv" #define MODSI3_LIBCALL "*lrem" #define UMODSI3_LIBCALL "*ulrem" #define MULSI3_LIBCALL "*lmul" #define UMULSI3_LIBCALL "*ulmul" /* Don't default to pcc-struct-return, because gcc is the only compiler, and we want to retain compatibility with older gcc versions. */ #define DEFAULT_PCC_STRUCT_RETURN 0 gcc-2.5.8/config/m68k/hp310.h100444 22011 13 1704 5374450762 14037 0ustar kenneruser/* Definitions of target machine for GNU compiler. HP-UX 68010 version. */ /* See m68k.h. 0 means 68000 without 68881 and no bitfields. */ #define TARGET_DEFAULT 0 #include "m68k/hp320.h" /* Don't try using XFmode. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 #undef CPP_SPEC #undef ASM_SPEC /* HP does not support a 68020 without a 68881 or a 68010 with a 68881. However, -m68020 does not imply -m68881. You must specify both if you want both. */ #ifdef HPUX_ASM #define CPP_SPEC "-D__HPUX_ASM__ %{m68881: -D__HAVE_68881__}\ %{m68020: -Dmc68020}%{mc68020: -Dmc68020}\ %{!traditional:-D_INCLUDE__STDC__}" #define ASM_SPEC "%{!m68020:%{!mc68020:+X}}" #else /* not HPUX_ASM */ #define CPP_SPEC "%{m68881: -D__HAVE_68881__}\ %{m68020: -Dmc68020}%{mc68020: -Dmc68020}\ %{!traditional:-D_INCLUDE__STDC__}" #define ASM_SPEC \ "%{m68000:-mc68000}%{mc68000:-mc68000}%{!mc68000:%{!m68000:-mc68020}}" #endif /* not HPUX_ASM */ gcc-2.5.8/config/m68k/hp310g.h100444 22011 13 555 5322242646 14162 0ustar kenneruser/* Definitions of target machine for GNU compiler. HP-UX 68010 version. Use this file if GCC is supposed to work with the GNU assembler, GNU linker and GNU debugger using DBX debugging information. (In other words, much of HPUX has been cast aside.) */ /* This wants DBX format. */ #define DBX_DEBUGGING_INFO #define USE_GAS #include "m68k/hp310.h" gcc-2.5.8/config/m68k/hp320.h100444 22011 13 54534 5453234663 14067 0ustar kenneruser/* Definitions of target machine for GNU compiler. HP-UX 68000/68020 version. Copyright (C) 1987, 1988 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Define USE_GAS if GCC is supposed to work with the GNU assembler, GNU linker and GNU debugger using DBX debugging information. (In other words, much of HPUX has been cast aside.) Undefine USE_GAS if you want GCC to feed the HP assembler. */ /* #define USE_GAS */ /* Use hp320g.h if you want this. */ /* Control assembler-syntax conditionals in m68k.md. */ #ifndef USE_GAS #define MOTOROLA /* Use Motorola syntax rather than "MIT" */ #define SGS /* Uses SGS assembler */ #define SGS_CMP_ORDER /* Takes cmp operands in reverse order */ #define HPUX_ASM #if !defined (CROSS_COMPILE) && !defined (NO_BUGS) /* The assembler on HP 9k3xx machines running HPUX 8.0 doesn't translate floating point constants behind some operands. The workaround is to use hex constants. Reported by Thomas Nau (nau@medizin.uni-ulm.de). */ #define AS_BUG_FLOATING_CONSTANT /* The assembler on HP 9k3xx machines running HPUX 8.0 doesn't accept labels followed by a text, data, or other section directive. Reported by Thomas Nau (nau@medizin.uni-ulm.de). */ #define AS_BUG_TRAILING_LABEL #endif #endif /* not USE_GAS */ /* gcc.c should find libgcc.a itself rather than expecting linker to. */ #define LINK_LIBGCC_SPECIAL /* The arguments of -L must be a separate argv element. */ #define SPACE_AFTER_L_OPTION /* HP/UX doesn't have libg.a. */ #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" /* Be compatible with system stddef.h. */ #define SIZE_TYPE "unsigned int" /* Use atexit for static constructors/destructors, instead of defining our own exit function. */ #define HAVE_ATEXIT #include "m68k/m68k.h" /* See m68k.h. 7 means 68020 with 68881. */ #ifndef TARGET_DEFAULT #define TARGET_DEFAULT 7 #endif /* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified. This will control the use of inline 68881 insns in certain macros. */ #ifdef HPUX_ASM #define ASM_SPEC "%{m68000:+X}%{mc68000:+X}" #if TARGET_DEFAULT & 02 /* -m68881 is the default */ /* These definitions differ from those used for GAS by defining __HPUX_ASM__. This is needed because some programs, particularly GDB, need to know which assembler is being used so that the correct `asm' instructions can be used. */ #define CPP_SPEC \ "%{!msoft-float:-D__HAVE_68881__ }\ %{!ansi:%{!mc68000:%{!m68000:-Dmc68020}} -D_HPUX_SOURCE} -D__HPUX_ASM__" #else /* default is -msoft-float */ #define CPP_SPEC \ "%{m68881:-D__HAVE_68881__ }\ %{!ansi:%{!mc68000:%{!m68000:-Dmc68020}} -D_HPUX_SOURCE} -D__HPUX_ASM__" #endif /* default is -msoft-float */ #else /* not HPUX_ASM */ #if TARGET_DEFAULT & 02 /* -m68881 is the default */ #define CPP_SPEC \ "%{!msoft-float:-D__HAVE_68881__ }\ %{!ansi:%{!mc68000:%{!m68000:-Dmc68020}} -D_HPUX_SOURCE}" #else /* default is -msoft-float */ #define CPP_SPEC \ "%{m68881:-D__HAVE_68881__ }\ %{!ansi:%{!mc68000:%{!m68000:-Dmc68020}} -D_HPUX_SOURCE}" #endif /* default is -msoft-float */ /* -m68000 requires special flags to the assembler. */ #define ASM_SPEC \ "%{m68000:-mc68000}%{mc68000:-mc68000}%{!mc68000:%{!m68000:-mc68020}}" /* Tell GCC to put a space after -L when generating such options. */ #define SPACE_AFTER_L_OPTION #endif /* Not HPUX_ASM */ /* Names to predefine in the preprocessor for this target machine (for non-strict-ANSI programs only). */ /* These are the ones defined by HPUX cc, plus mc68000 for uniformity with GCC on other 68000 systems. */ #define CPP_PREDEFINES "-Dhp9000s200 -Dhp9000s300 -DPWB -Dhpux -Dunix -D__hp9000s300 -D__hp9000s200 -D__PWB -D__hpux -D__unix -D__motorola__ -Asystem(unix) -Asystem(hpux) -Acpu(m68k) -Amachine(m68k)" /* Every structure or union's size must be a multiple of 2 bytes. */ #define STRUCTURE_SIZE_BOUNDARY 16 /* hpux doesn't use static area for struct returns. */ #undef PCC_STATIC_STRUCT_RETURN /* Generate calls to memcpy, memcmp and memset. */ #define TARGET_MEM_FUNCTIONS #if 0 /* No longer correct in HPUX version 6.5. */ /* Function calls don't save any fp registers on hpux. */ #undef CALL_USED_REGISTERS #define CALL_USED_REGISTERS \ {1, 1, 0, 0, 0, 0, 0, 0, \ 1, 1, 0, 0, 0, 0, 0, 1, \ 1, 1, 1, 1, 1, 1, 1, 1} #endif /* 0 */ #ifdef HPUX_ASM /* Override parts of m68k.h to fit the HPUX assembler. */ #undef TARGET_VERSION #undef REGISTER_NAMES #undef FUNCTION_PROLOGUE #undef FUNCTION_EPILOGUE #undef ASM_OUTPUT_REG_PUSH #undef ASM_OUTPUT_REG_POP #undef ASM_FILE_START #undef ASM_APP_ON #undef ASM_APP_OFF #undef TEXT_SECTION_ASM_OP #undef DATA_SECTION_ASM_OP #undef ASM_OUTPUT_DOUBLE #undef ASM_OUTPUT_FLOAT #undef ASM_OUTPUT_INT #undef ASM_OUTPUT_SHORT #undef ASM_OUTPUT_CHAR #undef ASM_OUTPUT_BYTE #undef ASM_OUTPUT_ADDR_VEC_ELT #undef ASM_OUTPUT_ADDR_DIFF_ELT #undef ASM_OUTPUT_ALIGN #undef ASM_OUTPUT_SKIP #undef ASM_OUTPUT_COMMON #undef ASM_OUTPUT_LOCAL #undef ASM_FORMAT_PRIVATE_NAME #undef PRINT_OPERAND #undef PRINT_OPERAND_ADDRESS #undef FUNCTION_PROFILER #undef ASM_OUTPUT_INTERNAL_LABEL #undef GLOBAL_ASM_OP #define TARGET_VERSION fprintf (stderr, " (68k, SGS/hpux syntax)"); #define REGISTER_NAMES \ {"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \ "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", \ "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7"} #define FUNCTION_PROLOGUE(FILE, SIZE) \ { register int regno; \ register int mask = 0; \ extern char call_used_regs[]; \ int fsize = (SIZE); \ if (frame_pointer_needed) \ { if (fsize < 0x8000) \ fprintf (FILE, "\tlink.w %%a6,&%d\n", -fsize); \ else if (TARGET_68020) \ fprintf (FILE, "\tlink.l %%a6,&%d\n", -fsize); \ else \ fprintf (FILE, "\tlink.w %%a6,&0\n\tsub.l &%d,%%sp\n", fsize); } \ for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ mask |= 1 << (regno - 16); \ if (mask != 0) \ fprintf (FILE, "\tfmovem &0x%x,-(%%sp)\n", mask & 0xff); \ mask = 0; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ mask |= 1 << (15 - regno); \ if (frame_pointer_needed) \ mask &= ~ (1 << (15-FRAME_POINTER_REGNUM)); \ if (exact_log2 (mask) >= 0) \ fprintf (FILE, "\tmov.l %s,-(%%sp)\n", reg_names[15 - exact_log2 (mask)]); \ else if (mask) fprintf (FILE, "\tmovm.l &0x%x,-(%%sp)\n", mask); } #define FUNCTION_PROFILER(FILE, LABEL_NO) \ fprintf (FILE, "\tmov.l &LP%d,%%a0\n\tjsr mcount\n", (LABEL_NO)); #define FUNCTION_EPILOGUE(FILE, SIZE) \ { register int regno; \ register int mask, fmask; \ register int nregs; \ int offset, foffset; \ extern char call_used_regs[]; \ int fsize = (SIZE); \ int big = 0; \ nregs = 0; fmask = 0; \ for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ { nregs++; fmask |= 1 << (23 - regno); } \ foffset = nregs * 12; \ nregs = 0; mask = 0; \ if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ { nregs++; mask |= 1 << regno; } \ offset = foffset + nregs * 4; \ if (offset + fsize >= 0x8000 && frame_pointer_needed) \ { fprintf (FILE, "\tmov.l &%d,%%a0\n", -fsize); \ fsize = 0, big = 1; } \ if (exact_log2 (mask) >= 0) { \ if (big) \ fprintf (FILE, "\tmov.l -%d(%%a6,%%a0.l),%s\n", \ offset + fsize, reg_names[exact_log2 (mask)]); \ else if (! frame_pointer_needed) \ fprintf (FILE, "\tmov.l (%%sp)+,%s\n", \ reg_names[exact_log2 (mask)]); \ else \ fprintf (FILE, "\tmov.l -%d(%%a6),%s\n", \ offset + fsize, reg_names[exact_log2 (mask)]); } \ else if (mask) { \ if (big) \ fprintf (FILE, "\tmovm.l -%d(%%a6,%%a0.l),&0x%x\n", \ offset + fsize, mask); \ else if (! frame_pointer_needed) \ fprintf (FILE, "\tmovm.l (%%sp)+,&0x%x\n", mask); \ else \ fprintf (FILE, "\tmovm.l -%d(%%a6),&0x%x\n", \ offset + fsize, mask); } \ if (fmask) { \ if (big) \ fprintf (FILE, "\tfmovem -%d(%%a6,%%a0.l),&0x%x\n", \ foffset + fsize, fmask); \ else if (! frame_pointer_needed) \ fprintf (FILE, "\tfmovem (%%sp)+,&0x%x\n", fmask); \ else \ fprintf (FILE, "\tfmovem -%d(%%a6),&0x%x\n", \ foffset + fsize, fmask); } \ if (frame_pointer_needed) \ fprintf (FILE, "\tunlk %%a6\n"); \ if (current_function_pops_args) \ fprintf (FILE, "\trtd &%d\n", current_function_pops_args); \ else fprintf (FILE, "\trts\n"); } /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tmov.l %s,-(%%sp)\n", reg_names[REGNO]) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tmov.l (%%sp)+,%s\n", reg_names[REGNO]) /* For HPUX versions before 6.5, define this macro as empty. */ #define ASM_FILE_START(FILE) \ if (TARGET_68020) \ { \ if (TARGET_68881) \ fprintf (FILE, "\tversion 3\n"); /* 68020 fp regs saved */ \ else \ fprintf (FILE, "\tversion 2\n"); /* 68020 no fp regs saved */ \ } \ else \ fprintf (FILE, "\tversion 1\n"); /* 68010 */ #define ASM_APP_ON "" #define ASM_APP_OFF "" #ifdef AS_BUG_TRAILING_LABEL #define TEXT_SECTION_ASM_OP "\tlalign\t1\ntext" #define DATA_SECTION_ASM_OP "\tlalign\t1\ndata" #else #define TEXT_SECTION_ASM_OP "text" #define DATA_SECTION_ASM_OP "data" #endif #define ASCII_DATA_ASM_OP "byte" /* This is the command to make the user-level label named NAME defined for reference from other files. */ #define GLOBAL_ASM_OP "global" /* This says how to output an assembler line to define a global common symbol. */ #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fputs ("\tcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (ROUNDED))) /* This says how to output an assembler line to define a local common symbol. */ #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( fputs ("\tlcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u,2\n", (ROUNDED))) /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12), \ sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO))) #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ do{ if (PREFIX[0] == 'L' && PREFIX[1] == 'I') \ fprintf(FILE, "\tset %s%d,.+2\n", PREFIX, NUM); \ else \ fprintf (FILE, "%s%d:\n", PREFIX, NUM); \ } while(0) #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \ do { char dstr[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ fprintf (FILE, "\tdouble 0f%s\n", dstr); \ } while (0) #define ASM_OUTPUT_FLOAT(FILE, VALUE) \ do { char dstr[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \ fprintf (FILE, "\tfloat 0f%s\n", dstr); \ } while (0) #undef ASM_OUTPUT_LONG_DOUBLE #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ do { long l[3]; \ REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ fprintf (FILE, "\tlong 0x%x,0x%x,0x%x\n", l[0], l[1], l[2]); \ } while (0) /* This is how to output an assembler line defining an `int' constant. */ #define ASM_OUTPUT_INT(FILE,VALUE) \ ( fprintf (FILE, "\tlong "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* Likewise for `char' and `short' constants. */ #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "\tshort "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ( fprintf (FILE, "\tbyte "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* This is how to output an assembler line for a numeric constant byte. */ #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf (FILE, "\tbyte 0x%x\n", (VALUE)) #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "\tlong L%d\n", VALUE) #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\tshort L%d-L%d\n", VALUE, REL) #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG) == 1) \ fprintf (FILE, "\tlalign 2\n"); \ else if ((LOG) != 0) \ abort (); #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\tspace %u\n", (SIZE)) #define ASM_OUTPUT_SOURCE_FILENAME(FILE, FILENAME) #define ASM_OUTPUT_SOURCE_LINE(FILE, LINENO) #ifdef AS_BUG_FLOATING_CONSTANT #define PRINT_OPERAND_FLOAT(CODE,FILE,VALUE,INT) \ do { REAL_VALUE_TO_TARGET_SINGLE (VALUE, INT); \ fprintf (FILE, "&0x%x", INT); } while (0) #else #define PRINT_OPERAND_FLOAT(CODE,FILE,VALUE,INT) \ do { if (CODE == 'f') \ { char dstr[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \ fprintf (FILE, "&0f%s", dstr); \ } \ else \ { \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, INT); \ fprintf (FILE, "&0x%x", INT); } } while (0) #endif /* AS_BUG_FLOATING_CONSTANT */ #define PRINT_OPERAND(FILE, X, CODE) \ { if (CODE == '.') fprintf (FILE, "."); \ else if (CODE == '#') fprintf (FILE, "&"); \ else if (CODE == '-') fprintf (FILE, "-(%%sp)"); \ else if (CODE == '+') fprintf (FILE, "(%%sp)+"); \ else if (CODE == '@') fprintf (FILE, "(%%sp)"); \ else if (CODE == '!') fprintf (FILE, "%%fpcr"); \ else if (CODE == '$') { if (TARGET_68040_ONLY) fprintf (FILE, "s"); } \ else if (CODE == '&') { if (TARGET_68040_ONLY) fprintf (FILE, "d"); } \ else if (CODE == '/') \ fprintf (FILE, "%%"); \ else if (GET_CODE (X) == REG) \ fprintf (FILE, "%s", reg_names[REGNO (X)]); \ else if (GET_CODE (X) == MEM) \ output_address (XEXP (X, 0)); \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \ { REAL_VALUE_TYPE r; long l; \ REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ PRINT_OPERAND_FLOAT (CODE, FILE, r, l); } \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode) \ { REAL_VALUE_TYPE r; char dstr[30]; \ REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ REAL_VALUE_TO_DECIMAL (r, "%.20g", dstr); \ fprintf (FILE, "&0f%s", dstr); } \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == XFmode) \ { REAL_VALUE_TYPE r; char dstr[30]; \ REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ REAL_VALUE_TO_DECIMAL (r, "%.20g", dstr); \ fprintf (FILE, "&0f%s", dstr); } \ else { putc ('&', FILE); output_addr_const (FILE, X); }} #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ { register rtx reg1, reg2, breg, ireg; \ register rtx addr = ADDR; \ rtx offset; \ switch (GET_CODE (addr)) \ { \ case REG: \ fprintf (FILE, "(%s)", reg_names[REGNO (addr)]); \ break; \ case PRE_DEC: \ fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case POST_INC: \ fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case PLUS: \ reg1 = 0; reg2 = 0; \ ireg = 0; breg = 0; \ offset = 0; \ if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \ { \ offset = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \ { \ offset = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) != PLUS) ; \ else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == MULT) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == MULT) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == REG) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == REG) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \ || GET_CODE (addr) == SIGN_EXTEND) \ { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \ /* for OLD_INDEXING \ else if (GET_CODE (addr) == PLUS) \ { \ if (GET_CODE (XEXP (addr, 0)) == REG) \ { \ reg2 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == REG) \ { \ reg2 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ } \ */ \ if (offset != 0) { if (addr != 0) abort (); addr = offset; } \ if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \ || GET_CODE (reg1) == MULT)) \ || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \ { breg = reg2; ireg = reg1; } \ else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \ { breg = reg1; ireg = reg2; } \ if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \ { int scale = 1; \ if (GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "L%d-LI%d(%%pc,%s.w", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (XEXP (ireg, 0))]); \ else \ fprintf (FILE, "L%d-LI%d(%%pc,%s.l", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (ireg)]); \ if (scale != 1) fprintf (FILE, "*%d", scale); \ putc (')', FILE); \ break; } \ if (ireg != 0 || breg != 0) \ { int scale = 1; \ if (breg == 0) \ abort (); \ if (addr != 0) \ output_addr_const (FILE, addr); \ fprintf (FILE, "(%s", reg_names[REGNO (breg)]); \ if (ireg != 0) \ putc (',', FILE); \ if (ireg != 0 && GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]); \ else if (ireg != 0) \ fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]); \ if (scale != 1) fprintf (FILE, "*%d", scale); \ putc (')', FILE); \ break; \ } \ else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \ { fprintf (FILE, "L%d-LI%d(%%pc,%s.w)", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (reg1)]); \ break; } \ default: \ if (GET_CODE (addr) == CONST_INT \ && INTVAL (addr) < 0x8000 \ && INTVAL (addr) >= -0x8000) \ fprintf (FILE, "%d.w", INTVAL (addr)); \ else \ output_addr_const (FILE, addr); \ }} #define ASM_OUTPUT_ASCII(f, p, size) \ { register int i; \ int inside; \ inside = FALSE; \ for (i = 0; i < (size); i++) { \ if (i % 8 == 0) { \ if (i != 0) { \ if (inside) \ putc('"', (f)); \ putc('\n', (f)); \ inside = FALSE; \ } \ fprintf((f), "\t%s ", ASCII_DATA_ASM_OP); \ } \ if ((p)[i] < 32 || (p)[i] == '\\' || (p)[i] == '"' || (p)[i] == 127) { \ if (inside) { \ putc('"', (f)); \ inside = FALSE; \ } \ if (i % 8 != 0) \ putc(',', (f)); \ fprintf((f), "%d", (p)[i]); \ } else { \ if (!inside) { \ if (i % 8 != 0) \ putc(',', (f)); \ putc('"', (f)); \ inside = TRUE; \ } \ putc((p)[i], (f)); \ } \ } \ if (inside) \ putc('"', (f)); \ putc('\n', (f)); \ } /* Translate Motorola opcodes such as `jbeq' into SGS opcodes such as `beq.w'. Delete the `e' in `move...' and `fmove'. Change `ftst' to `ftest'. */ #define ASM_OUTPUT_OPCODE(FILE, PTR) \ { if ((PTR)[0] == 'j' && (PTR)[1] == 'b') \ { ++(PTR); \ while (*(PTR) != ' ') \ { putc (*(PTR), (FILE)); ++(PTR); } \ fprintf ((FILE), ".w"); } \ else if ((PTR)[0] == 'f') \ { \ if (!strncmp ((PTR), "fmove", 5)) \ { fprintf ((FILE), "fmov"); (PTR) += 5; } \ else if (!strncmp ((PTR), "ftst", 4)) \ { fprintf ((FILE), "ftest"); (PTR) += 4; } \ } \ else if ((PTR)[0] == 'm' && (PTR)[1] == 'o' \ && (PTR)[2] == 'v' && (PTR)[3] == 'e') \ { fprintf ((FILE), "mov"); (PTR) += 4; } \ } /* Prevent output of `gcc_compiled.:'. */ #define ASM_IDENTIFY_GCC(FILE) #else /* not HPUX_ASM */ #undef FUNCTION_PROFILER /* HP-UX needs the call to mcount before the link instruction. Copy the return address onto the stack before the call to fake it out. */ #define FUNCTION_PROFILER(FILE, LABEL_NO) \ fprintf (FILE, "\tmovel a6@(4),sp@-\n" \ "\tmovl #LP%d,a0\n\tjsr mcount\n" \ "\taddqw #4,sp\n", (LABEL_NO)); #endif /* not HPUX_ASM */ gcc-2.5.8/config/m68k/hp320g.h100444 22011 13 563 5322242610 14151 0ustar kenneruser/* Definitions of target machine for GNU compiler. HP-UX 68000/68020 version. Use this file if GCC is supposed to work with the GNU assembler, GNU linker and GNU debugger using DBX debugging information. (In other words, much of HPUX has been cast aside.) */ /* This wants DBX format. */ #define DBX_DEBUGGING_INFO #define USE_GAS #include "m68k/hp320.h" gcc-2.5.8/config/m68k/hp3bsd.h100444 22011 13 2455 5453234666 14374 0ustar kenneruser#include "m68k/m68k.h" /* See m68k.h. 7 means 68020 with 68881. */ #define TARGET_DEFAULT 7 /* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified. This will control the use of inline 68881 insns in certain macros. */ #define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__ -D__HAVE_FPU__}" /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Dmc68000 -Dmc68020 -Dhp300 -Dhp9000 -Dunix -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)" /* Link with libg.a when debugging, for dbx's sake. */ #define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} " /* Every structure or union's size must be a multiple of 2 bytes. */ #define STRUCTURE_SIZE_BOUNDARY 16 /* This is BSD, so it wants DBX format. */ #define DBX_DEBUGGING_INFO /* Do not break .stabs pseudos into continuations. */ #define DBX_CONTIN_LENGTH 0 /* This is the char to use for continuation (in case we need to turn continuation back on). */ #define DBX_CONTIN_CHAR '?' /* Don't use the `xsfoo;' construct in DBX output; this system doesn't support it. */ #define DBX_NO_XREFS /* Don't default to pcc-struct-return, because gcc is the only compiler, and we want to retain compatibility with older gcc versions. */ #define DEFAULT_PCC_STRUCT_RETURN 0 gcc-2.5.8/config/m68k/hp3bsd44.h100444 22011 13 2775 5453234671 14545 0ustar kenneruser#include #include "m68k/m68k.h" /* See m68k.h. 7 means 68020 with 68881. */ #define TARGET_DEFAULT 7 /* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified. This will control the use of inline 68881 insns in certain macros. */ #define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__ -D__HAVE_FPU__}" /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Dmc68000 -Dmc68020 -Dhp300 -Dhp9000 -Dunix -D__BSD_4_4__ -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)" /* No more libg.a */ #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" /* Make gcc agree with */ #define SIZE_TYPE "unsigned int" #define PTRDIFF_TYPE "int" #undef WCHAR_TYPE #define WCHAR_TYPE "short unsigned int" #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE 16 /* Every structure or union's size must be a multiple of 2 bytes. */ #define STRUCTURE_SIZE_BOUNDARY 16 /* This is BSD, so it wants DBX format. */ #define DBX_DEBUGGING_INFO /* Do not break .stabs pseudos into continuations. */ #define DBX_CONTIN_LENGTH 0 /* This is the char to use for continuation (in case we need to turn continuation back on). */ #define DBX_CONTIN_CHAR '?' /* Don't use the `xsfoo;' construct in DBX output; this system doesn't support it. */ #define DBX_NO_XREFS /* Don't default to pcc-struct-return, because gcc is the only compiler, and we want to retain compatibility with older gcc versions. */ #define DEFAULT_PCC_STRUCT_RETURN 0 gcc-2.5.8/config/m68k/hpux7.h100444 22011 13 242 5470710601 14217 0ustar kenneruser/* tm.h for m68k running HPUX version 7. */ /* fletcher@cs.utexas.edu says this is needed. */ #define NO_DOT_IN_LABEL #define NO_BUGS #include "m68k/hp320.h" gcc-2.5.8/config/m68k/isi-nfp.h100444 22011 13 321 5374450760 14521 0ustar kenneruser/* Define target machine as an ISI 68000/68020 with no 68881. */ #define TARGET_DEFAULT 5 #include "m68k/isi.h" /* Don't try using XFmode. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 gcc-2.5.8/config/m68k/isi.h100444 22011 13 6101 5473647772 13775 0ustar kenneruser/* Definitions of target machine for GNU compiler. ISI 68000/68020 version. Intended only for use with GAS, and not ISI's assembler, which is buggy Copyright (C) 1988 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/m68k.h" /* See m68k.h. 7 means 68020 with 68881. */ #ifndef TARGET_DEFAULT #define TARGET_DEFAULT 7 #endif #if TARGET_DEFAULT & 2 /* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified. This will control the use of inline 68881 insns in certain macros. */ #define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__}" /* If the 68881 is used, link must load libmc.a before libc.a. */ #define LIB_SPEC "%{!msoft-float:%{!p:%{!pg:-lmc}}%{p:-lmc_p}%{pg:-lmc_p}} \ %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}" #else /* Define __HAVE_68881__ in preprocessor if -m68881 is specified. This will control the use of inline 68881 insns in certain macros. */ #define CPP_SPEC "%{m68881:-D__HAVE_68881__}" /* If the 68881 is used, link must load libmc.a instead of libc.a */ #define LIB_SPEC "%{m68881:%{!p:%{!pg:-lmc}}%{p:-lmc_p}%{pg:-lmc_p}} \ %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}" #endif /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Dunix -Dmc68000 -Dis68k -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)" /* This is BSD, so it wants DBX format. */ #define DBX_DEBUGGING_INFO /* Override parts of m68k.h to fit the ISI 68k machine. */ #undef FUNCTION_VALUE #undef LIBCALL_VALUE #undef FUNCTION_VALUE_REGNO_P #undef NEEDS_UNTYPED_CALL #undef ASM_FILE_START /* Every structure or union's size must be a multiple of 2 bytes. */ #define STRUCTURE_SIZE_BOUNDARY 16 /* If TARGET_68881, return SF and DF values in f0 instead of d0. */ #define FUNCTION_VALUE(VALTYPE,FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE)) #define LIBCALL_VALUE(MODE) \ gen_rtx (REG, (MODE), ((TARGET_68881 && ((MODE) == SFmode || (MODE) == DFmode)) ? 16 : 0)) /* 1 if N is a possible register number for a function value. D0 may be used, and F0 as well if -m68881 is specified. */ #define FUNCTION_VALUE_REGNO_P(N) \ ((N) == 0 || (TARGET_68881 && (N) == 16)) /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for more than one register. */ #define NEEDS_UNTYPED_CALL 1 /* Also output something to cause the correct _doprnt to be loaded. */ #define ASM_FILE_START(FILE) fprintf (FILE, "#NO_APP\n%s\n", TARGET_68881 ? ".globl fltused" : "") gcc-2.5.8/config/m68k/lynx.h100444 22011 13 2345 5453234701 14167 0ustar kenneruser/* Definitions for Motorola 680X0 running LynxOS. Copyright (C) 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/m68k.h" #include "lynx.h" /* See m68k.h. 7 means 68020 with 68881. */ #ifndef TARGET_DEFAULT #define TARGET_DEFAULT 7 #endif /* Names to predefine in the preprocessor for this target machine. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dunix -Dmc68000 -DM68K -DLynx -DIBITS32 -Asystem(unix) -Asystem(lynx) -Acpu(m68k) -Amachine(m68k)" /* Every structure or union's size must be a multiple of 2 bytes. */ #define STRUCTURE_SIZE_BOUNDARY 16 gcc-2.5.8/config/m68k/m68k.c100444 22011 13 166076 5466017772 14044 0ustar kenneruser/* Subroutines for insn-output.c for Motorola 68000 family. Copyright (C) 1987, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Some output-actions in m68k.md need these. */ #include #include "config.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "output.h" #include "insn-attr.h" /* Needed for use_return_insn. */ #include "flags.h" #ifdef SUPPORT_SUN_FPA /* Index into this array by (register number >> 3) to find the smallest class which contains that register. */ enum reg_class regno_reg_class[] = { DATA_REGS, ADDR_REGS, FP_REGS, LO_FPA_REGS, LO_FPA_REGS, FPA_REGS, FPA_REGS }; #endif /* defined SUPPORT_SUN_FPA */ /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END, if SGS_SWITCH_TABLE. */ int switch_table_difference_label_flag; static rtx find_addr_reg (); rtx legitimize_pic_address (); /* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the function at any time during the compilation process. In the future we should try and eliminate the USE if we can easily determine that all PIC references were deleted from the current function. That would save an address register */ void finalize_pic () { if (flag_pic && current_function_uses_pic_offset_table) emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx)); } /* This function generates the assembly code for function entry. STREAM is a stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. Refer to the array `regs_ever_live' to determine which registers to save; `regs_ever_live[I]' is nonzero if register number I is ever used in the function. This function is responsible for knowing which registers should not be saved even if used. */ /* Note that the order of the bit mask for fmovem is the opposite of the order for movem! */ void output_function_prologue (stream, size) FILE *stream; int size; { register int regno; register int mask = 0; int num_saved_regs = 0; extern char call_used_regs[]; int fsize = (size + 3) & -4; if (frame_pointer_needed) { /* Adding negative number is faster on the 68040. */ if (fsize < 0x8000 && !TARGET_68040) { #ifdef MOTOROLA asm_fprintf (stream, "\tlink.w %s,%0I%d\n", reg_names[FRAME_POINTER_REGNUM], -fsize); #else asm_fprintf (stream, "\tlink %s,%0I%d\n", reg_names[FRAME_POINTER_REGNUM], -fsize); #endif } else if (TARGET_68020) { #ifdef MOTOROLA asm_fprintf (stream, "\tlink.l %s,%0I%d\n", reg_names[FRAME_POINTER_REGNUM], -fsize); #else asm_fprintf (stream, "\tlink %s,%0I%d\n", reg_names[FRAME_POINTER_REGNUM], -fsize); #endif } else { #ifdef MOTOROLA asm_fprintf (stream, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n", reg_names[FRAME_POINTER_REGNUM], -fsize); #else asm_fprintf (stream, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n", reg_names[FRAME_POINTER_REGNUM], -fsize); #endif } } else if (fsize) { /* Adding negative number is faster on the 68040. */ if (fsize + 4 < 0x8000) { #ifdef MOTOROLA asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", - (fsize + 4)); #else asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", - (fsize + 4)); #endif } else { #ifdef MOTOROLA asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", - (fsize + 4)); #else asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", - (fsize + 4)); #endif } } #ifdef SUPPORT_SUN_FPA for (regno = 24; regno < 56; regno++) if (regs_ever_live[regno] && ! call_used_regs[regno]) { #ifdef MOTOROLA asm_fprintf (stream, "\tfpmovd %s,-(%Rsp)\n", reg_names[regno]); #else asm_fprintf (stream, "\tfpmoved %s,%Rsp@-\n", reg_names[regno]); #endif } #endif for (regno = 16; regno < 24; regno++) if (regs_ever_live[regno] && ! call_used_regs[regno]) mask |= 1 << (regno - 16); if ((mask & 0xff) != 0) { #ifdef MOTOROLA asm_fprintf (stream, "\tfmovm %0I0x%x,-(%Rsp)\n", mask & 0xff); #else asm_fprintf (stream, "\tfmovem %0I0x%x,%Rsp@-\n", mask & 0xff); #endif } mask = 0; for (regno = 0; regno < 16; regno++) if (regs_ever_live[regno] && ! call_used_regs[regno]) { mask |= 1 << (15 - regno); num_saved_regs++; } if (frame_pointer_needed) { mask &= ~ (1 << (15 - FRAME_POINTER_REGNUM)); num_saved_regs--; } #if NEED_PROBE fprintf (stream, "\ttstl sp@(%d)\n", NEED_PROBE - num_saved_regs * 4); #endif if (num_saved_regs <= 2) { /* Store each separately in the same order moveml uses. Using two movel instructions instead of a single moveml is about 15% faster for the 68020 and 68030 at no expense in code size */ int i; /* Undo the work from above. */ for (i = 0; i< 16; i++) if (mask & (1 << i)) asm_fprintf (stream, #ifdef MOTOROLA "\t%Omove.l %s,-(%Rsp)\n", #else "\tmovel %s,%Rsp@-\n", #endif reg_names[15 - i]); } else if (mask) { #ifdef MOTOROLA asm_fprintf (stream, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask); #else asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@-\n", mask); #endif } if (flag_pic && current_function_uses_pic_offset_table) { #ifdef MOTOROLA asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n", reg_names[PIC_OFFSET_TABLE_REGNUM]); #else asm_fprintf (stream, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n", reg_names[PIC_OFFSET_TABLE_REGNUM]); asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n", reg_names[PIC_OFFSET_TABLE_REGNUM], reg_names[PIC_OFFSET_TABLE_REGNUM]); #endif } } /* Return true if this function's epilogue can be output as RTL. */ int use_return_insn () { int regno; if (!reload_completed || frame_pointer_needed || get_frame_size () != 0) return 0; /* Copied from output_function_epilogue (). We should probably create a separate layout routine to perform the common work. */ for (regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno++) if (regs_ever_live[regno] && ! call_used_regs[regno]) return 0; return 1; } /* This function generates the assembly code for function exit, on machines that need it. Args are same as for FUNCTION_PROLOGUE. The function epilogue should not depend on the current stack pointer! It should use the frame pointer only, if there is a frame pointer. This is mandatory because of alloca; we also take advantage of it to omit stack adjustments before returning. */ void output_function_epilogue (stream, size) FILE *stream; int size; { register int regno; register int mask, fmask; register int nregs; int offset, foffset, fpoffset; extern char call_used_regs[]; int fsize = (size + 3) & -4; int big = 0; rtx insn = get_last_insn (); /* If the last insn was a BARRIER, we don't have to write any code. */ if (GET_CODE (insn) == NOTE) insn = prev_nonnote_insn (insn); if (insn && GET_CODE (insn) == BARRIER) { /* Output just a no-op so that debuggers don't get confused about which function the pc is in at this address. */ asm_fprintf (stream, "\tnop\n"); return; } #ifdef FUNCTION_EXTRA_EPILOGUE FUNCTION_EXTRA_EPILOGUE (stream, size); #endif nregs = 0; fmask = 0; fpoffset = 0; #ifdef SUPPORT_SUN_FPA for (regno = 24 ; regno < 56 ; regno++) if (regs_ever_live[regno] && ! call_used_regs[regno]) nregs++; fpoffset = nregs * 8; #endif nregs = 0; for (regno = 16; regno < 24; regno++) if (regs_ever_live[regno] && ! call_used_regs[regno]) { nregs++; fmask |= 1 << (23 - regno); } foffset = fpoffset + nregs * 12; nregs = 0; mask = 0; if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; for (regno = 0; regno < 16; regno++) if (regs_ever_live[regno] && ! call_used_regs[regno]) { nregs++; mask |= 1 << regno; } offset = foffset + nregs * 4; if (offset + fsize >= 0x8000 && frame_pointer_needed && (mask || fmask || fpoffset)) { #ifdef MOTOROLA asm_fprintf (stream, "\t%Omove.l %0I%d,%Ra0\n", -fsize); #else asm_fprintf (stream, "\tmovel %0I%d,%Ra0\n", -fsize); #endif fsize = 0, big = 1; } if (nregs <= 2) { /* Restore each separately in the same order moveml does. Using two movel instructions instead of a single moveml is about 15% faster for the 68020 and 68030 at no expense in code size. */ int i; /* Undo the work from above. */ for (i = 0; i< 16; i++) if (mask & (1 << i)) { if (big) { #ifdef MOTOROLA asm_fprintf (stream, "\t%Omove.l -%d(%s,%Ra0.l),%s\n", offset + fsize, reg_names[FRAME_POINTER_REGNUM], reg_names[i]); #else asm_fprintf (stream, "\tmovel %s@(-%d,%Ra0:l),%s\n", reg_names[FRAME_POINTER_REGNUM], offset + fsize, reg_names[i]); #endif } else if (! frame_pointer_needed) { #ifdef MOTOROLA asm_fprintf (stream, "\t%Omove.l (%Rsp)+,%s\n", reg_names[i]); #else asm_fprintf (stream, "\tmovel %Rsp@+,%s\n", reg_names[i]); #endif } else { #ifdef MOTOROLA asm_fprintf (stream, "\t%Omove.l -%d(%s),%s\n", offset + fsize, reg_names[FRAME_POINTER_REGNUM], reg_names[i]); #else asm_fprintf (stream, "\tmovel %s@(-%d),%s\n", reg_names[FRAME_POINTER_REGNUM], offset + fsize, reg_names[i]); #endif } offset = offset - 4; } } else if (mask) { if (big) { #ifdef MOTOROLA asm_fprintf (stream, "\tmovm.l -%d(%s,%Ra0.l),%0I0x%x\n", offset + fsize, reg_names[FRAME_POINTER_REGNUM], mask); #else asm_fprintf (stream, "\tmoveml %s@(-%d,%Ra0:l),%0I0x%x\n", reg_names[FRAME_POINTER_REGNUM], offset + fsize, mask); #endif } else if (! frame_pointer_needed) { #ifdef MOTOROLA asm_fprintf (stream, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask); #else asm_fprintf (stream, "\tmoveml %Rsp@+,%0I0x%x\n", mask); #endif } else { #ifdef MOTOROLA asm_fprintf (stream, "\tmovm.l -%d(%s),%0I0x%x\n", offset + fsize, reg_names[FRAME_POINTER_REGNUM], mask); #else asm_fprintf (stream, "\tmoveml %s@(-%d),%0I0x%x\n", reg_names[FRAME_POINTER_REGNUM], offset + fsize, mask); #endif } } if (fmask) { if (big) { #ifdef MOTOROLA asm_fprintf (stream, "\tfmovm -%d(%s,%Ra0.l),%0I0x%x\n", foffset + fsize, reg_names[FRAME_POINTER_REGNUM], fmask); #else asm_fprintf (stream, "\tfmovem %s@(-%d,%Ra0:l),%0I0x%x\n", reg_names[FRAME_POINTER_REGNUM], foffset + fsize, fmask); #endif } else if (! frame_pointer_needed) { #ifdef MOTOROLA asm_fprintf (stream, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask); #else asm_fprintf (stream, "\tfmovem %Rsp@+,%0I0x%x\n", fmask); #endif } else { #ifdef MOTOROLA asm_fprintf (stream, "\tfmovm -%d(%s),%0I0x%x\n", foffset + fsize, reg_names[FRAME_POINTER_REGNUM], fmask); #else asm_fprintf (stream, "\tfmovem %s@(-%d),%0I0x%x\n", reg_names[FRAME_POINTER_REGNUM], foffset + fsize, fmask); #endif } } if (fpoffset != 0) for (regno = 55; regno >= 24; regno--) if (regs_ever_live[regno] && ! call_used_regs[regno]) { if (big) { #ifdef MOTOROLA asm_fprintf (stream, "\tfpmovd -%d(%s,%Ra0.l), %s\n", fpoffset + fsize, reg_names[FRAME_POINTER_REGNUM], reg_names[regno]); #else asm_fprintf (stream, "\tfpmoved %s@(-%d,%Ra0:l), %s\n", reg_names[FRAME_POINTER_REGNUM], fpoffset + fsize, reg_names[regno]); #endif } else if (! frame_pointer_needed) { #ifdef MOTOROLA asm_fprintf (stream, "\tfpmovd (%Rsp)+,%s\n", reg_names[regno]); #else asm_fprintf (stream, "\tfpmoved %Rsp@+, %s\n", reg_names[regno]); #endif } else { #ifdef MOTOROLA asm_fprintf (stream, "\tfpmovd -%d(%s), %s\n", fpoffset + fsize, reg_names[FRAME_POINTER_REGNUM], reg_names[regno]); #else asm_fprintf (stream, "\tfpmoved %s@(-%d), %s\n", reg_names[FRAME_POINTER_REGNUM], fpoffset + fsize, reg_names[regno]); #endif } fpoffset -= 8; } if (frame_pointer_needed) fprintf (stream, "\tunlk %s\n", reg_names[FRAME_POINTER_REGNUM]); else if (fsize) { if (fsize + 4 < 0x8000) { #ifdef MOTOROLA asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", fsize + 4); #else asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", fsize + 4); #endif } else { #ifdef MOTOROLA asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", fsize + 4); #else asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", fsize + 4); #endif } } if (current_function_pops_args) asm_fprintf (stream, "\trtd %0I%d\n", current_function_pops_args); else fprintf (stream, "\trts\n"); } /* Similar to general_operand, but exclude stack_pointer_rtx. */ int not_sp_operand (op, mode) register rtx op; enum machine_mode mode; { return op != stack_pointer_rtx && general_operand (op, mode); } /* Return TRUE if X is a valid comparison operator for the dbcc instruction. Note it rejects floating point comparison operators. (In the future we could use Fdbcc). It also rejects some comparisons when CC_NO_OVERFLOW is set. */ int valid_dbcc_comparison_p (x, mode) rtx x; enum machine_mode mode; { /* We could add support for these in the future */ if (cc_prev_status.flags & CC_IN_68881) return 0; switch (GET_CODE (x)) { case EQ: case NE: case GTU: case LTU: case GEU: case LEU: return 1; /* Reject some when CC_NO_OVERFLOW is set. This may be over conservative */ case GT: case LT: case GE: case LE: return ! (cc_prev_status.flags & CC_NO_OVERFLOW); default: return 0; } } /* Output a dbCC; jCC sequence. Note we do not handle the floating point version of this sequence (Fdbcc). We also do not handle alternative conditions when CC_NO_OVERFLOW is set. It is assumed that valid_dbcc_comparison_p will kick those out before we get here. */ output_dbcc_and_branch (operands) rtx *operands; { switch (GET_CODE (operands[3])) { case EQ: #ifdef MOTOROLA output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands); #else output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands); #endif break; case NE: #ifdef MOTOROLA output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands); #else output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands); #endif break; case GT: #ifdef MOTOROLA output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands); #else output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands); #endif break; case GTU: #ifdef MOTOROLA output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands); #else output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands); #endif break; case LT: #ifdef MOTOROLA output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands); #else output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands); #endif break; case LTU: #ifdef MOTOROLA output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands); #else output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands); #endif break; case GE: #ifdef MOTOROLA output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands); #else output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands); #endif break; case GEU: #ifdef MOTOROLA output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands); #else output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands); #endif break; case LE: #ifdef MOTOROLA output_asm_insn ("dble %0,%l1\n\tjble %l2", operands); #else output_asm_insn ("dble %0,%l1\n\tjle %l2", operands); #endif break; case LEU: #ifdef MOTOROLA output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands); #else output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands); #endif break; default: abort (); } /* If the decrement is to be done in SImode, then we have to compensate for the fact that dbcc decrements in HImode. */ switch (GET_MODE (operands[0])) { case SImode: #ifdef MOTOROLA output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands); #else output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands); #endif break; case HImode: break; default: abort (); } } char * output_btst (operands, countop, dataop, insn, signpos) rtx *operands; rtx countop, dataop; rtx insn; int signpos; { operands[0] = countop; operands[1] = dataop; if (GET_CODE (countop) == CONST_INT) { register int count = INTVAL (countop); /* If COUNT is bigger than size of storage unit in use, advance to the containing unit of same size. */ if (count > signpos) { int offset = (count & ~signpos) / 8; count = count & signpos; operands[1] = dataop = adj_offsettable_operand (dataop, offset); } if (count == signpos) cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N; else cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N; /* These three statements used to use next_insns_test_no... but it appears that this should do the same job. */ if (count == 31 && next_insn_tests_no_inequality (insn)) return "tst%.l %1"; if (count == 15 && next_insn_tests_no_inequality (insn)) return "tst%.w %1"; if (count == 7 && next_insn_tests_no_inequality (insn)) return "tst%.b %1"; cc_status.flags = CC_NOT_NEGATIVE; } return "btst %0,%1"; } /* Returns 1 if OP is either a symbol reference or a sum of a symbol reference and a constant. */ int symbolic_operand (op, mode) register rtx op; enum machine_mode mode; { switch (GET_CODE (op)) { case SYMBOL_REF: case LABEL_REF: return 1; case CONST: op = XEXP (op, 0); return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF || GET_CODE (XEXP (op, 0)) == LABEL_REF) && GET_CODE (XEXP (op, 1)) == CONST_INT); #if 0 /* Deleted, with corresponding change in m68k.h, so as to fit the specs. No CONST_DOUBLE is ever symbolic. */ case CONST_DOUBLE: return GET_MODE (op) == mode; #endif default: return 0; } } /* Legitimize PIC addresses. If the address is already position-independent, we return ORIG. Newly generated position-independent addresses go to REG. If we need more than one register, we lose. An address is legitimized by making an indirect reference through the Global Offset Table with the name of the symbol used as an offset. The assembler and linker are responsible for placing the address of the symbol in the GOT. The function prologue is responsible for initializing a5 to the starting address of the GOT. The assembler is also responsible for translating a symbol name into a constant displacement from the start of the GOT. A quick example may make things a little clearer: When not generating PIC code to store the value 12345 into _foo we would generate the following code: movel #12345, _foo When generating PIC two transformations are made. First, the compiler loads the address of foo into a register. So the first transformation makes: lea _foo, a0 movel #12345, a0@ The code in movsi will intercept the lea instruction and call this routine which will transform the instructions into: movel a5@(_foo:w), a0 movel #12345, a0@ That (in a nutshell) is how *all* symbol and label references are handled. */ rtx legitimize_pic_address (orig, mode, reg) rtx orig, reg; enum machine_mode mode; { rtx pic_ref = orig; /* First handle a simple SYMBOL_REF or LABEL_REF */ if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) { if (reg == 0) abort (); pic_ref = gen_rtx (MEM, Pmode, gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig)); current_function_uses_pic_offset_table = 1; RTX_UNCHANGING_P (pic_ref) = 1; emit_move_insn (reg, pic_ref); return reg; } else if (GET_CODE (orig) == CONST) { rtx base, offset; /* Make sure this is CONST has not already been legitimized */ if (GET_CODE (XEXP (orig, 0)) == PLUS && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) return orig; if (reg == 0) abort (); /* legitimize both operands of the PLUS */ if (GET_CODE (XEXP (orig, 0)) == PLUS) { base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, base == reg ? 0 : reg); } else abort (); if (GET_CODE (orig) == CONST_INT) return plus_constant_for_output (base, INTVAL (orig)); pic_ref = gen_rtx (PLUS, Pmode, base, orig); /* Likewise, should we set special REG_NOTEs here? */ } return pic_ref; } /* Return the best assembler insn template for moving operands[1] into operands[0] as a fullword. */ static char * singlemove_string (operands) rtx *operands; { #ifdef SUPPORT_SUN_FPA if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1])) return "fpmoves %1,%0"; #endif if (DATA_REG_P (operands[0]) && GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 128 && INTVAL (operands[1]) >= -128) { #if defined (MOTOROLA) && !defined (CRDS) return "moveq%.l %1,%0"; #else return "moveq %1,%0"; #endif } if (operands[1] != const0_rtx) return "move%.l %1,%0"; if (! ADDRESS_REG_P (operands[0])) return "clr%.l %0"; return "sub%.l %0,%0"; } /* Output assembler code to perform a doubleword move insn with operands OPERANDS. */ char * output_move_double (operands) rtx *operands; { enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1; rtx latehalf[2]; rtx middlehalf[2]; rtx xops[2]; rtx addreg0 = 0, addreg1 = 0; int dest_overlapped_low = 0; int size = GET_MODE_SIZE (GET_MODE (operands[0])); middlehalf[0] = 0; middlehalf[1] = 0; /* First classify both operands. */ if (REG_P (operands[0])) optype0 = REGOP; else if (offsettable_memref_p (operands[0])) optype0 = OFFSOP; else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) optype0 = POPOP; else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) optype0 = PUSHOP; else if (GET_CODE (operands[0]) == MEM) optype0 = MEMOP; else optype0 = RNDOP; if (REG_P (operands[1])) optype1 = REGOP; else if (CONSTANT_P (operands[1])) optype1 = CNSTOP; else if (offsettable_memref_p (operands[1])) optype1 = OFFSOP; else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) optype1 = POPOP; else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) optype1 = PUSHOP; else if (GET_CODE (operands[1]) == MEM) optype1 = MEMOP; else optype1 = RNDOP; /* Check for the cases that the operand constraints are not supposed to allow to happen. Abort if we get one, because generating code for these cases is painful. */ if (optype0 == RNDOP || optype1 == RNDOP) abort (); /* If one operand is decrementing and one is incrementing decrement the former register explicitly and change that operand into ordinary indexing. */ if (optype0 == PUSHOP && optype1 == POPOP) { operands[0] = XEXP (XEXP (operands[0], 0), 0); if (size == 12) output_asm_insn ("sub%.l %#12,%0", operands); else output_asm_insn ("subq%.l %#8,%0", operands); if (GET_MODE (operands[1]) == XFmode) operands[0] = gen_rtx (MEM, XFmode, operands[0]); else if (GET_MODE (operands[0]) == DFmode) operands[0] = gen_rtx (MEM, DFmode, operands[0]); else operands[0] = gen_rtx (MEM, DImode, operands[0]); optype0 = OFFSOP; } if (optype0 == POPOP && optype1 == PUSHOP) { operands[1] = XEXP (XEXP (operands[1], 0), 0); if (size == 12) output_asm_insn ("sub%.l %#12,%1", operands); else output_asm_insn ("subq%.l %#8,%1", operands); if (GET_MODE (operands[1]) == XFmode) operands[1] = gen_rtx (MEM, XFmode, operands[1]); else if (GET_MODE (operands[1]) == DFmode) operands[1] = gen_rtx (MEM, DFmode, operands[1]); else operands[1] = gen_rtx (MEM, DImode, operands[1]); optype1 = OFFSOP; } /* If an operand is an unoffsettable memory ref, find a register we can increment temporarily to make it refer to the second word. */ if (optype0 == MEMOP) addreg0 = find_addr_reg (XEXP (operands[0], 0)); if (optype1 == MEMOP) addreg1 = find_addr_reg (XEXP (operands[1], 0)); /* Ok, we can do one word at a time. Normally we do the low-numbered word first, but if either operand is autodecrementing then we do the high-numbered word first. In either case, set up in LATEHALF the operands to use for the high-numbered word and in some cases alter the operands in OPERANDS to be suitable for the low-numbered word. */ if (size == 12) { if (optype0 == REGOP) { latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2); middlehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); } else if (optype0 == OFFSOP) { middlehalf[0] = adj_offsettable_operand (operands[0], 4); latehalf[0] = adj_offsettable_operand (operands[0], size - 4); } else { middlehalf[0] = operands[0]; latehalf[0] = operands[0]; } if (optype1 == REGOP) { latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); middlehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); } else if (optype1 == OFFSOP) { middlehalf[1] = adj_offsettable_operand (operands[1], 4); latehalf[1] = adj_offsettable_operand (operands[1], size - 4); } else if (optype1 == CNSTOP) { if (GET_CODE (operands[1]) == CONST_DOUBLE) { REAL_VALUE_TYPE r; long l[3]; REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); operands[1] = GEN_INT (l[0]); middlehalf[1] = GEN_INT (l[1]); latehalf[1] = GEN_INT (l[2]); } else if (CONSTANT_P (operands[1])) { /* actually, no non-CONST_DOUBLE constant should ever appear here. */ abort (); if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0) latehalf[1] = constm1_rtx; else latehalf[1] = const0_rtx; } } else { middlehalf[1] = operands[1]; latehalf[1] = operands[1]; } } else /* size is not 12: */ { if (optype0 == REGOP) latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); else if (optype0 == OFFSOP) latehalf[0] = adj_offsettable_operand (operands[0], size - 4); else latehalf[0] = operands[0]; if (optype1 == REGOP) latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); else if (optype1 == OFFSOP) latehalf[1] = adj_offsettable_operand (operands[1], size - 4); else if (optype1 == CNSTOP) split_double (operands[1], &operands[1], &latehalf[1]); else latehalf[1] = operands[1]; } /* If insn is effectively movd N(sp),-(sp) then we will do the high word first. We should use the adjusted operand 1 (which is N+4(sp)) for the low word as well, to compensate for the first decrement of sp. */ if (optype0 == PUSHOP && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) operands[1] = middlehalf[1] = latehalf[1]; /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), if the upper part of reg N does not appear in the MEM, arrange to emit the move late-half first. Otherwise, compute the MEM address into the upper part of N and use that as a pointer to the memory operand. */ if (optype0 == REGOP && (optype1 == OFFSOP || optype1 == MEMOP)) { rtx testlow = gen_rtx (REG, SImode, REGNO (operands[0])); if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) { /* If both halves of dest are used in the src memory address, compute the address into latehalf of dest. Note that this can't happen if the dest is two data regs. */ compadr: xops[0] = latehalf[0]; xops[1] = XEXP (operands[1], 0); output_asm_insn ("lea %a1,%0", xops); if( GET_MODE (operands[1]) == XFmode ) { operands[1] = gen_rtx (MEM, XFmode, latehalf[0]); middlehalf[1] = adj_offsettable_operand (operands[1], size-8); latehalf[1] = adj_offsettable_operand (operands[1], size-4); } else { operands[1] = gen_rtx (MEM, DImode, latehalf[0]); latehalf[1] = adj_offsettable_operand (operands[1], size-4); } } else if (size == 12 && reg_overlap_mentioned_p (middlehalf[0], XEXP (operands[1], 0))) { /* Check for two regs used by both source and dest. Note that this can't happen if the dest is all data regs. It can happen if the dest is d6, d7, a0. But in that case, latehalf is an addr reg, so the code at compadr does ok. */ if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) goto compadr; /* JRV says this can't happen: */ if (addreg0 || addreg1) abort (); /* Only the middle reg conflicts; simply put it last. */ output_asm_insn (singlemove_string (operands), operands); output_asm_insn (singlemove_string (latehalf), latehalf); output_asm_insn (singlemove_string (middlehalf), middlehalf); return ""; } else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))) /* If the low half of dest is mentioned in the source memory address, the arrange to emit the move late half first. */ dest_overlapped_low = 1; } /* If one or both operands autodecrementing, do the two words, high-numbered first. */ /* Likewise, the first move would clobber the source of the second one, do them in the other order. This happens only for registers; such overlap can't happen in memory unless the user explicitly sets it up, and that is an undefined circumstance. */ if (optype0 == PUSHOP || optype1 == PUSHOP || (optype0 == REGOP && optype1 == REGOP && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) || REGNO (operands[0]) == REGNO (latehalf[1]))) || dest_overlapped_low) { /* Make any unoffsettable addresses point at high-numbered word. */ if (addreg0) { if (size == 12) output_asm_insn ("addql %#8,%0", &addreg0); else output_asm_insn ("addql %#4,%0", &addreg0); } if (addreg1) { if (size == 12) output_asm_insn ("addql %#8,%0", &addreg1); else output_asm_insn ("addql %#4,%0", &addreg1); } /* Do that word. */ output_asm_insn (singlemove_string (latehalf), latehalf); /* Undo the adds we just did. */ if (addreg0) output_asm_insn ("subql %#4,%0", &addreg0); if (addreg1) output_asm_insn ("subql %#4,%0", &addreg1); if (size == 12) { output_asm_insn (singlemove_string (middlehalf), middlehalf); if (addreg0) output_asm_insn ("subql %#4,%0", &addreg0); if (addreg1) output_asm_insn ("subql %#4,%0", &addreg1); } /* Do low-numbered word. */ return singlemove_string (operands); } /* Normal case: do the two words, low-numbered first. */ output_asm_insn (singlemove_string (operands), operands); /* Do the middle one of the three words for long double */ if (size == 12) { if (addreg0) output_asm_insn ("addql %#4,%0", &addreg0); if (addreg1) output_asm_insn ("addql %#4,%0", &addreg1); output_asm_insn (singlemove_string (middlehalf), middlehalf); } /* Make any unoffsettable addresses point at high-numbered word. */ if (addreg0) output_asm_insn ("addql %#4,%0", &addreg0); if (addreg1) output_asm_insn ("addql %#4,%0", &addreg1); /* Do that word. */ output_asm_insn (singlemove_string (latehalf), latehalf); /* Undo the adds we just did. */ if (addreg0) { if (size == 12) output_asm_insn ("subql %#8,%0", &addreg0); else output_asm_insn ("subql %#4,%0", &addreg0); } if (addreg1) { if (size == 12) output_asm_insn ("subql %#8,%0", &addreg1); else output_asm_insn ("subql %#4,%0", &addreg1); } return ""; } /* Return a REG that occurs in ADDR with coefficient 1. ADDR can be effectively incremented by incrementing REG. */ static rtx find_addr_reg (addr) rtx addr; { while (GET_CODE (addr) == PLUS) { if (GET_CODE (XEXP (addr, 0)) == REG) addr = XEXP (addr, 0); else if (GET_CODE (XEXP (addr, 1)) == REG) addr = XEXP (addr, 1); else if (CONSTANT_P (XEXP (addr, 0))) addr = XEXP (addr, 1); else if (CONSTANT_P (XEXP (addr, 1))) addr = XEXP (addr, 0); else abort (); } if (GET_CODE (addr) == REG) return addr; abort (); } /* Store in cc_status the expressions that the condition codes will describe after execution of an instruction whose pattern is EXP. Do not alter them if the instruction would not alter the cc's. */ /* On the 68000, all the insns to store in an address register fail to set the cc's. However, in some cases these instructions can make it possibly invalid to use the saved cc's. In those cases we clear out some or all of the saved cc's so they won't be used. */ notice_update_cc (exp, insn) rtx exp; rtx insn; { /* If the cc is being set from the fpa and the expression is not an explicit floating point test instruction (which has code to deal with this), reinit the CC. */ if (((cc_status.value1 && FPA_REG_P (cc_status.value1)) || (cc_status.value2 && FPA_REG_P (cc_status.value2))) && !(GET_CODE (exp) == PARALLEL && GET_CODE (XVECEXP (exp, 0, 0)) == SET && XEXP (XVECEXP (exp, 0, 0), 0) == cc0_rtx)) { CC_STATUS_INIT; } else if (GET_CODE (exp) == SET) { if (GET_CODE (SET_SRC (exp)) == CALL) { CC_STATUS_INIT; } else if (ADDRESS_REG_P (SET_DEST (exp))) { if (cc_status.value1 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)) cc_status.value1 = 0; if (cc_status.value2 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)) cc_status.value2 = 0; } else if (!FP_REG_P (SET_DEST (exp)) && SET_DEST (exp) != cc0_rtx && (FP_REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == FIX || GET_CODE (SET_SRC (exp)) == FLOAT_TRUNCATE || GET_CODE (SET_SRC (exp)) == FLOAT_EXTEND)) { CC_STATUS_INIT; } /* A pair of move insns doesn't produce a useful overall cc. */ else if (!FP_REG_P (SET_DEST (exp)) && !FP_REG_P (SET_SRC (exp)) && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4 && (GET_CODE (SET_SRC (exp)) == REG || GET_CODE (SET_SRC (exp)) == MEM || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE)) { CC_STATUS_INIT; } else if (GET_CODE (SET_SRC (exp)) == CALL) { CC_STATUS_INIT; } else if (XEXP (exp, 0) != pc_rtx) { cc_status.flags = 0; cc_status.value1 = XEXP (exp, 0); cc_status.value2 = XEXP (exp, 1); } } else if (GET_CODE (exp) == PARALLEL && GET_CODE (XVECEXP (exp, 0, 0)) == SET) { if (ADDRESS_REG_P (XEXP (XVECEXP (exp, 0, 0), 0))) CC_STATUS_INIT; else if (XEXP (XVECEXP (exp, 0, 0), 0) != pc_rtx) { cc_status.flags = 0; cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0); cc_status.value2 = XEXP (XVECEXP (exp, 0, 0), 1); } } else CC_STATUS_INIT; if (cc_status.value2 != 0 && ADDRESS_REG_P (cc_status.value2) && GET_MODE (cc_status.value2) == QImode) CC_STATUS_INIT; if (cc_status.value2 != 0 && !(cc_status.value1 && FPA_REG_P (cc_status.value1))) switch (GET_CODE (cc_status.value2)) { case PLUS: case MINUS: case MULT: case DIV: case UDIV: case MOD: case UMOD: case NEG: case ASHIFT: case LSHIFT: case ASHIFTRT: case LSHIFTRT: case ROTATE: case ROTATERT: if (GET_MODE (cc_status.value2) != VOIDmode) cc_status.flags |= CC_NO_OVERFLOW; break; case ZERO_EXTEND: /* (SET r1 (ZERO_EXTEND r2)) on this machine ends with a move insn moving r2 in r2's mode. Thus, the cc's are set for r2. This can set N bit spuriously. */ cc_status.flags |= CC_NOT_NEGATIVE; } if (cc_status.value1 && GET_CODE (cc_status.value1) == REG && cc_status.value2 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) cc_status.value2 = 0; if (((cc_status.value1 && FP_REG_P (cc_status.value1)) || (cc_status.value2 && FP_REG_P (cc_status.value2))) && !((cc_status.value1 && FPA_REG_P (cc_status.value1)) || (cc_status.value2 && FPA_REG_P (cc_status.value2)))) cc_status.flags = CC_IN_68881; } char * output_move_const_double (operands) rtx *operands; { #ifdef SUPPORT_SUN_FPA if (TARGET_FPA && FPA_REG_P (operands[0])) { int code = standard_sun_fpa_constant_p (operands[1]); if (code != 0) { static char buf[40]; sprintf (buf, "fpmove%%.d %%%%%d,%%0", code & 0x1ff); return buf; } return "fpmove%.d %1,%0"; } else #endif { int code = standard_68881_constant_p (operands[1]); if (code != 0) { static char buf[40]; sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff); return buf; } return "fmove%.d %1,%0"; } } char * output_move_const_single (operands) rtx *operands; { #ifdef SUPPORT_SUN_FPA if (TARGET_FPA) { int code = standard_sun_fpa_constant_p (operands[1]); if (code != 0) { static char buf[40]; sprintf (buf, "fpmove%%.s %%%%%d,%%0", code & 0x1ff); return buf; } return "fpmove%.s %1,%0"; } else #endif /* defined SUPPORT_SUN_FPA */ { int code = standard_68881_constant_p (operands[1]); if (code != 0) { static char buf[40]; sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff); return buf; } return "fmove%.s %f1,%0"; } } /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get from the "fmovecr" instruction. The value, anded with 0xff, gives the code to use in fmovecr to get the desired constant. */ /* This code has been fixed for cross-compilation. */ static int inited_68881_table = 0; char *strings_68881[7] = { "0.0", "1.0", "10.0", "100.0", "10000.0", "1e8", "1e16" }; int codes_68881[7] = { 0x0f, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37 }; REAL_VALUE_TYPE values_68881[7]; /* Set up values_68881 array by converting the decimal values strings_68881 to binary. */ void init_68881_table () { int i; REAL_VALUE_TYPE r; enum machine_mode mode; mode = DFmode; for (i = 0; i < 7; i++) { if (i == 6) mode = SFmode; r = REAL_VALUE_ATOF (strings_68881[i], mode); values_68881[i] = r; } inited_68881_table = 1; } int standard_68881_constant_p (x) rtx x; { REAL_VALUE_TYPE r; int i; enum machine_mode mode; /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */ if (TARGET_68040) return 0; #ifndef REAL_ARITHMETIC #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT if (! flag_pretend_float) return 0; #endif #endif if (! inited_68881_table) init_68881_table (); REAL_VALUE_FROM_CONST_DOUBLE (r, x); for (i = 0; i < 6; i++) { if (REAL_VALUES_EQUAL (r, values_68881[i])) return (codes_68881[i]); } if (GET_MODE (x) == SFmode) return 0; if (REAL_VALUES_EQUAL (r, values_68881[6])) return (codes_68881[6]); /* larger powers of ten in the constants ram are not used because they are not equal to a `double' C constant. */ return 0; } /* If X is a floating-point constant, return the logarithm of X base 2, or 0 if X is not a power of 2. */ int floating_exact_log2 (x) rtx x; { REAL_VALUE_TYPE r, r1; int i; #ifndef REAL_ARITHMETIC #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT if (! flag_pretend_float) return 0; #endif #endif REAL_VALUE_FROM_CONST_DOUBLE (r, x); if (REAL_VALUES_LESS (r, dconst0)) return 0; r1 = dconst1; i = 0; while (REAL_VALUES_LESS (r1, r)) { r1 = REAL_VALUE_LDEXP (dconst1, i); if (REAL_VALUES_EQUAL (r1, r)) return i; i = i + 1; } return 0; } #ifdef SUPPORT_SUN_FPA /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get from the Sun FPA's constant RAM. The value returned, anded with 0x1ff, gives the code to use in fpmove to get the desired constant. */ static int inited_FPA_table = 0; char *strings_FPA[38] = { /* small rationals */ "0.0", "1.0", "0.5", "-1.0", "2.0", "3.0", "4.0", "8.0", "0.25", "0.125", "10.0", "-0.5", /* Decimal equivalents of double precision values */ "2.718281828459045091", /* D_E */ "6.283185307179586477", /* 2 pi */ "3.141592653589793116", /* D_PI */ "1.570796326794896619", /* pi/2 */ "1.414213562373095145", /* D_SQRT2 */ "0.7071067811865475244", /* 1/sqrt(2) */ "-1.570796326794896619", /* -pi/2 */ "1.442695040888963387", /* D_LOG2ofE */ "3.321928024887362182", /* D_LOG2of10 */ "0.6931471805599452862", /* D_LOGEof2 */ "2.302585092994045901", /* D_LOGEof10 */ "0.3010299956639811980", /* D_LOG10of2 */ "0.4342944819032518167", /* D_LOG10ofE */ /* Decimal equivalents of single precision values */ "2.718281745910644531", /* S_E */ "6.283185307179586477", /* 2 pi */ "3.141592741012573242", /* S_PI */ "1.570796326794896619", /* pi/2 */ "1.414213538169860840", /* S_SQRT2 */ "0.7071067811865475244", /* 1/sqrt(2) */ "-1.570796326794896619", /* -pi/2 */ "1.442695021629333496", /* S_LOG2ofE */ "3.321928024291992188", /* S_LOG2of10 */ "0.6931471824645996094", /* S_LOGEof2 */ "2.302585124969482442", /* S_LOGEof10 */ "0.3010300099849700928", /* S_LOG10of2 */ "0.4342944920063018799", /* S_LOG10ofE */ }; int codes_FPA[38] = { /* small rationals */ 0x200, 0xe, 0xf, 0x10, 0x11, 0xb1, 0x12, 0x13, 0x15, 0x16, 0x17, 0x2e, /* double precision */ 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, /* single precision */ 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d }; REAL_VALUE_TYPE values_FPA[38]; /* This code has been fixed for cross-compilation. */ void init_FPA_table () { enum machine_mode mode; int i; REAL_VALUE_TYPE r; mode = DFmode; for (i = 0; i < 38; i++) { if (i == 25) mode = SFmode; r = REAL_VALUE_ATOF (strings_FPA[i], mode); values_FPA[i] = r; } inited_FPA_table = 1; } int standard_sun_fpa_constant_p (x) rtx x; { REAL_VALUE_TYPE r; int i; #ifndef REAL_ARITHMETIC #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT if (! flag_pretend_float) return 0; #endif #endif if (! inited_FPA_table) init_FPA_table (); REAL_VALUE_FROM_CONST_DOUBLE (r, x); for (i=0; i<12; i++) { if (REAL_VALUES_EQUAL (r, values_FPA[i])) return (codes_FPA[i]); } if (GET_MODE (x) == SFmode) { for (i=25; i<38; i++) { if (REAL_VALUES_EQUAL (r, values_FPA[i])) return (codes_FPA[i]); } } else { for (i=12; i<25; i++) { if (REAL_VALUES_EQUAL (r, values_FPA[i])) return (codes_FPA[i]); } } return 0x0; } #endif /* define SUPPORT_SUN_FPA */ /* A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand X. X is an RTL expression. CODE is a value that can be used to specify one of several ways of printing the operand. It is used when identical operands must be printed differently depending on the context. CODE comes from the `%' specification that was used to request printing of the operand. If the specification was just `%DIGIT' then CODE is 0; if the specification was `%LTR DIGIT' then CODE is the ASCII code for LTR. If X is a register, this macro should print the register's name. The names can be found in an array `reg_names' whose type is `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. When the machine description has a specification `%PUNCT' (a `%' followed by a punctuation character), this macro is called with a null pointer for X and the punctuation character for CODE. The m68k specific codes are: '.' for dot needed in Motorola-style opcode names. '-' for an operand pushing on the stack: sp@-, -(sp) or -(%sp) depending on the style of syntax. '+' for an operand pushing on the stack: sp@+, (sp)+ or (%sp)+ depending on the style of syntax. '@' for a reference to the top word on the stack: sp@, (sp) or (%sp) depending on the style of syntax. '#' for an immediate operand prefix (# in MIT and Motorola syntax but & in SGS syntax). '!' for the cc register (used in an `and to cc' insn). '$' for the letter `s' in an op code, but only on the 68040. '&' for the letter `d' in an op code, but only on the 68040. '/' for register prefix needed by longlong.h. 'b' for byte insn (no effect, on the Sun; this is for the ISI). 'd' to force memory addressing to be absolute, not relative. 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather than directly). Second part of 'y' below. 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), or print pair of registers as rx:ry. 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs CONST_DOUBLE's as SunFPA constant RAM registers if possible, so it should not be used except for the SunFPA. */ void print_operand (file, op, letter) FILE *file; /* file to write to */ rtx op; /* operand to print */ int letter; /* % or 0 */ { int i; if (letter == '.') { #ifdef MOTOROLA asm_fprintf (file, "."); #endif } else if (letter == '#') { asm_fprintf (file, "%0I"); } else if (letter == '-') { #ifdef MOTOROLA asm_fprintf (file, "-(%Rsp)"); #else asm_fprintf (file, "%Rsp@-"); #endif } else if (letter == '+') { #ifdef MOTOROLA asm_fprintf (file, "(%Rsp)+"); #else asm_fprintf (file, "%Rsp@+"); #endif } else if (letter == '@') { #ifdef MOTOROLA asm_fprintf (file, "(%Rsp)"); #else asm_fprintf (file, "%Rsp@"); #endif } else if (letter == '!') { asm_fprintf (file, "%Rfpcr"); } else if (letter == '$') { if (TARGET_68040_ONLY) { fprintf (file, "s"); } } else if (letter == '&') { if (TARGET_68040_ONLY) { fprintf (file, "d"); } } else if (letter == '/') { asm_fprintf (file, "%R"); } else if (GET_CODE (op) == REG) { if (REGNO (op) < 16 && (letter == 'y' || letter == 'x') && GET_MODE (op) == DFmode) { fprintf (file, "%s:%s", reg_names[REGNO (op)], reg_names[REGNO (op)+1]); } else { fprintf (file, "%s", reg_names[REGNO (op)]); } } else if (GET_CODE (op) == MEM) { output_address (XEXP (op, 0)); if (letter == 'd' && ! TARGET_68020 && CONSTANT_ADDRESS_P (XEXP (op, 0)) && !(GET_CODE (XEXP (op, 0)) == CONST_INT && INTVAL (XEXP (op, 0)) < 0x8000 && INTVAL (XEXP (op, 0)) >= -0x8000)) { fprintf (file, ":l"); } } #ifdef SUPPORT_SUN_FPA else if ((letter == 'y' || letter == 'w') && GET_CODE (op) == CONST_DOUBLE && (i = standard_sun_fpa_constant_p (op))) { fprintf (file, "%%%d", i & 0x1ff); } #endif else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode) { REAL_VALUE_TYPE r; REAL_VALUE_FROM_CONST_DOUBLE (r, op); ASM_OUTPUT_FLOAT_OPERAND (letter, file, r); } else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode) { REAL_VALUE_TYPE r; REAL_VALUE_FROM_CONST_DOUBLE (r, op); ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r); } else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode) { REAL_VALUE_TYPE r; REAL_VALUE_FROM_CONST_DOUBLE (r, op); ASM_OUTPUT_DOUBLE_OPERAND (file, r); } else { asm_fprintf (file, "%0I"); output_addr_const (file, op); } } /* A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand that is a memory reference whose address is ADDR. ADDR is an RTL expression. Note that this contains a kludge that knows that the only reason we have an address (plus (label_ref...) (reg...)) when not generating PIC code is in the insn before a tablejump, and we know that m68k.md generates a label LInnn: on such an insn. It is possible for PIC to generate a (plus (label_ref...) (reg...)) and we handle that just like we would a (plus (symbol_ref...) (reg...)). Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results we want. This difference can be accommodated by using an assembler define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END macro. See m68k/sgs.h for an example; for versions without the bug. They also do not like things like "pea 1.w", so we simple leave off the .w on small constants. This routine is responsible for distinguishing between -fpic and -fPIC style relocations in an address. When generating -fpic code the offset is output in word mode (eg movel a5@(_foo:w), a0). When generating -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */ void print_operand_address (file, addr) FILE *file; rtx addr; { register rtx reg1, reg2, breg, ireg; rtx offset; switch (GET_CODE (addr)) { case REG: #ifdef MOTOROLA fprintf (file, "(%s)", reg_names[REGNO (addr)]); #else fprintf (file, "%s@", reg_names[REGNO (addr)]); #endif break; case PRE_DEC: #ifdef MOTOROLA fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); #else fprintf (file, "%s@-", reg_names[REGNO (XEXP (addr, 0))]); #endif break; case POST_INC: #ifdef MOTOROLA fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); #else fprintf (file, "%s@+", reg_names[REGNO (XEXP (addr, 0))]); #endif break; case PLUS: reg1 = reg2 = ireg = breg = offset = 0; if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) { offset = XEXP (addr, 0); addr = XEXP (addr, 1); } else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) { offset = XEXP (addr, 1); addr = XEXP (addr, 0); } if (GET_CODE (addr) != PLUS) { ; } else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) { reg1 = XEXP (addr, 0); addr = XEXP (addr, 1); } else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) { reg1 = XEXP (addr, 1); addr = XEXP (addr, 0); } else if (GET_CODE (XEXP (addr, 0)) == MULT) { reg1 = XEXP (addr, 0); addr = XEXP (addr, 1); } else if (GET_CODE (XEXP (addr, 1)) == MULT) { reg1 = XEXP (addr, 1); addr = XEXP (addr, 0); } else if (GET_CODE (XEXP (addr, 0)) == REG) { reg1 = XEXP (addr, 0); addr = XEXP (addr, 1); } else if (GET_CODE (XEXP (addr, 1)) == REG) { reg1 = XEXP (addr, 1); addr = XEXP (addr, 0); } if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT || GET_CODE (addr) == SIGN_EXTEND) { if (reg1 == 0) { reg1 = addr; } else { reg2 = addr; } addr = 0; } #if 0 /* for OLD_INDEXING */ else if (GET_CODE (addr) == PLUS) { if (GET_CODE (XEXP (addr, 0)) == REG) { reg2 = XEXP (addr, 0); addr = XEXP (addr, 1); } else if (GET_CODE (XEXP (addr, 1)) == REG) { reg2 = XEXP (addr, 1); addr = XEXP (addr, 0); } } #endif if (offset != 0) { if (addr != 0) { abort (); } addr = offset; } if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND || GET_CODE (reg1) == MULT)) || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) { breg = reg2; ireg = reg1; } else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) { breg = reg1; ireg = reg2; } if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF && ! (flag_pic && ireg == pic_offset_table_rtx)) { int scale = 1; if (GET_CODE (ireg) == MULT) { scale = INTVAL (XEXP (ireg, 1)); ireg = XEXP (ireg, 0); } if (GET_CODE (ireg) == SIGN_EXTEND) { #ifdef MOTOROLA #ifdef SGS asm_fprintf (file, "%LLD%d(%Rpc,%s.w", CODE_LABEL_NUMBER (XEXP (addr, 0)), reg_names[REGNO (XEXP (ireg, 0))]); #else asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.w", CODE_LABEL_NUMBER (XEXP (addr, 0)), CODE_LABEL_NUMBER (XEXP (addr, 0)), reg_names[REGNO (XEXP (ireg, 0))]); #endif #else asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:w", CODE_LABEL_NUMBER (XEXP (addr, 0)), CODE_LABEL_NUMBER (XEXP (addr, 0)), reg_names[REGNO (XEXP (ireg, 0))]); #endif } else { #ifdef MOTOROLA #ifdef SGS asm_fprintf (file, "%LLD%d(%Rpc,%s.l", CODE_LABEL_NUMBER (XEXP (addr, 0)), reg_names[REGNO (ireg)]); #else asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.l", CODE_LABEL_NUMBER (XEXP (addr, 0)), CODE_LABEL_NUMBER (XEXP (addr, 0)), reg_names[REGNO (ireg)]); #endif #else asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:l", CODE_LABEL_NUMBER (XEXP (addr, 0)), CODE_LABEL_NUMBER (XEXP (addr, 0)), reg_names[REGNO (ireg)]); #endif } if (scale != 1) { #ifdef MOTOROLA fprintf (file, "*%d", scale); #else fprintf (file, ":%d", scale); #endif } putc (')', file); break; } if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF && ! (flag_pic && breg == pic_offset_table_rtx)) { #ifdef MOTOROLA #ifdef SGS asm_fprintf (file, "%LLD%d(%Rpc,%s.l", CODE_LABEL_NUMBER (XEXP (addr, 0)), reg_names[REGNO (breg)]); #else asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.l", CODE_LABEL_NUMBER (XEXP (addr, 0)), CODE_LABEL_NUMBER (XEXP (addr, 0)), reg_names[REGNO (breg)]); #endif #else asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:l", CODE_LABEL_NUMBER (XEXP (addr, 0)), CODE_LABEL_NUMBER (XEXP (addr, 0)), reg_names[REGNO (breg)]); #endif putc (')', file); break; } if (ireg != 0 || breg != 0) { int scale = 1; if (breg == 0) { abort (); } if (! flag_pic && addr && GET_CODE (addr) == LABEL_REF) { abort (); } #ifdef MOTOROLA if (addr != 0) { output_addr_const (file, addr); if (flag_pic && (breg == pic_offset_table_rtx)) fprintf (file, "@GOT"); } fprintf (file, "(%s", reg_names[REGNO (breg)]); if (ireg != 0) { putc (',', file); } #else fprintf (file, "%s@(", reg_names[REGNO (breg)]); if (addr != 0) { output_addr_const (file, addr); if ((flag_pic == 1) && (breg == pic_offset_table_rtx)) fprintf (file, ":w"); if ((flag_pic == 2) && (breg == pic_offset_table_rtx)) fprintf (file, ":l"); } if (addr != 0 && ireg != 0) { putc (',', file); } #endif if (ireg != 0 && GET_CODE (ireg) == MULT) { scale = INTVAL (XEXP (ireg, 1)); ireg = XEXP (ireg, 0); } if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) { #ifdef MOTOROLA fprintf (file, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]); #else fprintf (file, "%s:w", reg_names[REGNO (XEXP (ireg, 0))]); #endif } else if (ireg != 0) { #ifdef MOTOROLA fprintf (file, "%s.l", reg_names[REGNO (ireg)]); #else fprintf (file, "%s:l", reg_names[REGNO (ireg)]); #endif } if (scale != 1) { #ifdef MOTOROLA fprintf (file, "*%d", scale); #else fprintf (file, ":%d", scale); #endif } putc (')', file); break; } else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF && ! (flag_pic && reg1 == pic_offset_table_rtx)) { #ifdef MOTOROLA #ifdef SGS asm_fprintf (file, "%LLD%d(%Rpc,%s.l)", CODE_LABEL_NUMBER (XEXP (addr, 0)), reg_names[REGNO (reg1)]); #else asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.l)", CODE_LABEL_NUMBER (XEXP (addr, 0)), CODE_LABEL_NUMBER (XEXP (addr, 0)), reg_names[REGNO (reg1)]); #endif #else asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:l)", CODE_LABEL_NUMBER (XEXP (addr, 0)), CODE_LABEL_NUMBER (XEXP (addr, 0)), reg_names[REGNO (reg1)]); #endif break; } /* FALL-THROUGH (is this really what we want? */ default: if (GET_CODE (addr) == CONST_INT && INTVAL (addr) < 0x8000 && INTVAL (addr) >= -0x8000) { #ifdef MOTOROLA #ifdef SGS /* Many SGS assemblers croak on size specifiers for constants. */ fprintf (file, "%d", INTVAL (addr)); #else fprintf (file, "%d.w", INTVAL (addr)); #endif #else fprintf (file, "%d:w", INTVAL (addr)); #endif } else { output_addr_const (file, addr); } break; } } /* Check for cases where a clr insns can be omitted from code using strict_low_part sets. For example, the second clrl here is not needed: clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ... MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear insn we are checking for redundancy. TARGET is the register set by the clear insn. */ int strict_low_part_peephole_ok (mode, first_insn, target) enum machine_mode mode; rtx first_insn; rtx target; { rtx p; p = prev_nonnote_insn (first_insn); while (p) { /* If it isn't an insn, then give up. */ if (GET_CODE (p) != INSN) return 0; if (reg_set_p (target, p)) { rtx set = single_set (p); rtx dest; /* If it isn't an easy to recognize insn, then give up. */ if (! set) return 0; dest = SET_DEST (set); /* If this sets the entire target register to zero, then our first_insn is redundant. */ if (rtx_equal_p (dest, target) && SET_SRC (set) == const0_rtx) return 1; else if (GET_CODE (dest) == STRICT_LOW_PART && GET_CODE (XEXP (dest, 0)) == REG && REGNO (XEXP (dest, 0)) == REGNO (target) && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0))) <= GET_MODE_SIZE (mode))) /* This is a strict low part set which modifies less than we are using, so it is safe. */ ; else return 0; } p = prev_nonnote_insn (p); } return 0; } gcc-2.5.8/config/m68k/m68k.h100444 22011 13 214751 5466405122 14031 0ustar kenneruser/* Definitions of target machine for GNU compiler. Sun 68000/68020 version. Copyright (C) 1987, 1988, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Note that some other tm.h files include this one and then override many of the definitions that relate to assembler syntax. */ /* Names to predefine in the preprocessor for this target machine. */ /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */ /* Print subsidiary information on the compiler version in use. */ #ifdef MOTOROLA #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)"); #else #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)"); #endif /* Define SUPPORT_SUN_FPA to include support for generating code for the Sun Floating Point Accelerator, an optional product for Sun 3 machines. By default, it is not defined. Avoid defining it unless you need to output code for the Sun3+FPA architecture, as it has the effect of slowing down the register set operations in hard-reg-set.h (total number of registers will exceed number of bits in a long, if defined, causing the set operations to expand to loops). SUPPORT_SUN_FPA is typically defined in sun3.h. */ /* Run-time compilation parameters selecting different hardware subsets. */ extern int target_flags; /* Macros used in the machine description to test the flags. */ /* Compile for a 68020 (not a 68000 or 68010). */ #define TARGET_68020 (target_flags & 1) /* Compile 68881 insns for floating point (not library calls). */ #define TARGET_68881 (target_flags & 2) /* Compile using 68020 bitfield insns. */ #define TARGET_BITFIELD (target_flags & 4) /* Compile using rtd insn calling sequence. This will not work unless you use prototypes at least for all functions that can take varying numbers of args. */ #define TARGET_RTD (target_flags & 8) /* Compile passing first two args in regs 0 and 1. This exists only to test compiler features that will be needed for RISC chips. It is not usable and is not intended to be usable on this cpu. */ #define TARGET_REGPARM (target_flags & 020) /* Compile with 16-bit `int'. */ #define TARGET_SHORT (target_flags & 040) /* Compile with special insns for Sun FPA. */ #ifdef SUPPORT_SUN_FPA #define TARGET_FPA (target_flags & 0100) #else #define TARGET_FPA 0 #endif /* Compile (actually, link) for Sun SKY board. */ #define TARGET_SKY (target_flags & 0200) /* Optimize for 68040, but still allow execution on 68020 (-m68020-40 or -m68040). The 68040 will execute all 68030 and 68881/2 instructions, but some of them must be emulated in software by the OS. When TARGET_68040 is turned on, these instructions won't be used. This code will still run on a 68030 and 68881/2. */ #define TARGET_68040 (target_flags & 01400) /* Use the 68040-only fp instructions (-m68040). */ #define TARGET_68040_ONLY (target_flags & 01000) /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */ #define TARGET_SWITCHES \ { { "68020", -01400}, \ { "c68020", -01400}, \ { "68020", 5}, \ { "c68020", 5}, \ { "68881", 2}, \ { "bitfield", 4}, \ { "68000", -01405}, \ { "c68000", -01405}, \ { "soft-float", -01102}, \ { "nobitfield", -4}, \ { "rtd", 8}, \ { "nortd", -8}, \ { "short", 040}, \ { "noshort", -040}, \ { "fpa", 0100}, \ { "nofpa", -0100}, \ { "sky", 0200}, \ { "nosky", -0200}, \ { "68020-40", 0407}, \ { "68030", -01400}, \ { "68030", 5}, \ { "68040", 01007}, \ { "68851", 0}, /* Affects *_SPEC and/or GAS. */ \ { "no-68851", 0}, /* Affects *_SPEC and/or GAS. */ \ { "68302", 0}, /* Affects *_SPEC and/or GAS. */ \ { "no-68302", 0}, /* Affects *_SPEC and/or GAS. */ \ { "68332", 0}, /* Affects *_SPEC and/or GAS. */ \ { "no-68332", 0}, /* Affects *_SPEC and/or GAS. */ \ SUBTARGET_SWITCHES \ { "", TARGET_DEFAULT}} /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */ /* This is meant to be redefined in the host dependent files */ #define SUBTARGET_SWITCHES #ifdef SUPPORT_SUN_FPA /* Blow away 68881 flag silently on TARGET_FPA (since we can't clear any bits in TARGET_SWITCHES above) */ #define OVERRIDE_OPTIONS \ { \ if (TARGET_FPA) target_flags &= ~2; \ if (! TARGET_68020 && flag_pic == 2) \ error("-fPIC is not currently supported on the 68000 or 68010\n"); \ SUBTARGET_OVERRIDE_OPTIONS \ } #else #define OVERRIDE_OPTIONS \ { \ if (! TARGET_68020 && flag_pic == 2) \ error("-fPIC is not currently supported on the 68000 or 68010\n"); \ SUBTARGET_OVERRIDE_OPTIONS \ } #endif /* defined SUPPORT_SUN_FPA */ /* This is meant to be redefined in the host dependent files */ #define SUBTARGET_OVERRIDE_OPTIONS /* target machine storage layout */ /* Define for XFmode extended real floating point support. This will automatically cause REAL_ARITHMETIC to be defined. */ #define LONG_DOUBLE_TYPE_SIZE 96 /* Define if you don't want extended real, but do want to use the software floating point emulator for REAL_ARITHMETIC and decimal <-> binary conversion. */ /* #define REAL_ARITHMETIC */ /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. This is true for 68020 insns such as bfins and bfexts. We make it true always by avoiding using the single-bit insns except in special cases with constant bit numbers. */ #define BITS_BIG_ENDIAN 1 /* Define this if most significant byte of a word is the lowest numbered. */ /* That is true on the 68000. */ #define BYTES_BIG_ENDIAN 1 /* Define this if most significant word of a multiword number is the lowest numbered. */ /* For 68000 we can decide arbitrarily since there are no machine instructions for them. So let's be consistent. */ #define WORDS_BIG_ENDIAN 1 /* number of bits in an addressable storage unit */ #define BITS_PER_UNIT 8 /* Width in bits of a "word", which is the contents of a machine register. Note that this is not necessarily the width of data type `int'; if using 16-bit ints on a 68000, this would still be 32. But on a machine with 16-bit registers, this would be 16. */ #define BITS_PER_WORD 32 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 4 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ #define POINTER_SIZE 32 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) /* Boundary (in *bits*) on which stack pointer should be aligned. */ #define STACK_BOUNDARY 16 /* Allocation boundary (in *bits*) for the code of a function. */ #define FUNCTION_BOUNDARY 16 /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 16 /* No data type wants to be aligned rounder than this. */ #define BIGGEST_ALIGNMENT 16 /* Set this nonzero if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 1 #define SELECT_RTX_SECTION(MODE, X) \ { \ if (!flag_pic) \ readonly_data_section(); \ else if (LEGITIMATE_PIC_OPERAND_P (X)) \ readonly_data_section(); \ else \ data_section(); \ } /* Define number of bits in most basic integer type. (If undefined, default is BITS_PER_WORD). */ #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) /* Define these to avoid dependence on meaning of `int'. Note that WCHAR_TYPE_SIZE is used in cexp.y, where TARGET_SHORT is not available. */ #define WCHAR_TYPE "long int" #define WCHAR_TYPE_SIZE 32 /* Standard register usage. */ /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. For the 68000, we give the data registers numbers 0-7, the address registers numbers 010-017, and the 68881 floating point registers numbers 020-027. */ #ifndef SUPPORT_SUN_FPA #define FIRST_PSEUDO_REGISTER 24 #else #define FIRST_PSEUDO_REGISTER 56 #endif /* This defines the register which is used to hold the offset table for PIC. */ #define PIC_OFFSET_TABLE_REGNUM 13 /* Used to output a (use pic_offset_table_rtx) so that we always save/restore a5 in functions that use PIC relocation at *any* time during the compilation process. */ #define FINALIZE_PIC finalize_pic() #ifndef SUPPORT_SUN_FPA /* 1 for registers that have pervasive standard uses and are not available for the register allocator. On the 68000, only the stack pointer is such. */ #define FIXED_REGISTERS \ {/* Data registers. */ \ 0, 0, 0, 0, 0, 0, 0, 0, \ \ /* Address registers. */ \ 0, 0, 0, 0, 0, 0, 0, 1, \ \ /* Floating point registers \ (if available). */ \ 0, 0, 0, 0, 0, 0, 0, 0 } /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. */ #define CALL_USED_REGISTERS \ {1, 1, 0, 0, 0, 0, 0, 0, \ 1, 1, 0, 0, 0, 0, 0, 1, \ 1, 1, 0, 0, 0, 0, 0, 0 } #else /* SUPPORT_SUN_FPA */ /* 1 for registers that have pervasive standard uses and are not available for the register allocator. On the 68000, only the stack pointer is such. */ /* fpa0 is also reserved so that it can be used to move shit back and forth between high fpa regs and everything else. */ #define FIXED_REGISTERS \ {/* Data registers. */ \ 0, 0, 0, 0, 0, 0, 0, 0, \ \ /* Address registers. */ \ 0, 0, 0, 0, 0, 0, 0, 1, \ \ /* Floating point registers \ (if available). */ \ 0, 0, 0, 0, 0, 0, 0, 0, \ \ /* Sun3 FPA registers. */ \ 1, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0 } /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. */ #define CALL_USED_REGISTERS \ {1, 1, 0, 0, 0, 0, 0, 0, \ 1, 1, 0, 0, 0, 0, 0, 1, \ 1, 1, 0, 0, 0, 0, 0, 0, \ /* FPA registers. */ \ 1, 1, 1, 1, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0 } #endif /* defined SUPPORT_SUN_FPA */ /* Make sure everything's fine if we *don't* have a given processor. This assumes that putting a register in fixed_regs will keep the compiler's mitts completely off it. We don't bother to zero it out of register classes. If neither TARGET_FPA or TARGET_68881 is set, the compiler won't touch since no instructions that use these registers will be valid. Reserve PIC_OFFSET_TABLE_REGNUM (a5) for doing PIC relocation if position independent code is being generated by making it a fixed register */ #ifndef SUPPORT_SUN_FPA #define CONDITIONAL_REGISTER_USAGE \ { \ if (flag_pic) \ fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ } #else /* defined SUPPORT_SUN_FPA */ #define CONDITIONAL_REGISTER_USAGE \ { \ int i; \ HARD_REG_SET x; \ if (!TARGET_FPA) \ { \ COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ if (TEST_HARD_REG_BIT (x, i)) \ fixed_regs[i] = call_used_regs[i] = 1; \ } \ if (TARGET_FPA) \ { \ COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ if (TEST_HARD_REG_BIT (x, i)) \ fixed_regs[i] = call_used_regs[i] = 1; \ } \ if (flag_pic) \ fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ } #endif /* defined SUPPORT_SUN_FPA */ /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. On the 68000, ordinary registers hold 32 bits worth; for the 68881 registers, a single register is always enough for anything that can be stored in them at all. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) #ifndef SUPPORT_SUN_FPA /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On the 68000, the cpu registers can hold any mode but the 68881 registers can hold only SFmode or DFmode. The 68881 registers can't hold anything if 68881 use is disabled. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ (((REGNO) < 16) \ || ((REGNO) < 24 \ && TARGET_68881 \ && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT))) #else /* defined SUPPORT_SUN_FPA */ /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On the 68000, the cpu registers can hold any mode but the 68881 registers can hold only SFmode or DFmode. And the 68881 registers can't hold anything if 68881 use is disabled. However, the Sun FPA register can (apparently) hold whatever you feel like putting in them. If using the fpa, don't put a double in d7/a0. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ (((REGNO) < 16 \ && !(TARGET_FPA \ && GET_MODE_CLASS ((MODE)) != MODE_INT \ && GET_MODE_UNIT_SIZE ((MODE)) > 4 \ && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \ && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \ || ((REGNO) < 24 \ ? TARGET_68881 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ : ((REGNO) < 56 ? TARGET_FPA : 0))) #endif /* defined SUPPORT_SUN_FPA */ /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. */ #define MODES_TIEABLE_P(MODE1, MODE2) \ (! TARGET_68881 \ || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))) /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ /* m68000 pc isn't overloaded on a register. */ /* #define PC_REGNUM */ /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM 15 /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM 14 /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */ #define FRAME_POINTER_REQUIRED 0 /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM 14 /* Register in which static-chain is passed to a function. */ #define STATIC_CHAIN_REGNUM 8 /* Register in which address to store a structure value is passed to a function. */ #define STRUCT_VALUE_REGNUM 9 /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. One of the classes must always be named ALL_REGS and include all hard regs. If there is more than one class, another class must be named NO_REGS and contain no registers. The name GENERAL_REGS must be the name of a class (or an alias for another name such as ALL_REGS). This is the class of registers that is allowed by "g" or "r" in a register constraint. Also, registers outside this class are allocated only when instructions express preferences for them. The classes must be numbered in nondecreasing order; that is, a larger-numbered class must never be contained completely in a smaller-numbered class. For any two classes, it is very desirable that there be another class that represents their union. */ /* The 68000 has three kinds of registers, so eight classes would be a complete set. One of them is not needed. */ #ifndef SUPPORT_SUN_FPA enum reg_class { NO_REGS, DATA_REGS, ADDR_REGS, FP_REGS, GENERAL_REGS, DATA_OR_FP_REGS, ADDR_OR_FP_REGS, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ { "NO_REGS", "DATA_REGS", \ "ADDR_REGS", "FP_REGS", \ "GENERAL_REGS", "DATA_OR_FP_REGS", \ "ADDR_OR_FP_REGS", "ALL_REGS" } /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS \ { \ 0x00000000, /* NO_REGS */ \ 0x000000ff, /* DATA_REGS */ \ 0x0000ff00, /* ADDR_REGS */ \ 0x00ff0000, /* FP_REGS */ \ 0x0000ffff, /* GENERAL_REGS */ \ 0x00ff00ff, /* DATA_OR_FP_REGS */ \ 0x00ffff00, /* ADDR_OR_FP_REGS */ \ 0x00ffffff, /* ALL_REGS */ \ } /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1) #else /* defined SUPPORT_SUN_FPA */ /* * Notes on final choices: * * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything * else. * 2) Removed all unions that involve address registers with * floating point registers (left in unions of address and data with * floating point). * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS. * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS. * 4) Left in everything else. */ enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS, FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS, DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS, GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \ "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \ "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \ "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" } /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS \ { \ {0, 0}, /* NO_REGS */ \ {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \ {0xff000000, 0x00ffffff}, /* FPA_REGS */ \ {0x00ff0000, 0x00000000}, /* FP_REGS */ \ {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \ {0x000000ff, 0x00000000}, /* DATA_REGS */ \ {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \ {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \ {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\ {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \ {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \ {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\ {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\ {0xffffffff, 0x00ffffff}, /* ALL_REGS */ \ } /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ extern enum reg_class regno_reg_class[]; #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3]) #endif /* SUPPORT_SUN_FPA */ /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS GENERAL_REGS #define BASE_REG_CLASS ADDR_REGS /* Get reg_class from a letter such as appears in the machine description. We do a trick here to modify the effective constraints on the machine description; we zorch the constraint letters that aren't appropriate for a specific target. This allows us to guarantee that a specific kind of register will not be used for a given target without fiddling with the register classes above. */ #ifndef SUPPORT_SUN_FPA #define REG_CLASS_FROM_LETTER(C) \ ((C) == 'a' ? ADDR_REGS : \ ((C) == 'd' ? DATA_REGS : \ ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ NO_REGS) : \ NO_REGS))) #else /* defined SUPPORT_SUN_FPA */ #define REG_CLASS_FROM_LETTER(C) \ ((C) == 'a' ? ADDR_REGS : \ ((C) == 'd' ? DATA_REGS : \ ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ NO_REGS) : \ ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \ NO_REGS) : \ ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \ NO_REGS) : \ NO_REGS))))) #endif /* defined SUPPORT_SUN_FPA */ /* The letters I, J, K, L and M in a register constraint string can be used to stand for particular ranges of immediate operands. This macro defines what the ranges are. C is the letter, and VALUE is a constant value. Return 1 if VALUE is in the range specified by C. For the 68000, `I' is used for the range 1 to 8 allowed as immediate shift counts and in addq. `J' is used for the range of signed numbers that fit in 16 bits. `K' is for numbers that moveq can't handle. `L' is for range -8 to -1, range of values that can be added with subq. */ #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \ (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \ (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \ (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : 0) /* * A small bit of explanation: * "G" defines all of the floating constants that are *NOT* 68881 * constants. this is so 68881 constants get reloaded and the * fpmovecr is used. "H" defines *only* the class of constants that * the fpa can use, because these can be gotten at in any fpa * instruction and there is no need to force reloads. */ #ifndef SUPPORT_SUN_FPA #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 ) #else /* defined SUPPORT_SUN_FPA */ #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \ (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0) #endif /* defined SUPPORT_SUN_FPA */ /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. On the 68000 series, use a data reg if possible when the value is a constant in the range where moveq could be used and we ensure that QImodes are reloaded into data regs. Also, if a floating constant needs reloading, put it in memory if possible. */ #define PREFERRED_RELOAD_CLASS(X,CLASS) \ ((GET_CODE (X) == CONST_INT \ && (unsigned) (INTVAL (X) + 0x80) < 0x100 \ && (CLASS) != ADDR_REGS) \ ? DATA_REGS \ : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \ ? DATA_REGS \ : (GET_CODE (X) == CONST_DOUBLE \ && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ ? NO_REGS \ : (CLASS)) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ /* On the 68000, this is the size of MODE in words, except in the FP regs, where a single reg is always enough. */ #ifndef SUPPORT_SUN_FPA #define CLASS_MAX_NREGS(CLASS, MODE) \ ((CLASS) == FP_REGS ? 1 \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Moves between fp regs and other regs are two insns. */ #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ ? 4 : 2) #else /* defined SUPPORT_SUN_FPA */ #define CLASS_MAX_NREGS(CLASS, MODE) \ ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Moves between fp regs and other regs are two insns. */ /* Likewise for high fpa regs and other regs. */ #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \ || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \ ? 4 : 2) #endif /* define SUPPORT_SUN_FPA */ /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack makes the stack pointer a smaller address. */ #define STACK_GROWS_DOWNWARD /* Nonzero if we need to generate stack-probe insns. On most systems they are not needed. When they are needed, define this as the stack offset to probe at. */ #define NEED_PROBE 0 /* Define this if the nominal address of the stack frame is at the high-address end of the local variables; that is, each additional local variable allocated goes at a more negative offset in the frame. */ #define FRAME_GROWS_DOWNWARD /* Offset within stack frame to start allocating local variables at. If FRAME_GROWS_DOWNWARD, this is the offset to the END of the first local allocated. Otherwise, it is the offset to the BEGINNING of the first local allocated. */ #define STARTING_FRAME_OFFSET 0 /* If we generate an insn to push BYTES bytes, this says how many the stack pointer really advances by. On the 68000, sp@- in a byte insn really pushes a word. */ #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1) /* Offset of first parameter from the argument pointer register value. */ #define FIRST_PARM_OFFSET(FNDECL) 8 /* Value is the number of byte of arguments automatically popped when returning from a subroutine call. FUNTYPE is the data type of the function (as a tree), or for a library call it is an identifier node for the subroutine name. SIZE is the number of bytes of arguments passed on the stack. On the 68000, the RTS insn cannot pop anything. On the 68010, the RTD insn may be used to pop them if the number of args is fixed, but if the number is variable then the caller must pop them all. RTD can't be used for library calls now because the library is compiled with the Unix compiler. Use of RTD is a selectable option, since it is incompatible with standard Unix calling sequences. If the option is not selected, the caller must always pop the args. */ #define RETURN_POPS_ARGS(FUNTYPE,SIZE) \ ((TARGET_RTD && TREE_CODE (FUNTYPE) != IDENTIFIER_NODE \ && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ == void_type_node))) \ ? (SIZE) : 0) /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */ /* On the 68000 the return value is in D0 regardless. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ gen_rtx (REG, TYPE_MODE (VALTYPE), 0) /* Define how to find the value returned by a library function assuming the value has mode MODE. */ /* On the 68000 the return value is in D0 regardless. */ #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0) /* 1 if N is a possible register number for a function value. On the 68000, d0 is the only register thus used. */ #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for more than one register. */ #define NEEDS_UNTYPED_CALL 0 /* Define this if PCC uses the nonreentrant convention for returning structure and union values. */ #define PCC_STATIC_STRUCT_RETURN /* 1 if N is a possible register number for function argument passing. On the 68000, no registers are used in this way. */ #define FUNCTION_ARG_REGNO_P(N) 0 /* Define a data type for recording info about an argument list during the scan of that argument list. This data type should hold all necessary information about the function itself and about the args processed so far, enough to enable macros such as FUNCTION_ARG to determine where the next arg should go. On the m68k, this is a single integer, which is a number of bytes of arguments scanned so far. */ #define CUMULATIVE_ARGS int /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. On the m68k, the offset starts at 0. */ #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ ((CUM) = 0) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ ((CUM) += ((MODE) != BLKmode \ ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ : (int_size_in_bytes (TYPE) + 3) & ~3)) /* Define where to put the arguments to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. MODE is the argument's machine mode. TYPE is the data type of the argument (as a tree). This is null for libcalls where that information may not be available. CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called. NAMED is nonzero if this argument is a named parameter (otherwise it is an extra parameter matching an ellipsis). */ /* On the 68000 all args are pushed, except if -mregparm is specified then the first two words of arguments are passed in d0, d1. *NOTE* -mregparm does not work. It exists only to test register calling conventions. */ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0) /* For an arg passed partly in registers and partly in memory, this is the number of registers used. For args passed entirely in registers or entirely in memory, zero. */ #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ ((TARGET_REGPARM && (CUM) < 8 \ && 8 < ((CUM) + ((MODE) == BLKmode \ ? int_size_in_bytes (TYPE) \ : GET_MODE_SIZE (MODE)))) \ ? 2 - (CUM) / 4 : 0) /* Generate the assembly code for function entry. */ #define FUNCTION_PROLOGUE(FILE, SIZE) output_function_prologue(FILE, SIZE) /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ #define FUNCTION_PROFILER(FILE, LABELNO) \ asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO)) /* Output assembler code to FILE to initialize this source file's basic block profiling info, if that has not already been done. */ #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ asm_fprintf (FILE, "\ttstl %LLPBX0\n\tbne %LLPI%d\n\tpea %LLPBX0\n\tjsr %U__bb_init_func\n\taddql %I4,%Rsp\n%LLPI%d:\n", \ LABELNO, LABELNO); /* Output assembler code to FILE to increment the entry-count for the BLOCKNO'th basic block in this source file. */ #define BLOCK_PROFILER(FILE, BLOCKNO) \ asm_fprintf (FILE, "\taddql %I1,%LLPBX2+%d\n", 4 * BLOCKNO) /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, the stack pointer does not matter. The value is tested only in functions that have frame pointers. No definition is equivalent to always zero. */ #define EXIT_IGNORE_STACK 1 /* Generate the assembly code for function exit. */ #define FUNCTION_EPILOGUE(FILE, SIZE) output_function_epilogue (FILE, SIZE) /* This is a hook for other tm files to change. */ /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */ /* Determine if the epilogue should be output as RTL. You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ #define USE_RETURN_INSN use_return_insn () /* Store in the variable DEPTH the initial difference between the frame pointer reg contents and the stack pointer reg contents, as of the start of the function body. This depends on the layout of the fixed parts of the stack frame and on how registers are saved. On the 68k, if we have a frame, we must add one word to its length to allow for the place that a6 is stored when we do have a frame pointer. Otherwise, we would need to compute the offset from the frame pointer of a local variable as a function of frame_pointer_needed, which is hard. */ #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ { int regno; \ int offset = -4; \ for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ offset += 12; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ offset += 4; \ (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \ + (get_frame_size () == 0 ? 0 : 4)); \ } /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. */ /* On the 68k, the trampoline looks like this: mov @#.,a0 jsr @#___trampoline jsr @#___trampoline .long STATIC .long FUNCTION The reason for having three jsr insns is so that an entire line of the instruction cache is filled in a predictable way that will always be the same. We always use the assembler label ___trampoline regardless of whether the system adds underscores. */ #define TRAMPOLINE_TEMPLATE(FILE) \ { \ ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x207c)); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4eb9)); \ ASM_OUTPUT_INT (FILE, gen_rtx (SYMBOL_REF, SImode, "*___trampoline"));\ ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4eb9)); \ ASM_OUTPUT_INT (FILE, gen_rtx (SYMBOL_REF, SImode, "*___trampoline"));\ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ ASM_OUTPUT_SHORT (FILE, const0_rtx); \ } /* Length in units of the trampoline for entering a nested function. */ #define TRAMPOLINE_SIZE 26 /* Alignment required for a trampoline. 16 is used to find the beginning of a line in the instruction cache. */ #define TRAMPOLINE_ALIGN 16 /* Emit RTL insns to initialize the variable parts of a trampoline. FNADDR is an RTX for the address of the function's pure code. CXT is an RTX for the static chain value for the function. */ #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 2)), TRAMP); \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 18)), CXT); \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 22)), FNADDR); \ } /* This is the library routine that is used to transfer control from the trampoline to the actual nested function. */ /* A colon is used with no explicit operands to cause the template string to be scanned for %-constructs. */ /* The function name __transfer_from_trampoline is not actually used. The function definition just permits use of "asm with operands" (though the operand list is empty). */ #define TRANSFER_FROM_TRAMPOLINE \ void \ __transfer_from_trampoline () \ { \ register char *a0 asm ("%a0"); \ asm (GLOBAL_ASM_OP " ___trampoline"); \ asm ("___trampoline:"); \ asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \ asm ("rts":); \ } /* Addressing modes, and classification of registers for them. */ #define HAVE_POST_INCREMENT /* #define HAVE_POST_DECREMENT */ #define HAVE_PRE_DECREMENT /* #define HAVE_PRE_INCREMENT */ /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. */ #define REGNO_OK_FOR_INDEX_P(REGNO) \ ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) #define REGNO_OK_FOR_BASE_P(REGNO) \ (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) #define REGNO_OK_FOR_DATA_P(REGNO) \ ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) #define REGNO_OK_FOR_FP_P(REGNO) \ (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) #ifdef SUPPORT_SUN_FPA #define REGNO_OK_FOR_FPA_P(REGNO) \ (((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56)) #endif /* Now macros that check whether X is a register and also, strictly, whether it is in a specified class. These macros are specific to the 68000, and may be used only in code for printing assembler insns and in conditions for define_optimization. */ /* 1 if X is a data register. */ #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) /* 1 if X is an fp register. */ #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) /* 1 if X is an address register */ #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) #ifdef SUPPORT_SUN_FPA /* 1 if X is a register in the Sun FPA. */ #define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X))) #else /* Answer must be no if we don't have an FPA. */ #define FPA_REG_P(X) 0 #endif /* Maximum number of registers that can appear in a valid memory address. */ #define MAX_REGS_PER_ADDRESS 2 /* Recognize any constant value that is a valid address. */ #define CONSTANT_ADDRESS_P(X) \ (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ || GET_CODE (X) == HIGH) /* Nonzero if the constant value X is a legitimate general operand. It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ #define LEGITIMATE_CONSTANT_P(X) 1 /* Nonzero if the constant value X is a legitimate general operand when generating PIC code. It is given that flag_pic is on and that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ #define LEGITIMATE_PIC_OPERAND_P(X) \ (! symbolic_operand (X, VOIDmode)) /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. The usual definition accepts all pseudo regs; the other rejects them unless they have been allocated suitable hard regs. The symbol REG_OK_STRICT causes the latter definition to be used. Most source files want to accept pseudo regs in the hope that they will get allocated to the class that the insn wants them to be in. Source files for reload pass need to be strict. After reload, it makes no difference, since pseudo regs have been eliminated by then. */ #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. */ #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) #else /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) #endif /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. When generating PIC, an address involving a SYMBOL_REF is legitimate if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF. We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses, and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF. Likewise for a LABEL_REF when generating PIC. The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ /* Allow SUBREG everywhere we allow REG. This results in better code. It also makes function inlining work when inline functions are called with arguments that are SUBREGs. */ #define LEGITIMATE_BASE_REG_P(X) \ ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ || (GET_CODE (X) == SUBREG \ && GET_CODE (SUBREG_REG (X)) == REG \ && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) #define INDIRECTABLE_1_ADDRESS_P(X) \ ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ || LEGITIMATE_BASE_REG_P (X) \ || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \ || (GET_CODE (X) == PLUS \ && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \ && GET_CODE (XEXP (X, 1)) == CONST_INT \ && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000) \ || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \ || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF)) \ #if 0 /* This should replace the last two (non-pic) lines except that Sun's assembler does not seem to handle such operands. */ && (TARGET_68020 ? CONSTANT_ADDRESS_P (XEXP (X, 1)) \ : (GET_CODE (XEXP (X, 1)) == CONST_INT \ && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)))) #endif #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; } /* Only labels on dispatch tables are valid for indexing from. */ #define GO_IF_INDEXABLE_BASE(X, ADDR) \ { rtx temp; \ if (GET_CODE (X) == LABEL_REF \ && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \ && GET_CODE (temp) == JUMP_INSN \ && (GET_CODE (PATTERN (temp)) == ADDR_VEC \ || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \ goto ADDR; \ if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; } #define GO_IF_INDEXING(X, ADDR) \ { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } #define GO_IF_INDEXED_ADDRESS(X, ADDR) \ { GO_IF_INDEXING (X, ADDR); \ if (GET_CODE (X) == PLUS) \ { if (GET_CODE (XEXP (X, 1)) == CONST_INT \ && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100) \ { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \ if (GET_CODE (XEXP (X, 0)) == CONST_INT \ && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100) \ { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } } #define LEGITIMATE_INDEX_REG_P(X) \ ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ || (GET_CODE (X) == SIGN_EXTEND \ && GET_CODE (XEXP (X, 0)) == REG \ && GET_MODE (XEXP (X, 0)) == HImode \ && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ || (GET_CODE (X) == SUBREG \ && GET_CODE (SUBREG_REG (X)) == REG \ && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) #define LEGITIMATE_INDEX_P(X) \ (LEGITIMATE_INDEX_REG_P (X) \ || (TARGET_68020 && GET_CODE (X) == MULT \ && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ && GET_CODE (XEXP (X, 1)) == CONST_INT \ && (INTVAL (XEXP (X, 1)) == 2 \ || INTVAL (XEXP (X, 1)) == 4 \ || INTVAL (XEXP (X, 1)) == 8))) /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */ #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ GO_IF_INDEXED_ADDRESS (X, ADDR); \ if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \ && LEGITIMATE_INDEX_P (XEXP (X, 0)) \ && GET_CODE (XEXP (X, 1)) == LABEL_REF) \ goto ADDR; } /* Don't call memory_address_noforce for the address to fetch the switch offset. This address is ok as it stands (see above), but memory_address_noforce would alter it. */ #define PIC_CASE_VECTOR_ADDRESS(index) index /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. OLDX is the address as it was before break_out_memory_refs was called. In some cases it is useful to look at this to decide what needs to be done. MODE and WIN are passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. It is always safe for this macro to do nothing. It exists to recognize opportunities to optimize the output. For the 68000, we handle X+REG by loading X into a register R and using R+REG. R will go in an address reg and indexing will be used. However, if REG is a broken-out memory address or multiplication, nothing needs to be done because REG can certainly go in an address reg. */ #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; } #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ { register int ch = (X) != (OLDX); \ if (GET_CODE (X) == PLUS) \ { int copied = 0; \ if (GET_CODE (XEXP (X, 0)) == MULT) \ { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \ if (GET_CODE (XEXP (X, 1)) == MULT) \ { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \ if (ch && GET_CODE (XEXP (X, 1)) == REG \ && GET_CODE (XEXP (X, 0)) == REG) \ goto WIN; \ if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ if (GET_CODE (XEXP (X, 0)) == REG \ || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \ && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \ { register rtx temp = gen_reg_rtx (Pmode); \ register rtx val = force_operand (XEXP (X, 1), 0); \ emit_move_insn (temp, val); \ COPY_ONCE (X); \ XEXP (X, 1) = temp; \ goto WIN; } \ else if (GET_CODE (XEXP (X, 1)) == REG \ || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \ && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \ { register rtx temp = gen_reg_rtx (Pmode); \ register rtx val = force_operand (XEXP (X, 0), 0); \ emit_move_insn (temp, val); \ COPY_ONCE (X); \ XEXP (X, 0) = temp; \ goto WIN; }}} /* Go to LABEL if ADDR (a legitimate address expression) has an effect that depends on the machine mode it is used for. On the 68000, only predecrement and postincrement address depend thus (the amount of decrement or increment being the length of the operand). */ #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE HImode /* Define this if the tablejump instruction expects the table to contain offsets from the address of the table. Do not define this if the table should contain absolute addresses. */ #define CASE_VECTOR_PC_RELATIVE /* Specify the tree operation to be used to convert reals to integers. */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR /* This is the kind of divide that is easiest to do in the general case. */ #define EASY_DIV_EXPR TRUNC_DIV_EXPR /* Define this as 1 if `char' should by default be signed; else as 0. */ #define DEFAULT_SIGNED_CHAR 1 /* Don't cse the address of the function being compiled. */ #define NO_RECURSIVE_FUNCTION_CSE /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ #define MOVE_MAX 4 /* Define this if zero-extension is slow (more than one real instruction). */ #define SLOW_ZERO_EXTEND /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS 0 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 /* We assume that the store-condition-codes instructions store 0 for false and some other value for true. This is the value stored for true. */ #define STORE_FLAG_VALUE -1 /* When a prototype says `char' or `short', really pass an `int'. */ #define PROMOTE_PROTOTYPES /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ #define Pmode SImode /* A function address in a call instruction is a byte address (for indexing purposes) so give the MEM rtx a byte's mode. */ #define FUNCTION_MODE QImode /* Compute the cost of computing a constant rtl expression RTX whose rtx-code is CODE. The body of this macro is a portion of a switch statement. If the code is computed here, return it with a return statement. Otherwise, break from the switch. */ #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ /* Constant zero is super cheap due to clr instruction. */ \ if (RTX == const0_rtx) return 0; \ /* Constants between -128 and 127 are cheap due to moveq */ \ if (INTVAL (RTX) >= -128 && INTVAL (RTX) <= 127) return 1; \ /* Constants between -136 and 254 are easily generated */ \ /* by intelligent uses of moveq, add[q], and subq */ \ if ((OUTER_CODE) == SET && INTVAL (RTX) >= -136 \ && INTVAL (RTX) <= 254) return 2; \ case CONST: \ case LABEL_REF: \ case SYMBOL_REF: \ return 3; \ case CONST_DOUBLE: \ return 5; /* Compute the cost of various arithmetic operations. These are vaguely right for a 68020. */ /* The costs for long multiply have been adjusted to work properly in synth_mult on the 68020, relative to an average of the time for add and the time for shift, taking away a little more because sometimes move insns are needed. */ #define MULL_COST (TARGET_68040 ? 5 : 13) #define MULW_COST (TARGET_68040 ? 3 : 8) #define RTX_COSTS(X,CODE,OUTER_CODE) \ case PLUS: \ /* An lea costs about three times as much as a simple add. */ \ if (GET_MODE (X) == SImode \ && GET_CODE (XEXP (X, 0)) == REG \ && GET_CODE (XEXP (X, 1)) == MULT \ && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ && GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT \ && (INTVAL (XEXP (XEXP (X, 1), 1)) == 2 \ || INTVAL (XEXP (XEXP (X, 1), 1)) == 4 \ || INTVAL (XEXP (XEXP (X, 1), 1)) == 8)) \ return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \ break; \ case ASHIFT: \ case ASHIFTRT: \ case LSHIFT: \ case LSHIFTRT: \ /* A shift by a big integer takes an extra instruction. */ \ if (GET_CODE (XEXP (X, 1)) == CONST_INT \ && (INTVAL (XEXP (X, 1)) == 16)) \ return COSTS_N_INSNS (2); /* clrw;swap */ \ if (GET_CODE (XEXP (X, 1)) == CONST_INT \ && !(INTVAL (XEXP (X, 1)) > 0 \ && INTVAL (XEXP (X, 1)) <= 8)) \ return COSTS_N_INSNS (3); /* lsr #i,dn */ \ break; \ case MULT: \ if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ return COSTS_N_INSNS (MULW_COST); \ else \ return COSTS_N_INSNS (MULL_COST); \ case DIV: \ case UDIV: \ case MOD: \ case UMOD: \ if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ return COSTS_N_INSNS (27); /* div.w */ \ return COSTS_N_INSNS (43); /* div.l */ /* Tell final.c how to eliminate redundant test instructions. */ /* Here we define machine-dependent flags and fields in cc_status (see `conditions.h'). */ /* Set if the cc value is actually in the 68881, so a floating point conditional branch must be output. */ #define CC_IN_68881 04000 /* Store in cc_status the expressions that the condition codes will describe after execution of an instruction whose pattern is EXP. Do not alter them if the instruction would not alter the cc's. */ /* On the 68000, all the insns to store in an address register fail to set the cc's. However, in some cases these instructions can make it possibly invalid to use the saved cc's. In those cases we clear out some or all of the saved cc's so they won't be used. */ #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN) #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ { if (cc_prev_status.flags & CC_IN_68881) \ return FLOAT; \ if (cc_prev_status.flags & CC_NO_OVERFLOW) \ return NO_OV; \ return NORMAL; } /* Control the assembler format that we output. */ /* Output at beginning of assembler file. */ #define ASM_FILE_START(FILE) \ fprintf (FILE, "#NO_APP\n"); /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ #define ASM_APP_ON "#APP\n" /* Output to assembler file text saying following lines no longer contain unusual constructs. */ #define ASM_APP_OFF "#NO_APP\n" /* Output before read-only data. */ #define TEXT_SECTION_ASM_OP ".text" /* Output before writable data. */ #define DATA_SECTION_ASM_OP ".data" /* Here are four prefixes that are used by asm_fprintf to facilitate customization for alternate assembler syntaxes. Machines with no likelihood of an alternate syntax need not define these and need not use asm_fprintf. */ /* The prefix for register names. Note that REGISTER_NAMES is supposed to include this prefix. */ #define REGISTER_PREFIX "" /* The prefix for local labels. You should be able to define this as an empty string, or any arbitrary string (such as ".", ".L%", etc) without having to make any other changes to account for the specific definition. Note it is a string literal, not interpreted by printf and friends. */ #define LOCAL_LABEL_PREFIX "" /* The prefix to add to user-visible assembler symbols. */ #define USER_LABEL_PREFIX "_" /* The prefix for immediate operands. */ #define IMMEDIATE_PREFIX "#" /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ #ifndef SUPPORT_SUN_FPA #define REGISTER_NAMES \ {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" } #else /* SUPPORTED_SUN_FPA */ #define REGISTER_NAMES \ {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \ "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \ "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \ "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \ "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" } #endif /* defined SUPPORT_SUN_FPA */ /* How to renumber registers for dbx and gdb. On the Sun-3, the floating point registers have numbers 18 to 25, not 16 to 23 as they do in the compiler. */ #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) /* This is how to output the definition of a user-level label named NAME, such as the label on a static function or variable NAME. */ #define ASM_OUTPUT_LABEL(FILE,NAME) \ do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) /* This is how to output a command to make the user-level label named NAME defined for reference from other files. */ #define GLOBAL_ASM_OP ".globl" #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ do { fprintf (FILE, "%s ", GLOBAL_ASM_OP); \ assemble_name (FILE, NAME); \ fputs ("\n", FILE);} while (0) /* This is how to output a reference to a user-level label named NAME. `assemble_name' uses this. */ #define ASM_OUTPUT_LABELREF(FILE,NAME) \ asm_fprintf (FILE, "%0U%s", NAME) /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM) /* This is how to store into the string LABEL the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM) /* This is how to output a `long double' extended real constant. */ #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ do { long l[3]; \ REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ if (sizeof (int) == sizeof (long)) \ fprintf (FILE, "\t.long 0x%x,0x%x,0x%x\n", l[0], l[1], l[2]); \ else \ fprintf (FILE, "\t.long 0x%lx,0x%lx,0x%lx\n", l[0], l[1], l[2]); \ } while (0) /* This is how to output an assembler line defining a `double' constant. */ #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { char dstr[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ fprintf (FILE, "\t.double 0r%s\n", dstr); \ } while (0) /* This is how to output an assembler line defining a `float' constant. */ #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { long l; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ if (sizeof (int) == sizeof (long)) \ fprintf (FILE, "\t.long 0x%x\n", l); \ else \ fprintf (FILE, "\t.long 0x%lx\n", l); \ } while (0) /* This is how to output an assembler line defining an `int' constant. */ #define ASM_OUTPUT_INT(FILE,VALUE) \ ( fprintf (FILE, "\t.long "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* Likewise for `char' and `short' constants. */ #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "\t.word "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ( fprintf (FILE, "\t.byte "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* This is how to output an assembler line for a numeric constant byte. */ #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO]) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO]) /* This is how to output an element of a case-vector that is absolute. (The 68000 does not use such vectors, but we must define this macro anyway.) */ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ asm_fprintf (FILE, "\t.long %LL%d\n", VALUE) /* This is how to output an element of a case-vector that is relative. */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL) /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ /* We don't have a way to align to more than a two-byte boundary, so do the best we can and don't complain. */ #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG) >= 1) \ fprintf (FILE, "\t.even\n"); #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t.skip %u\n", (SIZE)) /* This says how to output an assembler line to define a global common symbol. */ #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fputs (".comm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (ROUNDED))) /* This says how to output an assembler line to define a local common symbol. */ #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( fputs (".lcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (ROUNDED))) /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) /* Define the parentheses used to group arithmetic operations in assembler code. */ #define ASM_OPEN_PAREN "(" #define ASM_CLOSE_PAREN ")" /* Define results of standard character escape sequences. */ #define TARGET_BELL 007 #define TARGET_BS 010 #define TARGET_TAB 011 #define TARGET_NEWLINE 012 #define TARGET_VT 013 #define TARGET_FF 014 #define TARGET_CR 015 /* Output a float value (represented as a C double) as an immediate operand. This macro is a 68k-specific macro. */ #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ do { \ if (CODE == 'f') \ { \ char dstr[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \ asm_fprintf ((FILE), "%I0r%s", dstr); \ } \ else \ { \ long l; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ if (sizeof (int) == sizeof (long)) \ asm_fprintf ((FILE), "%I0x%x", l); \ else \ asm_fprintf ((FILE), "%I0x%lx", l); \ } \ } while (0) /* Output a double value (represented as a C double) as an immediate operand. This macro is a 68k-specific macro. */ #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ do { char dstr[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ asm_fprintf (FILE, "%I0r%s", dstr); \ } while (0) /* Note, long double immediate operands are not actually generated by m68k.md. */ #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \ do { char dstr[30]; \ REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ asm_fprintf (FILE, "%I0r%s", dstr); \ } while (0) /* Print operand X (an rtx) in assembler syntax to file FILE. CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. For `%' followed by punctuation, CODE is the punctuation and X is null. On the 68000, we use several CODE characters: '.' for dot needed in Motorola-style opcode names. '-' for an operand pushing on the stack: sp@-, -(sp) or -(%sp) depending on the style of syntax. '+' for an operand pushing on the stack: sp@+, (sp)+ or (%sp)+ depending on the style of syntax. '@' for a reference to the top word on the stack: sp@, (sp) or (%sp) depending on the style of syntax. '#' for an immediate operand prefix (# in MIT and Motorola syntax but & in SGS syntax). '!' for the fpcr register (used in some float-to-fixed conversions). '$' for the letter `s' in an op code, but only on the 68040. '&' for the letter `d' in an op code, but only on the 68040. '/' for register prefix needed by longlong.h. 'b' for byte insn (no effect, on the Sun; this is for the ISI). 'd' to force memory addressing to be absolute, not relative. 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather than directly). Second part of 'y' below. 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), or print pair of registers as rx:ry. 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs CONST_DOUBLE's as SunFPA constant RAM registers if possible, so it should not be used except for the SunFPA. */ #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \ || (CODE) == '$' || (CODE) == '&' || (CODE) == '/') /* A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand X. X is an RTL expression. CODE is a value that can be used to specify one of several ways of printing the operand. It is used when identical operands must be printed differently depending on the context. CODE comes from the `%' specification that was used to request printing of the operand. If the specification was just `%DIGIT' then CODE is 0; if the specification was `%LTR DIGIT' then CODE is the ASCII code for LTR. If X is a register, this macro should print the register's name. The names can be found in an array `reg_names' whose type is `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. When the machine description has a specification `%PUNCT' (a `%' followed by a punctuation character), this macro is called with a null pointer for X and the punctuation character for CODE. See m68k.c for the m68k specific codes. */ #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) /* A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand that is a memory reference whose address is ADDR. ADDR is an RTL expression. On some machines, the syntax for a symbolic address depends on the section that the address refers to. On these machines, define the macro `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and then check for it here. */ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) /* Definitions for generating bytecode */ /* Just so it's known this target is supported by the bytecode generator. If this define isn't found anywhere in the target config files, then dummy stubs are supplied by bytecode.h, and any attempt to use -fbytecode will result in an error message. */ #define TARGET_SUPPORTS_BYTECODE /* Minimal segment alignment within sections is 8 units. */ #define MACHINE_SEG_ALIGN 3 /* Integer alignment is two units. */ #define INT_ALIGN 2 /* Pointer alignment is eight units. */ #define PTR_ALIGN 3 /* Global symbols begin with `_' */ #define NAMES_HAVE_UNDERSCORES /* BC_xxx below are similar to their ASM_xxx counterparts above. */ #define BC_GLOBALIZE_LABEL(FP, NAME) bc_globalize_label(NAME) #define BC_OUTPUT_COMMON(FP, NAME, SIZE, ROUNDED) \ do { bc_emit_common(NAME, ROUNDED); bc_globalize_label(NAME); } while (0) #define BC_OUTPUT_LOCAL(FP, NAME, SIZE, ROUNDED) \ bc_emit_common(NAME, ROUNDED) #define BC_OUTPUT_ALIGN(FP, ALIGN) bc_align(ALIGN) #define BC_OUTPUT_LABEL(FP, NAME) bc_emit_labeldef(NAME) #define BC_OUTPUT_SKIP(FP, SIZE) bc_emit_skip(SIZE) #define BC_OUTPUT_LABELREF(FP, NAME) \ do { \ char *foo = (char *) xmalloc(strlen(NAME) + 2); \ strcpy(foo, "_"); \ strcat(foo, NAME); \ bc_emit_labelref (foo); \ free (foo); \ } while (0) #define BC_OUTPUT_FLOAT(FP, VAL) \ do { \ float F = VAL; \ bc_emit ((char *) &F, sizeof F); \ } while (0) #define BC_OUTPUT_DOUBLE(FP, VAL) \ do { \ double D = VAL; \ bc_emit ((char *) &D, sizeof D); \ } while (0) #define BC_OUTPUT_BYTE(FP, VAL) \ do { \ char C = VAL; \ bc_emit (&C, 1); \ } while (0) #define BC_OUTPUT_FILE ASM_OUTPUT_FILE #define BC_OUTPUT_ASCII ASM_OUTPUT_ASCII #define BC_OUTPUT_IDENT ASM_OUTPUT_IDENT /* Same as XSTR, but for bytecode */ #define BCXSTR(RTX) ((RTX)->bc_label) /* Flush bytecode buffer onto file */ #define BC_WRITE_FILE(FP) \ { \ fprintf (FP, ".text\n"); \ bc_seg_write (bc_text_seg, FP); \ fprintf(FP, "\n.data\n"); \ bc_seg_write (bc_data_seg, FP); \ bc_sym_write (FP); /* do .globl, .bss, etc. */ \ } /* Write one symbol */ #define BC_WRITE_SEGSYM(SEGSYM, FP) \ { \ prsym (FP, (SEGSYM)->sym->name); \ fprintf (FP, ":\n"); \ } /* Write one reloc entry */ #define BC_WRITE_RELOC_ENTRY(SEGRELOC, FP, OFFSET) \ { \ fprintf (FP, "\t.long "); \ prsym (FP, (SEGRELOC)->sym->name); \ fprintf (FP, " + %d\n", OFFSET); \ } /* Start new line of bytecodes */ #define BC_START_BYTECODE_LINE(FP) \ { \ fprintf (FP, "\t.byte"); \ } /* Write one bytecode */ #define BC_WRITE_BYTECODE(SEP, VAL, FP) \ { \ fprintf (FP, "%c0x%02X", (SEP), (VAL) & 0xff); \ } /* Write one bytecode RTL entry */ #define BC_WRITE_RTL(R, FP) \ { \ fprintf (FP, "%s+%d/0x%08X\n", (R)->label, (R)->offset, (R)->bc_label); \ } /* Emit function entry trampoline */ #define BC_EMIT_TRAMPOLINE(TRAMPSEG, CALLINFO) \ { \ short insn; \ \ /* Push a reference to the callinfo structure. */ \ insn = 0x4879; /* pea xxx.L */ \ seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \ seg_refsym (TRAMPSEG, CALLINFO, 0); \ \ /* Call __interp, pop arguments, and return. */ \ insn = 0x4eb9; /* jsr xxx.L */ \ seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \ seg_refsym (TRAMPSEG, "__callint", 0); \ insn = 0x588f; /* addql #4, sp */ \ seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \ insn = 0x4e75; /* rts */ \ seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \ } #if 0 #define VALIDATE_STACK() if (stack_depth < 0) abort (); #else #if 0 #define VALIDATE_STACK() \ fprintf (stderr, " %%%d%%", stack_depth); #endif #endif /* Define functions defined in aux-output.c and used in templates. */ extern char *output_move_double (); extern char *output_move_const_single (); extern char *output_move_const_double (); extern char *output_btst (); /* Local variables: version-control: t End: */ gcc-2.5.8/config/m68k/m68k.md100444 22011 13 503421 5476761252 14207 0ustar kenneruser;;- Machine description for GNU compiler ;;- Motorola 68000 Version ;; Copyright (C) 1987, 1988, 1993 Free Software Foundation, Inc. ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ;;- instruction definitions ;;- @@The original PO technology requires these to be ordered by speed, ;;- @@ so that assigner will pick the fastest. ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ;;- When naming insn's (operand 0 of define_insn) be careful about using ;;- names from other targets machine descriptions. ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code ;;- updates for most instructions. ;;- Operand classes for the register allocator: ;;- 'a' one of the address registers can be used. ;;- 'd' one of the data registers can be used. ;;- 'f' one of the m68881 registers can be used ;;- 'r' either a data or an address register can be used. ;;- 'x' if one of the Sun FPA registers ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15). ;;- Immediate Floating point operator constraints ;;- 'G' a floating point constant that is *NOT* one of the standard ;; 68881 constant values (to force calling output_move_const_double ;; to get it from rom if it is a 68881 constant). ;;- 'H' one of the standard FPA constant values ;; ;; See the functions standard_XXX_constant_p in output-m68k.c for more ;; info. ;;- Immediate integer operand constraints: ;;- 'I' 1 .. 8 ;;- 'J' -32768 .. 32767 ;;- 'K' all integers EXCEPT -128 .. 127 ;;- 'L' -8 .. -1 ;;- Assembler specs: ;;- "%." size separator ("." or "") move%.l d0,d1 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0 ;;- "%-" push operand "sp@-" move%.l d0,%- ;;- "%+" pop operand "sp@+" move%.l d0,%+ ;;- "%@" top of stack "sp@" move%.l d0,%@ ;;- "%!" fpcr register ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1 ;;- Information about 68040 port. ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must ;;- be emulated in software by the OS. It is faster to avoid these ;;- instructions and issue a library call rather than trapping into ;;- the kernel. The affected instructions are fintrz and fscale. The ;;- TARGET_68040 flag turns the use of the opcodes off. ;;- The '040 also implements a set of new floating-point instructions ;;- which specify the rounding precision in the opcode. This finally ;;- permit the 68k series to be truly IEEE compliant, and solves all ;;- issues of excess precision accumulating in the extended registers. ;;- By default, GCC does not use these instructions, since such code will ;;- not run on an '030. To use these instructions, use the -m68040-only ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY, ;;- you can make these instructions the default. ;;- These new instructions aren't directly in the md. They are brought ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather ;;- than "". ;;- FPA port explanation: ;;- Usage of the Sun FPA and the 68881 together ;;- The current port of gcc to the sun fpa disallows use of the m68881 ;;- instructions completely if code is targeted for the fpa. This is ;;- for the following reasons: ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you ;;- can, the 68881 otherwise, and data registers only if you are ;;- forced to it) is a bitch with the current constraint scheme, ;;- especially since it would have to work for any combination of ;;- -mfpa, -m68881. ;;- 2) There are no instructions to move between the two types of ;;- registers; the stack must be used as an intermediary. ;;- It could indeed be done; I think the best way would be to have ;;- separate patterns for TARGET_FPA (which implies a 68881), ;;- TARGET_68881, and no floating point co-processor. Use ;;- define_expands for all of the named instruction patterns, and ;;- include code in the FPA instruction to deal with the 68881 with ;;- preferences specifically set to favor the fpa. Some of this has ;;- already been done: ;;- ;;- 1) Separation of most of the patterns out into a TARGET_FPA ;;- case and a TARGET_68881 case (the exceptions are the patterns ;;- which would need one define_expand and three define_insn's under ;;- it (with a lot of duplicate code between them) to replace the ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the ;;- first two patterns in the md. ;;- ;;- Some would still have to be done: ;;- ;;- 1) Add code to the fpa patterns which correspond to 68881 ;;- patterns to deal with the 68881 case (including preferences!). ;;- What you might actually do here is combine the fpa and 68881 code ;;- back together into one pattern for those instructions where it's ;;- absolutely necessary and save yourself some duplicate code. I'm ;;- not completely sure as to whether you could get away with doing ;;- this only for the mov* insns, or if you'd have to do it for all ;;- named insns. ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle ;;- moving between fpa regs and 68881 regs. ;;- Since the fpa is more powerful than the 68881 and also has more ;;- registers, and since I think the resultant md would be medium ugly ;;- (lot's of duplicate code, ugly constraint strings), I elected not ;;- to do this change. ;;- Another reason why someone *might* want to do the change is to ;;- control which register classes are accessed in a slightly cleaner ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in ;;- the internals manual. ;;- Yet another reason why someone might want to do this change is to ;;- allow use of some of the 68881 insns which have no equivalent on ;;- the fpa. The sqrt instruction comes fairly quickly to mind. ;;- If this is ever done, don't forget to change sun3.h so that ;;- it *will* define __HAVE_68881__ when the FPA is in use. ;;- Condition code hack ;;- When a floating point compare is done in the fpa, the resulting ;;- condition codes are left in the fpastatus register. The values in ;;- this register must be moved into the 68000 cc register before any ;;- jump is executed. Once this has been done, regular jump ;;- instructions are fine (ie. floating point jumps are not necessary. ;;- They are only done if the cc is in the 68881). ;;- The instructions that move the fpastatus register to the 68000 ;;- register clobber a data register (the move cannot be done direct). ;;- These instructions might be bundled either with the compare ;;- instruction, or the branch instruction. If we were using both the ;;- fpa and the 68881 together, we would wish to only mark the ;;- register clobbered if we were doing the compare in the fpa, but I ;;- think that that decision (whether to clobber the register or not) ;;- must be done before register allocation (makes sense) and hence we ;;- can't know if the floating point compare will be done in the fpa ;;- or the fp. So whenever we are asked for code that uses the fpa, ;;- we will mark a data register as clobbered. This is reasonable, as ;;- almost all floating point compare operations done with fpa code ;;- enabled will be done in the fpa. It's even more reasonable since ;;- we decided to make the 68881 and the fpa mutually exclusive. ;;- We place to code to move the fpastatus register inside of a ;;- define_expand so that we can do it conditionally based on whether ;;- we are targeting an fpa or not. ;;- This still leaves us with the question of where we wish to put the ;;- code to move the fpastatus reg. If we put it in the compare ;;- instruction, we can restrict the clobbering of the register to ;;- floating point compares, but we can't take advantage of floating ;;- point subtracts & etc. that alter the fpastatus register. If we ;;- put it in the branch instruction, all branches compiled with fpa ;;- code enabled will clobber a data register, but we will be able to ;;- take advantage of fpa subtracts. This balance favors putting the ;;- code in with the compare instruction. ;;- Note that if some enterprising hacker should decide to switch ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC. ;;- Usage of the top 16 fpa registers ;;- The only locations which we may transfer fpa registers 16-31 from ;;- or to are the fpa registers 0-15. (68000 registers and memory ;;- locations are impossible). This causes problems in gcc, which ;;- assumes that mov?? instructions require no additional registers ;;- (see section 11.7) and since floating point moves *must* be ;;- supported into general registers (see section 12.3 under ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere. ;;- My solution was to reserve fpa0 for moves into or out of these top ;;- 16 registers and to disparage the choice to reload into or out of ;;- these registers as much as I could. That alternative is always ;;- last in the list, so it will not be used unless all else fails. I ;;- will note that according to my current information, sun's compiler ;;- doesn't use these top 16 registers at all. ;;- There is another possible way to do it. I *believe* that if you ;;- make absolutely sure that the code will not be executed in the ;;- reload pass, you can support the mov?? names with define_expands ;;- which require new registers. This may be possible by the ;;- appropriate juggling of constraints. I may come back to this later. ;;- Usage of constant RAM ;;- This has been handled correctly (I believe) but the way I've done ;;- it could use a little explanation. The constant RAM can only be ;;- accessed when the instruction is in "command register" mode. ;;- "command register" mode means that no accessing of memory or the ;;- 68000 registers is being done. This can be expressed easily in ;;- constraints, so generally the mode of the instruction is ;;- determined by a branch off of which_alternative. In outputting ;;- instructions, a 'w' means to output an access to the constant ram ;;- (if the arg is CONST_DOUBLE and is one of the available ;;- constants), and 'x' means to output a register pair (if the arg is ;;- a 68000 register) and a 'y' is the combination of the above two ;;- processes. You use a 'y' in two operand DF instructions where you ;;- *know* the other operand is an fpa register, you use an 'x' in DF ;;- instructions where the arg might be a 68000 register and the ;;- instruction is *not* in "command register" mode, and you use a 'w' ;;- in two situations: 1) The instruction *is* in command register ;;- mode (and hence won't be accessing 68000 registers), or 2) The ;;- instruction is a two operand SF instruction where you know the ;;- other operand is an fpa register. ;;- Optimization issues ;;- I actually think that I've included all of the fpa instructions ;;- that should be included. Note that if someone is interested in ;;- doing serious floating point work on the sun fpa, I would advise ;;- the use of the "asm" instruction in gcc to allow you to use the ;;- sin, cos, and exponential functions on the fpa board. ;;- END FPA Explanation Section. ;;- Some of these insn's are composites of several m68000 op codes. ;;- The assembler (or final @@??) insures that the appropriate one is ;;- selected. (define_insn "" [(set (match_operand:DF 0 "push_operand" "=m") (match_operand:DF 1 "general_operand" "ro<>fyE"))] "" "* { if (FP_REG_P (operands[1])) return \"fmove%.d %f1,%0\"; if (FPA_REG_P (operands[1])) return \"fpmove%.d %1, %x0\"; return output_move_double (operands); }") (define_insn "" [(set (match_operand:DI 0 "push_operand" "=m") (match_operand:DI 1 "general_operand" "ro<>Fy"))] "" "* { return output_move_double (operands); }") ;; We don't want to allow a constant operand for test insns because ;; (set (cc0) (const_int foo)) has no mode information. Such insns will ;; be folded while optimizing anyway. (define_insn "tstsi" [(set (cc0) (match_operand:SI 0 "nonimmediate_operand" "rm"))] "" "* { #ifdef ISI_OV /* ISI's assembler fails to handle tstl a0. */ if (! ADDRESS_REG_P (operands[0])) #else if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) #endif return \"tst%.l %0\"; /* If you think that the 68020 does not support tstl a0, reread page B-167 of the 68020 manual more carefully. */ /* On an address reg, cmpw may replace cmpl. */ #ifdef SGS_CMP_ORDER return \"cmp%.w %0,%#0\"; #else return \"cmp%.w %#0,%0\"; #endif }") ;; This can't use an address register, because comparisons ;; with address registers as second operand always test the whole word. (define_insn "tsthi" [(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "dm"))] "" "tst%.w %0") (define_insn "tstqi" [(set (cc0) (match_operand:QI 0 "nonimmediate_operand" "dm"))] "" "tst%.b %0") (define_expand "tstsf" [(set (cc0) (match_operand:SF 0 "general_operand" ""))] "TARGET_68881 || TARGET_FPA" " { if (TARGET_FPA) { emit_insn (gen_tstsf_fpa (operands[0])); DONE; } }") (define_insn "tstsf_fpa" [(set (cc0) (match_operand:SF 0 "general_operand" "xmdF")) (clobber (match_scratch:SI 1 "=d"))] "TARGET_FPA" "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc") (define_insn "" [(set (cc0) (match_operand:SF 0 "general_operand" "fdm"))] "TARGET_68881" "* { cc_status.flags = CC_IN_68881; if (FP_REG_P (operands[0])) return \"ftst%.x %0\"; return \"ftst%.s %0\"; }") (define_expand "tstdf" [(set (cc0) (match_operand:DF 0 "general_operand" ""))] "TARGET_68881 || TARGET_FPA" " { if (TARGET_FPA) { emit_insn (gen_tstsf_fpa (operands[0])); DONE; } }") (define_insn "tstdf_fpa" [(set (cc0) (match_operand:DF 0 "general_operand" "xrmF")) (clobber (match_scratch:SI 1 "=d"))] "TARGET_FPA" "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc") (define_insn "" [(set (cc0) (match_operand:DF 0 "general_operand" "fm"))] "TARGET_68881" "* { cc_status.flags = CC_IN_68881; if (FP_REG_P (operands[0])) return \"ftst%.x %0\"; return \"ftst%.d %0\"; }") ;; compare instructions. ;; A composite of the cmp, cmpa, & cmpi m68000 op codes. (define_insn "cmpsi" [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>") (match_operand:SI 1 "general_operand" "mr,Ksr,>")))] "" "* { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) #ifdef SGS_CMP_ORDER return \"cmpm%.l %0,%1\"; #else return \"cmpm%.l %1,%0\"; #endif if (REG_P (operands[1]) || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) { cc_status.flags |= CC_REVERSED; #ifdef SGS_CMP_ORDER return \"cmp%.l %d1,%d0\"; #else return \"cmp%.l %d0,%d1\"; #endif } #ifdef SGS_CMP_ORDER return \"cmp%.l %d0,%d1\"; #else return \"cmp%.l %d1,%d0\"; #endif }") (define_insn "cmphi" [(set (cc0) (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>") (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))] "" "* { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) #ifdef SGS_CMP_ORDER return \"cmpm%.w %0,%1\"; #else return \"cmpm%.w %1,%0\"; #endif if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1])) || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) { cc_status.flags |= CC_REVERSED; #ifdef SGS_CMP_ORDER return \"cmp%.w %d1,%d0\"; #else return \"cmp%.w %d0,%d1\"; #endif } #ifdef SGS_CMP_ORDER return \"cmp%.w %d0,%d1\"; #else return \"cmp%.w %d1,%d0\"; #endif }") (define_insn "cmpqi" [(set (cc0) (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>") (match_operand:QI 1 "general_operand" "dm,nd,>")))] "" "* { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) #ifdef SGS_CMP_ORDER return \"cmpm%.b %0,%1\"; #else return \"cmpm%.b %1,%0\"; #endif if (REG_P (operands[1]) || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) { cc_status.flags |= CC_REVERSED; #ifdef SGS_CMP_ORDER return \"cmp%.b %d1,%d0\"; #else return \"cmp%.b %d0,%d1\"; #endif } #ifdef SGS_CMP_ORDER return \"cmp%.b %d0,%d1\"; #else return \"cmp%.b %d1,%d0\"; #endif }") (define_expand "cmpdf" [(set (cc0) (compare (match_operand:DF 0 "general_operand" "") (match_operand:DF 1 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" " { if (TARGET_FPA) { emit_insn (gen_cmpdf_fpa (operands[0], operands[1])); DONE; } }") (define_insn "cmpdf_fpa" [(set (cc0) (compare (match_operand:DF 0 "general_operand" "x,y") (match_operand:DF 1 "general_operand" "xH,rmF"))) (clobber (match_scratch:SI 2 "=d,d"))] "TARGET_FPA" "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc") (define_insn "" [(set (cc0) (compare (match_operand:DF 0 "general_operand" "f,mG") (match_operand:DF 1 "general_operand" "fmG,f")))] "TARGET_68881" "* { cc_status.flags = CC_IN_68881; #ifdef SGS_CMP_ORDER if (REG_P (operands[0])) { if (REG_P (operands[1])) return \"fcmp%.x %0,%1\"; else return \"fcmp%.d %0,%f1\"; } cc_status.flags |= CC_REVERSED; return \"fcmp%.d %1,%f0\"; #else if (REG_P (operands[0])) { if (REG_P (operands[1])) return \"fcmp%.x %1,%0\"; else return \"fcmp%.d %f1,%0\"; } cc_status.flags |= CC_REVERSED; return \"fcmp%.d %f0,%1\"; #endif }") (define_expand "cmpsf" [(set (cc0) (compare (match_operand:SF 0 "general_operand" "") (match_operand:SF 1 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" " { if (TARGET_FPA) { emit_insn (gen_cmpsf_fpa (operands[0], operands[1])); DONE; } }") (define_insn "cmpsf_fpa" [(set (cc0) (compare (match_operand:SF 0 "general_operand" "x,y") (match_operand:SF 1 "general_operand" "xH,rmF"))) (clobber (match_scratch:SI 2 "=d,d"))] "TARGET_FPA" "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc") (define_insn "" [(set (cc0) (compare (match_operand:SF 0 "general_operand" "f,mdG") (match_operand:SF 1 "general_operand" "fmdG,f")))] "TARGET_68881" "* { cc_status.flags = CC_IN_68881; #ifdef SGS_CMP_ORDER if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) return \"fcmp%.x %0,%1\"; else return \"fcmp%.s %0,%f1\"; } cc_status.flags |= CC_REVERSED; return \"fcmp%.s %1,%f0\"; #else if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) return \"fcmp%.x %1,%0\"; else return \"fcmp%.s %f1,%0\"; } cc_status.flags |= CC_REVERSED; return \"fcmp%.s %f0,%1\"; #endif }") ;; Recognizers for btst instructions. (define_insn "" [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do") (const_int 1) (minus:SI (const_int 7) (match_operand:SI 1 "general_operand" "di"))))] "" "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") (define_insn "" [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d") (const_int 1) (minus:SI (const_int 31) (match_operand:SI 1 "general_operand" "di"))))] "" "* { return output_btst (operands, operands[1], operands[0], insn, 31); }") ;; The following two patterns are like the previous two ;; except that they use the fact that bit-number operands ;; are automatically masked to 3 or 5 bits. (define_insn "" [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do") (const_int 1) (minus:SI (const_int 7) (and:SI (match_operand:SI 1 "general_operand" "d") (const_int 7)))))] "" "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") (define_insn "" [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d") (const_int 1) (minus:SI (const_int 31) (and:SI (match_operand:SI 1 "general_operand" "d") (const_int 31)))))] "" "* { return output_btst (operands, operands[1], operands[0], insn, 31); }") ;; Nonoffsettable mem refs are ok in this one pattern ;; since we don't try to adjust them. (define_insn "" [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "md") (const_int 1) (match_operand:SI 1 "general_operand" "i")))] "GET_CODE (operands[1]) == CONST_INT && (unsigned) INTVAL (operands[1]) < 8" "* { operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1])); return output_btst (operands, operands[1], operands[0], insn, 7); }") (define_insn "" [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "do") (const_int 1) (match_operand:SI 1 "general_operand" "i")))] "GET_CODE (operands[1]) == CONST_INT" "* { if (GET_CODE (operands[0]) == MEM) { operands[0] = adj_offsettable_operand (operands[0], INTVAL (operands[1]) / 8); operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]) % 8); return output_btst (operands, operands[1], operands[0], insn, 7); } operands[1] = gen_rtx (CONST_INT, VOIDmode, 31 - INTVAL (operands[1])); return output_btst (operands, operands[1], operands[0], insn, 31); }") ;; move instructions ;; A special case in which it is not desirable ;; to reload the constant into a data register. (define_insn "" [(set (match_operand:SI 0 "push_operand" "=m") (match_operand:SI 1 "general_operand" "J"))] "GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000" "* { if (operands[1] == const0_rtx) return \"clr%.l %0\"; return \"pea %a1\"; }") ;This is never used. ;(define_insn "swapsi" ; [(set (match_operand:SI 0 "general_operand" "+r") ; (match_operand:SI 1 "general_operand" "+r")) ; (set (match_dup 1) (match_dup 0))] ; "" ; "exg %1,%0") ;; Special case of fullword move when source is zero. ;; The reason this is special is to avoid loading a zero ;; into a data reg with moveq in order to store it elsewhere. (define_insn "" [(set (match_operand:SI 0 "general_operand" "=g") (const_int 0))] ;; clr insns on 68000 read before writing. ;; This isn't so on the 68010, but we have no alternative for it. "(TARGET_68020 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))" "* { if (ADDRESS_REG_P (operands[0])) return \"sub%.l %0,%0\"; /* moveq is faster on the 68000. */ if (DATA_REG_P (operands[0]) && !TARGET_68020) #if defined(MOTOROLA) && !defined(CRDS) return \"moveq%.l %#0,%0\"; #else return \"moveq %#0,%0\"; #endif return \"clr%.l %0\"; }") ;; General case of fullword move. ;; ;; This is the main "hook" for PIC code. When generating ;; PIC, movsi is responsible for determining when the source address ;; needs PIC relocation and appropriately calling legitimize_pic_address ;; to perform the actual relocation. ;; ;; In both the PIC and non-PIC cases the patterns generated will ;; matched by the next define_insn. (define_expand "movsi" [(set (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))] "" " { if (flag_pic && symbolic_operand (operands[1], SImode)) { /* The source is an address which requires PIC relocation. Call legitimize_pic_address with the source, mode, and a relocation register (a new pseudo, or the final destination if reload_in_progress is set). Then fall through normally */ extern rtx legitimize_pic_address(); rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); operands[1] = legitimize_pic_address (operands[1], SImode, temp); } }") ;; General case of fullword move. The register constraints ;; force integer constants in range for a moveq to be reloaded ;; if they are headed for memory. (define_insn "" ;; Notes: make sure no alternative allows g vs g. ;; We don't allow f-regs since fixed point cannot go in them. ;; We do allow y and x regs since fixed point is allowed in them. [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m") (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))] "" "* { if (which_alternative == 3) return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\"; if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0])) return \"fpmove%.l %x1,%x0\"; if (GET_CODE (operands[1]) == CONST_INT) { if (operands[1] == const0_rtx && (DATA_REG_P (operands[0]) || GET_CODE (operands[0]) == MEM) /* clr insns on 68000 read before writing. This isn't so on the 68010, but we have no alternative for it. */ && (TARGET_68020 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) return \"clr%.l %0\"; else if (DATA_REG_P (operands[0]) && INTVAL (operands[1]) < 128 && INTVAL (operands[1]) >= -128) { #if defined(MOTOROLA) && !defined(CRDS) return \"moveq%.l %1,%0\"; #else return \"moveq %1,%0\"; #endif } #ifndef NO_ADDSUB_Q else if (DATA_REG_P (operands[0]) /* Do this with a moveq #N-8, dreg; addq #8,dreg */ && INTVAL (operands[1]) < 136 && INTVAL (operands[1]) >= 128) { operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); #if defined(MOTOROLA) && !defined(CRDS) return \"moveq%.l %1,%0\;addq%.w %#8,%0\"; #else return \"moveq %1,%0\;addq%.w %#8,%0\"; #endif } else if (DATA_REG_P (operands[0]) /* Do this with a moveq #N+8, dreg; subq #8,dreg */ && INTVAL (operands[1]) < -128 && INTVAL (operands[1]) >= -136) { operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) + 8); #if defined(MOTOROLA) && !defined(CRDS) return \"moveq%.l %1,%0;subq%.w %#8,%0\"; #else return \"moveq %1,%0;subq%.w %#8,%0\"; #endif } #endif else if (DATA_REG_P (operands[0]) /* If N is in the right range and is even, then use moveq #N/2, dreg; addl dreg,dreg */ && INTVAL (operands[1]) > 127 && INTVAL (operands[1]) <= 254 && INTVAL (operands[1]) % 2 == 0) { operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) / 2); #if defined(MOTOROLA) && !defined(CRDS) return \"moveq%.l %1,%0\;add%.w %0,%0\"; #else return \"moveq %1,%0\;add%.w %0,%0\"; #endif } else if (ADDRESS_REG_P (operands[0]) && INTVAL (operands[1]) < 0x8000 && INTVAL (operands[1]) >= -0x8000) return \"move%.w %1,%0\"; else if (push_operand (operands[0], SImode) && INTVAL (operands[1]) < 0x8000 && INTVAL (operands[1]) >= -0x8000) return \"pea %a1\"; } else if ((GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST) && push_operand (operands[0], SImode)) return \"pea %a1\"; else if ((GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST) && ADDRESS_REG_P (operands[0])) return \"lea %a1,%0\"; return \"move%.l %1,%0\"; }") (define_insn "movhi" [(set (match_operand:HI 0 "general_operand" "=g") (match_operand:HI 1 "general_operand" "g"))] "" "* { if (GET_CODE (operands[1]) == CONST_INT) { if (operands[1] == const0_rtx && (DATA_REG_P (operands[0]) || GET_CODE (operands[0]) == MEM) /* clr insns on 68000 read before writing. This isn't so on the 68010, but we have no alternative for it. */ && (TARGET_68020 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) return \"clr%.w %0\"; else if (DATA_REG_P (operands[0]) && INTVAL (operands[1]) < 128 && INTVAL (operands[1]) >= -128) { #if defined(MOTOROLA) && !defined(CRDS) return \"moveq%.l %1,%0\"; #else return \"moveq %1,%0\"; #endif } else if (INTVAL (operands[1]) < 0x8000 && INTVAL (operands[1]) >= -0x8000) return \"move%.w %1,%0\"; } else if (CONSTANT_P (operands[1])) return \"move%.l %1,%0\"; #ifndef SGS_NO_LI /* Recognize the insn before a tablejump, one that refers to a table of offsets. Such an insn will need to refer to a label on the insn. So output one. Use the label-number of the table of offsets to generate this label. */ if (GET_CODE (operands[1]) == MEM && GET_CODE (XEXP (operands[1], 0)) == PLUS && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF || GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF) && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) != PLUS) { rtx labelref; if (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF) labelref = XEXP (XEXP (operands[1], 0), 0); else labelref = XEXP (XEXP (operands[1], 0), 1); #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES) #ifdef SGS asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\", CODE_LABEL_NUMBER (XEXP (labelref, 0))); #else /* not SGS */ asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\", CODE_LABEL_NUMBER (XEXP (labelref, 0))); #endif /* not SGS */ #else /* SGS_SWITCH_TABLES or not MOTOROLA */ ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\", CODE_LABEL_NUMBER (XEXP (labelref, 0))); #ifdef SGS_SWITCH_TABLES /* Set flag saying we need to define the symbol LD%n (with value L%n-LI%n) at the end of the switch table. */ switch_table_difference_label_flag = 1; #endif /* SGS_SWITCH_TABLES */ #endif /* SGS_SWITCH_TABLES or not MOTOROLA */ } #endif /* SGS_NO_LI */ return \"move%.w %1,%0\"; }") (define_insn "movstricthi" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) (match_operand:HI 1 "general_operand" "rmn"))] "" "* { if (GET_CODE (operands[1]) == CONST_INT) { if (operands[1] == const0_rtx && (DATA_REG_P (operands[0]) || GET_CODE (operands[0]) == MEM) /* clr insns on 68000 read before writing. This isn't so on the 68010, but we have no alternative for it. */ && (TARGET_68020 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) return \"clr%.w %0\"; } return \"move%.w %1,%0\"; }") (define_insn "movqi" [(set (match_operand:QI 0 "general_operand" "=d,*a,m,m,?*a") (match_operand:QI 1 "general_operand" "dmi*a,d*a,dmi,?*a,m"))] "" "* { rtx xoperands[4]; /* This is probably useless, since it loses for pushing a struct of several bytes a byte at a time. */ if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx) { xoperands[1] = operands[1]; xoperands[2] = gen_rtx (MEM, QImode, gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx)); /* Just pushing a byte puts it in the high byte of the halfword. */ /* We must put it in the low-order, high-numbered byte. */ output_asm_insn (\"move%.b %1,%-\;move%.b %@,%2\", xoperands); return \"\"; } /* Moving a byte into an address register is not possible. */ /* Use d0 as an intermediate, but don't clobber its contents. */ if (ADDRESS_REG_P (operands[0]) && GET_CODE (operands[1]) == MEM) { /* ??? For 2.5, don't allow this choice and use secondary reloads instead. See if the address register is used in the address. If it is, we have to generate a more complex sequence than those below. */ if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, operands[1], NULL_RTX)) { /* See if the stack pointer is used in the address. If it isn't, we can push d0 or d1 (the insn can't use both of them) on the stack, perform our move into d0/d1, copy the byte from d0/1, and pop d0/1. */ if (! reg_mentioned_p (stack_pointer_rtx, operands[1])) { if (refers_to_regno_p (0, 1, operands[1], NULL_RTX)) return \"move%.l %/d0,%-\;move%.b %1,%/d0\;move%.l %/d0,%0\;move%.l %+,%/d0\"; else return \"move%.l %/d1,%-\;move%.b %1,%/d1\;move%.l %/d1,%0\;move%.l %+,%/d1\"; } else { /* Otherwise, we know that d0 cannot be used in the address (since sp and one address register is). Assume that sp is being used as a base register and replace the address register that is our operand[0] with d0. */ rtx reg_map[FIRST_PSEUDO_REGISTER]; int i; for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) reg_map[i] = 0; reg_map[REGNO (operands[0])] = gen_rtx (REG, Pmode, 0); operands[1] = copy_rtx (operands[1]); replace_regs (operands[1], reg_map, FIRST_PSEUDO_REGISTER, 0); return \"exg %/d0,%0\;move%.b %1,%/d0\;exg %/d0,%0\"; } } /* If the address of operand 1 uses d0, choose d1 as intermediate. */ if (refers_to_regno_p (0, 1, operands[1], NULL_RTX)) return \"exg %/d1,%0\;move%.b %1,%/d1\;exg %/d1,%0\"; /* Otherwise d0 is usable. (An effective address on the 68k can't use two d-regs.) */ else return \"exg %/d0,%0\;move%.b %1,%/d0\;exg %/d0,%0\"; } /* Likewise for moving from an address reg. */ if (ADDRESS_REG_P (operands[1]) && GET_CODE (operands[0]) == MEM) { /* ??? For 2.5, don't allow this choice and use secondary reloads instead. See if the address register is used in the address. If it is, we have to generate a more complex sequence than those below. */ if (refers_to_regno_p (REGNO (operands[1]), REGNO (operands[1]) + 1, operands[0], NULL_RTX)) { /* See if the stack pointer is used in the address. If it isn't, we can push d0 or d1 (the insn can't use both of them) on the stack, copy the byte to d0/1, perform our move from d0/d1, and pop d0/1. */ if (! reg_mentioned_p (stack_pointer_rtx, operands[0])) { if (refers_to_regno_p (0, 1, operands[0], NULL_RTX)) return \"move%.l %/d0,%-\;move%.l %1,%/d0\;move%.b %/d0,%0\;move%.l %+,%/d0\"; else return \"move%.l %/d1,%-\;move%.l %1,%/d1\;move%.b %/d1,%0\;move%.l %+,%/d1\"; } else { /* Otherwise, we know that d0 cannot be used in the address (since sp and one address register is). Assume that sp is being used as a base register and replace the address register that is our operand[1] with d0. */ rtx reg_map[FIRST_PSEUDO_REGISTER]; int i; for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) reg_map[i] = 0; reg_map[REGNO (operands[1])] = gen_rtx (REG, Pmode, 0); operands[0] = copy_rtx (operands[0]); replace_regs (operands[0], reg_map, FIRST_PSEUDO_REGISTER, 0); return \"exg %/d0,%1\;move%.b %/d0,%0\;exg %/d0,%1\"; } } if (refers_to_regno_p (0, 1, operands[0], NULL_RTX)) return \"exg %/d1,%1\;move%.b %/d1,%0\;exg %/d1,%1\"; else return \"exg %/d0,%1\;move%.b %/d0,%0\;exg %/d0,%1\"; } /* clr and st insns on 68000 read before writing. This isn't so on the 68010, but we have no alternative for it. */ if (TARGET_68020 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) { if (operands[1] == const0_rtx) return \"clr%.b %0\"; if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == -1) { CC_STATUS_INIT; return \"st %0\"; } } if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) return \"move%.l %1,%0\"; if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) return \"move%.w %1,%0\"; return \"move%.b %1,%0\"; }") (define_insn "movstrictqi" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) (match_operand:QI 1 "general_operand" "dmn"))] "" "* { if (operands[1] == const0_rtx /* clr insns on 68000 read before writing. This isn't so on the 68010, but we have no alternative for it. */ && (TARGET_68020 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) return \"clr%.b %0\"; return \"move%.b %1,%0\"; }") (define_insn "movsf" [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm") (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))] ; [(set (match_operand:SF 0 "general_operand" "=rmf") ; (match_operand:SF 1 "general_operand" "rmfF"))] "" "* { if (which_alternative >= 4) return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\"; if (FPA_REG_P (operands[0])) { if (FPA_REG_P (operands[1])) return \"fpmove%.s %x1,%x0\"; else if (GET_CODE (operands[1]) == CONST_DOUBLE) return output_move_const_single (operands); else if (FP_REG_P (operands[1])) return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\"; return \"fpmove%.s %x1,%x0\"; } if (FPA_REG_P (operands[1])) { if (FP_REG_P (operands[0])) return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\"; else return \"fpmove%.s %x1,%x0\"; } if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) return \"f%$move%.x %1,%0\"; else if (ADDRESS_REG_P (operands[1])) return \"move%.l %1,%-\;f%$move%.s %+,%0\"; else if (GET_CODE (operands[1]) == CONST_DOUBLE) return output_move_const_single (operands); return \"f%$move%.s %f1,%0\"; } if (FP_REG_P (operands[1])) { if (ADDRESS_REG_P (operands[0])) return \"fmove%.s %1,%-\;move%.l %+,%0\"; return \"fmove%.s %f1,%0\"; } return \"move%.l %1,%0\"; }") (define_insn "movdf" [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm") (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))] ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>") ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))] "" "* { if (which_alternative == 7) return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\"; if (FPA_REG_P (operands[0])) { if (GET_CODE (operands[1]) == CONST_DOUBLE) return output_move_const_double (operands); if (FP_REG_P (operands[1])) return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\"; return \"fpmove%.d %x1,%x0\"; } else if (FPA_REG_P (operands[1])) { if (FP_REG_P(operands[0])) return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\"; else return \"fpmove%.d %x1,%x0\"; } if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) return \"f%&move%.x %1,%0\"; if (REG_P (operands[1])) { rtx xoperands[2]; xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); output_asm_insn (\"move%.l %1,%-\", xoperands); output_asm_insn (\"move%.l %1,%-\", operands); return \"f%&move%.d %+,%0\"; } if (GET_CODE (operands[1]) == CONST_DOUBLE) return output_move_const_double (operands); return \"f%&move%.d %f1,%0\"; } else if (FP_REG_P (operands[1])) { if (REG_P (operands[0])) { output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); return \"move%.l %+,%0\"; } else return \"fmove%.d %f1,%0\"; } return output_move_double (operands); } ") (define_expand "movxf" [(set (match_operand:XF 0 "nonimmediate_operand" "") (match_operand:XF 1 "general_operand" ""))] "" " { if (CONSTANT_P (operands[1])) { operands[1] = force_const_mem (XFmode, operands[1]); if (! memory_address_p (XFmode, XEXP (operands[1], 0)) && ! reload_in_progress) operands[1] = change_address (operands[1], XFmode, XEXP (operands[1], 0)); } }") (define_insn "" [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f") (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))] "TARGET_68881" "* { if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) return \"fmove%.x %1,%0\"; if (REG_P (operands[1])) { rtx xoperands[2]; xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); output_asm_insn (\"move%.l %1,%-\", xoperands); xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); output_asm_insn (\"move%.l %1,%-\", xoperands); output_asm_insn (\"move%.l %1,%-\", operands); return \"fmove%.x %+,%0\"; } if (GET_CODE (operands[1]) == CONST_DOUBLE) return \"fmove%.x %1,%0\"; return \"fmove%.x %f1,%0\"; } if (REG_P (operands[0])) { output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands); operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); output_asm_insn (\"move%.l %+,%0\", operands); operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); return \"move%.l %+,%0\"; } return \"fmove%.x %f1,%0\"; } ") (define_insn "" [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>") (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))] "! TARGET_68881" "* { if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) return \"fmove%.x %1,%0\"; if (REG_P (operands[1])) { rtx xoperands[2]; xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); output_asm_insn (\"move%.l %1,%-\", xoperands); xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); output_asm_insn (\"move%.l %1,%-\", xoperands); output_asm_insn (\"move%.l %1,%-\", operands); return \"fmove%.x %+,%0\"; } if (GET_CODE (operands[1]) == CONST_DOUBLE) return \"fmove%.x %1,%0\"; return \"fmove%.x %f1,%0\"; } if (FP_REG_P (operands[1])) { if (REG_P (operands[0])) { output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands); operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); output_asm_insn (\"move%.l %+,%0\", operands); operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); return \"move%.l %+,%0\"; } else return \"fmove%.x %f1,%0\"; } return output_move_double (operands); } ") ;; movdi can apply to fp regs in some cases (define_insn "movdi" ;; Let's see if it really still needs to handle fp regs, and, if so, why. [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm") (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))] ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm") ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))] ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f") ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))] "" "* { if (which_alternative == 8) return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\"; if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1])) return \"fpmove%.d %x1,%x0\"; if (FP_REG_P (operands[0])) { if (FP_REG_P (operands[1])) return \"fmove%.x %1,%0\"; if (REG_P (operands[1])) { rtx xoperands[2]; xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); output_asm_insn (\"move%.l %1,%-\", xoperands); output_asm_insn (\"move%.l %1,%-\", operands); return \"fmove%.d %+,%0\"; } if (GET_CODE (operands[1]) == CONST_DOUBLE) return output_move_const_double (operands); return \"fmove%.d %f1,%0\"; } else if (FP_REG_P (operands[1])) { if (REG_P (operands[0])) { output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); return \"move%.l %+,%0\"; } else return \"fmove%.d %f1,%0\"; } return output_move_double (operands); } ") ;; Thus goes after the move instructions ;; because the move instructions are better (require no spilling) ;; when they can apply. It goes before the add/sub insns ;; so we will prefer it to them. (define_insn "pushasi" [(set (match_operand:SI 0 "push_operand" "=m") (match_operand:SI 1 "address_operand" "p"))] "" "pea %a1") ;; truncation instructions (define_insn "truncsiqi2" [(set (match_operand:QI 0 "general_operand" "=dm,d") (truncate:QI (match_operand:SI 1 "general_operand" "doJ,i")))] "" "* { if (GET_CODE (operands[0]) == REG) { /* Must clear condition codes, since the move.l bases them on the entire 32 bits, not just the desired 8 bits. */ CC_STATUS_INIT; return \"move%.l %1,%0\"; } if (GET_CODE (operands[1]) == MEM) operands[1] = adj_offsettable_operand (operands[1], 3); return \"move%.b %1,%0\"; }") (define_insn "trunchiqi2" [(set (match_operand:QI 0 "general_operand" "=dm,d") (truncate:QI (match_operand:HI 1 "general_operand" "doJ,i")))] "" "* { if (GET_CODE (operands[0]) == REG && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[1]) == CONST_INT)) { /* Must clear condition codes, since the move.w bases them on the entire 16 bits, not just the desired 8 bits. */ CC_STATUS_INIT; return \"move%.w %1,%0\"; } if (GET_CODE (operands[0]) == REG) { /* Must clear condition codes, since the move.l bases them on the entire 32 bits, not just the desired 8 bits. */ CC_STATUS_INIT; return \"move%.l %1,%0\"; } if (GET_CODE (operands[1]) == MEM) operands[1] = adj_offsettable_operand (operands[1], 1); return \"move%.b %1,%0\"; }") (define_insn "truncsihi2" [(set (match_operand:HI 0 "general_operand" "=dm,d") (truncate:HI (match_operand:SI 1 "general_operand" "roJ,i")))] "" "* { if (GET_CODE (operands[0]) == REG) { /* Must clear condition codes, since the move.l bases them on the entire 32 bits, not just the desired 8 bits. */ CC_STATUS_INIT; return \"move%.l %1,%0\"; } if (GET_CODE (operands[1]) == MEM) operands[1] = adj_offsettable_operand (operands[1], 2); return \"move%.w %1,%0\"; }") ;; zero extension instructions (define_expand "zero_extendhisi2" [(set (match_operand:SI 0 "register_operand" "") (const_int 0)) (set (strict_low_part (match_dup 2)) (match_operand:HI 1 "general_operand" ""))] "" " { operands[1] = make_safe_from (operands[1], operands[0]); if (GET_CODE (operands[0]) == SUBREG) operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]), SUBREG_WORD (operands[0])); else operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0); }") (define_expand "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "") (const_int 0)) (set (strict_low_part (match_dup 2)) (match_operand:QI 1 "general_operand" ""))] "" " { operands[1] = make_safe_from (operands[1], operands[0]); if (GET_CODE (operands[0]) == SUBREG) operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]), SUBREG_WORD (operands[0])); else operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0); }") (define_expand "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "") (const_int 0)) (set (strict_low_part (match_dup 2)) (match_operand:QI 1 "general_operand" ""))] "" " { operands[1] = make_safe_from (operands[1], operands[0]); if (GET_CODE (operands[0]) == SUBREG) operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]), SUBREG_WORD (operands[0])); else operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0); }") ;; Patterns to recognize zero-extend insns produced by the combiner. ;; We don't allow both operands in memory, because of aliasing problems. ;; Explicitly disallow two memory operands via the condition since reloading ;; of this case will result in worse code than the uncombined patterns. (define_insn "" [(set (match_operand:SI 0 "general_operand" "=do<>,d<") (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" "* { if (DATA_REG_P (operands[0])) { if (GET_CODE (operands[1]) == REG && REGNO (operands[0]) == REGNO (operands[1])) return \"and%.l %#0xFFFF,%0\"; if (reg_mentioned_p (operands[0], operands[1])) return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\"; return \"clr%.l %0\;move%.w %1,%0\"; } else if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) return \"move%.w %1,%0\;clr%.w %0\"; else if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == POST_INC) return \"clr%.w %0\;move%.w %1,%0\"; else { output_asm_insn (\"clr%.w %0\", operands); operands[0] = adj_offsettable_operand (operands[0], 2); return \"move%.w %1,%0\"; } }") (define_insn "" [(set (match_operand:HI 0 "general_operand" "=do<>,d") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" "* { if (DATA_REG_P (operands[0])) { if (GET_CODE (operands[1]) == REG && REGNO (operands[0]) == REGNO (operands[1])) return \"and%.w %#0xFF,%0\"; if (reg_mentioned_p (operands[0], operands[1])) return \"move%.b %1,%0\;and%.w %#0xFF,%0\"; return \"clr%.w %0\;move%.b %1,%0\"; } else if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) { if (REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM) { output_asm_insn (\"clr%.w %-\", operands); operands[0] = gen_rtx (MEM, GET_MODE (operands[0]), plus_constant (stack_pointer_rtx, 1)); return \"move%.b %1,%0\"; } else return \"move%.b %1,%0\;clr%.b %0\"; } else if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == POST_INC) return \"clr%.b %0\;move%.b %1,%0\"; else { output_asm_insn (\"clr%.b %0\", operands); operands[0] = adj_offsettable_operand (operands[0], 1); return \"move%.b %1,%0\"; } }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=do<>,d") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" "* { if (DATA_REG_P (operands[0])) { if (GET_CODE (operands[1]) == REG && REGNO (operands[0]) == REGNO (operands[1])) return \"and%.l %#0xFF,%0\"; if (reg_mentioned_p (operands[0], operands[1])) return \"move%.b %1,%0\;and%.l %#0xFF,%0\"; return \"clr%.l %0\;move%.b %1,%0\"; } else if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) { operands[0] = XEXP (XEXP (operands[0], 0), 0); #ifdef MOTOROLA #ifdef SGS return \"clr%.l -(%0)\;move%.b %1,3(%0)\"; #else return \"clr%.l -(%0)\;move%.b %1,(3,%0)\"; #endif #else return \"clrl %0@-\;moveb %1,%0@(3)\"; #endif } else if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == POST_INC) { operands[0] = XEXP (XEXP (operands[0], 0), 0); #ifdef MOTOROLA #ifdef SGS return \"clr%.l (%0)+\;move%.b %1,-1(%0)\"; #else return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\"; #endif #else return \"clrl %0@+\;moveb %1,%0@(-1)\"; #endif } else { output_asm_insn (\"clr%.l %0\", operands); operands[0] = adj_offsettable_operand (operands[0], 3); return \"move%.b %1,%0\"; } }") ;; sign extension instructions (define_insn "extendhisi2" [(set (match_operand:SI 0 "general_operand" "=*d,a") (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,rm")))] "" "* { if (ADDRESS_REG_P (operands[0])) return \"move%.w %1,%0\"; return \"ext%.l %0\"; }") (define_insn "extendqihi2" [(set (match_operand:HI 0 "general_operand" "=d") (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))] "" "ext%.w %0") (define_insn "extendqisi2" [(set (match_operand:SI 0 "general_operand" "=d") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))] "TARGET_68020" "extb%.l %0") ;; Conversions between float and double. (define_expand "extendsfdf2" [(set (match_operand:DF 0 "general_operand" "") (float_extend:DF (match_operand:SF 1 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=x,y") (float_extend:DF (match_operand:SF 1 "general_operand" "xH,rmF")))] "TARGET_FPA" "fpstod %w1,%0") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=*fdm,f") (float_extend:DF (match_operand:SF 1 "general_operand" "f,dmF")))] "TARGET_68881" "* { if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) { if (REGNO (operands[0]) == REGNO (operands[1])) { /* Extending float to double in an fp-reg is a no-op. NOTICE_UPDATE_CC has already assumed that the cc will be set. So cancel what it did. */ cc_status = cc_prev_status; return \"\"; } return \"f%&move%.x %1,%0\"; } if (FP_REG_P (operands[0])) return \"f%&move%.s %f1,%0\"; if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1])) { output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); return \"move%.l %+,%0\"; } return \"fmove%.d %f1,%0\"; }") ;; This cannot output into an f-reg because there is no way to be ;; sure of truncating in that case. ;; But on the Sun FPA, we can be sure. (define_expand "truncdfsf2" [(set (match_operand:SF 0 "general_operand" "") (float_truncate:SF (match_operand:DF 1 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=x,y") (float_truncate:SF (match_operand:DF 1 "general_operand" "xH,rmF")))] "TARGET_FPA" "fpdtos %y1,%0") ;; On the '040 we can truncate in a register accurately and easily. (define_insn "" [(set (match_operand:SF 0 "general_operand" "=f") (float_truncate:SF (match_operand:DF 1 "general_operand" "fmG")))] "TARGET_68040_ONLY" "* { if (FP_REG_P (operands[1])) return \"f%$move%.x %1,%0\"; return \"f%$move%.d %f1,%0\"; }") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=dm") (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] "TARGET_68881" "fmove%.s %f1,%0") ;; Conversion between fixed point and floating point. ;; Note that among the fix-to-float insns ;; the ones that start with SImode come first. ;; That is so that an operand that is a CONST_INT ;; (and therefore lacks a specific machine mode). ;; will be recognized as SImode (which is always valid) ;; rather than as QImode or HImode. (define_expand "floatsisf2" [(set (match_operand:SF 0 "general_operand" "") (float:SF (match_operand:SI 1 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=y,x") (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))] "TARGET_FPA" "fpltos %1,%0") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=f") (float:SF (match_operand:SI 1 "general_operand" "dmi")))] "TARGET_68881" "f%$move%.l %1,%0") (define_expand "floatsidf2" [(set (match_operand:DF 0 "general_operand" "") (float:DF (match_operand:SI 1 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=y,x") (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))] "TARGET_FPA" "fpltod %1,%0") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=f") (float:DF (match_operand:SI 1 "general_operand" "dmi")))] "TARGET_68881" "f%&move%.l %1,%0") (define_insn "floathisf2" [(set (match_operand:SF 0 "general_operand" "=f") (float:SF (match_operand:HI 1 "general_operand" "dmn")))] "TARGET_68881" "f%$move%.w %1,%0") (define_insn "floathidf2" [(set (match_operand:DF 0 "general_operand" "=f") (float:DF (match_operand:HI 1 "general_operand" "dmn")))] "TARGET_68881" "fmove%.w %1,%0") (define_insn "floatqisf2" [(set (match_operand:SF 0 "general_operand" "=f") (float:SF (match_operand:QI 1 "general_operand" "dmn")))] "TARGET_68881" "fmove%.b %1,%0") (define_insn "floatqidf2" [(set (match_operand:DF 0 "general_operand" "=f") (float:DF (match_operand:QI 1 "general_operand" "dmn")))] "TARGET_68881" "f%&move%.b %1,%0") ;; New routines to convert floating-point values to integers ;; to be used on the '040. These should be faster than trapping ;; into the kernel to emulate fintrz. They should also be faster ;; than calling the subroutines fixsfsi or fixdfsi. (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "general_operand" "=dm") (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f")))) (clobber (match_scratch:SI 2 "=d")) (clobber (match_scratch:SI 3 "=d"))] "TARGET_68881 && TARGET_68040" "* { CC_STATUS_INIT; return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\"; }") (define_insn "fix_truncdfhi2" [(set (match_operand:HI 0 "general_operand" "=dm") (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f")))) (clobber (match_scratch:SI 2 "=d")) (clobber (match_scratch:SI 3 "=d"))] "TARGET_68881 && TARGET_68040" "* { CC_STATUS_INIT; return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\"; }") (define_insn "fix_truncdfqi2" [(set (match_operand:QI 0 "general_operand" "=dm") (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f")))) (clobber (match_scratch:SI 2 "=d")) (clobber (match_scratch:SI 3 "=d"))] "TARGET_68881 && TARGET_68040" "* { CC_STATUS_INIT; return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\"; }") ;; Convert a float to a float whose value is an integer. ;; This is the first stage of converting it to an integer type. (define_insn "ftruncdf2" [(set (match_operand:DF 0 "general_operand" "=f") (fix:DF (match_operand:DF 1 "general_operand" "fFm")))] "TARGET_68881 && !TARGET_68040" "* { if (FP_REG_P (operands[1])) return \"fintrz%.x %f1,%0\"; return \"fintrz%.d %f1,%0\"; }") (define_insn "ftruncsf2" [(set (match_operand:SF 0 "general_operand" "=f") (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))] "TARGET_68881 && !TARGET_68040" "* { if (FP_REG_P (operands[1])) return \"fintrz%.x %f1,%0\"; return \"fintrz%.s %f1,%0\"; }") ;; Convert a float whose value is an integer ;; to an actual integer. Second stage of converting float to integer type. (define_insn "fixsfqi2" [(set (match_operand:QI 0 "general_operand" "=dm") (fix:QI (match_operand:SF 1 "general_operand" "f")))] "TARGET_68881" "fmove%.b %1,%0") (define_insn "fixsfhi2" [(set (match_operand:HI 0 "general_operand" "=dm") (fix:HI (match_operand:SF 1 "general_operand" "f")))] "TARGET_68881" "fmove%.w %1,%0") (define_insn "fixsfsi2" [(set (match_operand:SI 0 "general_operand" "=dm") (fix:SI (match_operand:SF 1 "general_operand" "f")))] "TARGET_68881" "fmove%.l %1,%0") (define_insn "fixdfqi2" [(set (match_operand:QI 0 "general_operand" "=dm") (fix:QI (match_operand:DF 1 "general_operand" "f")))] "TARGET_68881" "fmove%.b %1,%0") (define_insn "fixdfhi2" [(set (match_operand:HI 0 "general_operand" "=dm") (fix:HI (match_operand:DF 1 "general_operand" "f")))] "TARGET_68881" "fmove%.w %1,%0") (define_insn "fixdfsi2" [(set (match_operand:SI 0 "general_operand" "=dm") (fix:SI (match_operand:DF 1 "general_operand" "f")))] "TARGET_68881" "fmove%.l %1,%0") ;; Convert a float to an integer. ;; On the Sun FPA, this is done in one step. (define_insn "" [(set (match_operand:SI 0 "general_operand" "=x,y") (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))] "TARGET_FPA" "fpstol %w1,%0") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=x,y") (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))] "TARGET_FPA" "fpdtol %y1,%0") ;; add instructions ;; Note that the middle two alternatives are near-duplicates ;; in order to handle insns generated by reload. ;; This is needed since they are not themselves reloaded, ;; so commutativity won't apply to them. (define_insn "addsi3" [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r") (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0") (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))] "" "* { if (! operands_match_p (operands[0], operands[1])) { if (!ADDRESS_REG_P (operands[1])) { rtx tmp = operands[1]; operands[1] = operands[2]; operands[2] = tmp; } /* These insns can result from reloads to access stack slots over 64k from the frame pointer. */ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000) return \"move%.l %2,%0\;add%.l %1,%0\"; #ifdef SGS if (GET_CODE (operands[2]) == REG) return \"lea 0(%1,%2.l),%0\"; else return \"lea %c2(%1),%0\"; #else /* not SGS */ #ifdef MOTOROLA if (GET_CODE (operands[2]) == REG) return \"lea (%1,%2.l),%0\"; else return \"lea (%c2,%1),%0\"; #else /* not MOTOROLA (MIT syntax) */ if (GET_CODE (operands[2]) == REG) return \"lea %1@(0,%2:l),%0\"; else return \"lea %1@(%c2),%0\"; #endif /* not MOTOROLA */ #endif /* not SGS */ } if (GET_CODE (operands[2]) == CONST_INT) { #ifndef NO_ADDSUB_Q if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 8) return (ADDRESS_REG_P (operands[0]) ? \"addq%.w %2,%0\" : \"addq%.l %2,%0\"); if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8) { operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2])); return (ADDRESS_REG_P (operands[0]) ? \"subq%.w %2,%0\" : \"subq%.l %2,%0\"); } /* On everything except the 68000 it is faster to use two addqw instructions to add a small integer (8 < N <= 16) to an address register. Likewise for subqw.*/ if (INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 && ADDRESS_REG_P (operands[0]) && TARGET_68020) { operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); return \"addq%.w %#8,%0\;addq%.w %2,%0\"; } if (INTVAL (operands[2]) < -8 && INTVAL (operands[2]) >= -16 && ADDRESS_REG_P (operands[0]) && TARGET_68020) { operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]) - 8); return \"subq%.w %#8,%0\;subq%.w %2,%0\"; } #endif if (ADDRESS_REG_P (operands[0]) && INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) < 0x8000) return \"add%.w %2,%0\"; } return \"add%.l %2,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=a") (plus:SI (match_operand:SI 1 "general_operand" "0") (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm"))))] "" "add%.w %2,%0") (define_insn "addhi3" [(set (match_operand:HI 0 "general_operand" "=m,r") (plus:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_operand" "dn,rmn")))] "" "* { #ifndef NO_ADDSUB_Q if (GET_CODE (operands[2]) == CONST_INT) { /* If the constant would be a negative number when interpreted as HImode, make it negative. This is usually, but not always, done elsewhere in the compiler. First check for constants out of range, which could confuse us. */ if (INTVAL (operands[2]) >= 32768) operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 65536); if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 8) return \"addq%.w %2,%0\"; if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8) { operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2])); return \"subq%.w %2,%0\"; } /* On everything except the 68000 it is faster to use two addqw instructions to add a small integer (8 < N <= 16) to an address register. Likewise for subqw. */ if (INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 && ADDRESS_REG_P (operands[0]) && TARGET_68020) { operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); return \"addq%.w %#8,%0\;addq%.w %2,%0\"; } if (INTVAL (operands[2]) < -8 && INTVAL (operands[2]) >= -16 && ADDRESS_REG_P (operands[0]) && TARGET_68020) { operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]) - 8); return \"subq%.w %#8,%0\;subq%.w %2,%0\"; } } #endif return \"add%.w %2,%0\"; }") ;; These insns must use MATCH_DUP instead of the more expected ;; use of a matching constraint because the "output" here is also ;; an input, so you can't use the matching constraint. That also means ;; that you can't use the "%", so you need patterns with the matched ;; operand in both positions. (define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) (plus:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dn,rmn")))] "" "* { #ifndef NO_ADDSUB_Q if (GET_CODE (operands[1]) == CONST_INT) { /* If the constant would be a negative number when interpreted as HImode, make it negative. This is usually, but not always, done elsewhere in the compiler. First check for constants out of range, which could confuse us. */ if (INTVAL (operands[1]) >= 32768) operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 65536); if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8) return \"addq%.w %1,%0\"; if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) { operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); return \"subq%.w %1,%0\"; } /* On everything except the 68000 it is faster to use two addqw instructions to add a small integer (8 < N <= 16) to an address register. Likewise for subqw. */ if (INTVAL (operands[1]) > 8 && INTVAL (operands[1]) <= 16 && ADDRESS_REG_P (operands[0]) && TARGET_68020) { operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); return \"addq%.w %#8,%0\;addq%.w %1,%0\"; } if (INTVAL (operands[1]) < -8 && INTVAL (operands[1]) >= -16 && ADDRESS_REG_P (operands[0]) && TARGET_68020) { operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]) - 8); return \"subq%.w %#8,%0\;subq%.w %1,%0\"; } } #endif return \"add%.w %1,%0\"; }") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn") (match_dup 0)))] "" "* { #ifndef NO_ADDSUB_Q if (GET_CODE (operands[1]) == CONST_INT) { /* If the constant would be a negative number when interpreted as HImode, make it negative. This is usually, but not always, done elsewhere in the compiler. First check for constants out of range, which could confuse us. */ if (INTVAL (operands[1]) >= 32768) operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 65536); if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8) return \"addq%.w %1,%0\"; if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) { operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); return \"subq%.w %1,%0\"; } /* On everything except the 68000 it is faster to use two addqw instructions to add a small integer (8 < N <= 16) to an address register. Likewise for subqw. */ if (INTVAL (operands[1]) > 8 && INTVAL (operands[1]) <= 16 && ADDRESS_REG_P (operands[0]) && TARGET_68020) { operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); return \"addq%.w %#8,%0\;addq%.w %1,%0\"; } if (INTVAL (operands[1]) < -8 && INTVAL (operands[1]) >= -16 && ADDRESS_REG_P (operands[0]) && TARGET_68020) { operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]) - 8); return \"subq%.w %#8,%0\;subq%.w %1,%0\"; } } #endif return \"add%.w %1,%0\"; }") (define_insn "addqi3" [(set (match_operand:QI 0 "general_operand" "=m,d") (plus:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_operand" "dn,dmn")))] "" "* { #ifndef NO_ADDSUB_Q if (GET_CODE (operands[2]) == CONST_INT) { if (INTVAL (operands[2]) >= 128) operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 256); if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 8) return \"addq%.b %2,%0\"; if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8) { operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2])); return \"subq%.b %2,%0\"; } } #endif return \"add%.b %2,%0\"; }") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) (plus:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dn,dmn")))] "" "* { #ifndef NO_ADDSUB_Q if (GET_CODE (operands[1]) == CONST_INT) { if (INTVAL (operands[1]) >= 128) operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 256); if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8) return \"addq%.b %1,%0\"; if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) { operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); return \"subq%.b %1,%0\"; } } #endif return \"add%.b %1,%0\"; }") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn") (match_dup 0)))] "" "* { #ifndef NO_ADDSUB_Q if (GET_CODE (operands[1]) == CONST_INT) { if (INTVAL (operands[1]) >= 128) operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 256); if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8) return \"addq%.b %1,%0\"; if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) { operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); return \"subq%.b %1,%0\"; } } #endif return \"add%.b %1,%0\"; }") (define_expand "adddf3" [(set (match_operand:DF 0 "general_operand" "") (plus:DF (match_operand:DF 1 "general_operand" "") (match_operand:DF 2 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=x,y") (plus:DF (match_operand:DF 1 "general_operand" "%xH,y") (match_operand:DF 2 "general_operand" "xH,dmF")))] "TARGET_FPA" "* { if (rtx_equal_p (operands[0], operands[1])) return \"fpadd%.d %y2,%0\"; if (rtx_equal_p (operands[0], operands[2])) return \"fpadd%.d %y1,%0\"; if (which_alternative == 0) return \"fpadd3%.d %w2,%w1,%0\"; return \"fpadd3%.d %x2,%x1,%0\"; }") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=f") (plus:DF (match_operand:DF 1 "general_operand" "%0") (match_operand:DF 2 "general_operand" "fmG")))] "TARGET_68881" "* { if (REG_P (operands[2])) return \"f%&add%.x %2,%0\"; return \"f%&add%.d %f2,%0\"; }") (define_expand "addsf3" [(set (match_operand:SF 0 "general_operand" "") (plus:SF (match_operand:SF 1 "general_operand" "") (match_operand:SF 2 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=x,y") (plus:SF (match_operand:SF 1 "general_operand" "%xH,y") (match_operand:SF 2 "general_operand" "xH,rmF")))] "TARGET_FPA" "* { if (rtx_equal_p (operands[0], operands[1])) return \"fpadd%.s %w2,%0\"; if (rtx_equal_p (operands[0], operands[2])) return \"fpadd%.s %w1,%0\"; if (which_alternative == 0) return \"fpadd3%.s %w2,%w1,%0\"; return \"fpadd3%.s %2,%1,%0\"; }") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=f") (plus:SF (match_operand:SF 1 "general_operand" "%0") (match_operand:SF 2 "general_operand" "fdmF")))] "TARGET_68881" "* { if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) return \"f%$add%.x %2,%0\"; return \"f%$add%.s %f2,%0\"; }") ;; subtract instructions (define_insn "subsi3" [(set (match_operand:SI 0 "general_operand" "=m,r,!a,?d") (minus:SI (match_operand:SI 1 "general_operand" "0,0,a,mrIKs") (match_operand:SI 2 "general_operand" "dIKs,mrIKs,J,0")))] "" "* { if (! operands_match_p (operands[0], operands[1])) { if (operands_match_p (operands[0], operands[2])) { #ifndef NO_ADDSUB_Q if (GET_CODE (operands[1]) == CONST_INT) { if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8) return \"subq%.l %1,%0\;neg%.l %0\"; } #endif return \"sub%.l %1,%0\;neg%.l %0\"; } /* This case is matched by J, but negating -0x8000 in an lea would give an invalid displacement. So do this specially. */ if (INTVAL (operands[2]) == -0x8000) return \"move%.l %1,%0\;sub%.l %2,%0\"; #ifdef SGS return \"lea %n2(%1),%0\"; #else #ifdef MOTOROLA return \"lea (%n2,%1),%0\"; #else /* not MOTOROLA (MIT syntax) */ return \"lea %1@(%n2),%0\"; #endif /* not MOTOROLA */ #endif /* not SGS */ } if (GET_CODE (operands[2]) == CONST_INT) { #ifndef NO_ADDSUB_Q if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 8) return \"subq%.l %2,%0\"; /* Using two subqw for 8 < N <= 16 being subtracted from an address register is faster on all but 68000 */ if (INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 && ADDRESS_REG_P (operands[0]) && TARGET_68020) { operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); return \"subq%.w %#8,%0\;subq%.w %2,%0\"; } #endif if (ADDRESS_REG_P (operands[0]) && INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) < 0x8000) return \"sub%.w %2,%0\"; } return \"sub%.l %2,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=a") (minus:SI (match_operand:SI 1 "general_operand" "0") (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm"))))] "" "sub%.w %2,%0") (define_insn "subhi3" [(set (match_operand:HI 0 "general_operand" "=m,r") (minus:HI (match_operand:HI 1 "general_operand" "0,0") (match_operand:HI 2 "general_operand" "dn,rmn")))] "" "sub%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) (minus:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dn,rmn")))] "" "sub%.w %1,%0") (define_insn "subqi3" [(set (match_operand:QI 0 "general_operand" "=m,d") (minus:QI (match_operand:QI 1 "general_operand" "0,0") (match_operand:QI 2 "general_operand" "dn,dmn")))] "" "sub%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) (minus:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dn,dmn")))] "" "sub%.b %1,%0") (define_expand "subdf3" [(set (match_operand:DF 0 "general_operand" "") (minus:DF (match_operand:DF 1 "general_operand" "") (match_operand:DF 2 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=x,y,y") (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF") (match_operand:DF 2 "general_operand" "xH,dmF,0")))] "TARGET_FPA" "* { if (rtx_equal_p (operands[0], operands[2])) return \"fprsub%.d %y1,%0\"; if (rtx_equal_p (operands[0], operands[1])) return \"fpsub%.d %y2,%0\"; if (which_alternative == 0) return \"fpsub3%.d %w2,%w1,%0\"; return \"fpsub3%.d %x2,%x1,%0\"; }") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=f") (minus:DF (match_operand:DF 1 "general_operand" "0") (match_operand:DF 2 "general_operand" "fmG")))] "TARGET_68881" "* { if (REG_P (operands[2])) return \"f%&sub%.x %2,%0\"; return \"f%&sub%.d %f2,%0\"; }") (define_expand "subsf3" [(set (match_operand:SF 0 "general_operand" "") (minus:SF (match_operand:SF 1 "general_operand" "") (match_operand:SF 2 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=x,y,y") (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF") (match_operand:SF 2 "general_operand" "xH,rmF,0")))] "TARGET_FPA" "* { if (rtx_equal_p (operands[0], operands[2])) return \"fprsub%.s %w1,%0\"; if (rtx_equal_p (operands[0], operands[1])) return \"fpsub%.s %w2,%0\"; if (which_alternative == 0) return \"fpsub3%.s %w2,%w1,%0\"; return \"fpsub3%.s %2,%1,%0\"; }") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=f") (minus:SF (match_operand:SF 1 "general_operand" "0") (match_operand:SF 2 "general_operand" "fdmF")))] "TARGET_68881" "* { if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) return \"f%$sub%.x %2,%0\"; return \"f%$sub%.s %f2,%0\"; }") ;; multiply instructions (define_insn "mulhi3" [(set (match_operand:HI 0 "general_operand" "=d") (mult:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "dmn")))] "" "* { #if defined(MOTOROLA) && !defined(CRDS) return \"muls%.w %2,%0\"; #else return \"muls %2,%0\"; #endif }") (define_insn "mulhisi3" [(set (match_operand:SI 0 "general_operand" "=d") (mult:SI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%0")) (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm"))))] "" "* { #if defined(MOTOROLA) && !defined(CRDS) return \"muls%.w %2,%0\"; #else return \"muls %2,%0\"; #endif }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d") (mult:SI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%0")) (match_operand:SI 2 "const_int_operand" "n")))] "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff" "* { #if defined(MOTOROLA) && !defined(CRDS) return \"muls%.w %2,%0\"; #else return \"muls %2,%0\"; #endif }") (define_insn "mulsi3" [(set (match_operand:SI 0 "general_operand" "=d") (mult:SI (match_operand:SI 1 "general_operand" "%0") (match_operand:SI 2 "general_operand" "dmsK")))] "TARGET_68020" "muls%.l %2,%0") (define_insn "umulhisi3" [(set (match_operand:SI 0 "general_operand" "=d") (mult:SI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%0")) (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm"))))] "" "* { #if defined(MOTOROLA) && !defined(CRDS) return \"mulu%.w %2,%0\"; #else return \"mulu %2,%0\"; #endif }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d") (mult:SI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%0")) (match_operand:SI 2 "const_int_operand" "n")))] "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff" "* { #if defined(MOTOROLA) && !defined(CRDS) return \"mulu%.w %2,%0\"; #else return \"mulu %2,%0\"; #endif }") ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the ;; proper matching constraint. This is because the matching is between ;; the high-numbered word of the DImode operand[0] and operand[1]. (define_expand "umulsidi3" [(parallel [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1) (mult:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "nonimmediate_operand" ""))) (set (subreg:SI (match_dup 0) 0) (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) (zero_extend:DI (match_dup 2))) (const_int 32))))])] "TARGET_68020" "") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (mult:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "nonimmediate_operand" "dm"))) (set (match_operand:SI 3 "register_operand" "=d") (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) (zero_extend:DI (match_dup 2))) (const_int 32))))] "TARGET_68020" "mulu%.l %2,%3:%0") ; Match immediate case. For 2.4 only match things < 2^31. ; It's tricky with larger values in these patterns since we need to match ; values between the two parallel multiplies, between a CONST_DOUBLE and ; a CONST_INT. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (mult:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "const_int_operand" "n"))) (set (match_operand:SI 3 "register_operand" "=d") (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) (match_dup 2)) (const_int 32))))] "TARGET_68020 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff" "mulu%.l %2,%3:%0") (define_expand "mulsidi3" [(parallel [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1) (mult:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "nonimmediate_operand" ""))) (set (subreg:SI (match_dup 0) 0) (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) (sign_extend:DI (match_dup 2))) (const_int 32))))])] "TARGET_68020" "") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (mult:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "nonimmediate_operand" "dm"))) (set (match_operand:SI 3 "register_operand" "=d") (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) (sign_extend:DI (match_dup 2))) (const_int 32))))] "TARGET_68020" "muls%.l %2,%3:%0") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (mult:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "const_int_operand" "n"))) (set (match_operand:SI 3 "register_operand" "=d") (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) (match_dup 2)) (const_int 32))))] "TARGET_68020 /* This test is a noop on 32 bit machines, but important for a cross-compiler hosted on 64-bit machines. */ && INTVAL (operands[2]) <= 0x7fffffff && INTVAL (operands[2]) >= -0x80000000" "muls%.l %2,%3:%0") (define_expand "muldf3" [(set (match_operand:DF 0 "general_operand" "") (mult:DF (match_operand:DF 1 "general_operand" "") (match_operand:DF 2 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=x,y") (mult:DF (match_operand:DF 1 "general_operand" "%xH,y") (match_operand:DF 2 "general_operand" "xH,rmF")))] "TARGET_FPA" "* { if (rtx_equal_p (operands[1], operands[2])) return \"fpsqr%.d %y1,%0\"; if (rtx_equal_p (operands[0], operands[1])) return \"fpmul%.d %y2,%0\"; if (rtx_equal_p (operands[0], operands[2])) return \"fpmul%.d %y1,%0\"; if (which_alternative == 0) return \"fpmul3%.d %w2,%w1,%0\"; return \"fpmul3%.d %x2,%x1,%0\"; }") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=f") (mult:DF (match_operand:DF 1 "general_operand" "%0") (match_operand:DF 2 "general_operand" "fmG")))] "TARGET_68881" "* { if (GET_CODE (operands[2]) == CONST_DOUBLE && floating_exact_log2 (operands[2]) && !TARGET_68040) { int i = floating_exact_log2 (operands[2]); operands[2] = gen_rtx (CONST_INT, VOIDmode, i); return \"fscale%.l %2,%0\"; } if (REG_P (operands[2])) return \"f%&mul%.x %2,%0\"; return \"f%&mul%.d %f2,%0\"; }") (define_expand "mulsf3" [(set (match_operand:SF 0 "general_operand" "") (mult:SF (match_operand:SF 1 "general_operand" "") (match_operand:SF 2 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=x,y") (mult:SF (match_operand:SF 1 "general_operand" "%xH,y") (match_operand:SF 2 "general_operand" "xH,rmF")))] "TARGET_FPA" "* { if (rtx_equal_p (operands[1], operands[2])) return \"fpsqr%.s %w1,%0\"; if (rtx_equal_p (operands[0], operands[1])) return \"fpmul%.s %w2,%0\"; if (rtx_equal_p (operands[0], operands[2])) return \"fpmul%.s %w1,%0\"; if (which_alternative == 0) return \"fpmul3%.s %w2,%w1,%0\"; return \"fpmul3%.s %2,%1,%0\"; }") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=f") (mult:SF (match_operand:SF 1 "general_operand" "%0") (match_operand:SF 2 "general_operand" "fdmF")))] "TARGET_68881" "* { #ifdef FSGLMUL_USE_S if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) return (TARGET_68040_ONLY ? \"fsmul%.s %2,%0\" : \"fsglmul%.s %2,%0\"); #else if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) return (TARGET_68040_ONLY ? \"fsmul%.x %2,%0\" : \"fsglmul%.x %2,%0\"); #endif return (TARGET_68040_ONLY ? \"fsmul%.s %f2,%0\" : \"fsglmul%.s %f2,%0\"); }") ;; divide instructions (define_insn "divhi3" [(set (match_operand:HI 0 "general_operand" "=d") (div:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "dmn")))] "" "* { #ifdef MOTOROLA return \"ext%.l %0\;divs%.w %2,%0\"; #else return \"extl %0\;divs %2,%0\"; #endif }") ;; These patterns don't work because the divs instruction is undefined if ;; the quotient is more than 16 bits. This valid C would be miscompiled: ;; int n; short d; unsigned short q; ... q = (unsigned int) (n / d); ;; Imagine what happens when n = 100000 and d = 1. ;;(define_insn "divhisi3" ;; [(set (match_operand:HI 0 "general_operand" "=d") ;; (truncate:HI ;; (div:SI ;; (match_operand:SI 1 "general_operand" "0") ;; (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] ;; "" ;; "* ;;{ ;;#ifdef MOTOROLA ;; return \"divs%.w %2,%0\"; ;;#else ;; return \"divs %2,%0\"; ;;#endif ;;}") ;;(define_insn "" ;; [(set (match_operand:HI 0 "general_operand" "=d") ;; (truncate:HI (div:SI (match_operand:SI 1 "general_operand" "0") ;; (match_operand:SI 2 "const_int_operand" "n"))))] ;; "" ;; "* ;;{ ;;#ifdef MOTOROLA ;; return \"divs%.w %2,%0\"; ;;#else ;; return \"divs %2,%0\"; ;;#endif ;;}") (define_insn "udivhi3" [(set (match_operand:HI 0 "general_operand" "=d") (udiv:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "dmn")))] "" "* { #ifdef MOTOROLA return \"and%.l %#0xFFFF,%0\;divu%.w %2,%0\"; #else return \"andl %#0xFFFF,%0\;divu %2,%0\"; #endif }") ;; See comment before divhisi3 why these are commented out. ;;(define_insn "udivhisi3" ;; [(set (match_operand:HI 0 "general_operand" "=d") ;; (truncate:HI ;; (udiv:SI ;; (match_operand:SI 1 "general_operand" "0") ;; (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] ;; "" ;; "* ;;{ ;;#ifdef MOTOROLA ;; return \"divu%.w %2,%0\"; ;;#else ;; return \"divu %2,%0\"; ;;#endif ;;}") ;;(define_insn "" ;; [(set (match_operand:HI 0 "general_operand" "=d") ;; (truncate:HI (udiv:SI (match_operand:SI 1 "general_operand" "0") ;; (match_operand:SI 2 "const_int_operand" "n"))))] ;; "" ;; "* ;;{ ;;#ifdef MOTOROLA ;; return \"divu%.w %2,%0\"; ;;#else ;; return \"divu %2,%0\"; ;;#endif ;;}") (define_expand "divdf3" [(set (match_operand:DF 0 "general_operand" "") (div:DF (match_operand:DF 1 "general_operand" "") (match_operand:DF 2 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=x,y,y") (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF") (match_operand:DF 2 "general_operand" "xH,rmF,0")))] "TARGET_FPA" "* { if (rtx_equal_p (operands[0], operands[2])) return \"fprdiv%.d %y1,%0\"; if (rtx_equal_p (operands[0], operands[1])) return \"fpdiv%.d %y2,%0\"; if (which_alternative == 0) return \"fpdiv3%.d %w2,%w1,%0\"; return \"fpdiv3%.d %x2,%x1,%x0\"; }") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=f") (div:DF (match_operand:DF 1 "general_operand" "0") (match_operand:DF 2 "general_operand" "fmG")))] "TARGET_68881" "* { if (REG_P (operands[2])) return \"f%&div%.x %2,%0\"; return \"f%&div%.d %f2,%0\"; }") (define_expand "divsf3" [(set (match_operand:SF 0 "general_operand" "") (div:SF (match_operand:SF 1 "general_operand" "") (match_operand:SF 2 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=x,y,y") (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF") (match_operand:SF 2 "general_operand" "xH,rmF,0")))] "TARGET_FPA" "* { if (rtx_equal_p (operands[0], operands[1])) return \"fpdiv%.s %w2,%0\"; if (rtx_equal_p (operands[0], operands[2])) return \"fprdiv%.s %w1,%0\"; if (which_alternative == 0) return \"fpdiv3%.s %w2,%w1,%0\"; return \"fpdiv3%.s %2,%1,%0\"; }") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=f") (div:SF (match_operand:SF 1 "general_operand" "0") (match_operand:SF 2 "general_operand" "fdmF")))] "TARGET_68881" "* { #ifdef FSGLDIV_USE_S if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) return (TARGET_68040_ONLY ? \"fsdiv%.s %2,%0\" : \"fsgldiv%.s %2,%0\"); #else if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) return (TARGET_68040_ONLY ? \"fsdiv%.x %2,%0\" : \"fsgldiv%.x %2,%0\"); #endif return (TARGET_68040_ONLY ? \"fsdiv%.s %f2,%0\" : \"fsgldiv%.s %f2,%0\"); }") ;; Remainder instructions. (define_insn "modhi3" [(set (match_operand:HI 0 "general_operand" "=d") (mod:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "dmn")))] "" "* { /* The swap insn produces cc's that don't correspond to the result. */ CC_STATUS_INIT; #ifdef MOTOROLA return \"ext%.l %0\;divs%.w %2,%0\;swap %0\"; #else return \"extl %0\;divs %2,%0\;swap %0\"; #endif }") ;; See comment before divhisi3 why these are commented out. ;;(define_insn "modhisi3" ;; [(set (match_operand:HI 0 "general_operand" "=d") ;; (truncate:HI ;; (mod:SI ;; (match_operand:SI 1 "general_operand" "0") ;; (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] ;; "" ;; "* ;;{ ;; /* The swap insn produces cc's that don't correspond to the result. */ ;; CC_STATUS_INIT; ;;#ifdef MOTOROLA ;; return \"divs%.w %2,%0\;swap %0\"; ;;#else ;; return \"divs %2,%0\;swap %0\"; ;;#endif ;;}") ;;(define_insn "" ;; [(set (match_operand:HI 0 "general_operand" "=d") ;; (truncate:HI (mod:SI (match_operand:SI 1 "general_operand" "0") ;; (match_operand:SI 2 "const_int_operand" "n"))))] ;; "" ;; "* ;;{ ;; /* The swap insn produces cc's that don't correspond to the result. */ ;; CC_STATUS_INIT; ;;#ifdef MOTOROLA ;; return \"divs%.w %2,%0\;swap %0\"; ;;#else ;; return \"divs %2,%0\;swap %0\"; ;;#endif ;;}") (define_insn "umodhi3" [(set (match_operand:HI 0 "general_operand" "=d") (umod:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "dmn")))] "" "* { /* The swap insn produces cc's that don't correspond to the result. */ CC_STATUS_INIT; #ifdef MOTOROLA return \"and%.l %#0xFFFF,%0\;divu%.w %2,%0\;swap %0\"; #else return \"andl %#0xFFFF,%0\;divu %2,%0\;swap %0\"; #endif }") ;; See comment before divhisi3 why these are commented out. ;;(define_insn "umodhisi3" ;; [(set (match_operand:HI 0 "general_operand" "=d") ;; (truncate:HI ;; (umod:SI ;; (match_operand:SI 1 "general_operand" "0") ;; (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] ;; "" ;; "* ;;{ ;; /* The swap insn produces cc's that don't correspond to the result. */ ;; CC_STATUS_INIT; ;;#ifdef MOTOROLA ;; return \"divu%.w %2,%0\;swap %0\"; ;;#else ;; return \"divu %2,%0\;swap %0\"; ;;#endif ;;}") ;;(define_insn "" ;; [(set (match_operand:HI 0 "general_operand" "=d") ;; (truncate:HI (umod:SI (match_operand:SI 1 "general_operand" "0") ;; (match_operand:SI 2 "const_int_operand" "n"))))] ;; "" ;; "* ;;{ ;; /* The swap insn produces cc's that don't correspond to the result. */ ;; CC_STATUS_INIT; ;;#ifdef MOTOROLA ;; return \"divu%.w %2,%0\;swap %0\"; ;;#else ;; return \"divu %2,%0\;swap %0\"; ;;#endif ;;}") (define_insn "divmodsi4" [(set (match_operand:SI 0 "general_operand" "=d") (div:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "dmsK"))) (set (match_operand:SI 3 "general_operand" "=d") (mod:SI (match_dup 1) (match_dup 2)))] "TARGET_68020" "* { if (find_reg_note (insn, REG_UNUSED, operands[3])) return \"divs%.l %2,%0\"; else return \"divsl%.l %2,%3:%0\"; }") (define_insn "udivmodsi4" [(set (match_operand:SI 0 "general_operand" "=d") (udiv:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "dmsK"))) (set (match_operand:SI 3 "general_operand" "=d") (umod:SI (match_dup 1) (match_dup 2)))] "TARGET_68020" "* { if (find_reg_note (insn, REG_UNUSED, operands[3])) return \"divu%.l %2,%0\"; else return \"divul%.l %2,%3:%0\"; }") ;; logical-and instructions ;; Prevent AND from being made with sp. This doesn't exist in the machine ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we ;; can't allocate pseudos into it. (define_insn "andsi3" [(set (match_operand:SI 0 "not_sp_operand" "=m,d") (and:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_operand" "dKs,dmKs")))] "" "* { int logval; if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) | 0xffff) == 0xffffffff && (DATA_REG_P (operands[0]) || offsettable_memref_p (operands[0]))) { if (GET_CODE (operands[0]) != REG) operands[0] = adj_offsettable_operand (operands[0], 2); operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); /* Do not delete a following tstl %0 insn; that would be incorrect. */ CC_STATUS_INIT; if (operands[2] == const0_rtx) return \"clr%.w %0\"; return \"and%.w %2,%0\"; } if (GET_CODE (operands[2]) == CONST_INT && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0 && (DATA_REG_P (operands[0]) || offsettable_memref_p (operands[0]))) { if (DATA_REG_P (operands[0])) { operands[1] = gen_rtx (CONST_INT, VOIDmode, logval); } else { operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8)); operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8); } /* This does not set condition codes in a standard way. */ CC_STATUS_INIT; return \"bclr %1,%0\"; } return \"and%.l %2,%0\"; }") (define_insn "andhi3" [(set (match_operand:HI 0 "general_operand" "=m,d") (and:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_operand" "dn,dmn")))] "" "and%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) (and:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dn,dmn")))] "" "and%.w %1,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) (and:HI (match_operand:HI 1 "general_operand" "dn,dmn") (match_dup 0)))] "" "and%.w %1,%0") (define_insn "andqi3" [(set (match_operand:QI 0 "general_operand" "=m,d") (and:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_operand" "dn,dmn")))] "" "and%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) (and:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dn,dmn")))] "" "and%.b %1,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) (and:QI (match_operand:QI 1 "general_operand" "dn,dmn") (match_dup 0)))] "" "and%.b %1,%0") ;; inclusive-or instructions (define_insn "iorsi3" [(set (match_operand:SI 0 "general_operand" "=m,d") (ior:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_operand" "dKs,dmKs")))] "" "* { register int logval; if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >> 16 == 0 && (DATA_REG_P (operands[0]) || offsettable_memref_p (operands[0]))) { if (GET_CODE (operands[0]) != REG) operands[0] = adj_offsettable_operand (operands[0], 2); /* Do not delete a following tstl %0 insn; that would be incorrect. */ CC_STATUS_INIT; return \"or%.w %2,%0\"; } if (GET_CODE (operands[2]) == CONST_INT && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 && (DATA_REG_P (operands[0]) || offsettable_memref_p (operands[0]))) { if (DATA_REG_P (operands[0])) { operands[1] = gen_rtx (CONST_INT, VOIDmode, logval); } else { operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8)); operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8); } CC_STATUS_INIT; return \"bset %1,%0\"; } return \"or%.l %2,%0\"; }") (define_insn "iorhi3" [(set (match_operand:HI 0 "general_operand" "=m,d") (ior:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_operand" "dn,dmn")))] "" "or%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) (ior:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dn,dmn")))] "" "or%.w %1,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn") (match_dup 0)))] "" "or%.w %1,%0") (define_insn "iorqi3" [(set (match_operand:QI 0 "general_operand" "=m,d") (ior:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_operand" "dn,dmn")))] "" "or%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) (ior:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dn,dmn")))] "" "or%.b %1,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn") (match_dup 0)))] "" "or%.b %1,%0") ;; xor instructions (define_insn "xorsi3" [(set (match_operand:SI 0 "general_operand" "=do,m") (xor:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_operand" "di,dKs")))] "" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >> 16 == 0 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))) { if (! DATA_REG_P (operands[0])) operands[0] = adj_offsettable_operand (operands[0], 2); /* Do not delete a following tstl %0 insn; that would be incorrect. */ CC_STATUS_INIT; return \"eor%.w %2,%0\"; } return \"eor%.l %2,%0\"; }") (define_insn "xorhi3" [(set (match_operand:HI 0 "general_operand" "=dm") (xor:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "dn")))] "" "eor%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) (xor:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dn")))] "" "eor%.w %1,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) (xor:HI (match_operand:HI 1 "general_operand" "dn") (match_dup 0)))] "" "eor%.w %1,%0") (define_insn "xorqi3" [(set (match_operand:QI 0 "general_operand" "=dm") (xor:QI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "general_operand" "dn")))] "" "eor%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) (xor:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dn")))] "" "eor%.b %1,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) (xor:QI (match_operand:QI 1 "general_operand" "dn") (match_dup 0)))] "" "eor%.b %1,%0") ;; negation instructions (define_insn "negsi2" [(set (match_operand:SI 0 "general_operand" "=dm") (neg:SI (match_operand:SI 1 "general_operand" "0")))] "" "neg%.l %0") (define_insn "neghi2" [(set (match_operand:HI 0 "general_operand" "=dm") (neg:HI (match_operand:HI 1 "general_operand" "0")))] "" "neg%.w %0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) (neg:HI (match_dup 0)))] "" "neg%.w %0") (define_insn "negqi2" [(set (match_operand:QI 0 "general_operand" "=dm") (neg:QI (match_operand:QI 1 "general_operand" "0")))] "" "neg%.b %0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) (neg:QI (match_dup 0)))] "" "neg%.b %0") (define_expand "negsf2" [(set (match_operand:SF 0 "general_operand" "") (neg:SF (match_operand:SF 1 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=x,y") (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))] "TARGET_FPA" "fpneg%.s %w1,%0") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=f,d") (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))] "TARGET_68881" "* { if (DATA_REG_P (operands[0])) { operands[1] = gen_rtx (CONST_INT, VOIDmode, 31); return \"bchg %1,%0\"; } if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) return \"f%$neg%.x %1,%0\"; return \"f%$neg%.s %f1,%0\"; }") (define_expand "negdf2" [(set (match_operand:DF 0 "general_operand" "") (neg:DF (match_operand:DF 1 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=x,y") (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))] "TARGET_FPA" "fpneg%.d %y1, %0") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=f,d") (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))] "TARGET_68881" "* { if (DATA_REG_P (operands[0])) { operands[1] = gen_rtx (CONST_INT, VOIDmode, 31); return \"bchg %1,%0\"; } if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) return \"f%&neg%.x %1,%0\"; return \"f%&neg%.d %f1,%0\"; }") ;; Sqrt instruction for the 68881 (define_insn "sqrtdf2" [(set (match_operand:DF 0 "general_operand" "=f") (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))] "TARGET_68881" "* { if (FP_REG_P (operands[1])) return \"fsqrt%.x %1,%0\"; else return \"fsqrt%.d %1,%0\"; }") ;; Absolute value instructions (define_expand "abssf2" [(set (match_operand:SF 0 "general_operand" "") (abs:SF (match_operand:SF 1 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=x,y") (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))] "TARGET_FPA" "fpabs%.s %y1,%0") (define_insn "" [(set (match_operand:SF 0 "general_operand" "=f") (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))] "TARGET_68881" "* { if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) return \"f%$abs%.x %1,%0\"; return \"f%$abs%.s %f1,%0\"; }") (define_expand "absdf2" [(set (match_operand:DF 0 "general_operand" "") (abs:DF (match_operand:DF 1 "general_operand" "")))] "TARGET_68881 || TARGET_FPA" "") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=x,y") (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))] "TARGET_FPA" "fpabs%.d %y1,%0") (define_insn "" [(set (match_operand:DF 0 "general_operand" "=f") (abs:DF (match_operand:DF 1 "general_operand" "fmF")))] "TARGET_68881" "* { if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) return \"f%&abs%.x %1,%0\"; return \"f%&abs%.d %f1,%0\"; }") ;; one complement instructions (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "general_operand" "=dm") (not:SI (match_operand:SI 1 "general_operand" "0")))] "" "not%.l %0") (define_insn "one_cmplhi2" [(set (match_operand:HI 0 "general_operand" "=dm") (not:HI (match_operand:HI 1 "general_operand" "0")))] "" "not%.w %0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) (not:HI (match_dup 0)))] "" "not%.w %0") (define_insn "one_cmplqi2" [(set (match_operand:QI 0 "general_operand" "=dm") (not:QI (match_operand:QI 1 "general_operand" "0")))] "" "not%.b %0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) (not:QI (match_dup 0)))] "" "not%.b %0") ;; arithmetic shift instructions ;; We don't need the shift memory by 1 bit instruction ;; On all 68k models, this makes faster code in a special case. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (ashift:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)" "* { CC_STATUS_INIT; return \"swap %0\;clr%.w %0\"; }") ;; On the 68000, this makes faster code in a special case. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (ashift:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" "* { CC_STATUS_INIT; operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); return \"asl%.w %2,%0\;swap %0\;clr%.w %0\"; }") (define_insn "ashlsi3" [(set (match_operand:SI 0 "register_operand" "=d") (ashift:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "general_operand" "dI")))] "" "* { if (operands[2] == const1_rtx) return \"add%.l %0,%0\"; return \"asl%.l %2,%0\"; }") (define_insn "ashlhi3" [(set (match_operand:HI 0 "register_operand" "=d") (ashift:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] "" "asl%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (ashift:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dI")))] "" "asl%.w %1,%0") (define_insn "ashlqi3" [(set (match_operand:QI 0 "register_operand" "=d") (ashift:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] "" "asl%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (ashift:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] "" "asl%.b %1,%0") ;; On all 68k models, this makes faster code in a special case. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)" "swap %0\;ext%.l %0") ;; On the 68000, this makes faster code in a special case. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" "* { operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); return \"swap %0\;asr%.w %2,%0\;ext%.l %0\"; }") (define_insn "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "general_operand" "dI")))] "" "* { return \"asr%.l %2,%0\"; }") (define_insn "ashrhi3" [(set (match_operand:HI 0 "register_operand" "=d") (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] "" "asr%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (ashiftrt:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dI")))] "" "asr%.w %1,%0") (define_insn "ashrqi3" [(set (match_operand:QI 0 "register_operand" "=d") (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] "" "asr%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (ashiftrt:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] "" "asr%.b %1,%0") ;; logical shift instructions ;; On all 68k models, this makes faster code in a special case. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (lshift:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)" "* { CC_STATUS_INIT; return \"swap %0\;clr%.w %0\"; }") ;; On the 68000, this makes faster code in a special case. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (lshift:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" "* { CC_STATUS_INIT; operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\"; }") (define_insn "lshlsi3" [(set (match_operand:SI 0 "register_operand" "=d") (lshift:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "general_operand" "dI")))] "" "* { if (operands[2] == const1_rtx) return \"add%.l %0,%0\"; return \"lsl%.l %2,%0\"; }") (define_insn "lshlhi3" [(set (match_operand:HI 0 "register_operand" "=d") (lshift:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] "" "lsl%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (lshift:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dI")))] "" "lsl%.w %1,%0") (define_insn "lshlqi3" [(set (match_operand:QI 0 "register_operand" "=d") (lshift:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] "" "lsl%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (lshift:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] "" "lsl%.b %1,%0") ;; On all 68k models, this makes faster code in a special case. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)" "* { CC_STATUS_INIT; return \"clr%.w %0\;swap %0\"; }") ;; On the 68000, this makes faster code in a special case. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" "* { /* I think lsr%.w sets the CC properly. */ operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\"; }") (define_insn "lshrsi3" [(set (match_operand:SI 0 "register_operand" "=d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "general_operand" "dI")))] "" "* { return \"lsr%.l %2,%0\"; }") (define_insn "lshrhi3" [(set (match_operand:HI 0 "register_operand" "=d") (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] "" "lsr%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (lshiftrt:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dI")))] "" "lsr%.w %1,%0") (define_insn "lshrqi3" [(set (match_operand:QI 0 "register_operand" "=d") (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] "" "lsr%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (lshiftrt:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] "" "lsr%.b %1,%0") ;; rotate instructions (define_insn "rotlsi3" [(set (match_operand:SI 0 "register_operand" "=d") (rotate:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "general_operand" "dI")))] "" "rol%.l %2,%0") (define_insn "rotlhi3" [(set (match_operand:HI 0 "register_operand" "=d") (rotate:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] "" "rol%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (rotate:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dI")))] "" "rol%.w %1,%0") (define_insn "rotlqi3" [(set (match_operand:QI 0 "register_operand" "=d") (rotate:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] "" "rol%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (rotate:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] "" "rol%.b %1,%0") (define_insn "rotrsi3" [(set (match_operand:SI 0 "register_operand" "=d") (rotatert:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "general_operand" "dI")))] "" "ror%.l %2,%0") (define_insn "rotrhi3" [(set (match_operand:HI 0 "register_operand" "=d") (rotatert:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] "" "ror%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (rotatert:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dI")))] "" "ror%.w %1,%0") (define_insn "rotrqi3" [(set (match_operand:QI 0 "register_operand" "=d") (rotatert:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] "" "ror%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (rotatert:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] "" "ror%.b %1,%0") ;; Special cases of bit-field insns which we should ;; recognize in preference to the general case. ;; These handle aligned 8-bit and 16-bit fields, ;; which can usually be done with move instructions. ; ; Special case for 32-bit field in memory. This only occurs when 32-bit ; alignment of structure members is specified. ; ; The move is allowed to be odd byte aligned, because that's still faster ; than an odd byte aligned bit field instruction. ; (define_insn "" [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o") (match_operand:SI 1 "immediate_operand" "i") (match_operand:SI 2 "immediate_operand" "i")) (match_operand:SI 3 "general_operand" "rmi"))] "TARGET_68020 && TARGET_BITFIELD && GET_CODE (operands[1]) == CONST_INT && (INTVAL (operands[1]) == 32) && GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) % 8) == 0 && ! mode_dependent_address_p (XEXP (operands[0], 0))" "* { operands[0] = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8); return \"move%.l %3,%0\"; }") (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do") (match_operand:SI 1 "immediate_operand" "i") (match_operand:SI 2 "immediate_operand" "i")) (match_operand:SI 3 "general_operand" "d"))] "TARGET_68020 && TARGET_BITFIELD && GET_CODE (operands[1]) == CONST_INT && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 && (GET_CODE (operands[0]) == REG || ! mode_dependent_address_p (XEXP (operands[0], 0)))" "* { if (REG_P (operands[0])) { if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32) return \"bfins %3,%0{%b2:%b1}\"; } else operands[0] = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8); if (GET_CODE (operands[3]) == MEM) operands[3] = adj_offsettable_operand (operands[3], (32 - INTVAL (operands[1])) / 8); if (INTVAL (operands[1]) == 8) return \"move%.b %3,%0\"; return \"move%.w %3,%0\"; }") ; ; Special case for 32-bit field in memory. This only occurs when 32-bit ; alignment of structure members is specified. ; ; The move is allowed to be odd byte aligned, because that's still faster ; than an odd byte aligned bit field instruction. ; (define_insn "" [(set (match_operand:SI 0 "general_operand" "=rm") (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o") (match_operand:SI 2 "immediate_operand" "i") (match_operand:SI 3 "immediate_operand" "i")))] "TARGET_68020 && TARGET_BITFIELD && GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) == 32) && GET_CODE (operands[3]) == CONST_INT && (INTVAL (operands[3]) % 8) == 0 && ! mode_dependent_address_p (XEXP (operands[1], 0))" "* { operands[1] = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); return \"move%.l %1,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=&d") (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do") (match_operand:SI 2 "immediate_operand" "i") (match_operand:SI 3 "immediate_operand" "i")))] "TARGET_68020 && TARGET_BITFIELD && GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) && GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 && (GET_CODE (operands[1]) == REG || ! mode_dependent_address_p (XEXP (operands[1], 0)))" "* { cc_status.flags |= CC_NOT_NEGATIVE; if (REG_P (operands[1])) { if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) return \"bfextu %1{%b3:%b2},%0\"; } else operands[1] = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); output_asm_insn (\"clr%.l %0\", operands); if (GET_CODE (operands[0]) == MEM) operands[0] = adj_offsettable_operand (operands[0], (32 - INTVAL (operands[1])) / 8); if (INTVAL (operands[2]) == 8) return \"move%.b %1,%0\"; return \"move%.w %1,%0\"; }") ; ; Special case for 32-bit field in memory. This only occurs when 32-bit ; alignment of structure members is specified. ; ; The move is allowed to be odd byte aligned, because that's still faster ; than an odd byte aligned bit field instruction. ; (define_insn "" [(set (match_operand:SI 0 "general_operand" "=rm") (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o") (match_operand:SI 2 "immediate_operand" "i") (match_operand:SI 3 "immediate_operand" "i")))] "TARGET_68020 && TARGET_BITFIELD && GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) == 32) && GET_CODE (operands[3]) == CONST_INT && (INTVAL (operands[3]) % 8) == 0 && ! mode_dependent_address_p (XEXP (operands[1], 0))" "* { operands[1] = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); return \"move%.l %1,%0\"; }") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d") (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do") (match_operand:SI 2 "immediate_operand" "i") (match_operand:SI 3 "immediate_operand" "i")))] "TARGET_68020 && TARGET_BITFIELD && GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) && GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 && (GET_CODE (operands[1]) == REG || ! mode_dependent_address_p (XEXP (operands[1], 0)))" "* { if (REG_P (operands[1])) { if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) return \"bfexts %1{%b3:%b2},%0\"; } else operands[1] = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); if (INTVAL (operands[2]) == 8) return \"move%.b %1,%0\;extb%.l %0\"; return \"move%.w %1,%0\;ext%.l %0\"; }") ;; Bit field instructions, general cases. ;; "o,d" constraint causes a nonoffsettable memref to match the "o" ;; so that its address is reloaded. (define_insn "extv" [(set (match_operand:SI 0 "general_operand" "=d,d") (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d") (match_operand:SI 2 "general_operand" "di,di") (match_operand:SI 3 "general_operand" "di,di")))] "TARGET_68020 && TARGET_BITFIELD" "bfexts %1{%b3:%b2},%0") (define_insn "extzv" [(set (match_operand:SI 0 "general_operand" "=d,d") (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d") (match_operand:SI 2 "general_operand" "di,di") (match_operand:SI 3 "general_operand" "di,di")))] "TARGET_68020 && TARGET_BITFIELD" "* { if (GET_CODE (operands[2]) == CONST_INT) { if (INTVAL (operands[2]) != 32) cc_status.flags |= CC_NOT_NEGATIVE; } else { CC_STATUS_INIT; } return \"bfextu %1{%b3:%b2},%0\"; }") (define_insn "" [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") (match_operand:SI 1 "general_operand" "di,di") (match_operand:SI 2 "general_operand" "di,di")) (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2)) (match_operand 3 "immediate_operand" "i,i")))] "TARGET_68020 && TARGET_BITFIELD && GET_CODE (operands[3]) == CONST_INT && (INTVAL (operands[3]) == -1 || (GET_CODE (operands[1]) == CONST_INT && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))" "* { CC_STATUS_INIT; return \"bfchg %0{%b2:%b1}\"; }") (define_insn "" [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") (match_operand:SI 1 "general_operand" "di,di") (match_operand:SI 2 "general_operand" "di,di")) (const_int 0))] "TARGET_68020 && TARGET_BITFIELD" "* { CC_STATUS_INIT; return \"bfclr %0{%b2:%b1}\"; }") (define_insn "" [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") (match_operand:SI 1 "general_operand" "di,di") (match_operand:SI 2 "general_operand" "di,di")) (const_int -1))] "TARGET_68020 && TARGET_BITFIELD" "* { CC_STATUS_INIT; return \"bfset %0{%b2:%b1}\"; }") (define_insn "insv" [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") (match_operand:SI 1 "general_operand" "di,di") (match_operand:SI 2 "general_operand" "di,di")) (match_operand:SI 3 "general_operand" "d,d"))] "TARGET_68020 && TARGET_BITFIELD" "bfins %3,%0{%b2:%b1}") ;; Now recognize bit field insns that operate on registers ;; (or at least were intended to do so). (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d") (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d") (match_operand:SI 2 "general_operand" "di") (match_operand:SI 3 "general_operand" "di")))] "TARGET_68020 && TARGET_BITFIELD" "bfexts %1{%b3:%b2},%0") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=d") (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d") (match_operand:SI 2 "general_operand" "di") (match_operand:SI 3 "general_operand" "di")))] "TARGET_68020 && TARGET_BITFIELD" "* { if (GET_CODE (operands[2]) == CONST_INT) { if (INTVAL (operands[2]) != 32) cc_status.flags |= CC_NOT_NEGATIVE; } else { CC_STATUS_INIT; } return \"bfextu %1{%b3:%b2},%0\"; }") (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d") (match_operand:SI 1 "general_operand" "di") (match_operand:SI 2 "general_operand" "di")) (const_int 0))] "TARGET_68020 && TARGET_BITFIELD" "* { CC_STATUS_INIT; return \"bfclr %0{%b2:%b1}\"; }") (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d") (match_operand:SI 1 "general_operand" "di") (match_operand:SI 2 "general_operand" "di")) (const_int -1))] "TARGET_68020 && TARGET_BITFIELD" "* { CC_STATUS_INIT; return \"bfset %0{%b2:%b1}\"; }") (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d") (match_operand:SI 1 "general_operand" "di") (match_operand:SI 2 "general_operand" "di")) (match_operand:SI 3 "general_operand" "d"))] "TARGET_68020 && TARGET_BITFIELD" "* { #if 0 /* These special cases are now recognized by a specific pattern. */ if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16) return \"move%.w %3,%0\"; if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8) return \"move%.b %3,%0\"; #endif return \"bfins %3,%0{%b2:%b1}\"; }") ;; Special patterns for optimizing bit-field instructions. (define_insn "" [(set (cc0) (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") (match_operand:SI 1 "general_operand" "di") (match_operand:SI 2 "general_operand" "di")))] "TARGET_68020 && TARGET_BITFIELD && GET_CODE (operands[1]) == CONST_INT" "* { if (operands[1] == const1_rtx && GET_CODE (operands[2]) == CONST_INT) { int width = GET_CODE (operands[0]) == REG ? 31 : 7; return output_btst (operands, gen_rtx (CONST_INT, VOIDmode, width - INTVAL (operands[2])), operands[0], insn, 1000); /* Pass 1000 as SIGNPOS argument so that btst will not think we are testing the sign bit for an `and' and assume that nonzero implies a negative result. */ } if (INTVAL (operands[1]) != 32) cc_status.flags = CC_NOT_NEGATIVE; return \"bftst %0{%b2:%b1}\"; }") ;;; now handle the register cases (define_insn "" [(set (cc0) (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d") (match_operand:SI 1 "general_operand" "di") (match_operand:SI 2 "general_operand" "di")))] "TARGET_68020 && TARGET_BITFIELD && GET_CODE (operands[1]) == CONST_INT" "* { if (operands[1] == const1_rtx && GET_CODE (operands[2]) == CONST_INT) { int width = GET_CODE (operands[0]) == REG ? 31 : 7; return output_btst (operands, gen_rtx (CONST_INT, VOIDmode, width - INTVAL (operands[2])), operands[0], insn, 1000); /* Pass 1000 as SIGNPOS argument so that btst will not think we are testing the sign bit for an `and' and assume that nonzero implies a negative result. */ } if (INTVAL (operands[1]) != 32) cc_status.flags = CC_NOT_NEGATIVE; return \"bftst %0{%b2:%b1}\"; }") (define_insn "seq" [(set (match_operand:QI 0 "general_operand" "=d") (eq:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\"); ") (define_insn "sne" [(set (match_operand:QI 0 "general_operand" "=d") (ne:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\"); ") (define_insn "sgt" [(set (match_operand:QI 0 "general_operand" "=d") (gt:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0); ") (define_insn "sgtu" [(set (match_operand:QI 0 "general_operand" "=d") (gtu:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; return \"shi %0\"; ") (define_insn "slt" [(set (match_operand:QI 0 "general_operand" "=d") (lt:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ") (define_insn "sltu" [(set (match_operand:QI 0 "general_operand" "=d") (ltu:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; return \"scs %0\"; ") (define_insn "sge" [(set (match_operand:QI 0 "general_operand" "=d") (ge:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ") (define_insn "sgeu" [(set (match_operand:QI 0 "general_operand" "=d") (geu:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; return \"scc %0\"; ") (define_insn "sle" [(set (match_operand:QI 0 "general_operand" "=d") (le:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0); ") (define_insn "sleu" [(set (match_operand:QI 0 "general_operand" "=d") (leu:QI (cc0) (const_int 0)))] "" "* cc_status = cc_prev_status; return \"sls %0\"; ") ;; Basic conditional jump instructions. (define_insn "beq" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { #ifdef MOTOROLA OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\"); #else OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\"); #endif }") (define_insn "bne" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* { #ifdef MOTOROLA OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\"); #else OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\"); #endif }") (define_insn "bgt" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* #ifdef MOTOROLA OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0); #else OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0); #endif ") (define_insn "bgtu" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* #ifdef MOTOROLA return \"jbhi %l0\"; #else return \"jhi %l0\"; #endif ") (define_insn "blt" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* #ifdef MOTOROLA OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\"); #else OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\"); #endif ") (define_insn "bltu" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* #ifdef MOTOROLA return \"jbcs %l0\"; #else return \"jcs %l0\"; #endif ") (define_insn "bge" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* #ifdef MOTOROLA OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\"); #else OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\"); #endif ") (define_insn "bgeu" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* #ifdef MOTOROLA return \"jbcc %l0\"; #else return \"jcc %l0\"; #endif ") (define_insn "ble" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* #ifdef MOTOROLA OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0); #else OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0); #endif ") (define_insn "bleu" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "* #ifdef MOTOROLA return \"jbls %l0\"; #else return \"jls %l0\"; #endif ") ;; Negated conditional jump instructions. (define_insn "" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { #ifdef MOTOROLA OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\"); #else OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\"); #endif }") (define_insn "" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* { #ifdef MOTOROLA OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\"); #else OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\"); #endif }") (define_insn "" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* #ifdef MOTOROLA OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0); #else OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0); #endif ") (define_insn "" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* #ifdef MOTOROLA return \"jbls %l0\"; #else return \"jls %l0\"; #endif ") (define_insn "" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* #ifdef MOTOROLA OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\"); #else OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\"); #endif ") (define_insn "" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* #ifdef MOTOROLA return \"jbcc %l0\"; #else return \"jcc %l0\"; #endif ") (define_insn "" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* #ifdef MOTOROLA OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\"); #else OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\"); #endif ") (define_insn "" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* #ifdef MOTOROLA return \"jbcs %l0\"; #else return \"jcs %l0\"; #endif ") (define_insn "" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* #ifdef MOTOROLA OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0); #else OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0); #endif ") (define_insn "" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" "* #ifdef MOTOROLA return \"jbhi %l0\"; #else return \"jhi %l0\"; #endif ") ;; Unconditional and other jump instructions (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "* #ifdef MOTOROLA return \"jbra %l0\"; #else return \"jra %l0\"; #endif ") ;; We support two different ways of handling dispatch tables. ;; The NeXT uses absolute tables, and other machines use relative. ;; This define_expand can generate either kind. (define_expand "tablejump" [(parallel [(set (pc) (match_operand 0 "" "")) (use (label_ref (match_operand 1 "" "")))])] "" " { #ifdef CASE_VECTOR_PC_RELATIVE operands[0] = gen_rtx (PLUS, SImode, pc_rtx, operands[0]); #endif }") ;; Jump to variable address from dispatch table of absolute addresses. (define_insn "" [(set (pc) (match_operand:SI 0 "register_operand" "a")) (use (label_ref (match_operand 1 "" "")))] "" "* #ifdef MOTOROLA return \"jmp (%0)\"; #else return \"jmp %0@\"; #endif ") ;; Jump to variable address from dispatch table of relative addresses. (define_insn "" [(set (pc) (plus:SI (pc) (match_operand:HI 0 "register_operand" "r"))) (use (label_ref (match_operand 1 "" "")))] "" "* #ifdef ASM_RETURN_CASE_JUMP ASM_RETURN_CASE_JUMP; #else #ifdef SGS #ifdef ASM_OUTPUT_CASE_LABEL return \"jmp 6(%%pc,%0.w)\"; #else #ifdef CRDS return \"jmp 2(pc,%0.w)\"; #else return \"jmp 2(%%pc,%0.w)\"; #endif /* end !CRDS */ #endif #else /* not SGS */ #ifdef MOTOROLA return \"jmp (2,pc,%0.w)\"; #else return \"jmp pc@(2,%0:w)\"; #endif #endif #endif ") ;; Decrement-and-branch insns. (define_insn "" [(set (pc) (if_then_else (ne (match_operand:HI 0 "general_operand" "+g") (const_int 0)) (label_ref (match_operand 1 "" "")) (pc))) (set (match_dup 0) (plus:HI (match_dup 0) (const_int -1)))] "" "* { CC_STATUS_INIT; if (DATA_REG_P (operands[0])) return \"dbra %0,%l1\"; if (GET_CODE (operands[0]) == MEM) { #ifdef MOTOROLA #ifdef NO_ADDSUB_Q return \"sub%.w %#1,%0\;jbcc %l1\"; #else return \"subq%.w %#1,%0\;jbcc %l1\"; #endif #else /* not MOTOROLA */ return \"subqw %#1,%0\;jcc %l1\"; #endif } #ifdef MOTOROLA #ifdef SGS_CMP_ORDER #ifdef NO_ADDSUB_Q return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\"; #else return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\"; #endif #else /* not SGS_CMP_ORDER */ return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\"; #endif #else /* not MOTOROLA */ return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\"; #endif }") (define_insn "" [(set (pc) (if_then_else (ne (match_operand:SI 0 "general_operand" "+g") (const_int 0)) (label_ref (match_operand 1 "" "")) (pc))) (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))] "" "* { CC_STATUS_INIT; #ifdef MOTOROLA #ifdef NO_ADDSUB_Q if (DATA_REG_P (operands[0])) return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\"; if (GET_CODE (operands[0]) == MEM) return \"sub%.l %#1,%0\;jbcc %l1\"; #else if (DATA_REG_P (operands[0])) return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\"; if (GET_CODE (operands[0]) == MEM) return \"subq%.l %#1,%0\;jbcc %l1\"; #endif /* NO_ADDSUB_Q */ #ifdef SGS_CMP_ORDER #ifdef NO_ADDSUB_Q return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; #else return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; #endif #else /* not SGS_CMP_ORDER */ return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\"; #endif /* not SGS_CMP_ORDER */ #else /* not MOTOROLA */ if (DATA_REG_P (operands[0])) return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\"; if (GET_CODE (operands[0]) == MEM) return \"subql %#1,%0\;jcc %l1\"; return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\"; #endif /* not MOTOROLA */ }") ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce. (define_insn "" [(set (pc) (if_then_else (ge (plus:HI (match_operand:HI 0 "general_operand" "+g") (const_int -1)) (const_int 0)) (label_ref (match_operand 1 "" "")) (pc))) (set (match_dup 0) (plus:HI (match_dup 0) (const_int -1)))] "find_reg_note (insn, REG_NONNEG, 0)" "* { CC_STATUS_INIT; #ifdef MOTOROLA #ifdef NO_ADDSUB_Q if (DATA_REG_P (operands[0])) return \"dbra %0,%l1\"; if (GET_CODE (operands[0]) == MEM) return \"sub%.w %#1,%0\;jbcc %l1\"; #else if (DATA_REG_P (operands[0])) return \"dbra %0,%l1\"; if (GET_CODE (operands[0]) == MEM) return \"subq%.w %#1,%0\;jbcc %l1\"; #endif #ifdef SGS_CMP_ORDER #ifdef NO_ADDSUB_Q return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\"; #else return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\"; #endif #else /* not SGS_CMP_ORDER */ return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\"; #endif /* not SGS_CMP_ORDER */ #else /* not MOTOROLA */ if (DATA_REG_P (operands[0])) return \"dbra %0,%l1\"; if (GET_CODE (operands[0]) == MEM) return \"subqw %#1,%0\;jcc %l1\"; return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\"; #endif /* not MOTOROLA */ }") (define_insn "decrement_and_branch_until_zero" [(set (pc) (if_then_else (ge (plus:SI (match_operand:SI 0 "general_operand" "+g") (const_int -1)) (const_int 0)) (label_ref (match_operand 1 "" "")) (pc))) (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))] "find_reg_note (insn, REG_NONNEG, 0)" "* { CC_STATUS_INIT; #ifdef MOTOROLA #ifdef NO_ADDSUB_Q if (DATA_REG_P (operands[0])) return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\"; if (GET_CODE (operands[0]) == MEM) return \"sub%.l %#1,%0\;jbcc %l1\"; #else if (DATA_REG_P (operands[0])) return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\"; if (GET_CODE (operands[0]) == MEM) return \"subq%.l %#1,%0\;jbcc %l1\"; #endif #ifdef SGS_CMP_ORDER #ifdef NO_ADDSUB_Q return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; #else return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; #endif #else /* not SGS_CMP_ORDER */ return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\"; #endif /* not SGS_CMP_ORDER */ #else /* not MOTOROLA */ if (DATA_REG_P (operands[0])) return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\"; if (GET_CODE (operands[0]) == MEM) return \"subql %#1,%0\;jcc %l1\"; return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\"; #endif /* not MOTOROLA */ }") ;; PIC calls are handled by loading the address of the function into a ;; register (via movsi), then emitting a register indirect call using ;; the "jsr" function call syntax. ;; ;; It is important to note that the "jsr" syntax is always used for ;; PIC calls, even on machines in which GCC normally uses the "jbsr" ;; syntax for non-PIC calls. This keeps at least 1 assembler (Sun) ;; from emitting incorrect code for a PIC call. ;; ;; We have different patterns for PIC calls and non-PIC calls. The ;; different patterns are only used to choose the right syntax ;; ("jsr" vs "jbsr"). ;; ;; On svr4 m68k, PIC stuff is done differently. To be able to support ;; dynamic linker LAZY BINDING, all the procedure calls need to go ;; through the PLT (Procedure Linkage Table) section in PIC mode. The ;; svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC', ;; that tells the linker editor to create an entry for `FUNC' in PLT ;; section at link time. However, all global objects reference are still ;; done by using `OBJ@GOT'. So, the goal here is to output the function ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'. ;; We need to have a way to differentiate these two different operands. ;; ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs ;; to be changed to recognize function calls symbol_ref operand as a legal ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will ;; avoid the compiler to load this symbol_ref operand into a register. ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly ;; since the value is a PC relative offset, not a real address. ;; ;; All global objects are treated in the similar way as in SUN3. The only ;; difference is: on m68k svr4, the reference of such global object needs ;; to end with a suffix "@GOT" so the assembler and linker know to create ;; an entry for it in GOT (Global Offset Table) section. This is done in ;; m68k.c. ;; Call subroutine with no return value. (define_expand "call" [(call (match_operand:QI 0 "memory_operand" "") (match_operand:SI 1 "general_operand" ""))] ;; Operand 1 not really used on the m68000. "" " { if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) #ifdef MOTOROLA SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1; #else operands[0] = gen_rtx (MEM, GET_MODE (operands[0]), force_reg (Pmode, XEXP (operands[0], 0))); #endif }") ;; This is a normal call sequence. (define_insn "" [(call (match_operand:QI 0 "memory_operand" "o") (match_operand:SI 1 "general_operand" "g"))] ;; Operand 1 not really used on the m68000. "! flag_pic" "* #ifdef MOTOROLA return \"jsr %0\"; #else return \"jbsr %0\"; #endif ") ;; This is a PIC call sequence. (define_insn "" [(call (match_operand:QI 0 "memory_operand" "o") (match_operand:SI 1 "general_operand" "g"))] ;; Operand 1 not really used on the m68000. "flag_pic" "* #ifdef HPUX_ASM return \"bsr %0\"; #else #ifdef MOTOROLA if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) return \"bsr %0@PLTPC\"; #endif return \"jsr %0\"; #endif ") ;; Call subroutine, returning value in operand 0 ;; (which must be a hard register). ;; See comments before "call" regarding PIC calls. (define_expand "call_value" [(set (match_operand 0 "" "") (call (match_operand:QI 1 "memory_operand" "") (match_operand:SI 2 "general_operand" "")))] ;; Operand 2 not really used on the m68000. "" " { if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) #ifdef MOTOROLA SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1; #else operands[1] = gen_rtx (MEM, GET_MODE (operands[1]), force_reg (Pmode, XEXP (operands[1], 0))); #endif }") ;; This is a normal call_value (define_insn "" [(set (match_operand 0 "" "=rf") (call (match_operand:QI 1 "memory_operand" "o") (match_operand:SI 2 "general_operand" "g")))] ;; Operand 2 not really used on the m68000. "! flag_pic" "* #ifdef MOTOROLA return \"jsr %1\"; #else return \"jbsr %1\"; #endif ") ;; This is a PIC call_value (define_insn "" [(set (match_operand 0 "" "=rf") (call (match_operand:QI 1 "memory_operand" "o") (match_operand:SI 2 "general_operand" "g")))] ;; Operand 2 not really used on the m68000. "flag_pic" "* #ifdef HPUX_ASM return \"bsr %1\"; #else #ifdef MOTOROLA if (GET_CODE (operands[1]) == MEM && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) return \"bsr %1@PLTPC\"; #endif return \"jsr %1\"; #endif ") ;; Call subroutine returning any type. (define_expand "untyped_call" [(parallel [(call (match_operand 0 "" "") (const_int 0)) (match_operand 1 "" "") (match_operand 2 "" "")])] "NEEDS_UNTYPED_CALL" " { int i; emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); for (i = 0; i < XVECLEN (operands[2], 0); i++) { rtx set = XVECEXP (operands[2], 0, i); emit_move_insn (SET_DEST (set), SET_SRC (set)); } /* The optimizer does not know that the call sets the function value registers we stored in the result block. We avoid problems by claiming that all hard registers are used and clobbered at this point. */ emit_insn (gen_blockage ()); DONE; }") ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and ;; all of memory. This blocks insns from being moved across this point. (define_insn "blockage" [(unspec_volatile [(const_int 0)] 0)] "" "") (define_insn "nop" [(const_int 0)] "" "nop") (define_insn "probe" [(reg:SI 15)] "NEED_PROBE" "* { operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx, gen_rtx (CONST_INT, VOIDmode, NEED_PROBE)); return \"tstl %a0\"; }") ;; Used for frameless functions which save no regs and allocate no locals. (define_insn "return" [(return)] "USE_RETURN_INSN" "* { if (current_function_pops_args == 0) return \"rts\"; operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args); return \"rtd %0\"; }") (define_insn "indirect_jump" [(set (pc) (match_operand:SI 0 "address_operand" "p"))] "" "jmp %a0") ;; This should not be used unless the add/sub insns can't be. (define_insn "" [(set (match_operand:SI 0 "general_operand" "=a") (match_operand:QI 1 "address_operand" "p"))] "" "lea %a1,%0") ;; This is the first machine-dependent peephole optimization. ;; It is useful when a floating value is returned from a function call ;; and then is moved into an FP register. ;; But it is mainly intended to test the support for these optimizations. (define_peephole [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) (set (match_operand:DF 0 "register_operand" "=f") (match_operand:DF 1 "register_operand" "ad"))] "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" "* { rtx xoperands[2]; xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); output_asm_insn (\"move%.l %1,%@\", xoperands); output_asm_insn (\"move%.l %1,%-\", operands); return \"fmove%.d %+,%0\"; } ") ;; Optimize a stack-adjust followed by a push of an argument. ;; This is said to happen frequently with -msoft-float ;; when there are consecutive library calls. (define_peephole [(set (reg:SI 15) (plus:SI (reg:SI 15) (match_operand:SI 0 "immediate_operand" "n"))) (set (match_operand:SF 1 "push_operand" "=m") (match_operand:SF 2 "general_operand" "rmfF"))] "GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) >= 4 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])" "* { if (INTVAL (operands[0]) > 4) { rtx xoperands[2]; xoperands[0] = stack_pointer_rtx; xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4); #ifndef NO_ADDSUB_Q if (INTVAL (xoperands[1]) <= 8) output_asm_insn (\"addq%.w %1,%0\", xoperands); else if (INTVAL (xoperands[1]) <= 16 && TARGET_68020) { xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xoperands[1]) - 8); output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands); } else #endif if (INTVAL (xoperands[1]) <= 0x7FFF) output_asm_insn (\"add%.w %1,%0\", xoperands); else output_asm_insn (\"add%.l %1,%0\", xoperands); } if (FP_REG_P (operands[2])) return \"fmove%.s %2,%@\"; return \"move%.l %2,%@\"; }") ;; Speed up stack adjust followed by a fullword fixedpoint push. (define_peephole [(set (reg:SI 15) (plus:SI (reg:SI 15) (match_operand:SI 0 "immediate_operand" "n"))) (set (match_operand:SI 1 "push_operand" "=m") (match_operand:SI 2 "general_operand" "g"))] "GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) >= 4 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])" "* { if (INTVAL (operands[0]) > 4) { rtx xoperands[2]; xoperands[0] = stack_pointer_rtx; xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4); #ifndef NO_ADDSUB_Q if (INTVAL (xoperands[1]) <= 8) output_asm_insn (\"addq%.w %1,%0\", xoperands); else if (INTVAL (xoperands[1]) <= 16 && TARGET_68020) { xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xoperands[1]) - 8); output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands); } else #endif if (INTVAL (xoperands[1]) <= 0x7FFF) output_asm_insn (\"add%.w %1,%0\", xoperands); else output_asm_insn (\"add%.l %1,%0\", xoperands); } if (operands[2] == const0_rtx) return \"clr%.l %@\"; return \"move%.l %2,%@\"; }") ;; Speed up pushing a single byte but leaving four bytes of space. (define_peephole [(set (mem:QI (pre_dec:SI (reg:SI 15))) (match_operand:QI 1 "general_operand" "dami")) (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))] "! reg_mentioned_p (stack_pointer_rtx, operands[1])" "* { rtx xoperands[4]; if (GET_CODE (operands[1]) == REG) return \"move%.l %1,%-\"; xoperands[1] = operands[1]; xoperands[2] = gen_rtx (MEM, QImode, gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, gen_rtx (CONST_INT, VOIDmode, 3))); xoperands[3] = stack_pointer_rtx; output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands); return \"\"; }") (define_peephole [(set (match_operand:SI 0 "register_operand" "=d") (const_int 0)) (set (strict_low_part (subreg:HI (match_dup 0) 0)) (match_operand:HI 1 "general_operand" "rmn"))] "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])" "* { if (GET_CODE (operands[1]) == CONST_INT) { if (operands[1] == const0_rtx && (DATA_REG_P (operands[0]) || GET_CODE (operands[0]) == MEM) /* clr insns on 68000 read before writing. This isn't so on the 68010, but we have no alternative for it. */ && (TARGET_68020 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) return \"clr%.w %0\"; } return \"move%.w %1,%0\"; }") ;; dbCC peepholes ;; ;; Turns ;; loop: ;; [ ... ] ;; jCC label ; abnormal loop termination ;; dbra dN, loop ; normal loop termination ;; ;; Into ;; loop: ;; [ ... ] ;; dbCC dN, loop ;; jCC label ;; ;; Which moves the jCC condition outside the inner loop for free. ;; (define_peephole [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc))) (parallel [(set (pc) (if_then_else (ge (plus:HI (match_operand:HI 0 "register_operand" "+d") (const_int -1)) (const_int 0)) (label_ref (match_operand 1 "" "")) (pc))) (set (match_dup 0) (plus:HI (match_dup 0) (const_int -1)))])] "DATA_REG_P (operands[0])" "* { CC_STATUS_INIT; output_dbcc_and_branch (operands); return \"\"; }") (define_peephole [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc))) (parallel [(set (pc) (if_then_else (ge (plus:SI (match_operand:SI 0 "register_operand" "+d") (const_int -1)) (const_int 0)) (label_ref (match_operand 1 "" "")) (pc))) (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))])] "DATA_REG_P (operands[0])" "* { CC_STATUS_INIT; output_dbcc_and_branch (operands); return \"\"; }") ;; FPA multiply and add. (define_insn "" [(set (match_operand:DF 0 "register_operand" "=x,y,y") (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y") (match_operand:DF 2 "general_operand" "xH,y,y")) (match_operand:DF 3 "general_operand" "xH,y,dmF")))] "TARGET_FPA" "@ fpma%.d %1,%w2,%w3,%0 fpma%.d %x1,%x2,%x3,%0 fpma%.d %x1,%x2,%x3,%0") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=x,y,y") (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y") (match_operand:SF 2 "general_operand" "xH,y,ydmF")) (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))] "TARGET_FPA" "@ fpma%.s %1,%w2,%w3,%0 fpma%.s %1,%2,%3,%0 fpma%.s %1,%2,%3,%0") ;; FPA Multiply and subtract (define_insn "" [(set (match_operand:DF 0 "register_operand" "=x,y,y") (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y") (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y") (match_operand:DF 3 "general_operand" "x,y,rmF"))))] "TARGET_FPA" "@ fpms%.d %3,%w2,%w1,%0 fpms%.d %x3,%2,%x1,%0 fpms%.d %x3,%2,%x1,%0") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=x,y,y") (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF") (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y") (match_operand:SF 3 "general_operand" "x,y,yrmF"))))] "TARGET_FPA" "@ fpms%.s %3,%w2,%w1,%0 fpms%.s %3,%2,%1,%0 fpms%.s %3,%2,%1,%0") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=x,y,y") (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y") (match_operand:DF 2 "general_operand" "x,y,rmF")) (match_operand:DF 3 "general_operand" "xH,rmF,y")))] "TARGET_FPA" "@ fpmr%.d %2,%w1,%w3,%0 fpmr%.d %x2,%1,%x3,%0 fpmr%.d %x2,%1,%x3,%0") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=x,y,y") (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y") (match_operand:SF 2 "general_operand" "x,y,yrmF")) (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))] "TARGET_FPA" "@ fpmr%.s %2,%w1,%w3,%0 fpmr%.s %x2,%1,%x3,%0 fpmr%.s %x2,%1,%x3,%0") ;; FPA Add and multiply (define_insn "" [(set (match_operand:DF 0 "register_operand" "=x,y,y") (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y") (match_operand:DF 2 "general_operand" "x,y,rmF")) (match_operand:DF 3 "general_operand" "xH,rmF,y")))] "TARGET_FPA" "@ fpam%.d %2,%w1,%w3,%0 fpam%.d %x2,%1,%x3,%0 fpam%.d %x2,%1,%x3,%0") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=x,y,y") (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y") (match_operand:SF 2 "general_operand" "x,y,yrmF")) (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))] "TARGET_FPA" "@ fpam%.s %2,%w1,%w3,%0 fpam%.s %x2,%1,%x3,%0 fpam%.s %x2,%1,%x3,%0") ;;FPA Subtract and multiply (define_insn "" [(set (match_operand:DF 0 "register_operand" "=x,y,y") (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y") (match_operand:DF 2 "general_operand" "x,y,rmF")) (match_operand:DF 3 "general_operand" "xH,rmF,y")))] "TARGET_FPA" "@ fpsm%.d %2,%w1,%w3,%0 fpsm%.d %x2,%1,%x3,%0 fpsm%.d %x2,%1,%x3,%0") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=x,y,y") (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y") (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y") (match_operand:DF 3 "general_operand" "x,y,rmF"))))] "TARGET_FPA" "@ fpsm%.d %3,%w2,%w1,%0 fpsm%.d %x3,%2,%x1,%0 fpsm%.d %x3,%2,%x1,%0") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=x,y,y") (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y") (match_operand:SF 2 "general_operand" "x,y,yrmF")) (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))] "TARGET_FPA" "@ fpsm%.s %2,%w1,%w3,%0 fpsm%.s %x2,%1,%x3,%0 fpsm%.s %x2,%1,%x3,%0") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=x,y,y") (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF") (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y") (match_operand:SF 3 "general_operand" "x,y,yrmF"))))] "TARGET_FPA" "@ fpsm%.s %3,%w2,%w1,%0 fpsm%.s %x3,%2,%x1,%0 fpsm%.s %x3,%2,%x1,%0") (define_insn "tstxf" [(set (cc0) (match_operand:XF 0 "nonimmediate_operand" "fm"))] "TARGET_68881" "* { cc_status.flags = CC_IN_68881; return \"ftst%.x %0\"; }") (define_expand "cmpxf" [(set (cc0) (compare (match_operand:XF 0 "general_operand" "f,mG") (match_operand:XF 1 "general_operand" "fmG,f")))] "TARGET_68881" " { if (CONSTANT_P (operands[0])) operands[0] = force_const_mem (XFmode, operands[0]); if (CONSTANT_P (operands[1])) operands[1] = force_const_mem (XFmode, operands[1]); }") (define_insn "" [(set (cc0) (compare (match_operand:XF 0 "nonimmediate_operand" "f,mG") (match_operand:XF 1 "nonimmediate_operand" "fmG,f")))] "TARGET_68881" "* { cc_status.flags = CC_IN_68881; #ifdef SGS_CMP_ORDER if (REG_P (operands[0])) { if (REG_P (operands[1])) return \"fcmp%.x %0,%1\"; else return \"fcmp%.x %0,%f1\"; } cc_status.flags |= CC_REVERSED; return \"fcmp%.x %1,%f0\"; #else if (REG_P (operands[0])) { if (REG_P (operands[1])) return \"fcmp%.x %1,%0\"; else return \"fcmp%.x %f1,%0\"; } cc_status.flags |= CC_REVERSED; return \"fcmp%.x %f0,%1\"; #endif }") (define_insn "extendsfxf2" [(set (match_operand:XF 0 "general_operand" "=fm,f") (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))] "TARGET_68881" "* { if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) { if (REGNO (operands[0]) == REGNO (operands[1])) { /* Extending float to double in an fp-reg is a no-op. NOTICE_UPDATE_CC has already assumed that the cc will be set. So cancel what it did. */ cc_status = cc_prev_status; return \"\"; } return \"f%$move%.x %1,%0\"; } if (FP_REG_P (operands[0])) return \"f%$move%.s %f1,%0\"; return \"fmove%.x %f1,%0\"; }") (define_insn "extenddfxf2" [(set (match_operand:XF 0 "general_operand" "=fm,f") (float_extend:XF (match_operand:DF 1 "general_operand" "f,m")))] "TARGET_68881" "* { if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) { if (REGNO (operands[0]) == REGNO (operands[1])) { /* Extending float to double in an fp-reg is a no-op. NOTICE_UPDATE_CC has already assumed that the cc will be set. So cancel what it did. */ cc_status = cc_prev_status; return \"\"; } return \"fmove%.x %1,%0\"; } if (FP_REG_P (operands[0])) return \"f%&move%.d %f1,%0\"; return \"fmove%.x %f1,%0\"; }") (define_insn "truncxfdf2" [(set (match_operand:DF 0 "general_operand" "=m,!r") (float_truncate:DF (match_operand:XF 1 "general_operand" "f,f")))] "TARGET_68881" "* { if (REG_P (operands[0])) { output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); return \"move%.l %+,%0\"; } return \"fmove%.d %f1,%0\"; }") (define_insn "truncxfsf2" [(set (match_operand:SF 0 "general_operand" "=dm") (float_truncate:SF (match_operand:XF 1 "general_operand" "f")))] "TARGET_68881" "fmove%.s %f1,%0") (define_insn "floatsixf2" [(set (match_operand:XF 0 "general_operand" "=f") (float:XF (match_operand:SI 1 "general_operand" "dmi")))] "TARGET_68881" "fmove%.l %1,%0") (define_insn "floathixf2" [(set (match_operand:XF 0 "general_operand" "=f") (float:XF (match_operand:HI 1 "general_operand" "dmn")))] "TARGET_68881" "fmove%.w %1,%0") (define_insn "floatqixf2" [(set (match_operand:XF 0 "general_operand" "=f") (float:XF (match_operand:QI 1 "general_operand" "dmn")))] "TARGET_68881" "fmove%.b %1,%0") (define_insn "ftruncxf2" [(set (match_operand:XF 0 "general_operand" "=f") (fix:XF (match_operand:XF 1 "general_operand" "fFm")))] "TARGET_68881" "* { if (FP_REG_P (operands[1])) return \"fintrz%.x %f1,%0\"; return \"fintrz%.x %f1,%0\"; }") (define_insn "fixxfqi2" [(set (match_operand:QI 0 "general_operand" "=dm") (fix:QI (match_operand:XF 1 "general_operand" "f")))] "TARGET_68881" "fmove%.b %1,%0") (define_insn "fixxfhi2" [(set (match_operand:HI 0 "general_operand" "=dm") (fix:HI (match_operand:XF 1 "general_operand" "f")))] "TARGET_68881" "fmove%.w %1,%0") (define_insn "fixxfsi2" [(set (match_operand:SI 0 "general_operand" "=dm") (fix:SI (match_operand:XF 1 "general_operand" "f")))] "TARGET_68881" "fmove%.l %1,%0") (define_expand "addxf3" [(set (match_operand:XF 0 "general_operand" "") (plus:XF (match_operand:XF 1 "general_operand" "") (match_operand:XF 2 "general_operand" "")))] "TARGET_68881" " { if (CONSTANT_P (operands[1])) operands[1] = force_const_mem (XFmode, operands[1]); if (CONSTANT_P (operands[2])) operands[2] = force_const_mem (XFmode, operands[2]); }") (define_insn "" [(set (match_operand:XF 0 "general_operand" "=f") (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0") (match_operand:XF 2 "nonimmediate_operand" "fmG")))] "TARGET_68881" "* { if (REG_P (operands[2])) return \"fadd%.x %2,%0\"; return \"fadd%.x %f2,%0\"; }") (define_expand "subxf3" [(set (match_operand:XF 0 "general_operand" "") (minus:XF (match_operand:XF 1 "general_operand" "") (match_operand:XF 2 "general_operand" "")))] "TARGET_68881" " { if (CONSTANT_P (operands[1])) operands[1] = force_const_mem (XFmode, operands[1]); if (CONSTANT_P (operands[2])) operands[2] = force_const_mem (XFmode, operands[2]); }") (define_insn "" [(set (match_operand:XF 0 "general_operand" "=f") (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0") (match_operand:XF 2 "nonimmediate_operand" "fmG")))] "TARGET_68881" "* { if (REG_P (operands[2])) return \"fsub%.x %2,%0\"; return \"fsub%.x %f2,%0\"; }") (define_expand "mulxf3" [(set (match_operand:XF 0 "general_operand" "") (mult:XF (match_operand:XF 1 "general_operand" "") (match_operand:XF 2 "general_operand" "")))] "TARGET_68881" " { if (CONSTANT_P (operands[1])) operands[1] = force_const_mem (XFmode, operands[1]); if (CONSTANT_P (operands[2])) operands[2] = force_const_mem (XFmode, operands[2]); }") (define_insn "" [(set (match_operand:XF 0 "general_operand" "=f") (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0") (match_operand:XF 2 "nonimmediate_operand" "fmG")))] "TARGET_68881" "* { if (REG_P (operands[2])) return \"fmul%.x %2,%0\"; return \"fmul%.x %f2,%0\"; }") (define_expand "divxf3" [(set (match_operand:XF 0 "general_operand" "") (div:XF (match_operand:XF 1 "general_operand" "") (match_operand:XF 2 "general_operand" "")))] "TARGET_68881" " { if (CONSTANT_P (operands[1])) operands[1] = force_const_mem (XFmode, operands[1]); if (CONSTANT_P (operands[2])) operands[2] = force_const_mem (XFmode, operands[2]); }") (define_insn "" [(set (match_operand:XF 0 "general_operand" "=f") (div:XF (match_operand:XF 1 "nonimmediate_operand" "0") (match_operand:XF 2 "nonimmediate_operand" "fmG")))] "TARGET_68881" "* { if (REG_P (operands[2])) return \"fdiv%.x %2,%0\"; return \"fdiv%.x %f2,%0\"; }") (define_insn "negxf2" [(set (match_operand:XF 0 "general_operand" "=f") (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fmF")))] "TARGET_68881" "* { if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) return \"fneg%.x %1,%0\"; return \"fneg%.x %f1,%0\"; }") (define_insn "absxf2" [(set (match_operand:XF 0 "general_operand" "=f") (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fmF")))] "TARGET_68881" "* { if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) return \"fabs%.x %1,%0\"; return \"fabs%.x %f1,%0\"; }") (define_insn "sqrtxf2" [(set (match_operand:XF 0 "general_operand" "=f") (sqrt:XF (match_operand:DF 1 "nonimmediate_operand" "fm")))] "TARGET_68881" "* { return \"fsqrt%.x %1,%0\"; }") gcc-2.5.8/config/m68k/m68kv4.h100444 22011 13 24622 5453234704 14261 0ustar kenneruser/* Target definitions for GNU compiler for mc680x0 running System V.4 Copyright (C) 1991 Free Software Foundation, Inc. Written by Ron Guilmette (rfg@ncd.com) and Fred Fish (fnf@cygnus.com). This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Use SGS_* macros to control compilation in m68k.md */ #define SGS_SWITCH_TABLES /* Different switch table handling */ #include "m68k/sgs.h" /* The m68k/SVR4 assembler is SGS based */ #include "svr4.h" /* Pick up the generic SVR4 macros */ /* See m68k.h. 7 means 68020 with 68881. */ #ifndef TARGET_DEFAULT #define TARGET_DEFAULT (5 /*68020*/ + 2 /*68881*/) #endif /* Override the definition of NO_DOLLAR_IN_LABEL in svr4.h, for special g++ assembler names. When this is defined, g++ uses embedded '.' characters and some m68k assemblers have problems with this. The chances are much greater that any particular assembler will permit embedded '$' characters. */ #undef NO_DOLLAR_IN_LABEL /* Define PCC_STATIC_STRUCT_RETURN if the convention on the target machine is to use the nonreentrant technique for returning structure and union values, as commonly implemented by the AT&T Portable C Compiler (PCC). When defined, the gcc option -fpcc-struct-return can be used to cause this form to be generated. When undefined, the option does nothing. For m68k SVR4, the convention is to use a reentrant technique compatible with the gcc default, so override the definition of this macro in m68k.h */ #undef PCC_STATIC_STRUCT_RETURN /* Provide a set of pre-definitions and pre-assertions appropriate for the m68k running svr4. __svr4__ is our extension. */ #define CPP_PREDEFINES \ "-Dm68k -Dunix -D__svr4__ -D__motorola__ \ -Asystem(unix) -Asystem(svr4) -Acpu(m68k) -Amachine(m68k)" /* Test to see if the target includes a 68881 by default, and use CPP_SPEC to control whether or not __HAVE_68881__ is defined by default or not. If a 68881 is the default, gcc will use inline 68881 instructions, by predefining __HAVE_68881__, unless -msoft-float is specified. If a 68881 is not the default, gcc will only define __HAVE_68881__ if -m68881 is specified. */ #if TARGET_DEFAULT & 2 #define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__}" #else #define CPP_SPEC "%{m68881:-D__HAVE_68881__}" #endif /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. We override the definition in m68k.h and match the way the native m68k/SVR4 compiler does profiling, with the address of the profile counter in a1, not a0, and using bsr rather than jsr. */ #undef FUNCTION_PROFILER #define FUNCTION_PROFILER(FILE, LABELNO) \ asm_fprintf ((FILE), "\tlea.l\t(%LLP%d,%Rpc),%Ra1\n\tbsr\t_mcount\n", \ (LABELNO)) /* Local common symbols are declared to the assembler with ".lcomm" rather than ".bss", so override the definition in svr4.h */ #undef BSS_ASM_OP #define BSS_ASM_OP ".lcomm" /* Register in which address to store a structure value is passed to a function. The default in m68k.h is a1. For m68k/SVR4 it is a0. */ #undef STRUCT_VALUE_REGNUM #define STRUCT_VALUE_REGNUM 8 #define ASM_COMMENT_START "#" #undef TYPE_OPERAND_FMT #define TYPE_OPERAND_FMT "@%s" /* Define how the m68k registers should be numbered for Dwarf output. The numbering provided here should be compatible with the native SVR4 SDB debugger in the m68k/SVR4 reference port, where d0-d7 are 0-7, a0-a8 are 8-15, and fp0-fp7 are 16-23. */ #define DBX_REGISTER_NUMBER(REGNO) (REGNO) /* The ASM_OUTPUT_SKIP macro is first defined in m68k.h, using ".skip". It is then overridden by m68k/sgs.h to use ".space", and again by svr4.h to use ".zero". The m68k/SVR4 assembler uses ".space", so repeat the definition from m68k/sgs.h here. Note that ASM_NO_SKIP_IN_TEXT is defined in m68k/sgs.h, so we don't have to repeat it here. */ #undef ASM_OUTPUT_SKIP #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t%s %u\n", SPACE_ASM_OP, (SIZE)) /* 1 if N is a possible register number for a function value. For m68k/SVR4 allow d0, a0, or fp0 as return registers, for integral, pointer, or floating types, respectively. Reject fp0 if not using a 68881 coprocessor. */ #undef FUNCTION_VALUE_REGNO_P #define FUNCTION_VALUE_REGNO_P(N) \ ((N) == 0 || (N) == 8 || (TARGET_68881 && (N) == 16)) /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for more than one register. */ #undef NEEDS_UNTYPED_CALL #define NEEDS_UNTYPED_CALL 1 /* Define how to generate (in the callee) the output value of a function and how to find (in the caller) the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. For m68k/SVR4 generate the result in d0, a0, or fp0 as appropriate. */ #undef FUNCTION_VALUE #define FUNCTION_VALUE(VALTYPE, FUNC) \ (TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_68881 \ ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \ : (TREE_CODE (VALTYPE) == POINTER_TYPE \ ? gen_rtx (REG, TYPE_MODE (VALTYPE), 8) \ : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))) /* For compatibility with the large body of existing code which does not always properly declare external functions returning pointer types, the m68k/SVR4 convention is to copy the value returned for pointer functions from a0 to d0 in the function epilogue, so that callers that have neglected to properly declare the callee can still find the correct return value. */ extern int current_function_returns_pointer; #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) \ do { \ if ((current_function_returns_pointer) && \ ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode)) \ asm_fprintf (FILE, "\tmov.l %Ra0,%Rd0\n"); \ } while (0); /* Define how to find the value returned by a library function assuming the value has mode MODE. For m68k/SVR4 look for integer values in d0, pointer values in d0 (returned in both d0 and a0), and floating values in fp0. */ #undef LIBCALL_VALUE #define LIBCALL_VALUE(MODE) \ (((MODE) == SFmode || (MODE) == DFmode) && TARGET_68881 \ ? gen_rtx (REG, (MODE), 16) \ : gen_rtx (REG, (MODE), 0)) /* Boundary (in *bits*) on which stack pointer should be aligned. The m68k/SVR4 convention is to keep the stack pointer longword aligned. */ #undef STACK_BOUNDARY #define STACK_BOUNDARY 32 /* Alignment of field after `int : 0' in a structure. For m68k/SVR4, this is the next longword boundary. */ #undef EMPTY_FIELD_BOUNDARY #define EMPTY_FIELD_BOUNDARY 32 /* No data type wants to be aligned rounder than this. For m68k/SVR4, some types (doubles for example) are aligned on 8 byte boundaries */ #undef BIGGEST_ALIGNMENT #define BIGGEST_ALIGNMENT 64 /* SVR4 m68k assembler is bitching on the `comm i,1,1' which askes for 1 byte alignment. Don't generate alignment for COMMON seems to be safer until we the assembler is fixed. */ #undef ASM_OUTPUT_ALIGNED_COMMON /* Same problem with this one. */ #undef ASM_OUTPUT_ALIGNED_LOCAL /* The `string' directive on m68k svr4 does not handle string with escape char (ie., `\') right. Use normal way to output ASCII bytes seems to be safer. */ #undef ASM_OUTPUT_ASCII #define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ { \ register int sp = 0, lp = 0, ch; \ fprintf ((FILE), "\t%s ", BYTE_ASM_OP); \ do { \ ch = (PTR)[sp]; \ if (ch > ' ' && ! (ch & 0x80) && ch != '\\') \ { \ fprintf ((FILE), "'%c", ch); \ } \ else \ { \ fprintf ((FILE), "0x%x", ch); \ } \ if (++sp < (LEN)) \ { \ if ((sp % 10) == 0) \ { \ fprintf ((FILE), "\n\t%s ", BYTE_ASM_OP); \ } \ else \ { \ putc (',', (FILE)); \ } \ } \ } while (sp < (LEN)); \ putc ('\n', (FILE)); \ } /* SVR4 m68k assembler is bitching on the syntax `2.b'. So use the "LLDnnn-LLnnn" format. Define LLDnnn after the table. */ #undef ASM_OUTPUT_CASE_END #define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \ do { \ if (switch_table_difference_label_flag) \ asm_fprintf ((FILE), "\t%s %LLD%d,%LL%d\n", SET_ASM_OP, (NUM), (NUM));\ switch_table_difference_label_flag = 0; \ } while (0) int switch_table_difference_label_flag; #undef ASM_OUTPUT_COMMON #undef ASM_OUTPUT_LOCAL #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fputs (".comm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (SIZE))) #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( fputs (".lcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (SIZE))) /* Override the definition in svr4.h. In m68k svr4, using swbeg is the standard way to do switch table. */ #undef ASM_OUTPUT_BEFORE_CASE_LABEL #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \ fprintf ((FILE), "\t%s &%d\n", SWBEG_ASM_OP, XVECLEN (PATTERN (TABLE), 1)); /* In m68k svr4, a symbol_ref rtx can be a valid PIC operand if it is an operand of a function call. */ #undef LEGITIMATE_PIC_OPERAND_P #define LEGITIMATE_PIC_OPERAND_P(X) \ (! symbolic_operand (X, VOIDmode) \ || ((GET_CODE(X) == SYMBOL_REF) && SYMBOL_REF_FLAG(X))) /* Turn off function cse if we are doing PIC. We always want function call to be done as `bsr foo@PLTPC', so it will force the assembler to create the PLT entry for `foo'. Doing function cse will cause the address of `foo' to be loaded into a register, which is exactly what we want to avoid when we are doing PIC on svr4 m68k. */ #undef OVERRIDE_OPTIONS #define OVERRIDE_OPTIONS \ { \ if (flag_pic) flag_no_function_cse = 1; \ if (! TARGET_68020 && flag_pic == 2) \ error("-fPIC is not currently supported on the 68000 or 68010\n"); \ } gcc-2.5.8/config/m68k/mot3300.h100444 22011 13 72104 5474031746 14331 0ustar kenneruser/* Definitions of target machine for GNU compiler. SysV68 Motorola 3300 Delta Series Written by Abramo and Roberto Bagnara after Alex Crain's 3B1 definitions. Bug reports to bagnara@dipisa.di.unipi.it Copyright (C) 1987 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define MOTOROLA /* Use Motorola syntax rather than "MIT" */ #define SGS /* Uses SGS assembler */ #define SGS_CMP_ORDER /* Takes cmp operands in reverse order */ #define SGS_SWAP_W /* Use swap.w rather than just plain swap */ #define SGS_SWITCH_TABLES /* Different switch table handling */ #define NO_DOLLAR_IN_LABEL #define NO_DOT_IN_LABEL #include "m68k/m68k.h" /* See m68k.h. 7 means 68020 with 68881. */ #ifndef TARGET_DEFAULT #define TARGET_DEFAULT 7 #endif /* NYI: FP= is equivalent to -msoft-float */ /* We use /lib/libp/lib* when profiling. */ /* NYI: if FP=M68881U library is -lc881u */ /* NYI: if FP= library is -lc. */ /* Default for us: FP=M68881 library is -lc881 */ #undef LIB_SPEC #define LIB_SPEC "%{!shlib:%{p:-L/usr/lib/libp} %{pg:-L/usr/lib/libp} -lc881}" #define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__}" /* Shared libraries need to use crt0s.o */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{!shlib:%{pg:mcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}\ %{shlib:crt0s.o%s shlib.ifile%s} " /* Generate calls to memcpy, memcmp and memset. */ #define TARGET_MEM_FUNCTIONS /* size_t is unsigned int. */ #define SIZE_TYPE "unsigned int" /* Every structure or union's size must be a multiple of 2 bytes. */ #define STRUCTURE_SIZE_BOUNDARY 16 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ /* Be compatible with native compiler. */ #undef PARM_BOUNDARY #define PARM_BOUNDARY 16 /* cpp has to support a #sccs directive for the /usr/include files */ #define SCCS_DIRECTIVE /* Make output for SDB. */ #define SDB_DEBUGGING_INFO #undef REGISTER_PREFIX #define REGISTER_PREFIX "%" #undef IMMEDIATE_PREFIX #define IMMEDIATE_PREFIX "&" #undef REGISTER_NAMES #define REGISTER_NAMES \ {"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \ "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", \ "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7"} #if 0 /* phdm@info.ucl.ac.be says the standard ones work. */ #undef FUNCTION_PROLOGUE #define FUNCTION_PROLOGUE(FILE, SIZE) \ { register int regno; \ register int mask = 0; \ extern char call_used_regs[]; \ int fsize = (SIZE); \ if (frame_pointer_needed) \ { if (fsize < 0x8000) \ fprintf (FILE, "\tlink.w %%fp,&%d\n", -fsize); \ else if (TARGET_68020) \ fprintf (FILE, "\tlink.l %%fp,&%d\n", -fsize); \ else \ fprintf (FILE, "\tlink.w %%fp,&0\n\tsub.l &%d,%%sp\n", fsize); } \ for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ mask |= 1 << (regno - 16); \ if (mask != 0) \ fprintf (FILE, "\tfmovem &0x%x,-(%%sp)\n", mask & 0xff); \ mask = 0; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ mask |= 1 << (15 - regno); \ if (frame_pointer_needed) \ mask &= ~ (1 << (15-FRAME_POINTER_REGNUM)); \ if (exact_log2 (mask) >= 0) \ fprintf (FILE, "\tmov.l %s,-(%%sp)\n", reg_names[15 - exact_log2 (mask)]); \ else if (mask) fprintf (FILE, "\tmovm.l &0x%x,-(%%sp)\n", mask); } #endif /* 0 */ #undef FUNCTION_PROFILER #define FUNCTION_PROFILER(FILE, LABEL_NO) \ fprintf (FILE, "\tmov.l &LP%%%d,%%a0\n\tjsr mcount%%\n", (LABEL_NO)) #if 0 /* phdm@info.ucl.ac.be says the standard ones work. */ #undef FUNCTION_EPILOGUE #define FUNCTION_EPILOGUE(FILE, SIZE) \ { register int regno; \ register int mask, fmask; \ register int nregs; \ int offset, foffset; \ extern char call_used_regs[]; \ int fsize = (SIZE); \ int big = 0; \ nregs = 0; fmask = 0; \ for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ { nregs++; fmask |= 1 << (23 - regno); } \ foffset = nregs * 12; \ nregs = 0; mask = 0; \ if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ { nregs++; mask |= 1 << regno; } \ offset = foffset + nregs * 4; \ if (offset + fsize >= 0x8000 && frame_pointer_needed) \ { fprintf (FILE, "\tmov.l &%d,%%a0\n", -fsize); \ fsize = 0, big = 1; } \ if (exact_log2 (mask) >= 0) { \ if (big) \ fprintf (FILE, "\tmov.l -%d(%%fp,%%a0.l),%s\n", \ offset + fsize, reg_names[exact_log2 (mask)]); \ else if (! frame_pointer_needed) \ fprintf (FILE, "\tmov.l (%%sp)+,%s\n", \ reg_names[exact_log2 (mask)]); \ else \ fprintf (FILE, "\tmov.l -%d(%%fp),%s\n", \ offset + fsize, reg_names[exact_log2 (mask)]); } \ else if (mask) { \ if (big) \ fprintf (FILE, "\tmovm.l -%d(%%fp,%%a0.l),&0x%x\n", \ offset + fsize, mask); \ else if (! frame_pointer_needed) \ fprintf (FILE, "\tmovm.l (%%sp)+,&0x%x\n", mask); \ else \ fprintf (FILE, "\tmovm.l -%d(%%fp),&0x%x\n", \ offset + fsize, mask); } \ if (fmask) { \ if (big) \ fprintf (FILE, "\tfmovem -%d(%%fp,%%a0.l),&0x%x\n", \ foffset + fsize, fmask); \ else if (! frame_pointer_needed) \ fprintf (FILE, "\tfmovem (%%sp)+,&0x%x\n", fmask); \ else \ fprintf (FILE, "\tfmovem -%d(%%fp),&0x%x\n", \ foffset + fsize, fmask); } \ if (frame_pointer_needed) \ fprintf (FILE, "\tunlk %%fp\n"); \ if (current_function_pops_args) \ fprintf (FILE, "\trtd &%d\n", current_function_pops_args); \ else fprintf (FILE, "\trts\n"); } #endif /* 0 */ /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #undef ASM_OUTPUT_REG_PUSH #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tmov.l %s,-(%%sp)\n", reg_names[REGNO]) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #undef ASM_OUTPUT_REG_POP #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tmov.l (%%sp)+,%s\n", reg_names[REGNO]) #undef ASM_APP_ON #define ASM_APP_ON "" #undef ASM_APP_OFF #define ASM_APP_OFF "" #undef TEXT_SECTION_ASM_OP #define TEXT_SECTION_ASM_OP "text" #undef DATA_SECTION_ASM_OP #define DATA_SECTION_ASM_OP "data" #undef ASCII_DATA_ASM_OP #define ASCII_DATA_ASM_OP "byte" /* The file command should always begin the output. */ #undef ASM_FILE_START #define ASM_FILE_START(FILE) \ output_file_directive ((FILE), main_input_filename) /* Don't try to define `gcc_compiled.' since the assembler might not accept symbols with periods and GDB doesn't run on this machine anyway. */ #define ASM_IDENTIFY_GCC(FILE) /* Names to predefine in the preprocessor for this target machine. */ /* ihnp4!lmayk!lgm@eddie.mit.edu says mc68000 and m68k should not be here, on the other hand I don't care what he says. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dm68k -Dunix -DsysV68 -D__motorola__ -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)" #if 0 /* phdm@info.ucl.ac.be says the right way is with PARM_BOUNDARY. */ /* Specify how to pad function arguments. Value should be `upward', `downward' or `none'. Same as the default, except no padding for large or variable-size args. */ #define FUNCTION_ARG_PADDING(MODE, TYPE) \ (((MODE) == BLKmode \ ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ && int_size_in_bytes (TYPE) < PARM_BOUNDARY / BITS_PER_UNIT) \ : GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY) \ ? downward : none) #endif /* 0 */ /* Override part of the obstack macros. */ #define __PTR_TO_INT(P) ((int)(P)) #define __INT_TO_PTR(P) ((char *)(P)) #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (68k, SGS/AT&T sysV68 syntax)"); /* Function calls save all but a0, a1, d0, d1, fp0, fp1. */ #undef CALL_USED_REGISTERS #define CALL_USED_REGISTERS \ {1, 1, 0, 0, 0, 0, 0, 0, \ 1, 1, 0, 0, 0, 0, 0, 1, \ 1, 1, 0, 0, 0, 0, 0, 0} /* If TARGET_68881, return SF and DF values in fp0 instead of d0. */ /* NYI: If FP=M68881U return SF and DF values in d0. */ /* NYI: If -mold return pointer in a0 and d0 */ #undef FUNCTION_VALUE #define FUNCTION_VALUE(VALTYPE,FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE)) /* sysV68 (brain damaged) cc convention support. */ /* Commented out until we find a safe way to make it optional. */ #if 0 #define FUNCTION_VALUE(VALTYPE,FUNC) \ (TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_68881 \ ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \ : (TREE_CODE (VALTYPE) == POINTER_TYPE \ ? gen_rtx (REG, TYPE_MODE (VALTYPE), 8) \ : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))) #endif /* If TARGET_68881, SF and DF values are returned in fp0 instead of d0. */ #undef LIBCALL_VALUE #define LIBCALL_VALUE(MODE) \ gen_rtx (REG, (MODE), \ ((TARGET_68881 \ && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) \ ? 16 : 0)) /* 1 if N is a possible register number for a function value. d0 may be used, and fp0 as well if -msoft-float is not specified. */ #undef FUNCTION_VALUE_REGNO_P #define FUNCTION_VALUE_REGNO_P(N) \ ((N) == 0 || (TARGET_68881 && (N) == 16)) /* sysV68 (brain damaged) cc convention support. */ /* Commented out until we find a safe way to make it optional. */ #if 0 #define FUNCTION_VALUE_REGNO_P(N) \ ((N) == 0 || (N) == 8 || (TARGET_68881 && (N) == 16)) #endif /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for more than one register. */ #undef NEEDS_UNTYPED_CALL #define NEEDS_UNTYPED_CALL 1 /* This is the command to make the user-level label named NAME defined for reference from other files. */ #undef GLOBAL_ASM_OP #define GLOBAL_ASM_OP "global" /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #undef ASM_FORMAT_PRIVATE_NAME #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12), \ sprintf ((OUTPUT), "%s_%%%d", (NAME), (LABELNO))) /* The sysV68 as doesn't know about double's and float's. */ /* This is how to output an assembler line defining a `double' constant. */ #undef ASM_OUTPUT_DOUBLE #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { long l[2]; \ REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ fprintf (FILE, "\tlong 0x%x,0x%x\n", l[0], l[1]); \ } while (0) #undef ASM_OUTPUT_LONG_DOUBLE #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ do { long l[3]; \ REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ fprintf (FILE, "\tlong 0x%x,0x%x,0x%x\n", l[0], l[1], l[2]); \ } while (0) /* This is how to output an assembler line defining a `float' constant. */ #undef ASM_OUTPUT_FLOAT #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { long l; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ fprintf ((FILE), "\tlong 0x%x\n", l); \ } while (0) /* This is how to output an assembler line defining an `int' constant. */ #undef ASM_OUTPUT_INT #define ASM_OUTPUT_INT(FILE,VALUE) \ ( fprintf (FILE, "\tlong "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* Likewise for `char' and `short' constants. */ #undef ASM_OUTPUT_SHORT #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "\tshort "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #undef ASM_OUTPUT_CHAR #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ( fprintf (FILE, "\tbyte "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* This is how to output an assembler line for a numeric constant byte. */ #undef ASM_OUTPUT_BYTE #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf (FILE, "\tbyte 0x%x\n", (VALUE)) /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #undef ASM_OUTPUT_ALIGN #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG) == 1) \ fprintf (FILE, "\teven\n"); \ else if ((LOG) != 0) \ abort (); #undef ASM_OUTPUT_SKIP #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\tspace %u\n", (SIZE)) /* Can't use ASM_OUTPUT_SKIP in text section. */ #define ASM_NO_SKIP_IN_TEXT 1 /* The beginnings of sdb support... */ #undef ASM_OUTPUT_SOURCE_FILENAME #define ASM_OUTPUT_SOURCE_FILENAME(FILE, FILENAME) \ do { fprintf (FILE, "\tfile\t"); \ output_quoted_string (FILE, FILENAME); \ fprintf (FILE, "\n"); \ } while (0) #undef ASM_OUTPUT_SOURCE_LINE #define ASM_OUTPUT_SOURCE_LINE(FILE, LINENO) \ fprintf (FILE, "\tln\t%d\n", \ (sdb_begin_function_line \ ? last_linenum - sdb_begin_function_line : 1)) /* Yet another null terminated string format. */ #undef ASM_OUTPUT_ASCII #define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ { register int sp = 0, lp = 0; \ fprintf ((FILE), "\tbyte\t"); \ loop: \ if ((PTR)[sp] > ' ' && ! ((PTR)[sp] & 0x80) && (PTR)[sp] != '\\') \ { lp += 3; \ fprintf ((FILE), "'%c", (PTR)[sp]); } \ else \ { lp += 5; \ fprintf ((FILE), "0x%x", (PTR)[sp]); } \ if (++sp < (LEN)) \ { if (lp > 60) \ { lp = 0; \ fprintf ((FILE), "\n\t%s ", ASCII_DATA_ASM_OP); } \ else \ putc (',', (FILE)); \ goto loop; } \ putc ('\n', (FILE)); } /* Print operand X (an rtx) in assembler syntax to file FILE. CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. For `%' followed by punctuation, CODE is the punctuation and X is null. On the 68000, we use several CODE characters: '.' for dot needed in Motorola-style opcode names. '-' for an operand pushing on the stack: sp@-, -(sp) or -(%sp) depending on the style of syntax. '+' for an operand pushing on the stack: sp@+, (sp)+ or (%sp)+ depending on the style of syntax. '@' for a reference to the top word on the stack: sp@, (sp) or (%sp) depending on the style of syntax. '#' for an immediate operand prefix (# in MIT and Motorola syntax but & in SGS syntax). '!' for the fpcr register (used in some float-to-fixed conversions). '$' for the letter `s' in an op code, but only on the 68040. '&' for the letter `d' in an op code, but only on the 68040. 'b' for byte insn (no effect, on the Sun; this is for the ISI). 'd' to force memory addressing to be absolute, not relative. 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather than directly). Second part of 'y' below. 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), or print pair of registers as rx:ry. 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs CONST_DOUBLE's as SunFPA constant RAM registers if possible, so it should not be used except for the SunFPA. */ #undef PRINT_OPERAND #define PRINT_OPERAND(FILE, X, CODE) \ { if (CODE == '.') fprintf (FILE, "."); \ else if (CODE == '#') fprintf (FILE, "&"); \ else if (CODE == '-') fprintf (FILE, "-(%%sp)"); \ else if (CODE == '+') fprintf (FILE, "(%%sp)+"); \ else if (CODE == '@') fprintf (FILE, "(%%sp)"); \ else if (CODE == '!') fprintf (FILE, "%%fpcr"); \ else if (CODE == '$') { if (TARGET_68040_ONLY) fprintf (FILE, "s"); } \ else if (CODE == '&') { if (TARGET_68040_ONLY) fprintf (FILE, "d"); } \ else if (CODE == '/') \ fprintf (FILE, "%%"); \ else if (GET_CODE (X) == REG) \ fprintf (FILE, "%s", reg_names[REGNO (X)]); \ else if (GET_CODE (X) == MEM) \ output_address (XEXP (X, 0)); \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \ { REAL_VALUE_TYPE r; long l; \ REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ REAL_VALUE_TO_TARGET_SINGLE (r, l); \ /* Use hex representation even if CODE is f. as needs it. */ \ fprintf (FILE, "&0x%x", l); } \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode) \ { REAL_VALUE_TYPE r; int i[2]; \ REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ REAL_VALUE_TO_TARGET_DOUBLE (r, i); \ fprintf (FILE, "&0x%08x%08x", i[0], i[1]); } \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == XFmode) \ { REAL_VALUE_TYPE r; \ REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ ASM_OUTPUT_LONG_DOUBLE_OPERAND (FILE, r); } \ else { putc ('&', FILE); output_addr_const (FILE, X); }} #undef PRINT_OPERAND_ADDRESS #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ { register rtx reg1, reg2, breg, ireg; \ register rtx addr = ADDR; \ rtx offset; \ switch (GET_CODE (addr)) \ { \ case REG: \ fprintf (FILE, "(%s)", reg_names[REGNO (addr)]); \ break; \ case PRE_DEC: \ fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case POST_INC: \ fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case PLUS: \ reg1 = 0; reg2 = 0; \ ireg = 0; breg = 0; \ offset = 0; \ if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \ { \ offset = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \ { \ offset = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) != PLUS) ; \ else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == MULT) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == MULT) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == REG) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == REG) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \ || GET_CODE (addr) == SIGN_EXTEND) \ { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \ /* for OLD_INDEXING \ else if (GET_CODE (addr) == PLUS) \ { \ if (GET_CODE (XEXP (addr, 0)) == REG) \ { \ reg2 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == REG) \ { \ reg2 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ } \ */ \ if (offset != 0) { if (addr != 0) abort (); addr = offset; } \ if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \ || GET_CODE (reg1) == MULT)) \ || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \ { breg = reg2; ireg = reg1; } \ else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \ { breg = reg1; ireg = reg2; } \ if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \ { int scale = 1; \ if (GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "12(%%pc,%s.w", \ reg_names[REGNO (XEXP (ireg, 0))]); \ else \ fprintf (FILE, "12(%%pc,%s.l", \ reg_names[REGNO (ireg)]); \ if (scale != 1) fprintf (FILE, "*%d", scale); \ fprintf (FILE, ")"); \ break; } \ if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF) \ { fprintf (FILE, "12(%%pc,%s.l", \ reg_names[REGNO (breg)]); \ putc (')', FILE); \ break; } \ if (ireg != 0 || breg != 0) \ { int scale = 1; \ if (breg == 0) \ abort (); \ if (addr != 0) \ output_addr_const (FILE, addr); \ fprintf (FILE, "(%s", reg_names[REGNO (breg)]); \ if (ireg != 0) \ putc (',', FILE); \ if (ireg != 0 && GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]); \ else if (ireg != 0) \ fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]); \ if (scale != 1) fprintf (FILE, "*%d", scale); \ putc (')', FILE); \ break; \ } \ else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \ { fprintf (FILE, "12(%%pc,%s.w)", \ reg_names[REGNO (reg1)]); \ break; } \ default: \ if (GET_CODE (addr) == CONST_INT \ && INTVAL (addr) < 0x8000 \ && INTVAL (addr) >= -0x8000) \ fprintf (FILE, "%d", INTVAL (addr)); \ else \ output_addr_const (FILE, addr); \ }} /* This is how to store into the string LABEL the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. */ #undef ASM_GENERATE_INTERNAL_LABEL #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ sprintf ((LABEL), "%s%%%d", (PREFIX), (NUM)) /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. */ #undef ASM_OUTPUT_INTERNAL_LABEL #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, "%s%%%d:\n", PREFIX, NUM) /* This is how to output a reference to a user-level label named NAME. `assemble_name' uses this. */ #undef ASM_OUTPUT_LABELREF #define ASM_OUTPUT_LABELREF(FILE,NAME) \ fprintf (FILE, "%s", NAME) /* This is how to output an element of a case-vector that is absolute. (The 68000 does not use such vectors, but we must define this macro anyway.) */ #undef ASM_OUTPUT_ADDR_VEC_ELT #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "\tlong L%%%d\n", (VALUE)) /* This is how to output an element of a case-vector that is relative. */ #undef ASM_OUTPUT_ADDR_DIFF_ELT #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\tshort L%%%d-L%%%d\n", (VALUE), (REL)) #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \ fprintf (FILE, "\tswbeg &%d\n%s%%%d:\n", \ XVECLEN (PATTERN (TABLE), 1), (PREFIX), (NUM)) #if 0 /* At end of a switch table, define LD%n iff the symbol LI%n was defined. */ #define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \ { if (switch_table_difference_label_flag) \ asm_fprintf (FILE, "\t%s %LLD%d,%LL%d-%LLI%d-2.b\n",\ SET_ASM_OP, (NUM), (NUM), (NUM)) \ switch_table_difference_label_flag = 0; } #endif /* We have to define this to avoid errors. */ int switch_table_difference_label_flag; /* Translate some opcodes to fit the sysV68 assembler syntax. */ /* The opcodes fdmov and fsmov are guesses. */ #define SWITCH_JUMP_MATCH "jmp 6(%%pc," /* cliffm@netcom.com says no need for .w suffix on jumps. */ #undef ASM_OUTPUT_OPCODE #define ASM_OUTPUT_OPCODE(FILE, PTR) \ { if ((PTR)[0] == 'j' && (PTR)[1] == 'b') \ { ++(PTR); \ while (*(PTR) != ' ') \ { putc (*(PTR), (FILE)); ++(PTR); } \ } \ else if ((PTR)[0] == 's') \ { \ if (!strncmp ((PTR), "swap", 4)) \ { fprintf ((FILE), "swap.w"); (PTR) += 4; } \ } \ else if ((PTR)[0] == 'f') \ { \ if (!strncmp ((PTR), "fmove", 5)) \ { fprintf ((FILE), "fmov"); (PTR) += 5; } \ else if (!strncmp ((PTR), "f%$move", 7)) \ { if (TARGET_68040_ONLY) \ { fprintf ((FILE), "fsmov"); (PTR) += 7; } \ else \ { fprintf ((FILE), "fmov"); (PTR) += 7; } } \ else if (!strncmp ((PTR), "f%&move", 7)) \ { if (TARGET_68040_ONLY) \ { fprintf ((FILE), "fdmov"); (PTR) += 7; } \ else \ { fprintf ((FILE), "fmov"); (PTR) += 7; } } \ else if (!strncmp ((PTR), "ftst", 4)) \ { fprintf ((FILE), "ftest"); (PTR) += 4; } \ else if (!strncmp ((PTR), "fbne", 4)) \ { fprintf ((FILE), "fbneq"); (PTR) += 4; } \ else if (!strncmp ((PTR), "fsne", 4)) \ { fprintf ((FILE), "fsneq"); (PTR) += 4; } \ } \ /* MOVE, MOVEA, MOVEQ, MOVEC ==> MOV */ \ else if ((PTR)[0] == 'm' && (PTR)[1] == 'o' \ && (PTR)[2] == 'v' && (PTR)[3] == 'e') \ { fprintf ((FILE), "mov"); (PTR) += 4; \ if ((PTR)[0] == 'q' || (PTR)[0] == 'a' \ || (PTR)[0] == 'c') (PTR)++; } \ /* SUB, SUBQ, SUBA, SUBI ==> SUB */ \ else if ((PTR)[0] == 's' && (PTR)[1] == 'u' \ && (PTR)[2] == 'b') \ { fprintf ((FILE), "sub"); (PTR) += 3; \ if ((PTR)[0] == 'q' || (PTR)[0] == 'i' \ || (PTR)[0] == 'a') (PTR)++; } \ /* CMP, CMPA, CMPI, CMPM ==> CMP */ \ else if ((PTR)[0] == 'c' && (PTR)[1] == 'm' \ && (PTR)[2] == 'p') \ { fprintf ((FILE), "cmp"); (PTR) += 3; \ if ((PTR)[0] == 'a' || (PTR)[0] == 'i' \ || (PTR)[0] == 'm') (PTR)++; } \ /* JMP to switch label */ \ else if (!strncmp((PTR), (SWITCH_JUMP_MATCH), sizeof(SWITCH_JUMP_MATCH) - 1)) \ { while (*(PTR)++ != '('); \ fprintf ((FILE), "jmp 8("); } \ } /* phdm@info.ucl.ac.be says to pass SIZE, not ROUNDED. */ /* This says how to output an assembler line to define a global common symbol. */ #undef ASM_OUTPUT_COMMON #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fputs ("\tcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (SIZE))) /* This says how to output an assembler line to define a local common symbol. */ #undef ASM_OUTPUT_LOCAL #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( fputs ("\tlcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (SIZE))) /* Override usual definitions of SDB output macros. These definitions differ only in the absence of the period at the beginning of the name of the directive and in the use of `~' as the symbol for the current location. */ #define PUT_SDB_SCL(a) fprintf(asm_out_file, "\tscl\t%d;", (a)) #define PUT_SDB_INT_VAL(a) fprintf (asm_out_file, "\tval\t%d;", (a)) #define PUT_SDB_VAL(a) \ ( fputs ("\tval\t", asm_out_file), \ output_addr_const (asm_out_file, (a)), \ fputc (';', asm_out_file)) #define PUT_SDB_DEF(a) \ do { fprintf (asm_out_file, "\tdef\t"); \ ASM_OUTPUT_LABELREF (asm_out_file, a); \ fprintf (asm_out_file, ";"); } while (0) #define PUT_SDB_PLAIN_DEF(a) fprintf(asm_out_file,"\tdef\t~%s;",a) #define PUT_SDB_ENDEF fputs("\tendef\n", asm_out_file) #define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\ttype\t0%o;", a) #define PUT_SDB_SIZE(a) fprintf(asm_out_file, "\tsize\t%d;", a) #define PUT_SDB_START_DIM fprintf(asm_out_file, "\tdim\t") #define PUT_SDB_NEXT_DIM(a) fprintf(asm_out_file, "%d,", a) #define PUT_SDB_LAST_DIM(a) fprintf(asm_out_file, "%d;", a) #define PUT_SDB_TAG(a) \ do { fprintf (asm_out_file, "\ttag\t"); \ ASM_OUTPUT_LABELREF (asm_out_file, a); \ fprintf (asm_out_file, ";"); } while (0) #define PUT_SDB_BLOCK_START(LINE) \ fprintf (asm_out_file, \ "\tdef\t~bb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n", \ (LINE)) #define PUT_SDB_BLOCK_END(LINE) \ fprintf (asm_out_file, \ "\tdef\t~eb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n", \ (LINE)) #define PUT_SDB_FUNCTION_START(LINE) \ fprintf (asm_out_file, \ "\tdef\t~bf;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n", \ (LINE)) #define PUT_SDB_FUNCTION_END(LINE) \ fprintf (asm_out_file, \ "\tdef\t~ef;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n", \ (LINE)) #define PUT_SDB_EPILOGUE_END(NAME) \ fprintf (asm_out_file, \ "\tdef\t%s;\tval\t~;\tscl\t-1;\tendef\n", \ (NAME)) #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \ sprintf ((BUFFER), "~%dfake", (NUMBER)); /* Define subroutines to call to handle multiply, divide, and remainder. Use the subroutines that the 3b1's library provides. The `*' prevents an underscore from being prepended by the compiler. */ #define DIVSI3_LIBCALL "*ldiv" #define UDIVSI3_LIBCALL "*uldiv" #define MODSI3_LIBCALL "*lrem" #define UMODSI3_LIBCALL "*ulrem" #define MULSI3_LIBCALL "*lmul" #define UMULSI3_LIBCALL "*ulmul" gcc-2.5.8/config/m68k/news.h100444 22011 13 42043 5472070773 14200 0ustar kenneruser/* Definitions of target machine for GNU compiler. SONY NEWS-OS 4 version. Copyright (C) 1987, 1989, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef USE_GAS /* This controls conditionals in m68k.h. */ #define MOTOROLA /* Use Motorola syntax rather than "MIT" */ #define SGS_NO_LI /* Suppress jump table label usage */ #endif #define NO_DOLLAR_IN_LABEL #define NO_DOT_IN_LABEL #include "m68k/m68k.h" /* See m68k.h. 7 means 68020 with 68881. */ #define TARGET_DEFAULT 7 /* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified. This will control the use of inline 68881 insns in certain macros. */ #define CPP_SPEC "%{!msoft-float:-D__HAVE_68881__}" /* Names to predefine in the preprocessor for this target machine. */ /* These are the ones defined by Sony, plus mc68000 for uniformity with GCC on other 68000 systems. */ #ifdef MOTOROLA #define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dnews700 -D__motorola__ -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)" #else #define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dnews700 -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)" #endif /* These conditionals tested for different submodels, but they were incorrect since they tested the host rather than the target. The choice of model shouldn't actually matter. */ #if 0 #ifdef news800 #define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dnews800 -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)" #endif #ifdef news900 #define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dnews900 -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)" #endif #ifdef news1500 #define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dmc68030 -Dnews1500 -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)" #endif #ifdef news1700 #define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dmc68030 -Dnews1700 -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)" #endif #ifdef news1800 #define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dmc68030 -Dnews1800 -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)" #endif #ifdef news1900 #define CPP_PREDEFINES "-Dunix -Dbsd43 -Dsony -Dsony_news -Dmc68000 -Dmc68020 -Dmc68030 -Dnews1900 -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)" #endif #endif /* Link with libg.a when debugging, for dbx's sake. */ #define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} " /* This is BSD, so it wants DBX format. */ #define DBX_DEBUGGING_INFO #if 0 /* This is to be compatible with types.h. It was found to be necessary with Newsos 3. */ #define SIZE_TYPE "long int" #endif /* Override parts of m68k.h to fit Sony's assembler syntax. */ #undef BIGGEST_ALIGNMENT #undef CALL_USED_REGISTERS #undef FUNCTION_VALUE #undef LIBCALL_VALUE #undef FUNCTION_PROFILER #ifdef MOTOROLA #undef FUNCTION_PROLOGUE #undef FUNCTION_EPILOGUE #undef REGISTER_NAMES #undef ASM_OUTPUT_REG_PUSH #undef ASM_OUTPUT_REG_POP #undef ASM_OUTPUT_DOUBLE #undef ASM_OUTPUT_SKIP #undef ASM_FORMAT_PRIVATE_NAME #undef PRINT_OPERAND #undef PRINT_OPERAND_ADDRESS #endif #undef ASM_OUTPUT_ALIGN /* There is no point aligning anything to a rounder boundary than this. */ #define BIGGEST_ALIGNMENT 32 /* A bitfield declared as `int' forces `int' alignment for the struct. */ #define PCC_BITFIELD_TYPE_MATTERS 1 /* NEWS makes d2, d3, fp2 and fp3 unsaved registers, unlike the Sun system. */ #define CALL_USED_REGISTERS \ {1, 1, 1, 1, 0, 0, 0, 0, \ 1, 1, 0, 0, 0, 0, 0, 1, \ 1, 1, 1, 1, 0, 0, 0, 0} /* NEWS returns floats and doubles in fp0, not d0/d1. */ #define FUNCTION_VALUE(VALTYPE,FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE)) #define LIBCALL_VALUE(MODE) \ gen_rtx (REG, (MODE), \ ((TARGET_68881 \ && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) \ ? 16 : 0)) #define ASM_OUTPUT_ALIGN(FILE,LOG) \ fprintf (FILE, "\t.align %d\n", (LOG)) #ifdef MOTOROLA /* Don't try to define `gcc_compiled.' since the assembler does not accept symbols with periods. This is no real loss since GDB only really needs it for parms passed in registers. */ #define ASM_IDENTIFY_GCC(FILE) #define FUNCTION_PROLOGUE(FILE, SIZE) \ { register int regno; \ register int mask = 0; \ extern char call_used_regs[]; \ int fsize = ((SIZE) + 3) & -4; \ if (frame_pointer_needed) \ { if (fsize < 0x8000) \ fprintf (FILE, "\tlink fp,#%d\n", -fsize); \ else if (TARGET_68020) \ fprintf (FILE, "\tlink.l fp,#%d\n", -fsize); \ else \ fprintf (FILE, "\tlink fp,#0\n\tsub.l #%d,sp\n", fsize);\ } \ else if (fsize) \ { \ int amt = fsize + 4; \ /* Adding negative number is faster on the 68040. */ \ if (fsize + 4 < 0x8000) \ asm_fprintf (FILE, "\tadd.w %0I%d,%Rsp\n", - amt); \ else \ asm_fprintf (FILE, "\tadd.l %0I%d,%Rsp\n", - amt); \ } \ for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ mask |= 1 << (regno - 16); \ if (mask != 0) \ fprintf (FILE, "\tfmovem.x #0x%x,-(sp)\n", mask & 0xff); \ mask = 0; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ mask |= 1 << (15 - regno); \ if (frame_pointer_needed) \ mask &= ~ (1 << (15-FRAME_POINTER_REGNUM)); \ if (exact_log2 (mask) >= 0) \ fprintf (FILE, "\tmove.l %s,-(sp)\n", reg_names[15 - exact_log2 (mask)]); \ else if (mask) fprintf (FILE, "\tmovem.l #0x%x,-(sp)\n", mask); } #define FUNCTION_PROFILER(FILE, LABEL_NO) \ fprintf (FILE, "\tmove.l #LP%d,d0\n\tjsr mcount\n", (LABEL_NO)); #define FUNCTION_EPILOGUE(FILE, SIZE) \ { register int regno; \ register int mask, fmask; \ register int nregs; \ int offset, foffset; \ extern char call_used_regs[]; \ int fsize = ((SIZE) + 3) & -4; \ int big = 0; \ nregs = 0; fmask = 0; \ for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ { nregs++; fmask |= 1 << (23 - regno); } \ foffset = nregs * 12; \ nregs = 0; mask = 0; \ if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ { nregs++; mask |= 1 << regno; } \ offset = foffset + nregs * 4; \ if (offset + fsize >= 0x8000 \ && frame_pointer_needed \ && (mask || fmask)) \ { fprintf (FILE, "\tmove.l #%d,a0\n", -fsize); \ fsize = 0, big = 1; } \ if (exact_log2 (mask) >= 0) { \ if (big) \ fprintf (FILE, "\tmove.l (-%d,fp,a0.l),%s\n", \ offset + fsize, reg_names[exact_log2 (mask)]); \ else if (! frame_pointer_needed) \ fprintf (FILE, "\tmove.l (sp)+,%s\n", \ reg_names[exact_log2 (mask)]); \ else \ fprintf (FILE, "\tmove.l (-%d,fp),%s\n", \ offset + fsize, reg_names[exact_log2 (mask)]); } \ else if (mask) { \ if (big) \ fprintf (FILE, "\tmovem.l (-%d,fp,a0.l),#0x%x\n", \ offset + fsize, mask); \ else if (! frame_pointer_needed) \ fprintf (FILE, "\tmovem.l (sp)+,#0x%x\n", mask); \ else \ fprintf (FILE, "\tmovem.l (-%d,fp),#0x%x\n", \ offset + fsize, mask); } \ if (fmask) { \ if (big) \ fprintf (FILE, "\tfmovem.x (-%d,fp,a0.l),#0x%x\n", \ foffset + fsize, fmask); \ else if (! frame_pointer_needed) \ fprintf (FILE, "\tfmovem.x (sp)+,#0x%x\n", fmask); \ else \ fprintf (FILE, "\tfmovem.x (-%d,fp),#0x%x\n", \ foffset + fsize, fmask); } \ if (frame_pointer_needed) \ fprintf (FILE, "\tunlk fp\n"); \ else if (fsize) \ { \ if (fsize + 4 < 0x8000) \ fprintf (FILE, "\tadd.w #%d,sp\n", fsize + 4); \ else \ fprintf (FILE, "\tadd.l #%d,sp\n", fsize + 4); \ } \ if (current_function_pops_args) \ fprintf (FILE, "\trtd #%d\n", current_function_pops_args); \ else fprintf (FILE, "\trts\n"); } /* Difference from m68k.h is in `fp' instead of `a6'. */ #define REGISTER_NAMES \ {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ "a0", "a1", "a2", "a3", "a4", "a5", "fp", "sp", \ "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7"} /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tmove.l %s,-(sp)\n", reg_names[REGNO]) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tmove.l (sp)+,%s\n", reg_names[REGNO]) #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { char dstr[30]; \ REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \ fprintf (FILE, "\t.double 0d%s\n", dstr); \ } while (0) #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t.space %u\n", (SIZE)) #if 0 /* The NEWS assembler in version 3.4 complains about fmove.d, but this macro proved not to work right. 3.4 is old, so forget about it. */ #define ASM_OUTPUT_OPCODE(FILE, STRING) \ { \ if (!strncmp (STRING, "fmove.d", 7) \ && CONSTANT_P (operands[1])) \ { \ fprintf (FILE, "fmove.x"); \ STRING += 7; \ } \ } #endif /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 13), \ sprintf ((OUTPUT), "%s$$$%d", (NAME), (LABELNO))) #define PRINT_OPERAND(FILE, X, CODE) \ { if (CODE == '.') fprintf (FILE, "."); \ else if (CODE == '#') fprintf (FILE, "#"); \ else if (CODE == '-') fprintf (FILE, "-(sp)"); \ else if (CODE == '+') fprintf (FILE, "(sp)+"); \ else if (CODE == '@') fprintf (FILE, "(sp)"); \ else if (CODE == '!') fprintf (FILE, "fpcr"); \ else if (CODE == '$') {if (TARGET_68040_ONLY) fprintf (FILE, "s");} \ else if (CODE == '&') {if (TARGET_68040_ONLY) fprintf (FILE, "d");} \ else if (CODE == '/') \ ; \ else if (GET_CODE (X) == REG) \ fprintf (FILE, "%s", reg_names[REGNO (X)]); \ else if (GET_CODE (X) == MEM) \ output_address (XEXP (X, 0)); \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \ { REAL_VALUE_TYPE r; \ REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ if (CODE == 'f') \ { char dstr[30]; \ REAL_VALUE_TO_DECIMAL (r, "%.9e", dstr); \ fprintf (FILE, "#0f%s", dstr); \ } \ else \ { long l; \ REAL_VALUE_TO_TARGET_SINGLE (r, l); \ fprintf (FILE, "#0x%x", l); \ }} \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == XFmode) \ { REAL_VALUE_TYPE r; \ REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ ASM_OUTPUT_LONG_DOUBLE_OPERAND (FILE, r); } \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != DImode) \ { REAL_VALUE_TYPE r; char dstr[30]; \ REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ REAL_VALUE_TO_DECIMAL (r, "%.20e", dstr ); \ fprintf (FILE, "#0d%s", dstr); } \ else if (CODE == 'b') output_addr_const (FILE, X); \ else { putc ('#', FILE); output_addr_const (FILE, X); }} #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ { register rtx reg1, reg2, breg, ireg; \ register rtx addr = ADDR; \ rtx offset; \ switch (GET_CODE (addr)) \ { \ case REG: \ fprintf (FILE, "(%s)", reg_names[REGNO (addr)]); \ break; \ case PRE_DEC: \ fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case POST_INC: \ fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case PLUS: \ reg1 = 0; reg2 = 0; \ ireg = 0; breg = 0; \ offset = 0; \ if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \ { \ offset = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \ { \ offset = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) != PLUS) ; \ else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == MULT) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == MULT) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == REG) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == REG) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \ || GET_CODE (addr) == SIGN_EXTEND) \ { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \ if (offset != 0) { if (addr != 0) abort (); addr = offset; } \ if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \ || GET_CODE (reg1) == MULT)) \ || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \ { breg = reg2; ireg = reg1; } \ else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \ { breg = reg1; ireg = reg2; } \ if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \ { int scale = 1; \ if (GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "(L%d.b,pc,%s.w", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (XEXP (ireg, 0))]); \ else \ fprintf (FILE, "(L%d.b,pc,%s.l", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (ireg)]); \ if (scale != 1) fprintf (FILE, "*%d", scale); \ putc (')', FILE); \ break; } \ if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF) \ { fprintf (FILE, "(L%d.b,pc,%s.l", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (breg)]); \ putc (')', FILE); \ break; } \ if (ireg != 0 || breg != 0) \ { int scale = 1; \ if (breg == 0) \ abort (); \ if (addr && GET_CODE (addr) == LABEL_REF) abort (); \ fprintf (FILE, "("); \ if (addr != 0) { \ output_addr_const (FILE, addr); \ putc (',', FILE); } \ fprintf (FILE, "%s", reg_names[REGNO (breg)]); \ if (ireg != 0) \ putc (',', FILE); \ if (ireg != 0 && GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]); \ else if (ireg != 0) \ fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]); \ if (scale != 1) fprintf (FILE, "*%d", scale); \ putc (')', FILE); \ break; \ } \ else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \ { fprintf (FILE, "(L%d.b,pc,%s.l)", \ CODE_LABEL_NUMBER (XEXP (addr, 0)), \ reg_names[REGNO (reg1)]); \ break; } \ default: \ if (GET_CODE (addr) == CONST_INT \ && INTVAL (addr) < 0x8000 \ && INTVAL (addr) >= -0x8000) \ fprintf (FILE, "%d.w", INTVAL (addr)); \ else \ output_addr_const (FILE, addr); \ }} #else /* Using GAS, which uses the MIT assembler syntax, like a Sun. */ #define FUNCTION_PROFILER(FILE, LABEL_NO) \ fprintf (FILE, "\tmovl #LP%d,d0\n\tjsr mcount\n", (LABEL_NO)); #endif /* MOTOROLA */ gcc-2.5.8/config/m68k/news3.h100444 22011 13 223 5322244751 14206 0ustar kenneruser#include "m68k/news.h" /* This is to be compatible with types.h. It was found to be necessary with Newsos 3. */ #define SIZE_TYPE "long int" gcc-2.5.8/config/m68k/news3gas.h100444 22011 13 226 5322244740 14702 0ustar kenneruser#include "m68k/newsgas.h" /* This is to be compatible with types.h. It was found to be necessary with Newsos 3. */ #define SIZE_TYPE "long int" gcc-2.5.8/config/m68k/newsgas.h100444 22011 13 366 5322244726 14630 0ustar kenneruser/* In Sony versions before 3.0, use the GNU Assembler, because the system's assembler has no way to assemble the difference of two labels for the displacement in a switch-dispatch instruction. */ #define USE_GAS #include "m68k/news.h" gcc-2.5.8/config/m68k/next.c100444 22011 13 352 5361400414 14114 0ustar kenneruser/* next.c: Functions for NeXT as target machine for GNU C compiler. */ /* Note that the include below means that we can't debug routines in m68k.c when running on a COFF system. */ #include "m68k/m68k.c" #include "nextstep.c" gcc-2.5.8/config/m68k/next.h100444 22011 13 16503 5453234720 14175 0ustar kenneruser/* Target definitions for GNU compiler for mc680x0 running NeXTSTEP Copyright (C) 1989, 1990, 1991, 1992, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/m68k.h" #include "nextstep.h" #include "machmode.h" #include "real.h" /* See m68k.h. 0407 means 68040 (or 68030 or 68020, with 68881/2). */ #define TARGET_DEFAULT 0407 /* Boundary (in *bits*) on which stack pointer should be aligned. */ #undef STACK_BOUNDARY #define STACK_BOUNDARY 32 /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Dmc68000 -Dm68k -DNeXT -Dunix -D__MACH__ -D__BIG_ENDIAN__ -D__ARCHITECTURE__=\"m68k\" -Asystem(unix) -Asystem(mach) -Acpu(m68k) -Amachine(m68k)" /* Every structure or union's size must be a multiple of 2 bytes. (Why isn't this in m68k.h?) */ #define STRUCTURE_SIZE_BOUNDARY 16 /* This is how to output an assembler line defining a `double' constant. */ #undef ASM_OUTPUT_DOUBLE #ifdef REAL_VALUE_TO_TARGET_DOUBLE #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { \ long hex[2]; \ REAL_VALUE_TO_TARGET_DOUBLE (VALUE, hex); \ fprintf (FILE, "\t.long 0x%x\n\t.long 0x%x\n", hex[0], hex[1]); \ } while (0) #else #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { if (REAL_VALUE_ISINF (VALUE)) \ { \ if (REAL_VALUE_NEGATIVE (VALUE)) \ fprintf (FILE, "\t.double 0r-99e999\n"); \ else \ fprintf (FILE, "\t.double 0r99e999\n"); \ } \ else \ { char dstr[30]; \ REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \ fprintf (FILE, "\t.double 0r%s\n", dstr); \ } \ } while (0) #endif /* This is how to output an assembler line defining a `float' constant. */ #undef ASM_OUTPUT_FLOAT #ifdef REAL_VALUE_TO_TARGET_SINGLE #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { \ long hex; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, hex); \ fprintf (FILE, "\t.long 0x%x\n", hex); \ } while (0) #else #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { if (REAL_VALUE_ISINF (VALUE)) \ { \ if (REAL_VALUE_NEGATIVE (VALUE)) \ fprintf (FILE, "\t.single 0r-99e999\n"); \ else \ fprintf (FILE, "\t.single 0r99e999\n"); \ } \ else \ { char dstr[30]; \ REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \ fprintf (FILE, "\t.single 0r%s\n", dstr); \ } \ } while (0) #endif #undef ASM_OUTPUT_FLOAT_OPERAND #ifdef REAL_VALUE_TO_TARGET_SINGLE #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ do { \ long hex; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, hex); \ fprintf (FILE, "#0%c%x", (CODE) == 'f' ? 'b' : 'x', hex); \ } while (0) #else #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ do{ \ if (CODE != 'f') \ { \ long l; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ if (sizeof (int) == sizeof (long)) \ asm_fprintf ((FILE), "%I0x%x", l); \ else \ asm_fprintf ((FILE), "%I0x%lx", l); \ } \ else if (REAL_VALUE_ISINF (VALUE)) \ { \ if (REAL_VALUE_NEGATIVE (VALUE)) \ fprintf (FILE, "#0r-99e999"); \ else \ fprintf (FILE, "#0r99e999"); \ } \ else \ { char dstr[30]; \ REAL_VALUE_TO_DECIMAL ((VALUE), "%.9g", dstr); \ fprintf (FILE, "#0r%s", dstr); \ } \ } while (0) #endif #undef ASM_OUTPUT_DOUBLE_OPERAND #ifdef REAL_VALUE_TO_TARGET_DOUBLE #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ do { \ long hex[2]; \ REAL_VALUE_TO_TARGET_DOUBLE (VALUE, hex); \ fprintf (FILE, "#0b%x%08x", hex[0], hex[1]); \ } while (0) #else #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ do { if (REAL_VALUE_ISINF (VALUE)) \ { \ if (REAL_VALUE_NEGATIVE (VALUE)) \ fprintf (FILE, "#0r-99e999"); \ else \ fprintf (FILE, "#0r99e999"); \ } \ else \ { char dstr[30]; \ REAL_VALUE_TO_DECIMAL ((VALUE), "%.20g", dstr); \ fprintf (FILE, "#0r%s", dstr); \ } \ } while (0) #endif /* We do not define JUMP_TABLES_IN_TEXT_SECTION, since we wish to keep the text section pure. There is no point in addressing the jump tables using pc relative addressing, since they are not in the text section, so we undefine CASE_VECTOR_PC_RELATIVE. This also causes the compiler to use absolute addresses in the jump table, so we redefine CASE_VECTOR_MODE to be SImode. */ #undef CASE_VECTOR_MODE #define CASE_VECTOR_MODE SImode #undef CASE_VECTOR_PC_RELATIVE /* Make sure jump tables have the same alignment as other pointers. */ #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \ { ASM_OUTPUT_ALIGN (FILE, 1); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); } /* Don't treat addresses involving labels differently from symbol names. Previously, references to labels generated pc-relative addressing modes while references to symbol names generated absolute addressing modes. */ #undef GO_IF_INDEXABLE_BASE(X, ADDR) #define GO_IF_INDEXABLE_BASE(X, ADDR) \ { if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR; } /* This accounts for the return pc and saved fp on the m68k. */ #define OBJC_FORWARDING_STACK_OFFSET 8 #define OBJC_FORWARDING_MIN_OFFSET 8 /* INITIALIZE_TRAMPOLINE is changed so that it also enables executable stack. The __enable_execute_stack also clears the insn cache. */ /* NOTE: part of this is copied from m68k.h */ #undef INITIALIZE_TRAMPOLINE #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ rtx _addr, _func; \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 2)), TRAMP); \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 18)), CXT); \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 22)), FNADDR); \ _addr = memory_address (SImode, (TRAMP)); \ _func = gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"); \ emit_library_call (_func, 0, VOIDmode, 1, _addr, Pmode); \ } /* A C expression used to clear the instruction cache from address BEG to address END. On NeXTSTEP this i a system trap. */ #define CLEAR_INSN_CACHE(BEG, END) \ asm volatile ("trap #2") gcc-2.5.8/config/m68k/pbb.h100444 22011 13 12376 5453234723 13771 0ustar kenneruser/* Definitions of target machine for GNU compiler. Citicorp/TTI Unicom PBB version (using GAS with a %-register prefix) Copyright (C) 1987, 1988, 1990 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Note: This config uses a version of gas with a postprocessing stage that converts the output of gas to coff containing stab debug symbols. (See vasta@apollo.com or mb@soldev.tti.com) */ #include "m68k/m68k.h" /* See m68k.h. 5 means 68020 without 68881. */ #define TARGET_DEFAULT 5 /* Don't try using XFmode. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 /* Every structure or union's size must be a multiple of 2 bytes. */ #define STRUCTURE_SIZE_BOUNDARY 16 /* Define __HAVE_68881__ in preprocessor if -m68881 is specified. This will control the use of inline 68881 insns in certain macros. */ #define CPP_SPEC "%{m68881:-D__HAVE_68881__}" /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Dm68k -Dunix -DUnicomPBB -Dmc68k -Dmc68020 -Dmc68k32 -Asystem(unix) -Acpu(m68k) -Amachine(m68k)" /* We want DBX format for use with gdb under COFF. */ #define DBX_DEBUGGING_INFO /* Generate calls to memcpy, memcmp and memset. */ #define TARGET_MEM_FUNCTIONS /* -m68000 requires special flags to the assembler. */ #define ASM_SPEC \ " %{m68000:-mc68010}%{mc68000:-mc68010}" /* we use /lib/libp/lib* when profiling */ #define LIB_SPEC "%{p:-L/usr/lib/libp} %{pg:-L/usr/lib/libp} -lc" /* Use crt1.o as a startup file and crtn.o as a closing file. */ /* * The loader directive file gcc.ifile defines how to merge the constructor * sections into the data section. Also, since gas only puts out those * sections in response to N_SETT stabs, and does not (yet) have a * ".sections" directive, gcc.ifile also defines the list symbols * __DTOR_LIST__ and __CTOR_LIST__. * * Finally, we must explicitly specify the file from libgcc.a that defines * exit(), otherwise if the user specifies (for example) "-lc_s" on the * command line, the wrong exit() will be used and global destructors will * not get called . */ #define STARTFILE_SPEC \ "%{!r: gcc.ifile%s} %{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} \ %{!r:_exit.o%s}" #define ENDFILE_SPEC "crtn.o%s" /* cpp has to support a #sccs directive for the /usr/include files */ #define SCCS_DIRECTIVE /* GAS register prefix assembly syntax: */ /* User labels have no prefix */ #undef USER_LABEL_PREFIX #define USER_LABEL_PREFIX "" /* local labels are prefixed with ".L" */ #undef LOCAL_LABEL_PREFIX #define LOCAL_LABEL_PREFIX "." /* registers are prefixed with "%" */ #undef REGISTER_PREFIX #define REGISTER_PREFIX "%" #undef REGISTER_NAMES #define REGISTER_NAMES \ {"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \ "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp", \ "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7"} #undef FUNCTION_EXTRA_EPILOGUE #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) \ { extern int current_function_returns_pointer; \ if ((current_function_returns_pointer) && \ ! find_equiv_reg (0, get_last_insn (), 0, 0, 0, 8, Pmode)) \ asm_fprintf (FILE, "\tmovl %Rd0,%Ra0\n"); } #define ASM_RETURN_CASE_JUMP return "jmp %%pc@(2,%0:w)" /* Although the gas we use can create .ctor and .dtor sections from N_SETT stabs, it does not support section directives, so we need to have the loader define the lists. */ #define CTOR_LISTS_DEFINED_EXTERNALLY /* similar to default, but allows for the table defined by ld with gcc.ifile. nptrs is always 0. So we need to instead check that __DTOR_LIST__[1] != 0. The old check is left in so that the same macro can be used if and when a future version of gas does support section directives. */ #define DO_GLOBAL_DTORS_BODY {int nptrs = *(int *)__DTOR_LIST__; int i; \ if (nptrs == -1 || (__DTOR_LIST__[0] == 0 && __DTOR_LIST__[1] != 0)) \ for (nptrs = 0; __DTOR_LIST__[nptrs + 1] != 0; nptrs++); \ for (i = nptrs; i >= 1; i--) \ __DTOR_LIST__[i] (); } /* * Here is an example gcc.ifile. I've tested it on PBB 68k and on sco 386 * systems. The NEXT(0x200000) works on just about all 386 and m68k systems, * but can be reduced to any power of 2 that is >= NBPS (0x10000 on a pbb). SECTIONS { .text BIND(0x200200) BLOCK (0x200) : { *(.init) *(.text) vfork = fork; *(.fini) } GROUP BIND( NEXT(0x200000) + ADDR(.text) + SIZEOF(.text)): { .data : { __CTOR_LIST__ = . ; . += 4; *(.ctor) . += 4 ; __DTOR_LIST__ = . ; . += 4; *(.dtor) . += 4 ; } .bss : { } } } */ /* Local variables: version-control: t End: */ gcc-2.5.8/config/m68k/plexus.h100444 22011 13 6273 5453234726 14530 0ustar kenneruser/* Definitions of target machine for GNU compiler. Copyright (C) 1990 Free Software Foundation, Inc. Written by Randy Welch Send bug reports, questions and improvements to any of the following addresses: randy@kcin.alphacdc.com rwelch@isis.cs.du.eu rwelch@csn.org For Plexus P/60 and assumably P/35 P/75 P/95's running System V.2 This file outputs assembler source for gas-1.38.1 with the COFF patches The patches for gas-1.38.1 to support COFF is on ftp.cs.umb.edu in pub/gnu No debugging is supported, due to the fact that the only debugger Plexus had was adb *sigh*. This is configured for label output default by gas as LXXX instead of plexus cc/as combination requires .LXXX This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 1, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/m68k.h" /* Define __HAVE_68881 in preprocessor only if -m68881 is specified. This will control the use of inline 68881 insns in certain macros. */ #define TARGET_DEFAULT 5 /* set to 5 if on a '020 box */ /* Don't try using XFmode. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 #define CPP_SPEC "%{m68881:-D__HAVE_68881__}" #define CPP_PREDEFINES "-Dm68 -Dunix -Dplexus -Asystem(unix) -Acpu(m68k) -Amachine(m68k)" #if TARGET_DEFAULT & 01 #define ASM_SPEC\ "%{m68000:-mc68000}%{mc68000:-mc68000}%{!mc68000:%{!m68000:-mc68020}}" #undef STRICT_ALIGNMENT #define STRICT_ALIGNMENT 0 #else #define ASM_SPEC\ "%{m68020:-mc68020}%{mc68020:-mc68020}%{!mc68020:%{!mc68020:-mc68000}}" #endif /***************************************************************************/ /* Un comment the following if you want adb to be able to follow a core */ /* file if you compile a program with -O */ /***************************************************************************/ /* #define FRAME_POINTER_REQUIRED */ /* Let's be compatible with the Plexus C compiler by default. Why not? */ #define PLEXUS_CC_COMPAT #ifdef PLEXUS_CC_COMPAT #define STRUCTURE_SIZE_BOUNDARY 16 /* for compatibility with cc */ #undef STACK_BOUNDARY #define STACK_BOUNDARY 32 /* ditto */ #endif #undef NEED_PROBE #define NEED_PROBE -132 /* plexus needs a stack probe */ #undef DBX_DEBUGGING_INFO /* no real debugger */ #undef SDB_DEBUGGING_INFO #define TARGET_MEM_FUNCTIONS /***********************************************************************/ /* items for collect2 */ /***********************************************************************/ #define NM_FLAGS "" #define NO_SYS_SIGLIST #define NO_DUP2 #define SIZE_TYPE "int" gcc-2.5.8/config/m68k/sgs.h100444 22011 13 37027 5356407127 14024 0ustar kenneruser/* Definitions of target machine for GNU compiler for m68k targets using assemblers derived from AT&T "SGS" releases. Copyright (C) 1991, 1993 Free Software Foundation, Inc. Written by Fred Fish (fnf@cygnus.com) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 1, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Control assembler-syntax conditionals in m68k.md and conditionals in m68k.h. Note that some systems may also require SGS_SWAP_W and/or SGS_SWITCH_TABLES to be defined as well. */ #define MOTOROLA /* Use Motorola syntax rather than "MIT" */ #define SGS /* Uses SGS assembler */ #define SGS_CMP_ORDER /* Takes cmp operands in reverse order */ #include "m68k/m68k.h" /* SGS specific assembler pseudo ops. */ #define BYTE_ASM_OP ".byte" #define WORD_ASM_OP ".short" #define LONG_ASM_OP ".long" #define SPACE_ASM_OP ".space" #define ALIGN_ASM_OP ".align" #undef GLOBAL_ASM_OP #define GLOBAL_ASM_OP ".global" #define SWBEG_ASM_OP ".swbeg" #define SET_ASM_OP ".set" #define UNALIGNED_SHORT_ASM_OP ".short" /* Used in dwarfout.c */ #define UNALIGNED_INT_ASM_OP ".long" /* Used in dwarfout.c */ #define ASM_PN_FORMAT "%s_%d" /* Format for private names */ /* Here are four prefixes that are used by asm_fprintf to facilitate customization for alternate assembler syntaxes. Machines with no likelihood of an alternate syntax need not define these and need not use asm_fprintf. */ /* The prefix for register names. Note that REGISTER_NAMES is supposed to include this prefix. Also note that this is NOT an fprintf format string, it is a literal string */ #undef REGISTER_PREFIX #define REGISTER_PREFIX "%" /* The prefix for local (compiler generated) labels. These labels will not appear in the symbol table. */ #undef LOCAL_LABEL_PREFIX #define LOCAL_LABEL_PREFIX "." /* The prefix to add to user-visible assembler symbols. */ #undef USER_LABEL_PREFIX #define USER_LABEL_PREFIX "" /* The prefix for immediate operands. */ #undef IMMEDIATE_PREFIX #define IMMEDIATE_PREFIX "&" /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number. Motorola format uses different register names than defined in m68k.h. We also take this chance to convert 'a6' to 'fp' */ #undef REGISTER_NAMES #ifndef SUPPORT_SUN_FPA #define REGISTER_NAMES \ {"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \ "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", \ "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7" } #else /* SUPPORTED_SUN_FPA */ #define REGISTER_NAMES \ {"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \ "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", \ "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7", \ "%fpa0", "%fpa1", "%fpa2", "%fpa3", "%fpa4", "%fpa5", "%fpa6","%fpa7", \ "%fpa8", "%fpa9", "%fpa10","%fpa11","%fpa12","%fpa13","%fpa14","%fpa15", \ "%fpa16","%fpa17","%fpa18","%fpa19","%fpa20","%fpa21","%fpa22","%fpa23", \ "%fpa24","%fpa25","%fpa26","%fpa27","%fpa28","%fpa29","%fpa30","%fpa31" } #endif /* defined SUPPORT_SUN_FPA */ /* When using an SGS assembler, modify the name of the artificial label which identifies this file as having been compiled with gcc, and the macro that emits such a label in the assembly output, to use '%' rather than '.' */ #define ASM_IDENTIFY_GCC(FILE) \ { fprintf ((FILE), "%s:\n", "gcc2_compiled%"); } /* This is how to output an assembler line defining an `int' constant. */ /* The SGS assembler doesn't understand ".word". */ #undef ASM_OUTPUT_SHORT #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf ((FILE), "\t%s ", WORD_ASM_OP), \ output_addr_const ((FILE), (VALUE)), \ fprintf ((FILE), "\n")) #undef ASM_OUTPUT_LONG_DOUBLE #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ do { long l[3]; \ REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ fprintf ((FILE), "\t%s 0x%x,0x%x,0x%x\n", LONG_ASM_OP, \ l[0], l[1], l[2]); \ } while (0) /* This is how to output an assembler line defining a `double' constant. */ #undef ASM_OUTPUT_DOUBLE #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { long l[2]; \ REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ fprintf ((FILE), "\t%s 0x%x,0x%x\n", LONG_ASM_OP, \ l[0], l[1]); \ } while (0) /* This is how to output an assembler line defining a `float' constant. */ #undef ASM_OUTPUT_FLOAT #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { long l; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ fprintf ((FILE), "\t%s 0x%x\n", LONG_ASM_OP, l); \ } while (0) /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #undef ASM_OUTPUT_ALIGN #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG) > 0) \ fprintf ((FILE), "\t%s \t%u\n", ALIGN_ASM_OP, 1 << (LOG)); \ else if ((LOG) > 31) \ abort (); /* The routine used to output null terminated string literals. We cannot use the ".string" pseudo op, because it silently truncates strings to 1023 bytes. There is no "partial string op" which works like ".string" but doesn't append a null byte, so we can't chop the input string up into small pieces and use that. Our only remaining alternative is to output the string one byte at a time. */ #define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ { \ register int sp = 0, lp = 0, ch; \ fprintf ((FILE), "\t%s ", BYTE_ASM_OP); \ do { \ ch = (PTR)[sp]; \ if (ch > ' ' && ! (ch & 0x80) && ch != '\\') \ { \ fprintf ((FILE), "'%c", ch); \ } \ else \ { \ fprintf ((FILE), "0x%x", ch); \ } \ if (++sp < (LEN)) \ { \ if ((sp % 10) == 0) \ { \ fprintf ((FILE), "\n\t%s ", BYTE_ASM_OP); \ } \ else \ { \ putc (',', (FILE)); \ } \ } \ } while (sp < (LEN)); \ putc ('\n', (FILE)); \ } /* SGS based assemblers don't understand #NO_APP and #APP, so just don't bother emitting them. */ #undef ASM_APP_ON #define ASM_APP_ON "" #undef ASM_APP_OFF #define ASM_APP_OFF "" /* When using SGS derived assemblers, change the "MIT" or "MOTOROLA" to "SGS/AT&T" */ #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (68k, SGS/AT&T syntax)"); /* Use proper assembler syntax for these macros. */ #undef ASM_OUTPUT_REG_PUSH #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ asm_fprintf (FILE, "\t%Omove.l %s,-(%Rsp)\n", reg_names[REGNO]) #undef ASM_OUTPUT_REG_POP #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ asm_fprintf (FILE, "\t%Omove.l (%Rsp)+,%s\n", reg_names[REGNO]) #undef ASM_OUTPUT_FLOAT_OPERAND #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ do { long l; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ asm_fprintf ((FILE), "%I0x%x", l); \ } while (0) #undef ASM_OUTPUT_DOUBLE_OPERAND #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ do { long l[2]; \ REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ asm_fprintf ((FILE), "%I0x%x%08x", l[0], l[1]); \ } while (0) /* How to output a block of SIZE zero bytes. Note that the `space' pseudo, when used in the text segment, causes SGS assemblers to output nop insns rather than 0s, so we set ASM_NO_SKIP_IN_TEXT to prevent this. */ #define ASM_NO_SKIP_IN_TEXT 1 #undef ASM_OUTPUT_SKIP #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t%s %u\n", SPACE_ASM_OP, (SIZE)) /* Translate Motorola opcodes such as `jbeq' into SGS opcodes such as `beq.w'. Delete the `e' in `move...' and `fmove'. Change `ftst' to `ftest'. Change `fbne' to `fbneq' Change `fsne' to `fsneq' Change `divsl' to `tdivs' (32/32 -> 32r:32q) Change `divul' to `tdivu' (32/32 -> 32r:32q) Optionally change swap to swap.w. */ #ifdef SGS_SWAP_W #define ASM_OUTPUT_OPCODE(FILE, PTR) \ { \ extern int flag_pic; \ if (!strncmp ((PTR), "jbsr", 4)) \ { if (flag_pic) \ fprintf ((FILE), "bsr"); \ else \ fprintf ((FILE), "jsr"); \ (PTR) += 4; } \ else if ((PTR)[0] == 'j' && (PTR)[1] == 'b') \ { ++(PTR); \ while (*(PTR) != ' ') \ { putc (*(PTR), (FILE)); ++(PTR); } \ fprintf ((FILE), ".w"); } \ else if ((PTR)[0] == 's') \ { \ if (!strncmp ((PTR), "swap", 4)) \ { fprintf ((FILE), "swap.w"); (PTR) += 4; } \ } \ /* FMOVE ==> FMOV, (and F%& F%$ translations) */ \ else if ((PTR)[0] == 'f') \ { \ if (!strncmp ((PTR), "fmove", 5)) \ { fprintf ((FILE), "fmov"); (PTR) += 5; } \ else if (!strncmp ((PTR), "ftst", 4)) \ { fprintf ((FILE), "ftest"); (PTR) += 4; } \ else if (!strncmp ((PTR), "fbne", 4)) \ { fprintf ((FILE), "fbneq"); (PTR) += 4; } \ else if (!strncmp ((PTR), "fsne", 4)) \ { fprintf ((FILE), "fsneq"); (PTR) += 4; } \ else if (!strncmp ((PTR), "f%$move", 7)) \ { (PTR) += 7; \ if (TARGET_68040_ONLY) \ fprintf ((FILE), "fsmov"); \ else fprintf ((FILE), "fmov"); } \ else if (!strncmp ((PTR), "f%&move", 7)) \ { (PTR) += 7; \ if (TARGET_68040_ONLY) \ fprintf ((FILE), "fdmov"); \ else fprintf ((FILE), "fmov"); } \ } \ /* MOVE, MOVEA, MOVEQ, MOVEC ==> MOV */ \ else if ((PTR)[0] == 'm' && (PTR)[1] == 'o' \ && (PTR)[2] == 'v' && (PTR)[3] == 'e') \ { fprintf ((FILE), "mov"); (PTR) += 4; \ if ((PTR)[0] == 'q' || (PTR)[0] == 'a' \ || (PTR)[0] == 'c') (PTR)++; } \ /* SUB, SUBQ, SUBA, SUBI ==> SUB */ \ else if ((PTR)[0] == 's' && (PTR)[1] == 'u' \ && (PTR)[2] == 'b') \ { fprintf ((FILE), "sub"); (PTR) += 3; \ if ((PTR)[0] == 'q' || (PTR)[0] == 'i' \ || (PTR)[0] == 'a') (PTR)++; } \ /* CMP, CMPA, CMPI, CMPM ==> CMP */ \ else if ((PTR)[0] == 'c' && (PTR)[1] == 'm' \ && (PTR)[2] == 'p') \ { fprintf ((FILE), "cmp"); (PTR) += 3; \ if ((PTR)[0] == 'a' || (PTR)[0] == 'i' \ || (PTR)[0] == 'm') (PTR)++; } \ /* DIVSL ==> TDIVS */ \ else if ((PTR)[0] == 'd' && (PTR)[1] == 'i' \ && (PTR)[2] == 'v' && (PTR)[3] == 's' \ && (PTR)[4] == 'l') \ { fprintf ((FILE), "tdivs"); (PTR) += 5; } \ /* DIVUL ==> TDIVU */ \ else if ((PTR)[0] == 'd' && (PTR)[1] == 'i' \ && (PTR)[2] == 'v' && (PTR)[3] == 'u' \ && (PTR)[4] == 'l') \ { fprintf ((FILE), "tdivu"); (PTR) += 5; } \ } #else /* not SGS_SWAP_W */ #define ASM_OUTPUT_OPCODE(FILE, PTR) \ { \ extern int flag_pic; \ if (!strncmp ((PTR), "jbsr", 4)) \ { if (flag_pic) \ fprintf ((FILE), "bsr"); \ else \ fprintf ((FILE), "jsr"); \ (PTR) += 4; } \ else if ((PTR)[0] == 'j' && (PTR)[1] == 'b') \ { ++(PTR); \ while (*(PTR) != ' ') \ { putc (*(PTR), (FILE)); ++(PTR); } \ fprintf ((FILE), ".w"); } \ /* FMOVE ==> FMOV, (and F%& F%$ translations) */ \ else if ((PTR)[0] == 'f') \ { \ if (!strncmp ((PTR), "fmove", 5)) \ { fprintf ((FILE), "fmov"); (PTR) += 5; } \ else if (!strncmp ((PTR), "ftst", 4)) \ { fprintf ((FILE), "ftest"); (PTR) += 4; } \ else if (!strncmp ((PTR), "fbne", 4)) \ { fprintf ((FILE), "fbneq"); (PTR) += 4; } \ else if (!strncmp ((PTR), "fsne", 4)) \ { fprintf ((FILE), "fsneq"); (PTR) += 4; } \ else if (!strncmp ((PTR), "f%$move", 7)) \ { (PTR) += 7; \ if (TARGET_68040_ONLY) \ fprintf ((FILE), "fsmov"); \ else fprintf ((FILE), "fmov"); } \ else if (!strncmp ((PTR), "f%&move", 7)) \ { (PTR) += 7; \ if (TARGET_68040_ONLY) \ fprintf ((FILE), "fdmov"); \ else fprintf ((FILE), "fmov"); } \ } \ /* MOVE, MOVEA, MOVEQ, MOVEC ==> MOV */ \ else if ((PTR)[0] == 'm' && (PTR)[1] == 'o' \ && (PTR)[2] == 'v' && (PTR)[3] == 'e') \ { fprintf ((FILE), "mov"); (PTR) += 4; \ if ((PTR)[0] == 'q' || (PTR)[0] == 'a' \ || (PTR)[0] == 'c') (PTR)++; } \ /* SUB, SUBQ, SUBA, SUBI ==> SUB */ \ else if ((PTR)[0] == 's' && (PTR)[1] == 'u' \ && (PTR)[2] == 'b') \ { fprintf ((FILE), "sub"); (PTR) += 3; \ if ((PTR)[0] == 'q' || (PTR)[0] == 'i' \ || (PTR)[0] == 'a') (PTR)++; } \ /* CMP, CMPA, CMPI, CMPM ==> CMP */ \ else if ((PTR)[0] == 'c' && (PTR)[1] == 'm' \ && (PTR)[2] == 'p') \ { fprintf ((FILE), "cmp"); (PTR) += 3; \ if ((PTR)[0] == 'a' || (PTR)[0] == 'i' \ || (PTR)[0] == 'm') (PTR)++; } \ /* DIVSL ==> TDIVS */ \ else if ((PTR)[0] == 'd' && (PTR)[1] == 'i' \ && (PTR)[2] == 'v' && (PTR)[3] == 's' \ && (PTR)[4] == 'l') \ { fprintf ((FILE), "tdivs"); (PTR) += 5; } \ /* DIVUL ==> TDIVU */ \ else if ((PTR)[0] == 'd' && (PTR)[1] == 'i' \ && (PTR)[2] == 'v' && (PTR)[3] == 'u' \ && (PTR)[4] == 'l') \ { fprintf ((FILE), "tdivu"); (PTR) += 5; } \ } #endif /* not SGS_SWAP_W */ /* This macro outputs the label at the start of a switch table. The ".swbeg " is an assembler directive that causes the switch table size to be inserted into the object code so that disassemblers, for example, can identify that it is the start of a switch table. */ #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \ fprintf ((FILE), "\t%s &%d\n", SWBEG_ASM_OP, XVECLEN (PATTERN (TABLE), 1)); #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \ do { \ ASM_OUTPUT_BEFORE_CASE_LABEL((FILE),(PREFIX),(NUM),(TABLE)); \ ASM_OUTPUT_INTERNAL_LABEL((FILE),(PREFIX),(NUM)); \ } while (0) /* At end of a switch table, define LDnnn iff the symbol LInnn was defined. Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)" fails to assemble. Luckily "LDnnn(pc,d0.l*2)" produces the results we want. This difference can be accommodated by making the assembler define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END macro. */ #undef ASM_OUTPUT_CASE_END #define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \ { if (switch_table_difference_label_flag) \ asm_fprintf (FILE, "\t%s %LLD%d,%LL%d-%LLI%d-2.b\n",\ SET_ASM_OP, (NUM), (NUM), (NUM)) \ switch_table_difference_label_flag = 0; } int switch_table_difference_label_flag; /* This is how to output an element of a case-vector that is relative. */ #undef ASM_OUTPUT_ADDR_DIFF_ELT #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ asm_fprintf (FILE, "\t%s %LL%d-%LL%d\n", WORD_ASM_OP, VALUE, REL) /* Currently, JUMP_TABLES_IN_TEXT_SECTION must be defined in order to keep switch tables in the text section. */ #define JUMP_TABLES_IN_TEXT_SECTION 1 /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #undef ASM_FORMAT_PRIVATE_NAME #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ sprintf ((OUTPUT), ASM_PN_FORMAT, (NAME), (LABELNO))) gcc-2.5.8/config/m68k/sun2.h100444 22011 13 4760 5453234730 14071 0ustar kenneruser/* Definitions of target machine for GNU compiler. Sun 68010 version. Copyright (C) 1987, 1988 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/m68k.h" /* See m68k.h. 0 means 68000 with no 68881. */ #define TARGET_DEFAULT 0 /* Don't try using XFmode. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 /* Define __HAVE_68881 in preprocessor only if -m68881 is specified. This will control the use of inline 68881 insns in certain macros. Also inform the program which CPU this is for. */ #define CPP_SPEC "%{m68881:-D__HAVE_68881__} \ %{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}" /* -m68020 requires special flags to the assembler. */ #define ASM_SPEC \ "%{m68020:-mc68020}%{mc68020:-mc68020}%{!mc68020:%{!m68020:-mc68010}} \ %{fpic:-k} %{fPIC:-k}" /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Dmc68000 -Dsun -Dunix -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)" /* Prevent error on `-sun2' and `-target sun2' options. */ #define CC1_SPEC "%{sun2:} %{target:}" /* These compiler options take an argument. We ignore -target for now. */ #define WORD_SWITCH_TAKES_ARG(STR) \ (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \ || !strcmp (STR, "target") || !strcmp (STR, "assert")) /* Specify what to link with. */ /* Link with libg.a when debugging, for dbx's sake. */ /* Include the support for -a when appropriate. */ #define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \ %{a:/usr/lib/bb_link.o -lc} " /* Alignment of field after `int : 0' in a structure. */ #undef EMPTY_FIELD_BOUNDARY #define EMPTY_FIELD_BOUNDARY 16 /* Every structure or union's size must be a multiple of 2 bytes. */ #define STRUCTURE_SIZE_BOUNDARY 16 /* This is BSD, so it wants DBX format. */ #define DBX_DEBUGGING_INFO gcc-2.5.8/config/m68k/sun2o4.h100444 22011 13 13501 5374334074 14351 0ustar kenneruser/* Definitions of target machine for GNU compiler. Sun 2 running Sunos 4. Copyright (C) 1987, 1988, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/sun2.h" /* Define __HAVE_SKY__ in preprocessor, according to the -m flags. Also inform the program which CPU this is for. */ #undef CPP_SPEC #undef PTRDIFF_TYPE #define PTRDIFF_TYPE "int" #undef SIZE_TYPE #define SIZE_TYPE "int" #undef WCHAR_TYPE #define WCHAR_TYPE "short unsigned int" #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE 16 #if TARGET_DEFAULT & 0200 /* -msky is the default */ #define CPP_SPEC \ "%{!msoft-float:-D__HAVE_SKY__}\ %{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}" #else /* -msoft-float is the default */ #define CPP_SPEC \ "%{msky:-D__HAVE_SKY__ }\ %{!ansi:%{m68020:-Dmc68020}%{mc68020:-Dmc68020}%{!mc68020:%{!m68020:-Dmc68010}}}" #endif /* STARTFILE_SPEC to include sun floating point initialization This is necessary (tr: Sun does it) for the sky routines. I'm not sure what would happen below if people gave contradictory arguments (eg. -msoft-float -mfpa) */ #undef STARTFILE_SPEC #if TARGET_DEFAULT & 0200 /* -msky is the default */ #define STARTFILE_SPEC \ "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}} \ %{msoft-float:Fcrt1.o%s} \ %{!msoft-float:Scrt1.o%s}" #else /* -msoft-float is the default */ #define STARTFILE_SPEC \ "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}} \ %{msky:Scrt1.o%s} \ %{!msky:Fcrt1.o%s}" #endif /* Specify library to handle `-a' basic block profiling. Control choice of libm.a (if user says -lm) based on fp arith default and options. */ #undef LIB_SPEC #if TARGET_DEFAULT & 0200 /* -msky is the default */ #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \ %{a:/usr/lib/bb_link.o -lc} %{g:-lg} \ %{msoft-float:-L/usr/lib/fsoft} \ %{!msoft_float:-L/usr/lib/fsky}" #else /* -msoft-float is the default */ #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \ %{a:/usr/lib/bb_link.o -lc} %{g:-lg} \ %{!msky:-L/usr/lib/fsoft} \ %{msky:-L/usr/lib/ffpa}" #endif #undef LINK_SPEC #define LINK_SPEC \ "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic}" #undef ASM_OUTPUT_DOUBLE #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { if (REAL_VALUE_ISINF (VALUE)) \ { \ if (REAL_VALUE_NEGATIVE (VALUE)) \ fprintf (FILE, "\t.double 0r-99e999\n"); \ else \ fprintf (FILE, "\t.double 0r99e999\n"); \ } \ else if (REAL_VALUE_MINUS_ZERO (VALUE)) \ { \ fprintf (FILE, "\t.long 0x80000000,0\n"); \ } \ else \ { char dstr[30]; \ REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \ fprintf (FILE, "\t.double 0r%s\n", dstr); \ } \ } while (0) /* This is how to output an assembler line defining a `float' constant. */ #undef ASM_OUTPUT_FLOAT #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { if (REAL_VALUE_ISINF (VALUE)) \ { \ if (REAL_VALUE_NEGATIVE (VALUE)) \ fprintf (FILE, "\t.single 0r-99e999\n"); \ else \ fprintf (FILE, "\t.single 0r99e999\n"); \ } \ else if (REAL_VALUE_MINUS_ZERO (VALUE)) \ { \ fprintf (FILE, "\t.long 0x80000000\n"); \ } \ else \ { char dstr[30]; \ REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \ fprintf (FILE, "\t.single 0r%s\n", dstr); \ } \ } while (0) #undef ASM_OUTPUT_FLOAT_OPERAND #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ do { \ if (CODE != 'f') \ { \ long l; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ if (sizeof (int) == sizeof (long)) \ asm_fprintf ((FILE), "%I0x%x", l); \ else \ asm_fprintf ((FILE), "%I0x%lx", l); \ } \ else if (REAL_VALUE_ISINF (VALUE)) \ { \ if (REAL_VALUE_NEGATIVE (VALUE)) \ fprintf (FILE, "#0r-99e999"); \ else \ fprintf (FILE, "#0r99e999"); \ } \ else if (REAL_VALUE_MINUS_ZERO (VALUE)) \ { \ fprintf (FILE, "#0r-0.0"); \ } \ else \ { char dstr[30]; \ REAL_VALUE_TO_DECIMAL ((VALUE), "%.9g", dstr); \ fprintf (FILE, "#0r%s", dstr); \ } \ } while (0) #undef ASM_OUTPUT_DOUBLE_OPERAND #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ do { if (REAL_VALUE_ISINF (VALUE)) \ { \ if (REAL_VALUE_NEGATIVE (VALUE)) \ fprintf (FILE, "#0r-99e999"); \ else \ fprintf (FILE, "#0r99e999"); \ } \ else if (REAL_VALUE_MINUS_ZERO (VALUE)) \ { \ fprintf (FILE, "#0r-0.0"); \ } \ else \ { char dstr[30]; \ REAL_VALUE_TO_DECIMAL ((VALUE), "%.20g", dstr); \ fprintf (FILE, "#0r%s", dstr); \ } \ } while (0) gcc-2.5.8/config/m68k/sun3.h100444 22011 13 23165 5457071054 14114 0ustar kenneruser/* Definitions of target machine for GNU compiler. Sun 68000/68020 version. Copyright (C) 1987, 1988, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* This comment is here to see if it will keep Sun's cpp from dying. */ /* If you do not need to generate floating point code for the optional Sun FPA board, you can safely comment out the SUPPORT_SUN_FPA define to gain a little speed and code size. */ #define SUPPORT_SUN_FPA #include "m68k/m68k.h" /* See m68k.h. 7 means 68020 with 68881. */ #ifndef TARGET_DEFAULT #define TARGET_DEFAULT 7 #endif /* Define __HAVE_FPA__ or __HAVE_68881__ in preprocessor, according to the -m flags. This will control the use of inline 68881 insns in certain macros. Also inform the program which CPU this is for. */ #if TARGET_DEFAULT & 02 /* -m68881 is the default */ #define CPP_SPEC \ "%{!msoft-float:%{mfpa:-D__HAVE_FPA__ }%{!mfpa:-D__HAVE_68881__ }}\ %{m68000:-D__mc68010__}%{mc68000:-D__mc68010__}%{!mc68000:%{!m68000:-D__mc68020__}} \ %{!ansi:%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}}" #else /* -msoft-float is the default */ #define CPP_SPEC \ "%{m68881:-D__HAVE_68881__ }%{mfpa:-D__HAVE_FPA__ }\ %{m68000:-D__mc68010__}%{mc68000:-D__mc68010__}%{!mc68000:%{!m68000:-D__mc68020__}} \ %{!ansi:%{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}}" #endif /* Prevent error on `-sun3' and `-target sun3' options. */ #define CC1_SPEC "%{sun3:} %{target:}" #define PTRDIFF_TYPE "int" /* We must override m68k.h. */ #undef WCHAR_TYPE #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE "short unsigned int" #define WCHAR_TYPE_SIZE 16 /* These compiler options take an argument. We ignore -target for now. */ #define WORD_SWITCH_TAKES_ARG(STR) \ (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \ || !strcmp (STR, "target") || !strcmp (STR, "assert")) /* -m68000 requires special flags to the assembler. */ #define ASM_SPEC \ "%{m68000:-mc68010}%{mc68000:-mc68010}%{!mc68000:%{!m68000:-mc68020}} \ %{fpic:-k} %{fPIC:-k}" /* Names to predefine in the preprocessor for this target machine. */ /* For a while, -D_CROSS_TARGET_ARCH=SUN3 was included here, but it doesn't work, partly because SUN3 etc. aren't defined (and shouldn't be). It seems that on a native compiler _CROSS_TARGET_ARCH should not be defined. For cross compilers, let's do things as we normally do in GCC. -- rms. */ #define CPP_PREDEFINES "-Dmc68000 -Dsun -Dunix -Asystem(unix) -Asystem(bsd) -Acpu(m68k) -Amachine(m68k)" /* STARTFILE_SPEC to include sun floating point initialization This is necessary (tr: Sun does it) for both the m68881 and the fpa routines. Note that includes knowledge of the default specs for gcc, ie. no args translates to the same effect as -m68881 I'm not sure what would happen below if people gave contradictory arguments (eg. -msoft-float -mfpa) */ #if TARGET_DEFAULT & 0100 /* -mfpa is the default */ #define STARTFILE_SPEC \ "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}} \ %{m68881:Mcrt1.o%s} \ %{msoft-float:Fcrt1.o%s} \ %{!m68881:%{!msoft-float:Wcrt1.o%s}}" #else #if TARGET_DEFAULT & 2 /* -m68881 is the default */ #define STARTFILE_SPEC \ "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}} \ %{mfpa:Wcrt1.o%s} \ %{msoft-float:Fcrt1.o%s} \ %{!mfpa:%{!msoft-float:Mcrt1.o%s}}" #else /* -msoft-float is the default */ #define STARTFILE_SPEC \ "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}} \ %{m68881:Mcrt1.o%s} \ %{mfpa:Wcrt1.o%s} \ %{!m68881:%{!mfpa:Fcrt1.o%s}}" #endif #endif /* Specify library to handle `-a' basic block profiling. Control choice of libm.a (if user says -lm) based on fp arith default and options. */ #if TARGET_DEFAULT & 0100 /* -mfpa is the default */ #define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \ %{a:/usr/lib/bb_link.o} %{g:-lg} \ %{msoft-float:-L/usr/lib/fsoft}%{m68881:-L/usr/lib/f68881}\ %{!msoft_float:%{!m68881:-L/usr/lib/ffpa}}" #else #if TARGET_DEFAULT & 2 /* -m68881 is the default */ #define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \ %{a:/usr/lib/bb_link.o} %{g:-lg} \ %{msoft-float:-L/usr/lib/fsoft}%{!msoft-float:%{!mfpa:-L/usr/lib/f68881}}\ %{mfpa:-L/usr/lib/ffpa}" #else /* -msoft-float is the default */ #define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \ %{a:/usr/lib/bb_link.o} %{g:-lg} \ %{!m68881:%{!mfpa:-L/usr/lib/fsoft}}%{m68881:-L/usr/lib/f68881}\ %{mfpa:-L/usr/lib/ffpa}" #endif #endif /* Provide required defaults for linker -e and -d switches. */ #define LINK_SPEC \ "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}" /* Every structure or union's size must be a multiple of 2 bytes. */ #define STRUCTURE_SIZE_BOUNDARY 16 /* This is BSD, so it wants DBX format. */ #define DBX_DEBUGGING_INFO /* Allow folding division by zero. */ #define REAL_INFINITY /* Generate calls to memcpy, memcmp and memset. */ #define TARGET_MEM_FUNCTIONS /* This is not a good idea. It prevents interoperation between files compiled with -m68881 and those compiled with -msoft-float. */ #if 0 #define FUNCTION_VALUEX(MODE) \ gen_rtx (REG, (MODE), \ ((TARGET_68881 \ && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) \ ? 16 : 0)) #undef FUNCTION_VALUE #define FUNCTION_VALUE(VALTYPE,FUNC) FUNCTION_VALUEX (TYPE_MODE (VALTYPE)) #endif /* 0 */ /* This is how to output an assembler line defining a `double' constant. */ #undef ASM_OUTPUT_DOUBLE #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ { \ if (REAL_VALUE_ISINF (VALUE)) \ { \ if (REAL_VALUE_NEGATIVE (VALUE)) \ fprintf (FILE, "\t.double 0r-99e999\n"); \ else \ fprintf (FILE, "\t.double 0r99e999\n"); \ } \ else if (REAL_VALUE_ISNAN (VALUE)) \ { long l[2]; \ REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), l); \ fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n", l[0], l[1]); \ } \ else \ { char dstr[30]; \ REAL_VALUE_TO_DECIMAL ((VALUE), "%.17g", dstr); \ fprintf (FILE, "\t.double 0r%s\n", dstr); \ } \ } /* This is how to output an assembler line defining a `float' constant. */ #undef ASM_OUTPUT_FLOAT #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ { \ if (REAL_VALUE_ISINF (VALUE)) \ { \ if (REAL_VALUE_NEGATIVE (VALUE)) \ fprintf (FILE, "\t.single 0r-99e999\n"); \ else \ fprintf (FILE, "\t.single 0r99e999\n"); \ } \ else if (REAL_VALUE_ISNAN (VALUE)) \ { long l; \ REAL_VALUE_TO_TARGET_SINGLE ((VALUE), l); \ fprintf (FILE, "\t.long 0x%lx\n", l); \ } \ else \ { char dstr[30]; \ REAL_VALUE_TO_DECIMAL ((VALUE), "%.9g", dstr); \ fprintf (FILE, "\t.single 0r%s\n", dstr); \ } \ } /* This is how to output an assembler lines defining floating operands. There's no way to output a NaN's fraction, so we lose it. */ #undef ASM_OUTPUT_FLOAT_OPERAND #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ do { \ if (CODE != 'f') \ { \ long l; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ if (sizeof (int) == sizeof (long)) \ asm_fprintf ((FILE), "%I0x%x", l); \ else \ asm_fprintf ((FILE), "%I0x%lx", l); \ } \ else if (REAL_VALUE_ISINF (VALUE)) \ { \ if (REAL_VALUE_NEGATIVE (VALUE)) \ asm_fprintf (FILE, "%I0r-99e999"); \ else \ asm_fprintf (FILE, "%I0r99e999"); \ } \ else if (REAL_VALUE_MINUS_ZERO (VALUE)) \ { \ asm_fprintf (FILE, "%I0r-0.0"); \ } \ else \ { char dstr[30]; \ REAL_VALUE_TO_DECIMAL ((VALUE), "%.9g", dstr); \ asm_fprintf (FILE, "%I0r%s", dstr); \ } \ } while (0) #undef ASM_OUTPUT_DOUBLE_OPERAND #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ do { if (REAL_VALUE_ISINF (VALUE)) \ { \ if (REAL_VALUE_NEGATIVE (VALUE)) \ asm_fprintf (FILE, "%I0r-99e999"); \ else \ asm_fprintf (FILE, "%I0r99e999"); \ } \ else if (REAL_VALUE_MINUS_ZERO (VALUE)) \ { \ asm_fprintf (FILE, "%I0r-0.0"); \ } \ else \ { char dstr[30]; \ REAL_VALUE_TO_DECIMAL ((VALUE), "%.17g", dstr); \ asm_fprintf (FILE, "%I0r%s", dstr); \ } \ } while (0) #undef BLOCK_PROFILER_CODE #define BLOCK_PROFILER_CODE \ extern int ___tcov_init; \ \ __bb_init_func (blocks) \ struct bb *blocks; \ { \ if (! ___tcov_init) \ ___tcov_init_func (); \ \ ___bb_link (blocks->filename, blocks->counts, blocks->ncounts); \ } gcc-2.5.8/config/m68k/sun3mach.h100444 22011 13 1043 5453234737 14721 0ustar kenneruser#include "m68k/sun3.h" #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dmc68000 -Dsun -Dsun3 -Dunix -DMACH -DCMU -DMTXINU -DBIT_MSF -DBYTE_MSF -Asystem(unix) -Asystem(mach) -Acpu(m68k) -Amachine(m68k)" /* Specify extra dir to search for include files. */ #define SYSTEM_INCLUDE_DIR "/usr/mach/include" /* LINK_SPEC is needed only for Sunos 4. */ #undef LINK_SPEC /* Don't default to pcc-struct-return, because gcc is the only compiler, and we want to retain compatibility with older gcc versions. */ #define DEFAULT_PCC_STRUCT_RETURN 0 gcc-2.5.8/config/m68k/sun3n.h100444 22011 13 307 5374450755 14232 0ustar kenneruser/* Define target machine as a Sun 3 with no 68881. */ #define TARGET_DEFAULT 5 #include "m68k/sun3.h" /* Don't try using XFmode. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 gcc-2.5.8/config/m68k/sun3n3.h100444 22011 13 130 5322244444 14274 0ustar kenneruser#include "m68k/sun3n.h" /* LINK_SPEC is needed only for Sunos 4. */ #undef LINK_SPEC gcc-2.5.8/config/m68k/sun3o3.h100444 22011 13 127 5322244416 14302 0ustar kenneruser#include "m68k/sun3.h" /* LINK_SPEC is needed only for Sunos 4. */ #undef LINK_SPEC gcc-2.5.8/config/m68k/t-hp320g100444 22011 13 333 5305522633 14166 0ustar kenneruser# Control how libgcc.a is made. LIBGCC1 = libgcc1.conv AR = $(AR_FOR_TARGET) AR_FLAGS = $(AR_FOR_TARGET_FLAGS) RANLIB = $(RANLIB_FOR_TARGET) RANLIB_TEST = $(RANLIB_TEST_FOR_TARGET) LIBCONVERT=$(TARGET_TOOLPREFIX)hpxt gcc-2.5.8/config/m68k/t-next100444 22011 13 345 5443705732 14152 0ustar kenneruser# libgcc1.c is not needed, since the standard library has these functions. LIBGCC1=libgcc1.null CROSS_LIBGCC1=libgcc1.null # Specify other dirs of system header files to be fixed. OTHER_FIXINCLUDES_DIRS= /LocalDeveloper/Headers gcc-2.5.8/config/m68k/tower-as.h100444 22011 13 57040 5453234742 14765 0ustar kenneruser/* Definitions of target machine for GNU compiler. Copyright (C) 1990, 1993 Free Software Foundation, Inc. Written by Robert Andersson, International Systems, Oslo, Norway. Send bug reports, questions and improvements to ra@intsys.no. For NCR Tower 32/4x0 and 32/6x0 running System V Release 3. This file outputs assembler source suitable for the native Tower as and with sdb debugging symbols. See tower.h for more comments. This file was based on m68k.h, hp320.h and 3b1.h as of the 1.37.1 version. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/tower.h" #undef SELECT_RTX_SECTION /* Use default settings for system V.3. */ #include "svr3.h" /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_600 -D__motorola__ -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)" /* Define __HAVE_68881 in preprocessor only if -m68881 is specified. This will control the use of inline 68881 insns in certain macros. Also, define special define used to identify the Tower assembler. */ #define CPP_SPEC "-D__TOWER_ASM__ %{m68881:-D__HAVE_68881__}" /* We don't want local labels to start with period. See ASM_OUTPUT_INTERNAL_LABEL. */ #undef LOCAL_LABEL_PREFIX #define LOCAL_LABEL_PREFIX "" /* These four macros control how m68k.md is expanded. */ #define MOTOROLA /* Use Motorola syntax rather than "MIT" */ #define SGS /* Uses SGS assembler */ #define SGS_CMP_ORDER /* Takes cmp operands in reverse order */ #define SGS_NO_LI /* Suppress jump table label usage */ /* Turn on SDB debugging info. */ #define SDB_DEBUGGING_INFO /* This is only useful if gdb is changed, but doesn't harm anyway. */ #define ASM_IDENTIFY_GCC(FILE) \ fprintf (FILE, "gcc2_compiled%%:\n") /* All the ASM_OUTPUT macros need to conform to the Tower as syntax. */ #define ASM_OUTPUT_SOURCE_FILENAME(FILE, FILENAME) \ do { \ fprintf (FILE, "\tfile\t"); \ output_quoted_string (FILE, FILENAME); \ fprintf (FILE, "\n"); \ fprintf (FILE, "section ~init,\"x\"\n"); \ fprintf (FILE, "section ~fini,\"x\"\n"); \ fprintf (FILE, "section ~rodata,\"x\"\n"); \ fprintf (FILE, "text\n"); \ } while (0) #define ASM_OUTPUT_SOURCE_LINE(FILE, LINENO) \ fprintf (FILE, "\tln\t%d\n", \ (sdb_begin_function_line \ ? last_linenum - sdb_begin_function_line : 1)) #undef ASM_OUTPUT_IDENT #define ASM_OUTPUT_IDENT(FILE, NAME) \ fprintf (FILE, "\tident\t\"%s\" \n", NAME) #define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ { register int sp = 0, lp = 0; \ fprintf ((FILE), "\tbyte\t"); \ loop: \ if ((PTR)[sp] > ' ' && ! ((PTR)[sp] & 0x80) && (PTR)[sp] != '\\') \ { lp += 3; \ fprintf ((FILE), "'%c", (PTR)[sp]); } \ else \ { lp += 5; \ fprintf ((FILE), "0x%x", (PTR)[sp]); } \ if (++sp < (LEN)) \ { if (lp > 60) \ { lp = 0; \ fprintf ((FILE), "\n\tbyte\t"); } \ else \ putc (',', (FILE)); \ goto loop; } \ putc ('\n', (FILE)); } /* Translate Motorola opcodes such as `jbeq' into SGS/Tower opcodes such as `beq.w'. Change `move' to `mov'. Change `cmpm' to `cmp'. Change `divsl' to `tdivs'. Change `divul' to `tdivu'. Change `ftst' to `ftest'. Change `fmove' to `fmov'. */ #define ASM_OUTPUT_OPCODE(FILE, PTR) \ { if ((PTR)[0] == 'j' && (PTR)[1] == 'b') \ { ++(PTR); \ while (*(PTR) != ' ') \ { putc (*(PTR), (FILE)); ++(PTR); } \ fprintf ((FILE), ".w"); } \ else if ((PTR)[0] == 'm' && (PTR)[1] == 'o' \ && (PTR)[2] == 'v' && (PTR)[3] == 'e') \ { fprintf ((FILE), "mov"); (PTR) += 4; } \ else if ((PTR)[0] == 'c' && (PTR)[1] == 'm' \ && (PTR)[2] == 'p' && (PTR)[3] == 'm') \ { fprintf ((FILE), "cmp"); (PTR) += 4; } \ else if ((PTR)[0] == 'd' && (PTR)[1] == 'i' \ && (PTR)[2] == 'v' && (PTR)[3] == 's' \ && (PTR)[4] == 'l') \ { fprintf ((FILE), "tdivs"); (PTR) += 5; } \ else if ((PTR)[0] == 'd' && (PTR)[1] == 'i' \ && (PTR)[2] == 'v' && (PTR)[3] == 'u' \ && (PTR)[4] == 'l') \ { fprintf ((FILE), "tdivu"); (PTR) += 5; } \ else if ((PTR)[0] == 'f' && (PTR)[1] == 't' \ && (PTR)[2] == 's' && (PTR)[3] == 't') \ { fprintf ((FILE), "ftest"); (PTR) += 4; } \ else if ((PTR)[0] == 'f' && (PTR)[1] == 'm' \ && (PTR)[2] == 'o' && (PTR)[3] == 'v' \ && (PTR)[4] == 'e') \ { fprintf ((FILE), "fmov"); (PTR) += 5; } \ } /* Override parts of m68k.h to fit the Tower assembler. This section needs to track changes done to m68k.h in the future. */ #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (68k, Motorola/SGS/Tower32 syntax)"); #undef FUNCTION_BLOCK_PROFILER #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ do { \ char label1[20], label2[20]; \ ASM_GENERATE_INTERNAL_LABEL (label1, "LPBX", 0); \ ASM_GENERATE_INTERNAL_LABEL (label2, "LPI", LABELNO); \ fprintf (FILE, "\ttst.l %s\n\tbne %s\n\tpea %s\n\tjsr __bb_init_func\n\taddq.l &4,%%sp\n", \ label1, label2, label1); \ ASM_OUTPUT_INTERNAL_LABEL (FILE, "LPI", LABELNO); \ putc ('\n', FILE); \ } while (0) #undef BLOCK_PROFILER #define BLOCK_PROFILER(FILE, BLOCKNO) \ do { \ char label[20]; \ ASM_GENERATE_INTERNAL_LABEL (label, "LPBX", 2); \ fprintf (FILE, "\taddq.l &1,%s+%d\n", label, 4 * BLOCKNO); \ } while (0) #undef FUNCTION_PROFILER #define FUNCTION_PROFILER(FILE, LABEL_NO) \ fprintf (FILE, "\tmov.l &LP%%%d,%%a0\n\tjsr mcount%%\n", (LABEL_NO)) /* The prologue is identical to the one in m68k.h except that the assembler syntax is different. */ #undef FUNCTION_PROLOGUE #define FUNCTION_PROLOGUE(FILE, SIZE) \ { register int regno; \ register int mask = 0; \ extern char call_used_regs[]; \ int fsize = ((SIZE) + 3) & -4; \ if (frame_pointer_needed) \ { if (TARGET_68020 || fsize < 0x8000) \ fprintf (FILE, "\tlink %%a6,&%d\n", -fsize); \ else \ fprintf (FILE, "\tlink %%a6,&0\n\tsub.l &%d,%%sp\n", fsize); } \ for (regno = 16; regno < 24; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ mask |= 1 << (regno - 16); \ if ((mask & 0xff) != 0) \ fprintf (FILE, "\tfmovm &0x%x,-(%%sp)\n", mask & 0xff); \ mask = 0; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ mask |= 1 << (15 - regno); \ if (frame_pointer_needed) \ mask &= ~ (1 << (15-FRAME_POINTER_REGNUM)); \ if (exact_log2 (mask) >= 0) \ fprintf (FILE, "\tmov.l %s,-(%%sp)\n", reg_names[15 - exact_log2 (mask)]); \ else if (mask) fprintf (FILE, "\tmovm.l &0x%x,-(%%sp)\n", mask); } /* The epilogue is identical to the one in m68k.h except that: a) The assembler syntax is different. b) Pointers are returned both in %d0 and %a0. c) FUNCTION_EXTRA_EPILOGUE is not needed. */ #undef FUNCTION_EPILOGUE #define FUNCTION_EPILOGUE(FILE, SIZE) \ { register int regno; \ register int mask, fmask; \ register int nregs; \ int offset, foffset; \ extern char call_used_regs[]; \ int fsize = ((SIZE) + 3) & -4; \ int big = 0; \ nregs = 0; fmask = 0; \ for (regno = 16; regno < 24; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ { nregs++; fmask |= 1 << (23 - regno); } \ foffset = nregs * 12; \ nregs = 0; mask = 0; \ if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; \ for (regno = 0; regno < 16; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ { nregs++; mask |= 1 << regno; } \ offset = foffset + nregs * 4; \ if (offset + fsize >= 0x8000 \ && frame_pointer_needed \ && (mask || fmask)) \ { fprintf (FILE, "\tmov.l &%d,%%a0\n", -fsize); \ fsize = 0, big = 1; } \ if (exact_log2 (mask) >= 0) { \ if (big) \ fprintf (FILE, "\tmov.l -%d(%%a6,%%a0.l),%s\n", \ offset + fsize, reg_names[exact_log2 (mask)]); \ else if (! frame_pointer_needed) \ fprintf (FILE, "\tmov.l (%%sp)+,%s\n", \ reg_names[exact_log2 (mask)]); \ else \ fprintf (FILE, "\tmov.l -%d(%%a6),%s\n", \ offset + fsize, reg_names[exact_log2 (mask)]); } \ else if (mask) { \ if (big) \ fprintf (FILE, "\tmovm.l -%d(%%a6,%%a0.l),&0x%x\n", \ offset + fsize, mask); \ else if (! frame_pointer_needed) \ fprintf (FILE, "\tmovm.l (%%sp)+,&0x%x\n", mask); \ else \ fprintf (FILE, "\tmovm.l -%d(%%a6),&0x%x\n", \ offset + fsize, mask); } \ if (fmask) { \ if (big) \ fprintf (FILE, "\tfmovm -%d(%%a6,%%a0.l),&0x%x\n", \ foffset + fsize, fmask); \ else if (! frame_pointer_needed) \ fprintf (FILE, "\tfmovm (%%sp)+,&0x%x\n", fmask); \ else \ fprintf (FILE, "\tfmovm -%d(%%a6),&0x%x\n", \ foffset + fsize, fmask); } \ if (current_function_returns_pointer) \ fprintf (FILE, "\tmov.l %%d0,%%a0\n"); \ if (frame_pointer_needed) \ fprintf (FILE, "\tunlk %%a6\n"); \ if (current_function_pops_args) \ fprintf (FILE, "\trtd &%d\n", current_function_pops_args); \ else fprintf (FILE, "\trts\n"); } /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #undef ASM_OUTPUT_REG_PUSH #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tmov.l %s,-(%%sp)\n", reg_names[REGNO]) /* This is how to output an insn to pop a register from the stack. It need not be very fast code. */ #undef ASM_OUTPUT_REG_POP #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tmov.l (%%sp)+,%s\n", reg_names[REGNO]) #undef ASM_FILE_START #define ASM_FILE_START(FILE) \ ( fprintf (FILE, "#NO_APP\n"), \ output_file_directive ((FILE), main_input_filename)) #undef TEXT_SECTION_ASM_OP #define TEXT_SECTION_ASM_OP "text" #undef DATA_SECTION_ASM_OP #define DATA_SECTION_ASM_OP "data" /* This says how to output an assembler line to define a global common symbol. We use SIZE rather than ROUNDED, as this is what the native cc does. */ #undef ASM_OUTPUT_COMMON #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fputs ("\tcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%d\n", ((SIZE) == 0) ? (ROUNDED) : (SIZE))) /* This says how to output an assembler line to define a local common symbol. We use SIZE rather than ROUNDED, as this is what the native cc does. */ #undef ASM_OUTPUT_LOCAL #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( fputs ("\tlcomm ", (FILE)), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%d\n", ((SIZE) == 0) ? (ROUNDED) : (SIZE))) /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #undef ASM_FORMAT_PRIVATE_NAME #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 11), \ sprintf ((OUTPUT), "%s%%%%%d", (NAME), (LABELNO))) /* This is the command to make the user-level label named NAME defined for reference from other files. */ #undef GLOBAL_ASM_OP #define GLOBAL_ASM_OP "global" #undef ASM_GENERATE_INTERNAL_LABEL #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ sprintf ((LABEL), "%s%%%d", (PREFIX), (NUM)) #undef ASM_OUTPUT_INTERNAL_LABEL #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf ((FILE), "%s%%%d:\n", (PREFIX), (NUM)) #undef ASM_OUTPUT_CASE_LABEL #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \ fprintf (FILE, "\tswbeg &%d\n%s%%%d:\n", \ XVECLEN (PATTERN (TABLE), 1), (PREFIX), (NUM)); \ #undef ASM_OUTPUT_DOUBLE #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { long l[2]; \ REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ fprintf (FILE, "\tlong 0x%x,0x%x\n", l[0], l[1]); \ } while (0) #undef ASM_OUTPUT_LONG_DOUBLE #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ do { long l[3]; \ REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ fprintf (FILE, "\tlong 0x%x,0x%x,0x%x\n", l[0], l[1], l[2]); \ } while (0) #undef ASM_OUTPUT_FLOAT #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { long l; \ REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ fprintf ((FILE), "\tlong 0x%x\n", l); \ } while (0) /* This is how to output an assembler line defining an `int' constant. */ #undef ASM_OUTPUT_INT #define ASM_OUTPUT_INT(FILE,VALUE) \ ( fprintf (FILE, "\tlong "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* Likewise for `char' and `short' constants. */ #undef ASM_OUTPUT_SHORT #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "\tshort "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #undef ASM_OUTPUT_CHAR #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ( fprintf (FILE, "\tbyte "), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* This is how to output an assembler line for a numeric constant byte. */ #undef ASM_OUTPUT_BYTE #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf (FILE, "\tbyte 0x%x\n", (VALUE)) #undef ASM_OUTPUT_ADDR_VEC_ELT #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "\tlong L%%%d\n", (VALUE)) #undef ASM_OUTPUT_ADDR_DIFF_ELT #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ fprintf (FILE, "\tshort L%%%d-L%%%d\n", (VALUE), (REL)) #undef ASM_OUTPUT_ALIGN #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG) == 1) \ fprintf (FILE, "\teven\n"); \ else if ((LOG) != 0) \ abort (); #undef ASM_OUTPUT_SKIP #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\tspace %d\n", (SIZE)) #undef PRINT_OPERAND #define PRINT_OPERAND(FILE, X, CODE) \ { if (CODE == '.') fprintf (FILE, "."); \ else if (CODE == '#') fprintf (FILE, "&"); \ else if (CODE == '-') fprintf (FILE, "-(%%sp)"); \ else if (CODE == '+') fprintf (FILE, "(%%sp)+"); \ else if (CODE == '@') fprintf (FILE, "(%%sp)"); \ else if (CODE == '!') fprintf (FILE, "%%fpcr"); \ else if (CODE == '/') \ fprintf (FILE, "%%"); \ else if (CODE == '$') { if (TARGET_68040_ONLY) fprintf (FILE, "s"); } \ else if (CODE == '&') { if (TARGET_68040_ONLY) fprintf (FILE, "d"); } \ else if (GET_CODE (X) == REG) \ fprintf (FILE, "%s", reg_names[REGNO (X)]); \ else if (GET_CODE (X) == MEM) \ output_address (XEXP (X, 0)); \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \ { REAL_VALUE_TYPE r; long l; \ REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ REAL_VALUE_TO_TARGET_SINGLE (r, l); \ fprintf (FILE, "&0x%x", l); } \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode) \ { REAL_VALUE_TYPE r; int i[2]; \ REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ REAL_VALUE_TO_TARGET_DOUBLE (r, i); \ fprintf (FILE, "&0x%x%08x", i[0], i[1]); } \ else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == XFmode) \ { REAL_VALUE_TYPE r; \ REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ ASM_OUTPUT_LONG_DOUBLE_OPERAND (FILE, r); } \ else { putc ('&', FILE); output_addr_const (FILE, X); }} /* Note that this contains a kludge that knows that the only reason we have an address (plus (label_ref...) (reg...)) is in the insn before a tablejump, and we know that the table is exactly 10 bytes away. */ #undef PRINT_OPERAND_ADDRESS #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ { register rtx reg1, reg2, breg, ireg; \ register rtx addr = ADDR; \ rtx offset; \ switch (GET_CODE (addr)) \ { \ case REG: \ fprintf (FILE, "(%s)", reg_names[REGNO (addr)]); \ break; \ case PRE_DEC: \ fprintf (FILE, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case POST_INC: \ fprintf (FILE, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); \ break; \ case PLUS: \ reg1 = 0; reg2 = 0; \ ireg = 0; breg = 0; \ offset = 0; \ if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \ { \ offset = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \ { \ offset = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) != PLUS) ; \ else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == MULT) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == MULT) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ else if (GET_CODE (XEXP (addr, 0)) == REG) \ { \ reg1 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == REG) \ { \ reg1 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \ || GET_CODE (addr) == SIGN_EXTEND) \ { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \ /* for OLD_INDEXING \ else if (GET_CODE (addr) == PLUS) \ { \ if (GET_CODE (XEXP (addr, 0)) == REG) \ { \ reg2 = XEXP (addr, 0); \ addr = XEXP (addr, 1); \ } \ else if (GET_CODE (XEXP (addr, 1)) == REG) \ { \ reg2 = XEXP (addr, 1); \ addr = XEXP (addr, 0); \ } \ } \ */ \ if (offset != 0) { if (addr != 0) abort (); addr = offset; } \ if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \ || GET_CODE (reg1) == MULT)) \ || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \ { breg = reg2; ireg = reg1; } \ else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \ { breg = reg1; ireg = reg2; } \ if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \ { int scale = 1; \ if (GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "10(%%pc,%s.w", \ reg_names[REGNO (XEXP (ireg, 0))]); \ else \ fprintf (FILE, "10(%%pc,%s.l", \ reg_names[REGNO (ireg)]); \ if (scale != 1) fprintf (FILE, "*%d", scale); \ putc (')', FILE); \ break; } \ if (ireg != 0 || breg != 0) \ { int scale = 1; \ if (breg == 0) \ abort (); \ if (addr != 0) \ output_addr_const (FILE, addr); \ fprintf (FILE, "(%s", reg_names[REGNO (breg)]); \ if (ireg != 0) \ putc (',', FILE); \ if (ireg != 0 && GET_CODE (ireg) == MULT) \ { scale = INTVAL (XEXP (ireg, 1)); \ ireg = XEXP (ireg, 0); } \ if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \ fprintf (FILE, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]); \ else if (ireg != 0) \ fprintf (FILE, "%s.l", reg_names[REGNO (ireg)]); \ if (scale != 1) fprintf (FILE, "*%d", scale); \ putc (')', FILE); \ break; \ } \ else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \ { fprintf (FILE, "10(%%pc,%s.w)", \ reg_names[REGNO (reg1)]); \ break; } \ default: \ output_addr_const (FILE, addr); \ }} /* Override usual definitions of SDB output macros. These definitions differ only in the absence of the period at the beginning of the name of the directive and in the use of `~' as the symbol for the current location. */ #define PUT_SDB_SCL(a) fprintf(asm_out_file, "\tscl\t%d;", (a)) #define PUT_SDB_INT_VAL(a) fprintf (asm_out_file, "\tval\t%d;", (a)) #define PUT_SDB_VAL(a) \ ( fputs ("\tval\t", asm_out_file), \ output_addr_const (asm_out_file, (a)), \ fputc (';', asm_out_file)) #define PUT_SDB_DEF(a) \ do { fprintf (asm_out_file, "\tdef\t"); \ ASM_OUTPUT_LABELREF (asm_out_file, a); \ fprintf (asm_out_file, ";"); } while (0) #define PUT_SDB_PLAIN_DEF(a) fprintf(asm_out_file,"\tdef\t~%s;",a) #define PUT_SDB_ENDEF fputs("\tendef\n", asm_out_file) #define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\ttype\t0%o;", a) #define PUT_SDB_SIZE(a) fprintf(asm_out_file, "\tsize\t%d;", a) #define PUT_SDB_START_DIM fprintf(asm_out_file, "\tdim\t") #define PUT_SDB_NEXT_DIM(a) fprintf(asm_out_file, "%d,", a) #define PUT_SDB_LAST_DIM(a) fprintf(asm_out_file, "%d;", a) #define PUT_SDB_TAG(a) \ do { fprintf (asm_out_file, "\ttag\t"); \ ASM_OUTPUT_LABELREF (asm_out_file, a); \ fprintf (asm_out_file, ";"); } while (0) #define PUT_SDB_BLOCK_START(LINE) \ fprintf (asm_out_file, \ "\tdef\t~bb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n", \ (LINE)) #define PUT_SDB_BLOCK_END(LINE) \ fprintf (asm_out_file, \ "\tdef\t~eb;\tval\t~;\tscl\t100;\tline\t%d;\tendef\n", \ (LINE)) #define PUT_SDB_FUNCTION_START(LINE) \ fprintf (asm_out_file, \ "\tdef\t~bf;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n", \ (LINE)) #define PUT_SDB_FUNCTION_END(LINE) \ fprintf (asm_out_file, \ "\tdef\t~ef;\tval\t~;\tscl\t101;\tline\t%d;\tendef\n", \ (LINE)) #define PUT_SDB_EPILOGUE_END(NAME) \ fprintf (asm_out_file, \ "\tdef\t%s;\tval\t~;\tscl\t-1;\tendef\n", \ (NAME)) #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \ sprintf ((BUFFER), "~%dfake", (NUMBER)); #define NO_DOLLAR_IN_LABEL #define NO_DOT_IN_LABEL /* The usual definitions don't work because neither $ nor . is allowed. */ #define CONSTRUCTOR_NAME_FORMAT "_GLOBAL_%%I\%%%s" /* Define a few machine-specific details of the implementation of constructors. The __CTORS_LIST__ goes in the .init section. Define CTOR_LIST_BEGIN and CTOR_LIST_END to contribute to the .init section an instruction to push a word containing 0 (or some equivalent of that). ASM_OUTPUT_CONSTRUCTOR should be defined to push the address of the constructor. */ #define ASM_LONG "\tlong" #undef INIT_SECTION_ASM_OP #define INIT_SECTION_ASM_OP "section\t~init" #undef FINI_SECTION_ASM_OP #define FINI_SECTION_ASM_OP "section\t~fini" #undef CONST_SECTION_ASM_OP #define CONST_SECTION_ASM_OP "section\t~rodata" #define CTOR_LIST_BEGIN \ asm (INIT_SECTION_ASM_OP); \ asm ("clr.l -(%sp)") #define CTOR_LIST_END CTOR_LIST_BEGIN #define BSS_SECTION_ASM_OP "section\t~bss" #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ do { \ init_section (); \ fprintf (FILE, "\tmov.l &"); \ assemble_name (FILE, NAME); \ fprintf (FILE, ",-(%%sp)\n"); \ } while (0) /* We do not want leading underscores. */ #undef ASM_OUTPUT_LABELREF #define ASM_OUTPUT_LABELREF(FILE,NAME) \ fprintf (FILE, "%s", NAME) gcc-2.5.8/config/m68k/tower.h100444 22011 13 7204 5453234745 14344 0ustar kenneruser/* Definitions of target machine for GNU compiler. Copyright (C) 1990 Free Software Foundation, Inc. Written by Robert Andersson, International Systems, Oslo, Norway. Please send bug reports, questions and improvements to ra@intsys.no. For NCR Tower 32/4x0 and 32/6x0 running System V Release 3. I don't have access to 200/700/800/850 machines, so I don't know if it works on those as well. It shouldn't be far from it however. The hardware floating point support is completely untested, as I do not have access to a machine with a 6888x FPU in it. It does not work on the System V Release 2 based OS releases. Making it work will not be easy, due to the silly way in which stack expansion is implemented in the OS. This file is included in tower-as.h. Do *NOT* include this file directly. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/m68k.h" /* See m68k.h. 5 means 68020 with no 68881. */ #define TARGET_DEFAULT 5 /* Don't try using XFmode. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_200 -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)" #if 0 /* It is incorrect to test these symbols. They describe the host, not the target. It should not matter which model is specified. */ #ifdef tower32_600 #define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_600 -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)" #endif #ifdef tower32_700 #define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_700 -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)" #endif #ifdef tower32_800 #define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_800 -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)" #endif #ifdef tower32_850 #define CPP_PREDEFINES "-Dunix -Dtower32 -Dtower32_850 -Asystem(unix) -Asystem(svr3) -Acpu(m68k) -Amachine(m68k)" #endif #endif /* The startfiles and libraries depend on the -p and -m68881 options. The Tower does not support the -pg option. */ #define LINK_SPEC \ "%{p:%{m68881:-L/usr/lib/fp/libp} -L/usr/lib/libp} \ %{m68881:-L/usr/lib/fp}" #define LIB_SPEC \ "%{shlib:-lc_s} -lc crtend.o%s crtn.o%s" #define STARTFILE_SPEC \ "%{p:mcrt1.o%s} %{!p:crt1.o%s} crtbegin.o%s" /* Use mem* functions, recognize #ident lines. */ #define TARGET_MEM_FUNCTIONS #define IDENT_DIRECTIVE /* Every structure and union's size must be a multiple of two bytes. */ #define STRUCTURE_SIZE_BOUNDARY 16 /* All register names should have a leading % character. */ #undef REGISTER_NAMES #define REGISTER_NAMES \ {"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \ "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp", \ "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7"}; /* We do not want leading underscores. */ #undef ASM_OUTPUT_LABELREF #define ASM_OUTPUT_LABELREF(FILE,NAME) \ fprintf (FILE, "%s", NAME) gcc-2.5.8/config/m68k/x-alloca-c100444 22011 13 20 5433344557 14624 0ustar kenneruserALLOCA=alloca.o gcc-2.5.8/config/m68k/x-amix100444 22011 13 1703 5233050473 14145 0ustar kenneruser# Makefile configuration for Commodore Amiga running SVR4. # (configure amiga-amix) # The Amiga ships with gcc installed, so use it as the default CC. CC = /usr/public/bin/gcc # The AT&T compiler is still available in /usr/ccs/bin/cc and should # be used to compile the things that should not be compiled with gcc. OLDCC = /usr/ccs/bin/cc # Link the executables with -ansi to get ANSI floating point ranges. # Otherwise the values returned on overflow or underflow will be wrong. # NOTE: some early releases of Amiga Unix contained a bug in ptod.o # that prevents the correct values being returned from strtod/atof, even # when linked with -ansi. Sometimes -static will fix this since at least # one version had a fixed copy in the static libc.a. LDFLAGS = -ansi # The manual pages go in /usr/man/1l (section 1, local) without any filename # extension. The man command will automatically create the /usr/catman/1l # entry. mandir = /usr/man/1l manext = gcc-2.5.8/config/m68k/x-apollo68100444 22011 13 1321 5413417044 14650 0ustar kenneruser# x-apollo68 -- 680x0 based Apollos as host system # vasta@apollo.com says this is how to compile on an Apollo (SR10.x). # Use a Berkeley environment. CC=cc -g -A nansi -A cpu,3000 -A runtype,bsd4.3 -A systype,any -DSHORT_ENUM_BUG OLDCC=cc -g -A nansi -A cpu,3000 -A runtype,bsd4.3 -A systype,any -DSHORT_ENUM_BUG # This used to redefine CFLAGS and LIBGCC2_CFLAGS to eliminate the unsupported # -g flag from both macros. This gives an undebugable stage1 compiler which # is bad, and it also does the wrong thing if we are cross compiling to a # target which does support debugging. There is currently no way to avoid # the -g option that doesn't break something else. # Apollo does not have B option. TAROUTOPTS=xpf gcc-2.5.8/config/m68k/x-crds100444 22011 13 357 5216465236 14136 0ustar kenneruserCC = cc -Wx,-X23 # The following line might be necessary as well or instead of the above. # If you find out that it is necessary, # or if you find out that it is not necessary, # please inform bug-gcc@prep.ai.mit.edu. # ALLOCA = alloca.o gcc-2.5.8/config/m68k/x-dpx2100444 22011 13 1237 5427264131 14071 0ustar kenneruser# need this when using cc ALLOCA = alloca.o # avoid lossage assembling alloca. ALLOCA_FLAGS=-S ALLOCA_FINISH = $(AS) -o alloca.o alloca.s # be sure not to confuse ./as with /bin/as AS=`if [ x$(OLDCC) = x$(CC) ] ; then echo /bin/as; else echo $(GAS); fi` GAS = gas # # as of gcc-2.2.1 gcc -g produces too many .stabd's for /bin/ld # to link cc1plus, so use -g with /bin/cc, but -O with gcc CFLAGS=`if [ x$(OLDCC) = x$(CC) ] ; then echo -g; else echo -O; fi` # CLIB=-lmalloc -lld -lm # tell CC whether we are a 200 or 300 X_CFLAGS=-D_POSIX_SOURCE -D_XOPEN_SOURCE -D_BULL_SOURCE -D__DPX2__ `if [ -d /makesys/kernel/cf/ncl_mr ]; then echo -Dncl_mr=1; else echo -Dncl_el; fi` gcc-2.5.8/config/m68k/x-hp2bsd100444 22011 13 213 5216465333 14352 0ustar kenneruser# Make assignments for compilation for hp200 running 4.3bsd CC=gcc OLDCC=oldcc # You must have a previous version of gcc for bootstrapping gcc-2.5.8/config/m68k/x-hp320100444 22011 13 763 5374542613 14040 0ustar kenneruser# Make assignments for compilation on HPUX with their C compiler. CC=cc -Wc,-Nw2000 -Wc,-Ns2000 -Wc,-Ne700 -Wc,-Np300 OLDCC=cc -Wc,-Nw2000 -Wc,-Ns2000 -Wc,-Ne700 -Wc,-Np300 ALLOCA=alloca.o # B option not supported on hpux. TAROUTOPTS = xpf # For CCLIBFLAGS you might want to specify the switch that # forces only 68000 instructions to be used. # Version 5 of HPUX had a compiler bug that made it crash with -g. # You must set CFLAGS to empty on version 5. # You must get alloca.c from GNU Emacs. gcc-2.5.8/config/m68k/x-hp320g100444 22011 13 745 5374542630 14206 0ustar kenneruser# Make assignments for compilation on HPUX with their C compiler. CC=cc -Wc,-Nw2000 -Wc,-Ns2000 -Wc,-Ne700 -Wc,-Np300 OLDCC=cc -Wc,-Nw2000 -Wc,-Ns2000 -Wc,-Ne700 -Wc,-Np300 ALLOCA=alloca.o # B option not supported on hpux. TAROUTOPTS = xpf # For CCLIBFLAGS you might want to specify the switch that # forces only 68000 instructions to be used. X_CFLAGS= -I../hp-include # Version 5 of HPUX had a compiler bug that made it crash with -g. # You must set CFLAGS to empty on version 5. gcc-2.5.8/config/m68k/x-hp3bsd44100444 22011 13 47 5352706506 14511 0ustar kenneruserCC=/usr/local/bin/gcc INSTALL_HEADERS= gcc-2.5.8/config/m68k/x-next100444 22011 13 272 5276105743 14155 0ustar kenneruser# Make assignments for compiling on NeXT with their compiler version. CC=cc -traditional-cpp OLDCC=cc -traditional-cpp libgcc2.a: stdarg.h stdarg.h: cp $(srcdir)/gstdarg.h ./stdarg.h gcc-2.5.8/config/m68k/x-tower100444 22011 13 730 5235134271 14327 0ustar kenneruser# On the NCR Tower 32 running SVR3, says ra@intsys.no : # Do *not* enable optimization in CFLAGS when using the native cc, because: # a) The optimizer seems to loop when invoked with -O2. # b) The -O1 level does stack/frame pointer optimizations that make the # assembler alloca in libPW.a fail, and the C alloca eats *lots* of memory. # c) gcc will eventually be recompiled with itself, so all this doesn't matter. X_CFLAGS = -O0 CCLIBFLAGS = -O2 CLIB = -lmalloc -lPW gcc-2.5.8/config/m68k/xm-3b1.h100444 22011 13 275 5322246171 14163 0ustar kenneruser#define USG #include "m68k/xm-m68k.h" #define bcopy(a,b,c) memcpy (b,a,c) #define bzero(a,b) memset (a,0,b) #define bcmp(a,b,c) memcmp (a,b,c) #define index strchr #define rindex strrchr gcc-2.5.8/config/m68k/xm-altos3068.h100444 22011 13 221 5322246157 15234 0ustar kenneruser#define USG #include "m68k/xm-m68k.h" #define bcopy(a,b,c) memcpy (b,a,c) #define bzero(a,b) memset (a,0,b) #define bcmp(a,b,c) memcmp (a,b,c) gcc-2.5.8/config/m68k/xm-amix.h100444 22011 13 3346 5463534660 14567 0ustar kenneruser/* Definitions of host machine for GNU compiler. Commodore Amiga A3000UX version. Copyright (C) 1991 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 1, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m68k/xm-m68kv.h" /* Use the System V flavor of m68k host */ #define HAVE_VPRINTF /* Host has vprintf() in library */ #define rindex strrchr #define index strchr /* Define FULL_PROTOTYPES for protoize.c, to get included. We need this file for things like R_OK, not necessarily prototypes. */ #define FULL_PROTOTYPES #if defined (__GNUC__) && __GNUC__ == 1 #define alloca __builtin_alloca #endif #if 0 /* I don't want individual ports to be inconsistent about this. I regard fancy_abort as a half-solution and not the right way to do things. --rms. */ /* The m88k and mips ports make use of fancy_abort to give possibly helpful abort information rather than just dumping core. They do it in their tm-* files. It seems more logical that this is a characteristic of the host machine and not the target machine, so we do it here. */ #define abort fancy_abort /* give possibly helpful abort info */ #endif gcc-2.5.8/config/m68k/xm-crds.h100444 22011 13 505 5413066322 14524 0ustar kenneruser#define USG #ifndef unos #define unos #endif #include "m68k/xm-m68k.h" #define bcopy(a,b,c) memcpy (b,a,c) #define bzero(a,b) memset (a,0,b) #define bcmp(a,b,c) memcmp (a,b,c) /* Avoid conflict with C library by changing name of this symbol. */ #define gettime gcc_gettime #ifndef __GNUC__ #define USE_C_ALLOCA #endif gcc-2.5.8/config/m68k/xm-hp320.h100444 22011 13 715 5322246105 14426 0ustar kenneruser/* USG is needed to prevent trying to use getrusage and getwd. */ #define USG #include "m68k/xm-m68k.h" #define bcopy(a,b,c) memcpy (b,a,c) #define bzero(a,b) memset (a,0,b) #define bcmp(a,b,c) memcmp (a,b,c) #define rindex strrchr #define index strchr /* If compiling with HPUX compiler, we are probably using alloca.c, so help it work right. */ #ifndef __GNUC__ #define USE_C_ALLOCA #endif /* Don't try to use sys_siglist. */ #define NO_SYS_SIGLIST gcc-2.5.8/config/m68k/xm-m68k.h100444 22011 13 2473 5413066271 14407 0ustar kenneruser/* Configuration for GNU C-compiler for Motorola 68000 family. Copyright (C) 1987, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* #defines that need visibility everywhere. */ #define FALSE 0 #define TRUE 1 /* This describes the machine the compiler is hosted on. */ #define HOST_BITS_PER_CHAR 8 #define HOST_BITS_PER_SHORT 16 #define HOST_BITS_PER_INT 32 #define HOST_BITS_PER_LONG 32 #define HOST_BITS_PER_LONGLONG 64 #define HOST_WORDS_BIG_ENDIAN /* target machine dependencies. tm.h is a symbolic link to the actual target specific file. */ #include "tm.h" /* Arguments to use with `exit'. */ #define SUCCESS_EXIT_CODE 0 #define FATAL_EXIT_CODE 33 gcc-2.5.8/config/m68k/xm-m68kv.h100444 22011 13 442 5322246072 14545 0ustar kenneruser/* Host environment for 68000's running System V. */ #include "m68k/xm-m68k.h" #define USG #define bcopy(a,b,c) memcpy (b,a,c) #define bzero(a,b) memset (a,0,b) #define bcmp(a,b,c) memcmp (a,b,c) #define rindex strrchr #define index strchr #ifndef __GNUC__ #define USE_C_ALLOCA #endif gcc-2.5.8/config/m68k/xm-mot3300.h100444 22011 13 404 5350220031 14661 0ustar kenneruser#define USG #include "m68k/xm-m68k.h" #define bcopy(a,b,c) memcpy (b,a,c) #define bzero(a,b) memset (a,0,b) #define bcmp(a,b,c) memcmp (a,b,c) #define rindex strrchr #define index strchr #define NO_SYS_SIGLIST #ifndef __GNUC__ #define USE_C_ALLOCA #endif gcc-2.5.8/config/m68k/xm-next.h100444 22011 13 203 5322246044 14542 0ustar kenneruser#include "m68k/xm-m68k.h" /* malloc does better with chunks the size of a page. */ #define OBSTACK_CHUNK_SIZE (getpagesize ()) gcc-2.5.8/config/m68k/xm-plexus.h100444 22011 13 540 5322246030 15103 0ustar kenneruser/* Host environment for 68000's running System V. */ #include "m68k/xm-m68k.h" #define USG #define bcopy(a,b,c) memcpy (b,a,c) #define bzero(a,b) memset (a,0,b) #define bcmp(a,b,c) memcmp (a,b,c) #define rindex strrchr #define index strchr #ifndef __GNUC__ #define USE_C_ALLOCA #endif #ifndef _SIZE_T_ typedef int size_t; #define _SIZE_T_ #endif gcc-2.5.8/config/m68k/xm-tower.h100444 22011 13 105 5322246013 14721 0ustar kenneruser#include "m68k/xm-m68k.h" #include "xm-svr3.h" #define HAVE_VPRINTF gcc-2.5.8/config/m88k/ 40777 22011 13 0 5502603156 12732 5ustar kennerusergcc-2.5.8/config/m88k/dgux.h100444 22011 13 20727 5467020227 14173 0ustar kenneruser/* Definitions of target machine for GNU compiler. Motorola m88100 running DG/UX. Copyright (C) 1988, 1989, 1990, 1991 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@mcc.com) Enhanced by Michael Meissner (meissner@osf.org) Version 2 port by Tom Wood (Tom_Wood@NeXT.com) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* You're not seeing double! To transition to dwarf debugging, both are supported. The option -msvr4 and -mversion-03.00 specify (for DG/UX) `real' elf. With these combinations, -g means dwarf. */ /* DWARF_DEBUGGING_INFO defined in svr4.h. */ #define SDB_DEBUGGING_INFO #define PREFERRED_DEBUGGING_TYPE \ (GET_VERSION_0300_SYNTAX ? DWARF_DEBUG : SDB_DEBUG) /* This controls a bug fix in cp-decl.c. For version 2.6, someone should figure out the right condition. */ #define RMS_QUICK_HACK_1 #ifndef NO_BUGS #define AS_BUG_IMMEDIATE_LABEL /* The DG/UX 4.30 assembler doesn't accept the symbol `fcr63'. */ #define AS_BUG_FLDCR #endif #include "svr4.h" #include "m88k/m88k.h" /* Augment TARGET_SWITCHES with the MXDB options. */ #define MASK_STANDARD 0x40000000 /* Retain standard information */ #define MASK_LEGEND 0x20000000 /* Retain legend information */ #define MASK_EXTERNAL_LEGEND 0x10000000 /* Make external legends */ #define TARGET_STANDARD (target_flags & MASK_STANDARD) #define TARGET_LEGEND (target_flags & MASK_LEGEND) #define TARGET_EXTERNAL_LEGEND (target_flags & MASK_EXTERNAL_LEGEND) #undef SUBTARGET_SWITCHES #define SUBTARGET_SWITCHES \ { "standard", MASK_STANDARD }, \ { "legend", MASK_LEGEND }, \ { "external-legend", MASK_EXTERNAL_LEGEND }, \ /* the following is used only in the *_SPEC's */ \ { "keep-coff", 0 }, /* Default switches */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_CHECK_ZERO_DIV | \ MASK_OCS_DEBUG_INFO | \ MASK_OCS_FRAME_POSITION) #undef CPU_DEFAULT #define CPU_DEFAULT MASK_88000 /* Macros to be automatically defined. __svr4__ is our extension. __CLASSIFY_TYPE__ is used in the and header files with DG/UX revision 5.40 and later. This allows GNU CC to operate without installing the header files. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dm88000 -Dm88k -Dunix -DDGUX -D__CLASSIFY_TYPE__=2\ -D__svr4__ -Asystem(unix) -Asystem(svr4) -Acpu(m88k) -Amachine(m88k)" /* If -m88100 is in effect, add -Dm88100; similarly for -m88110. Here, the CPU_DEFAULT is assumed to be -m88000. If not -ansi, -traditional, or restricting include files to one specific source target, specify full DG/UX features. */ #undef CPP_SPEC #define CPP_SPEC "%{!m88000:%{!m88100:%{m88110:-D__m88110__}}} \ %{!m88000:%{!m88110:%{m88100:-D__m88100__}}} \ %{!ansi:%{!traditional:-D__OPEN_NAMESPACE__}}" /* Assembler support (-V, silicon filter, legends for mxdb). */ #undef ASM_SPEC #define ASM_SPEC "\ %{V} %{v:%{!V:-V}} %{pipe:%{!.s: - }\ %{msvr4:%{mversion-03.00:-KV3}%{!mversion-03.00:%{mversion-*:-KV%*}}}}\ %{!mlegend:%{mstandard:-Wc,off}}\ %{mlegend:-Wc,-fix-bb,-h\"gcc-2.3.3\",-s\"%i\"\ %{traditional:,-lc}%{!traditional:,-lansi-c}\ %{mstandard:,-keep-std}\ %{mkeep-coff:,-keep-coff}\ %{mexternal-legend:,-external}\ %{mocs-frame-position:,-ocs}}" /* Override svr4.h. */ #undef ASM_FINAL_SPEC #undef STARTFILE_SPEC /* Linker and library spec's. -static, -shared, -symbolic, -h* and -z* access AT&T V.4 link options. -svr4 instructs gcc to place /usr/lib/values-X[cat].o on link the line. The absense of -msvr4 indicates linking done in a COFF environment and adds the link script to the link line. In all environments, the first and last objects are crtbegin.o and crtend.o. When the -G link option is used (-shared and -symbolic) a final link is not being done. */ #undef LIB_SPEC #define LIB_SPEC "%{msvr4:%{!shared:-lstaticdgc}} %{!shared:%{!symbolic:-lc}} crtend.o%s" #undef LINK_SPEC #define LINK_SPEC "%{z*} %{h*} %{V} %{v:%{!V:-V}} \ %{static:-dn -Bstatic} \ %{shared:-G -dy} \ %{symbolic:-Bsymbolic -G -dy} \ %{pg:-L/usr/lib/libp}%{p:-L/usr/lib/libp}" #undef STARTFILE_SPEC #define STARTFILE_SPEC "%{!shared:%{!symbolic:%{pg:gcrt0.o%s} \ %{!pg:%{p:/lib/mcrt0.o}%{!p:/lib/crt0.o}} \ %{!msvr4:m88kdgux.ld%s} crtbegin.o%s \ %{svr4:%{ansi:/lib/values-Xc.o} \ %{!ansi:%{traditional:/lib/values-Xt.o} \ %{!traditional:/usr/lib/values-Xa.o}}}}}" /* Fast DG/UX version of profiler that does not require lots of registers to be stored. */ #undef FUNCTION_PROFILER #define FUNCTION_PROFILER(FILE, LABELNO) \ output_function_profiler (FILE, LABELNO, "gcc.mcount", 0) /* DGUX V.4 isn't quite ELF--yet. */ #undef VERSION_0300_SYNTAX #define VERSION_0300_SYNTAX (TARGET_SVR4 && m88k_version_0300) /* Same, but used before OVERRIDE_OPTIONS has been processed. */ #define GET_VERSION_0300_SYNTAX \ (TARGET_SVR4 && m88k_version != 0 && strcmp (m88k_version, "03.00") >= 0) /* Output the legend info for mxdb when debugging except if standard debugging information only is explicitly requested. */ #undef ASM_FIRST_LINE #define ASM_FIRST_LINE(FILE) \ do { \ if (m88k_version) \ fprintf (FILE, "\t%s\t \"%s\"\n", VERSION_ASM_OP, m88k_version); \ if (write_symbols != NO_DEBUG \ && ! (TARGET_STANDARD && ! TARGET_LEGEND)) \ { \ fprintf (FILE, ";legend_info -fix-bb -h\"gcc-%s\" -s\"%s\"", \ VERSION_STRING, main_input_filename); \ fputs (flag_traditional ? " -lc" : " -lansi-c", FILE); \ if (TARGET_STANDARD) \ fputs (" -keep-std", FILE); \ if (TARGET_EXTERNAL_LEGEND) \ fputs (" -external", FILE); \ if (TARGET_OCS_FRAME_POSITION) \ fputs (" -ocs", FILE); \ fputc ('\n', FILE); \ } \ } while (0) /* Override svr4.h. */ #undef PTRDIFF_TYPE #undef WCHAR_TYPE #undef WCHAR_TYPE_SIZE /* Override svr4.h and m88k.h except when compiling crtstuff.c. These must be constant strings when compiling crtstuff.c. Otherwise, respect the -mversion-STRING option used. */ #if !defined (CRT_BEGIN) && !defined (CRT_END) #undef INIT_SECTION_ASM_OP #define INIT_SECTION_ASM_OP (VERSION_0300_SYNTAX \ ? "section\t .init,\"xa\"" \ : "section\t .init,\"x\"") #undef CTORS_SECTION_ASM_OP #define CTORS_SECTION_ASM_OP (VERSION_0300_SYNTAX \ ? "section\t .ctors,\"aw\"" \ : "section\t .ctors,\"d\"") #undef DTORS_SECTION_ASM_OP #define DTORS_SECTION_ASM_OP (VERSION_0300_SYNTAX \ ? "section\t .dtors,\"aw\"" \ : "section\t .dtors,\"d\"") #endif /* crtstuff.c */ /* The lists of global object constructors and global destructors are always placed in the .ctors/.dtors sections. This requires the use of a link script if the COFF linker is used, but otherwise COFF and ELF objects can be intermixed. A COFF object will pad the section to 16 bytes with zeros; and ELF object will not contain padding. We deal with this by putting a -1 marker at the begin and end of the list and ignoring zero entries. */ /* Mark the end of the .ctors/.dtors sections with a -1. */ #define CTOR_LIST_END \ asm (CTORS_SECTION_ASM_OP); \ func_ptr __CTOR_END__[1] = { (func_ptr) (-1) } #define DTOR_LIST_END \ asm (DTORS_SECTION_ASM_OP); \ func_ptr __DTOR_END__[1] = { (func_ptr) (-1) } /* Walk the list ignoring NULL entries till we hit the terminating -1. */ #define DO_GLOBAL_CTORS_BODY \ do { \ int i; \ for (i=1;(int)(__CTOR_LIST__[i]) != -1; i++) \ if (((int *)__CTOR_LIST__)[i] != 0) \ __CTOR_LIST__[i] (); \ } while (0) /* Walk the list looking for the terminating -1 that marks the end. Go backward and ignore any NULL entries. */ #define DO_GLOBAL_DTORS_BODY \ do { \ int i; \ for (i=1;(int)(__DTOR_LIST__[i]) != -1; i++); \ for (i-=1;(int)(__DTOR_LIST__[i]) != -1; i--) \ if (((int *)__DTOR_LIST__)[i] != 0) \ __DTOR_LIST__[i] (); \ } while (0) gcc-2.5.8/config/m88k/dgux.ld100444 22011 13 4303 5317420365 14314 0ustar kenneruser/* m88kdgux.ld - COFF linker directives for G++ on an AViiON This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. On The AViiON we start the output .text section somewhere after the first 64kb (0x10000) of logical address space so that the first 64kb can be mapped out, thus catching references through null pointers. We actually start at 0x10200 (for efficiency). Ideally, we want the page offset of a given word of the .text (output) section to be the same as it's page offset in the actual (output) linked core file so that paging of the .text section is efficient. In order to do this we allow for up to 0x200 bytes of header stuff in the output (linked) object file. For .data, the OCS says that regions with different "protections" (i.e. read/write, read-only) should not share any 4 megabyte chunk of the logical address space, so we start the .data segment at the first (lowest) 4 MB boundary past the end of the .text segment. For some reason, you can't start right at the 4 MB boundary. You have to start at some distance past that. The distance must be equal to the distance from the start of the last 64 KB segment in the (output) .text segment to the actual end of the (output) .text segment. */ SECTIONS { .text 0x10200 BLOCK(0x200) : { *(.init) *(.initp) *(.finip) *(.text) *(.tdesc) } GROUP BIND (((((ADDR(.text) + SIZEOF(.text) - 1) / 0x400000) + 1) * 0x400000) + ((ADDR(.text) + SIZEOF (.text)) % 0x10000)) : { .data : { *(.data) *(.ctors) *(.dtors) } .bss : {} } } gcc-2.5.8/config/m88k/dolph.h100444 22011 13 3514 5473747621 14320 0ustar kenneruser/* Definitions of target machine for GNU compiler. Motorola m88100 running the Dolphin UNIX System V/88 Release 3.2, Version 3.8/7.83 and 3.6/5.86 Copyright (C) 1992, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m88k/sysv3.h" #define SDB_ALLOW_FORWARD_REFERENCES #define SDB_ALLOW_UNKNOWN_REFERENCES /* Override m88k/sysv3.h */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dm88000 -Dm88k -DOCS88 -DDOLPHIN -Dunix -DsysV88 -D__CLASSIFY_TYPE__=2 -Asystem(unix) -Asystem(svr3) -Acpu(m88k) -Amachine(m88k)" /* If you want to detect dereferencing of NULL pointers, uncomment the following two lines. Alternatively, edit the appropriate specs file. #undef LINK_SPEC #define LINK_SPEC "gcc.ld%s" */ #undef CPU_DEFAULT #define CPU_DEFAULT MASK_88000 #undef INITIALIZE_TRAMPOLINE #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 40)), FNADDR); \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 36)), CXT); \ emit_call_insn (gen_call( gen_rtx (MEM, SImode, \ gen_rtx(SYMBOL_REF,Pmode, \ "__enable_execute_stack")), \ const0_rtx)); \ } gcc-2.5.8/config/m88k/dolphin.ld100444 22011 13 2575 5473750557 15027 0ustar kenneruser/* COFF linker directives for the Dolphin Triton88 for GNU compiler. Copyright (C) 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ This file does the following: - Sets VIRTUAL addr of .text to 0x400200 Sets FILE addr of .text to 0x200 (BLOCK directive) - Depending on size of .text section rounds up to next 4 MG boundary, adds (size of .text and vaddr of .text) mod 64K This is to handle sections larger than 4 MG. */ SECTIONS { .text 0x400200 BLOCK (0x200): { *(.init) *(.text) *(.rodata) *(.tdesc) *(.fini)} GROUP BIND( (((SIZEOF(.text)+ADDR(.text)) / 0x400000 * 0x400000) + 0x400000) + ((SIZEOF(.text) + ADDR(.text)) % 0x10000) ) : { .data : { } .bss : { } } } gcc-2.5.8/config/m88k/luna.h100444 22011 13 4144 5453234754 14145 0ustar kenneruser/* Definitions of target machine for GNU compiler. Motorola m88100 running Omron Luna/88k. Copyright (C) 1991 Free Software Foundation, Inc. Contributed by Jeffery Friedl (jfriedl@omron.co.jp) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* The Omron Luna/88k is MACH and uses BSD a.out, not COFF or ELF. */ #ifndef MACH #define MACH #endif #define DBX_DEBUGGING_INFO #define DEFAULT_GDB_EXTENSIONS 0 #include "aoutos.h" #include "m88k/m88k.h" /* Identify the compiler. */ #undef VERSION_INFO1 #define VERSION_INFO1 "Omron Luna/88k, " /* Macros to be automatically defined. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES \ "-DMACH -Dm88k -Dunix -Dluna -Dluna88k -D__CLASSIFY_TYPE__=2 -Asystem(unix) -Asystem(mach) -Acpu(m88k) -Amachine(m88k)" /* If -m88000 is in effect, add -Dmc88000; similarly for -m88100 and -m88110. However, reproduce the effect of -Dmc88100 previously in CPP_PREDEFINES. Here, the CPU_DEFAULT is assumed to be -m88100. */ #undef CPP_SPEC #define CPP_SPEC "%{m88000:-D__mc88000__} \ %{!m88000:%{m88100:%{m88110:-D__mc88000__}}} \ %{!m88000:%{!m88100:%{m88110:-D__mc88110__}}} \ %{!m88000:%{!m88110:%{!ansi:%{traditional:-Dmc88100}} \ -D__mc88100__ -D__mc88100}}" /* Specify extra dir to search for include files. */ #undef SYSTEM_INCLUDE_DIR #define SYSTEM_INCLUDE_DIR "/usr/mach/include" /* For the Omron Luna/88k, a float function returns a double in traditional mode (and a float in ansi mode). */ #undef TRADITIONAL_RETURN_FLOAT gcc-2.5.8/config/m88k/m88k-move.sh100555 22011 13 24527 5453141104 15140 0ustar kenneruser#!/bin/sh # # If your shell doesn't support functions (true for some BSD users), # you might try using GNU's bash. # #ident "@(#) m88k-move.sh 1-Sep-92" # # This file provided by Data General, February 1990. # # This script generates the necessary movstr library functions # for the m88100. These functions are called from the expansion # of movstrsi. There are eight modules created by this script, # each with multiple entry points. One module, moveSI64n # implements a word aligned loop; the other modules, moveXINx # implement a straight line copy of N bytes in mode XI. # # By analysis of the best memcpy function, it can be determined # what appear to be certain magic numbers. For example, a # memcpy of 13 bytes, where the pointers are determined at run # time to be word aligned takes 28 cycles. A call to # __movstrQI13x13 also takes 28 cycles. The break even point # for a HImode copy is 38 bytes. Just to be on the safe side, # these are bumped to 16 and 48 respectively. # # The smaller, odd-remainder modules are provided to help # mitigate the overhead of copying the last bytes. # # Changes to these functions should not be taken lightly if you # want to be able to link programs built with older movstr # parameters. # #.Revision History # # 1-Sep-92 Stan Cox Added moveDI96x, moveDI41x through moveDI47x. # 2-Jan-92 Tom Wood Renamed files to comply with SVR3 14 char limit. # 26-Oct-90 Tom Wood Delete movstr.h; moved to out-m88k.c. # 17-Oct-90 Tom Wood Files are named *.asm rather than *.s. # 11-Sep-90 Jeffrey Friedl # On my BSD 4.3 awk and my GNU-awk, only the # first character of an argument to -F is passed # through, so I can't get this to work. # 5-Sep-90 Ray Essick/Tom Wood # Added a -no-tdesc option. # 27-Aug-90 Vince Guarna/Tom Wood # Version 3 assembler syntax (-abi). # 16-Aug-90 Ron Guilmette # Avoid problems on a Sparc. The common # denominator among shells seems to be '...\' # rather than '...\\'. # 15-Aug-90 Ron Guilmette # Avoid awk syntax errors on a Sun by not using # the `!' operator. # 22-Feb-90 Tom Wood Created. # 20-Jun-90 Tom Wood Emit file directives. # #.End]=--------------------------------------------------------------*/ usage() { echo "usage: $0 [ -abi ] [ -no-tdesc ]" 1>&2 exit 1 } awk_flag="-F:"; awk_begin="BEGIN { " ps=""; us="_"; tf="x"; la="@L"; fb="8"; nt=""; do_file() { echo " file $1"; } while [ $# -gt 0 ] ; do case $1 in -no-tdesc) awk_begin="$awk_begin no_tdesc=1;" nt=";";; -abi) awk_begin="$awk_begin abi=1;" ps="#"; us=""; tf="a"; la=".L"; fb="16"; do_file() { echo ' version "03.00"'; echo " file $1"; };; *) usage;; esac shift done rm -f move?I*[xn].s move?I*[xn].asm #.Implementation_continued[=----------------------------------------------- # # This generates the word aligned loop. The loop is entered # from the callable entry points ___movstrSI64nN, where at # least N bytes will be copied. r2 is the destination pointer # offset by 4, r3 is the source pointer offset by 4, r6 is the # loop count. Thus, the total bytes moved is 64 * r6 + N. The # first value is is preloaded into r4 or r5 (r4 if N/4 is odd; # r5 if N/4 is even). Upon returning, r2 and r3 have been # updated and may be used for the remainder bytes to move. # # The code for this loop is generated by the awk program # following. Edit *it*, not what it generates! # #.End]=------------------------------------------------------------------*/ gen_movstrN() { awk $awk_flag "$awk_begin"' if (abi) { ps="#"; us=""; tf="a"; la=".L"; fb=16; } else { ps=""; us="_"; tf="x"; la="@L"; fb=8; } } NR == 1 && NF == 4 { mode = $1; suffix = $2; align = $3; count = $4; ld = align; st = 0; printf "; The following was calculated using awk.\n"; printf "\ttext\n"; printf "\talign\t%d\n", fb; printf "%sloop%s%d:\n", la, mode, count * align; printf "\taddu\t%sr3,%sr3,%d\n", ps, ps, count * align; printf "\taddu\t%sr2,%sr2,%d\n", ps, ps, count * align; printf "\tsubu\t%sr6,%sr6,1\n", ps, ps; for (r = count + 1; r >= 1; r--) { evenp = r % 2; name = sprintf("__%smovstr%s%dn%d", us, mode, count * align, r * align); if (r > 1) { printf "\tglobal\t%s\n", name; printf "%s:\n", name; } if (r > 2) { printf "\tld%s\t%sr%d,%sr3,%d\n", suffix, ps, 4 + evenp, ps, ld; printf "\tst%s\t%sr%d,%sr2,%d\n", suffix, ps, 5 - evenp, ps, st; } else if (r == 2) { printf "\tld%s\t%sr%d,%sr3,%d\n", suffix, ps, 4 + evenp, ps, ld; printf "\tbcnd.n\t%sgt0,%sr6,%sloop%s%d\n", ps, ps, la, mode, count * align; printf "\tst%s\t%sr%d,%sr2,%d\n", suffix, ps, 5 - evenp, ps, st; printf "\tjmp.n\t%sr1\n", ps; } else { printf "\tst%s\t%sr%d,%sr2,%d\n", suffix, ps, 5 - evenp, ps, st; } ld += align; st += align; } if (!no_tdesc) { printf "%send%s%d:\n", la, mode, count * align; printf "\tsection\t.tdesc,\"%s\"\n", tf; printf "\tword\t0x42,1,%sloop%s%d", la, mode, count * align; printf ",%send%s%d\n", la, mode, count * align; printf "\tword\t0x0100001f,0,1,0\n"; printf "\ttext\n"; } printf "; End of awk generated code.\n"; exit; }' } (do_file '"movstrSI64n.s"'; echo 'SI::4:16' | gen_movstrN) > moveSI64n.asm #.Implementation_continued[=----------------------------------------------- # # This generates the even-remainder, straight-line modules. # The code is entered from the callable entry points # ___movstrXINxM, where exactly M bytes will be copied in XI # mode. r2 is the destination pointer, r3 is the source # pointer, neither being offset. The first value is preloaded # into r4 or r5 (r4 if M-N/B is even; r5 if M-N/B is odd, where # B is the mode size of XI). Upon returning, r2 and r3 have not # been changed. # # The code for these cases is generated by the awk program # following. Edit *it*, not what it generates! # #.End]=------------------------------------------------------------------*/ gen_movstrX0() { awk $awk_flag "$awk_begin"' if (abi) { ps="#"; us=""; tf="a"; la=".L"; fb=16; } else { ps=""; us="_"; tf="x"; la="@L"; fb=8; } } NR == 1 && NF == 4 { mode = $1; suffix = $2; align = $3; bytes = $4; ld = align; st = 0; count = bytes / align; reg[0] = 4; if (align == 8) reg[1] = 6; else reg[1] = 5; printf "; The following was calculated using awk.\n"; printf "\ttext\n"; printf "\talign\t%d\n", fb; for (r = count; r >= 1; r--) { evenp = r % 2; name = sprintf("__%smovstr%s%dx%d", us, mode, count * align, r * align); if (r > 1) { printf "\tglobal\t%s\n", name; printf "%s:\n", name; } if (r == 1) printf "\tjmp.n\t%sr1\n", ps; else printf "\tld%s\t%sr%d,%sr3,%d\n", suffix, ps, reg[evenp], ps, ld; printf "\tst%s\t%sr%d,%sr2,%d\n", suffix, ps, reg[1-evenp], ps, st; ld += align; st += align; } if (!no_tdesc) { printf "%send%s%dx:\n", la, mode, count * align; printf "\tsection\t.tdesc,\"%s\"\n", tf; printf "\tword\t0x42,1,__%smovstr%s%dx%d", us, mode, count * align, count * align; printf ",%send%s%dx\n", la, mode, count * align; printf "\tword\t0x0100001f,0,1,0\n"; printf "\ttext\n"; } printf "; End of awk generated code.\n" exit; }' } (do_file '"movstrQI16x.s"'; echo 'QI:.b:1:16' | gen_movstrX0) > moveQI16x.asm (do_file '"movstrHI48x.s"'; echo 'HI:.h:2:48' | gen_movstrX0) > moveHI48x.asm (do_file '"movstrSI96x.s"'; echo 'SI::4:96' | gen_movstrX0) > moveSI96x.asm (do_file '"movstrDI96x.s"'; echo 'DI:.d:8:96' | gen_movstrX0) > moveDI96x.asm #.Implementation_continued[=----------------------------------------------- # # This generates the odd-remainder, straight-line modules. The # interface is the same as that for the even-remainder modules. # #.End]=------------------------------------------------------------------*/ gen_movstrXr() { awk $awk_flag "$awk_begin"' if (abi) { ps="#"; us=""; tf="a"; la=".L"; fb=16; } else { ps=""; us="_"; tf="x"; la="@L"; fb=8; } } NR == 1 && NF == 4 { mode = $1; rem = $2; most = $3; count = $4; suffix[1] = ".b"; suffix[2] = ".h"; suffix[4] = ""; suffix[8] = ".d"; prev = align = most; ld = align; st = 0; total = count - rem - most; evenp = int(total/align) % 2; reg[0] = 4; if (align == 8) reg[1] = 6; else reg[1] = 5; printf "; The following was calculated using awk.\n"; printf "\ttext\n"; printf "\talign\t%d\n", fb; for (bytes = total; bytes >= 0; bytes -= align) { if (bytes < align) { if (bytes >= 4) align = 4; else if (bytes >= 2) align = 2; else align = 1; } name = sprintf("__%smovstr%s%dx%d", us, mode, total + most, bytes + most); if (bytes > most) { printf "\tglobal\t%s\n", name; printf "%s:\n", name; } if (bytes == 0) printf "\tjmp.n\t%sr1\n", ps; else printf "\tld%s\t%sr%d,%sr3,%d\n", suffix[align], ps, reg[evenp], ps, ld; printf "\tst%s\t%sr%d,%sr2,%d\n", suffix[prev], ps, reg[1-evenp], ps, st; ld += align; st += prev; prev = align; evenp = 1 - evenp; } if (!no_tdesc) { printf "%send%s%dx:\n", la, mode, total + most; printf "\tsection\t.tdesc,\"%s\"\n", tf; printf "\tword\t0x42,1,__%smovstr%s%dx%d", us, mode, total + most, total + most; printf ",%send%s%dx\n", la, mode, total + most; printf "\tword\t0x0100001f,0,1,0\n"; printf "\ttext\n"; } printf "; End of awk generated code.\n" exit; }' } (do_file '"movstrDI47x.s"'; echo 'DI:1:8:48' | gen_movstrXr) > moveDI47x.asm (do_file '"movstrDI46x.s"'; echo 'DI:2:8:48' | gen_movstrXr) > moveDI46x.asm (do_file '"movstrDI45x.s"'; echo 'DI:3:8:48' | gen_movstrXr) > moveDI45x.asm (do_file '"movstrDI44x.s"'; echo 'DI:4:8:48' | gen_movstrXr) > moveDI44x.asm (do_file '"movstrDI43x.s"'; echo 'DI:5:8:48' | gen_movstrXr) > moveDI43x.asm (do_file '"movstrDI42x.s"'; echo 'DI:6:8:48' | gen_movstrXr) > moveDI42x.asm (do_file '"movstrDI41x.s"'; echo 'DI:7:8:48' | gen_movstrXr) > moveDI41x.asm (do_file '"movstrSI47x.s"'; echo 'SI:1:4:48' | gen_movstrXr) > moveSI47x.asm (do_file '"movstrSI46x.s"'; echo 'SI:2:4:48' | gen_movstrXr) > moveSI46x.asm (do_file '"movstrSI45x.s"'; echo 'SI:3:4:48' | gen_movstrXr) > moveSI45x.asm (do_file '"movstrHI15x.s"'; echo 'HI:1:2:16' | gen_movstrXr) > moveHI15x.asm gcc-2.5.8/config/m88k/m88k.c100444 22011 13 254167 5467075242 14044 0ustar kenneruser/* Subroutines for insn-output.c for Motorola 88000. Copyright (C) 1988, 1989, 1990, 1991 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@mcc.com) Enhanced by Michael Meissner (meissner@osf.org) Version 2 port by Tom Wood (Tom_Wood@NeXT.com) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include #include #include #include "assert.h" #include "config.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "output.h" #include "insn-attr.h" #include "tree.h" #include "c-tree.h" #include "expr.h" #include "flags.h" extern char *version_string; extern time_t time (); extern char *ctime (); extern int flag_traditional; extern FILE *asm_out_file; static char out_sccs_id[] = "@(#)m88k.c 2.3.3.2 12/16/92 08:26:06"; static char tm_sccs_id [] = TM_SCCS_ID; char *m88k_pound_sign = ""; /* Either # for SVR4 or empty for SVR3 */ char *m88k_short_data; char *m88k_version; char m88k_volatile_code; int m88k_gp_threshold; int m88k_prologue_done = 0; /* Ln directives can now be emitted */ int m88k_function_number = 0; /* Counter unique to each function */ int m88k_fp_offset = 0; /* offset of frame pointer if used */ int m88k_stack_size = 0; /* size of allocated stack (including frame) */ int m88k_case_index; int m88k_version_0300; /* Version is at least 03.00 */ rtx m88k_compare_reg; /* cmp output pseudo register */ rtx m88k_compare_op0; /* cmpsi operand 0 */ rtx m88k_compare_op1; /* cmpsi operand 1 */ enum attr_cpu m88k_cpu; /* target cpu */ /* Determine what instructions are needed to manufacture the integer VALUE in the given MODE. */ enum m88k_instruction classify_integer (mode, value) enum machine_mode mode; register int value; { register int mask; if (value == 0) return m88k_zero; else if (SMALL_INTVAL (value)) return m88k_or; else if (SMALL_INTVAL (-value)) return m88k_subu; else if (mode == HImode) return m88k_or_lo16; else if (mode == QImode) return m88k_or_lo8; else if ((value & 0xffff) == 0) return m88k_oru_hi16; else if (integer_ok_for_set (value)) return m88k_set; else return m88k_oru_or; } /* Return the bit number in a compare word corresponding to CONDITION. */ int condition_value (condition) rtx condition; { switch (GET_CODE (condition)) { case EQ: return 2; case NE: return 3; case GT: return 4; case LE: return 5; case LT: return 6; case GE: return 7; case GTU: return 8; case LEU: return 9; case LTU: return 10; case GEU: return 11; default: abort (); } } int integer_ok_for_set (value) register unsigned value; { /* All the "one" bits must be contiguous. If so, MASK + 1 will be a power of two or zero. */ register unsigned mask = (value | (value - 1)); return (value && POWER_OF_2_or_0 (mask + 1)); } char * output_load_const_int (mode, operands) enum machine_mode mode; rtx *operands; { static char *patterns[] = { "or %0,%#r0,0", "or %0,%#r0,%1", "subu %0,%#r0,%n1", "or %0,%#r0,%h1", "or %0,%#r0,%q1", "set %0,%#r0,%s1", "or.u %0,%#r0,%X1", "or.u %0,%#r0,%X1\n\tor %0,%0,%x1", }; if (! REG_P (operands[0]) || GET_CODE (operands[1]) != CONST_INT) abort (); return patterns[classify_integer (mode, INTVAL (operands[1]))]; } /* These next two routines assume that floating point numbers are represented in a manner which is consistent between host and target machines. */ char * output_load_const_float (operands) rtx *operands; { /* These can return 0 under some circumstances when cross-compiling. */ operands[0] = operand_subword (operands[0], 0, 0, SFmode); operands[1] = operand_subword (operands[1], 0, 0, SFmode); return output_load_const_int (SImode, operands); } char * output_load_const_double (operands) rtx *operands; { rtx latehalf[2]; /* These can return zero on some cross-compilers, but there's nothing we can do about it. */ latehalf[0] = operand_subword (operands[0], 1, 0, DFmode); latehalf[1] = operand_subword (operands[1], 1, 0, DFmode); operands[0] = operand_subword (operands[0], 0, 0, DFmode); operands[1] = operand_subword (operands[1], 0, 0, DFmode); output_asm_insn (output_load_const_int (SImode, operands), operands); operands[0] = latehalf[0]; operands[1] = latehalf[1]; return output_load_const_int (SImode, operands); } char * output_load_const_dimode (operands) rtx *operands; { rtx latehalf[2]; latehalf[0] = operand_subword (operands[0], 1, 0, DImode); latehalf[1] = operand_subword (operands[1], 1, 0, DImode); operands[0] = operand_subword (operands[0], 0, 0, DImode); operands[1] = operand_subword (operands[1], 0, 0, DImode); output_asm_insn (output_load_const_int (SImode, operands), operands); operands[0] = latehalf[0]; operands[1] = latehalf[1]; return output_load_const_int (SImode, operands); } /* Emit insns to move operands[1] into operands[0]. Return 1 if we have written out everything that needs to be done to do the move. Otherwise, return 0 and the caller will emit the move normally. SCRATCH if non zero can be used as a scratch register for the move operation. It is provided by a SECONDARY_RELOAD_* macro if needed. */ int emit_move_sequence (operands, mode, scratch) rtx *operands; enum machine_mode mode; rtx scratch; { register rtx operand0 = operands[0]; register rtx operand1 = operands[1]; /* Handle most common case first: storing into a register. */ if (register_operand (operand0, mode)) { if (register_operand (operand1, mode) || (GET_CODE (operand1) == CONST_INT && SMALL_INT (operand1)) || GET_CODE (operand1) == HIGH /* Only `general_operands' can come here, so MEM is ok. */ || GET_CODE (operand1) == MEM) { /* Run this case quickly. */ emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1)); return 1; } } else if (GET_CODE (operand0) == MEM) { if (register_operand (operand1, mode) || (operand1 == const0_rtx && GET_MODE_SIZE (mode) <= UNITS_PER_WORD)) { /* Run this case quickly. */ emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1)); return 1; } if (! reload_in_progress && ! reload_completed) { operands[0] = validize_mem (operand0); operands[1] = operand1 = force_reg (mode, operand1); } } /* Simplify the source if we need to. */ if (GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) { if (GET_CODE (operand1) != CONST_INT && GET_CODE (operand1) != CONST_DOUBLE) { rtx temp = ((reload_in_progress || reload_completed) ? operand0 : 0); operands[1] = legitimize_address (flag_pic && symbolic_address_p (operand1), operand1, temp, scratch); if (mode != SImode) operands[1] = gen_rtx (SUBREG, mode, operands[1], 0); } } /* Now have insn-emit do whatever it normally does. */ return 0; } /* Return a legitimate reference for ORIG (either an address or a MEM) using the register REG. If PIC and the address is already position-independent, use ORIG. Newly generated position-independent addresses go into a reg. This is REG if non zero, otherwise we allocate register(s) as necessary. If this is called during reload, and we need a second temp register, then we use SCRATCH, which is provided via the SECONDARY_INPUT_RELOAD_CLASS mechanism. */ struct rtx_def * legitimize_address (pic, orig, reg, scratch) int pic; rtx orig; rtx reg; rtx scratch; { rtx addr = (GET_CODE (orig) == MEM ? XEXP (orig, 0) : orig); rtx new = orig; rtx temp, insn; if (pic) { if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF) { if (reg == 0) { if (reload_in_progress || reload_completed) abort (); else reg = gen_reg_rtx (Pmode); } if (flag_pic == 2) { /* If not during reload, allocate another temp reg here for loading in the address, so that these instructions can be optimized properly. */ temp = ((reload_in_progress || reload_completed) ? reg : gen_reg_rtx (Pmode)); emit_insn (gen_rtx (SET, VOIDmode, temp, gen_rtx (HIGH, SImode, addr))); emit_insn (gen_rtx (SET, VOIDmode, temp, gen_rtx (LO_SUM, SImode, temp, addr))); addr = temp; } new = gen_rtx (MEM, Pmode, gen_rtx (PLUS, SImode, pic_offset_table_rtx, addr)); current_function_uses_pic_offset_table = 1; RTX_UNCHANGING_P (new) = 1; insn = emit_move_insn (reg, new); /* Put a REG_EQUAL note on this insn, so that it can be optimized by loop. */ REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, orig, REG_NOTES (insn)); new = reg; } else if (GET_CODE (addr) == CONST) { rtx base, offset; if (GET_CODE (XEXP (addr, 0)) == PLUS && XEXP (XEXP (addr, 0), 0) == pic_offset_table_rtx) return orig; if (reg == 0) { if (reload_in_progress || reload_completed) abort (); else reg = gen_reg_rtx (Pmode); } if (GET_CODE (XEXP (addr, 0)) != PLUS) abort (); base = legitimize_address (1, XEXP (XEXP (addr, 0), 0), reg, 0); addr = legitimize_address (1, XEXP (XEXP (addr, 0), 1), base == reg ? 0 : reg, 0); if (GET_CODE (addr) == CONST_INT) { if (SMALL_INT (addr)) return plus_constant_for_output (base, INTVAL (addr)); else if (! reload_in_progress && ! reload_completed) addr = force_reg (Pmode, addr); /* We can't create any new registers during reload, so use the SCRATCH reg provided by the reload_insi pattern. */ else if (scratch) { emit_move_insn (scratch, addr); addr = scratch; } else /* If we reach here, then the SECONDARY_INPUT_RELOAD_CLASS macro needs to be adjusted so that a scratch reg is provided for this address. */ abort (); } new = gen_rtx (PLUS, SImode, base, addr); /* Should we set special REG_NOTEs here? */ } } else if (! SHORT_ADDRESS_P (addr, temp)) { if (reg == 0) { if (reload_in_progress || reload_completed) abort (); else reg = gen_reg_rtx (Pmode); } emit_insn (gen_rtx (SET, VOIDmode, reg, gen_rtx (HIGH, SImode, addr))); new = gen_rtx (LO_SUM, SImode, reg, addr); } if (new != orig && GET_CODE (orig) == MEM) { new = gen_rtx (MEM, GET_MODE (orig), new); RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (orig); MEM_VOLATILE_P (new) = MEM_VOLATILE_P (orig); MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (orig); } return new; } /* Support functions for code to emit a block move. There are four methods used to perform the block move: + call memcpy + call the looping library function, e.g. __movstrSI64n8 + call a non-looping library function, e.g. __movstrHI15x11 + produce an inline sequence of ld/st instructions The parameters below describe the library functions produced by movstr-m88k.sh. */ #define MOVSTR_LOOP 64 /* __movstrSI64n68 .. __movstrSI64n8 */ #define MOVSTR_QI 16 /* __movstrQI16x16 .. __movstrQI16x2 */ #define MOVSTR_HI 48 /* __movstrHI48x48 .. __movstrHI48x4 */ #define MOVSTR_SI 96 /* __movstrSI96x96 .. __movstrSI96x8 */ #define MOVSTR_DI 96 /* __movstrDI96x96 .. __movstrDI96x16 */ #define MOVSTR_ODD_HI 16 /* __movstrHI15x15 .. __movstrHI15x5 */ #define MOVSTR_ODD_SI 48 /* __movstrSI47x47 .. __movstrSI47x11, __movstrSI46x46 .. __movstrSI46x10, __movstrSI45x45 .. __movstrSI45x9 */ #define MOVSTR_ODD_DI 48 /* __movstrDI47x47 .. __movstrDI47x23, __movstrDI46x46 .. __movstrDI46x22, __movstrDI45x45 .. __movstrDI45x21, __movstrDI44x44 .. __movstrDI44x20, __movstrDI43x43 .. __movstrDI43x19, __movstrDI42x42 .. __movstrDI42x18, __movstrDI41x41 .. __movstrDI41x17 */ /* Limits for using the non-looping movstr functions. For the m88100 processor, we assume the source and destination are word aligned. The QImode and HImode limits are the break even points where memcpy does just as well and beyond which memcpy does better. For the m88110, we tend to assume double word alignment, but also analyze the word aligned cases. The analysis is complicated because memcpy may use the cache control instructions for better performance. */ #define MOVSTR_QI_LIMIT_88100 13 #define MOVSTR_HI_LIMIT_88100 38 #define MOVSTR_SI_LIMIT_88100 MOVSTR_SI #define MOVSTR_DI_LIMIT_88100 MOVSTR_SI #define MOVSTR_QI_LIMIT_88000 16 #define MOVSTR_HI_LIMIT_88000 38 #define MOVSTR_SI_LIMIT_88000 72 #define MOVSTR_DI_LIMIT_88000 72 #define MOVSTR_QI_LIMIT_88110 16 #define MOVSTR_HI_LIMIT_88110 38 #define MOVSTR_SI_LIMIT_88110 72 #define MOVSTR_DI_LIMIT_88110 72 static enum machine_mode mode_from_align[] = {VOIDmode, QImode, HImode, VOIDmode, SImode, VOIDmode, VOIDmode, VOIDmode, DImode}; static int max_from_align[] = {0, MOVSTR_QI, MOVSTR_HI, 0, MOVSTR_SI, 0, 0, 0, MOVSTR_DI}; static int all_from_align[] = {0, MOVSTR_QI, MOVSTR_ODD_HI, 0, MOVSTR_ODD_SI, 0, 0, 0, MOVSTR_ODD_DI}; static int best_from_align[3][9] = {0, MOVSTR_QI_LIMIT_88100, MOVSTR_HI_LIMIT_88100, 0, MOVSTR_SI_LIMIT_88100, 0, 0, 0, MOVSTR_DI_LIMIT_88100, 0, MOVSTR_QI_LIMIT_88110, MOVSTR_HI_LIMIT_88110, 0, MOVSTR_SI_LIMIT_88110, 0, 0, 0, MOVSTR_DI_LIMIT_88110, 0, MOVSTR_QI_LIMIT_88000, MOVSTR_HI_LIMIT_88000, 0, MOVSTR_SI_LIMIT_88000, 0, 0, 0, MOVSTR_DI_LIMIT_88000}; static void block_move_loop (); static void block_move_no_loop (); static void block_move_sequence (); /* Emit code to perform a block move. Choose the best method. OPERANDS[0] is the destination. OPERANDS[1] is the source. OPERANDS[2] is the size. OPERANDS[3] is the alignment safe to use. */ void expand_block_move (dest_mem, src_mem, operands) rtx dest_mem; rtx src_mem; rtx *operands; { int align = INTVAL (operands[3]); int constp = (GET_CODE (operands[2]) == CONST_INT); int bytes = (constp ? INTVAL (operands[2]) : 0); int target = (int) m88k_cpu; assert (CPU_M88100 == 0); assert (CPU_M88110 == 1); assert (CPU_M88000 == 2); if (constp && bytes <= 0) return; /* Determine machine mode to do move with. */ if (align > 4 && !TARGET_88110) align = 4; else if (align <= 0 || align == 3) abort (); /* block move invalid alignment. */ if (constp && bytes <= 3 * align) block_move_sequence (operands[0], dest_mem, operands[1], src_mem, bytes, align, 0); else if (constp && bytes <= best_from_align[target][align]) block_move_no_loop (operands[0], dest_mem, operands[1], src_mem, bytes, align); else if (constp && align == 4 && TARGET_88100) block_move_loop (operands[0], dest_mem, operands[1], src_mem, bytes, align); else { #ifdef TARGET_MEM_FUNCTIONS emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0, VOIDmode, 3, operands[0], Pmode, operands[1], Pmode, operands[2], SImode); #else emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0, VOIDmode, 3, operands[1], Pmode, operands[0], Pmode, operands[2], SImode); #endif } } /* Emit code to perform a block move by calling a looping movstr library function. SIZE and ALIGN are known constants. DEST and SRC are registers. */ static void block_move_loop (dest, dest_mem, src, src_mem, size, align) rtx dest, dest_mem; rtx src, src_mem; int size; int align; { enum machine_mode mode; int count; int units; int remainder; rtx offset_rtx; rtx value_rtx; char entry[30]; tree entry_name; /* Determine machine mode to do move with. */ if (align != 4) abort (); /* Determine the structure of the loop. */ count = size / MOVSTR_LOOP; units = (size - count * MOVSTR_LOOP) / align; if (units < 2) { count--; units += MOVSTR_LOOP / align; } if (count <= 0) { block_move_no_loop (dest, dest_mem, src, src_mem, size, align); return; } remainder = size - count * MOVSTR_LOOP - units * align; mode = mode_from_align[align]; sprintf (entry, "__movstr%s%dn%d", GET_MODE_NAME (mode), MOVSTR_LOOP, units * align); entry_name = get_identifier (entry); offset_rtx = gen_rtx (CONST_INT, VOIDmode, MOVSTR_LOOP + (1 - units) * align); value_rtx = gen_rtx (MEM, MEM_IN_STRUCT_P (src_mem) ? mode : BLKmode, gen_rtx (PLUS, Pmode, gen_rtx (REG, Pmode, 3), offset_rtx)); RTX_UNCHANGING_P (value_rtx) = RTX_UNCHANGING_P (src_mem); MEM_VOLATILE_P (value_rtx) = MEM_VOLATILE_P (src_mem); MEM_IN_STRUCT_P (value_rtx) = 1; emit_insn (gen_call_movstrsi_loop (gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (entry_name)), dest, src, offset_rtx, value_rtx, gen_rtx (REG, mode, ((units & 1) ? 4 : 5)), gen_rtx (CONST_INT, VOIDmode, count))); if (remainder) block_move_sequence (gen_rtx (REG, Pmode, 2), dest_mem, gen_rtx (REG, Pmode, 3), src_mem, remainder, align, MOVSTR_LOOP + align); } /* Emit code to perform a block move by calling a non-looping library function. SIZE and ALIGN are known constants. DEST and SRC are registers. OFFSET is the known starting point for the output pattern. */ static void block_move_no_loop (dest, dest_mem, src, src_mem, size, align) rtx dest, dest_mem; rtx src, src_mem; int size; int align; { enum machine_mode mode = mode_from_align[align]; int units = size / align; int remainder = size - units * align; int most; int value_reg; rtx offset_rtx; rtx value_rtx; char entry[30]; tree entry_name; if (remainder && size <= all_from_align[align]) { most = all_from_align[align] - (align - remainder); remainder = 0; } else { most = max_from_align[align]; } sprintf (entry, "__movstr%s%dx%d", GET_MODE_NAME (mode), most, size - remainder); entry_name = get_identifier (entry); offset_rtx = gen_rtx (CONST_INT, VOIDmode, most - (size - remainder)); value_rtx = gen_rtx (MEM, MEM_IN_STRUCT_P (src_mem) ? mode : BLKmode, gen_rtx (PLUS, Pmode, gen_rtx (REG, Pmode, 3), offset_rtx)); RTX_UNCHANGING_P (value_rtx) = RTX_UNCHANGING_P (src_mem); MEM_VOLATILE_P (value_rtx) = MEM_VOLATILE_P (src_mem); MEM_IN_STRUCT_P (value_rtx) = 1; value_reg = ((((most - (size - remainder)) / align) & 1) == 0 ? (align == 8 ? 6 : 5) : 4); emit_insn (gen_call_block_move (gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (entry_name)), dest, src, offset_rtx, value_rtx, gen_rtx (REG, mode, value_reg))); if (remainder) block_move_sequence (gen_rtx (REG, Pmode, 2), dest_mem, gen_rtx (REG, Pmode, 3), src_mem, remainder, align, most); } /* Emit code to perform a block move with an offset sequence of ld/st instructions (..., ld 0, st 1, ld 1, st 0, ...). SIZE and ALIGN are known constants. DEST and SRC are registers. OFFSET is the known starting point for the output pattern. */ static void block_move_sequence (dest, dest_mem, src, src_mem, size, align, offset) rtx dest, dest_mem; rtx src, src_mem; int size; int align; int offset; { rtx temp[2]; enum machine_mode mode[2]; int amount[2]; int active[2]; int phase = 0; int next; int offset_ld = offset; int offset_st = offset; active[0] = active[1] = FALSE; /* Establish parameters for the first load and for the second load if it is known to be the same mode as the first. */ amount[0] = amount[1] = align; mode[0] = mode_from_align[align]; temp[0] = gen_reg_rtx (mode[0]); if (size >= 2 * align) { mode[1] = mode[0]; temp[1] = gen_reg_rtx (mode[1]); } do { rtx srcp, dstp; next = phase; phase = !phase; if (size > 0) { /* Change modes as the sequence tails off. */ if (size < amount[next]) { amount[next] = (size >= 4 ? 4 : (size >= 2 ? 2 : 1)); mode[next] = mode_from_align[amount[next]]; temp[next] = gen_reg_rtx (mode[next]); } size -= amount[next]; srcp = gen_rtx (MEM, MEM_IN_STRUCT_P (src_mem) ? mode[next] : BLKmode, gen_rtx (PLUS, Pmode, src, gen_rtx (CONST_INT, SImode, offset_ld))); RTX_UNCHANGING_P (srcp) = RTX_UNCHANGING_P (src_mem); MEM_VOLATILE_P (srcp) = MEM_VOLATILE_P (src_mem); MEM_IN_STRUCT_P (srcp) = 1; emit_insn (gen_rtx (SET, VOIDmode, temp[next], srcp)); offset_ld += amount[next]; active[next] = TRUE; } if (active[phase]) { active[phase] = FALSE; dstp = gen_rtx (MEM, MEM_IN_STRUCT_P (dest_mem) ? mode[phase] : BLKmode, gen_rtx (PLUS, Pmode, dest, gen_rtx (CONST_INT, SImode, offset_st))); RTX_UNCHANGING_P (dstp) = RTX_UNCHANGING_P (dest_mem); MEM_VOLATILE_P (dstp) = MEM_VOLATILE_P (dest_mem); MEM_IN_STRUCT_P (dstp) = 1; emit_insn (gen_rtx (SET, VOIDmode, dstp, temp[phase])); offset_st += amount[phase]; } } while (active[next]); } /* Emit the code to do an AND operation. */ char * output_and (operands) rtx operands[]; { unsigned int value; if (REG_P (operands[2])) return "and %0,%1,%2"; value = INTVAL (operands[2]); if (SMALL_INTVAL (value)) return "mask %0,%1,%2"; else if ((value & 0xffff0000) == 0xffff0000) return "and %0,%1,%x2"; else if ((value & 0xffff) == 0xffff) return "and.u %0,%1,%X2"; else if ((value & 0xffff) == 0) return "mask.u %0,%1,%X2"; else if (integer_ok_for_set (~value)) return "clr %0,%1,%S2"; else return "and.u %0,%1,%X2\n\tand %0,%0,%x2"; } /* Emit the code to do an inclusive OR operation. */ char * output_ior (operands) rtx operands[]; { unsigned int value; if (REG_P (operands[2])) return "or %0,%1,%2"; value = INTVAL (operands[2]); if (SMALL_INTVAL (value)) return "or %0,%1,%2"; else if ((value & 0xffff) == 0) return "or.u %0,%1,%X2"; else if (integer_ok_for_set (value)) return "set %0,%1,%s2"; else return "or.u %0,%1,%X2\n\tor %0,%0,%x2"; } /* Emit the instructions for doing an XOR. */ char * output_xor (operands) rtx operands[]; { unsigned int value; if (REG_P (operands[2])) return "xor %0,%1,%2"; value = INTVAL (operands[2]); if (SMALL_INTVAL (value)) return "xor %0,%1,%2"; else if ((value & 0xffff) == 0) return "xor.u %0,%1,%X2"; else return "xor.u %0,%1,%X2\n\txor %0,%0,%x2"; } /* Output a call. Normally this is just bsr or jsr, but this also deals with accomplishing a branch after the call by incrementing r1. This requires that various assembler bugs be accommodated. The 4.30 DG/UX assembler requires that forward references not occur when computing the difference of two labels. The [version?] Motorola assembler computes a word difference. No doubt there's more to come! It would seem the same idea could be used to tail call, but in this case, the epilogue will be non-null. */ static rtx sb_name = 0; static rtx sb_high = 0; static rtx sb_low = 0; char * output_call (operands, addr) rtx operands[]; rtx addr; { operands[0] = addr; if (final_sequence) { rtx jump; rtx seq_insn; /* This can be generalized, but there is currently no need. */ if (XVECLEN (final_sequence, 0) != 2) abort (); /* The address of interior insns is not computed, so use the sequence. */ seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); jump = XVECEXP (final_sequence, 0, 1); if (GET_CODE (jump) == JUMP_INSN) { rtx low, high; char *last; rtx dest = XEXP (SET_SRC (PATTERN (jump)), 0); int delta = 4 * (insn_addresses[INSN_UID (dest)] - insn_addresses[INSN_UID (seq_insn)] - 2); #if (MONITOR_GCC & 0x2) /* How often do long branches happen? */ if ((unsigned) (delta + 0x8000) >= 0x10000) warning ("Internal gcc monitor: short-branch(%x)", delta); #endif /* Delete the jump. */ PUT_CODE (jump, NOTE); NOTE_LINE_NUMBER (jump) = NOTE_INSN_DELETED; NOTE_SOURCE_FILE (jump) = 0; /* We only do this optimization if -O2, modifying the value of r1 in the delay slot confuses debuggers and profilers on some systems. If we loose, we must use the non-delay form. This is unlikely to ever happen. If it becomes a problem, claim that a call has two delay slots and only the second can be filled with a jump. The 88110 can lose when a jsr.n r1 is issued and a page fault occurs accessing the delay slot. So don't use jsr.n form when jumping thru r1. */ #ifdef AS_BUG_IMMEDIATE_LABEL /* The assembler restricts immediate values. */ if (optimize < 2 || ! ADD_INTVAL (delta * 2) #else if (optimize < 2 || ! ADD_INTVAL (delta) #endif || (REG_P (addr) && REGNO (addr) == 1)) { operands[1] = dest; return (REG_P (addr) ? "jsr %0\n\tbr %l1" : (flag_pic ? "bsr %0#plt\n\tbr %l1" : "bsr %0\n\tbr %l1")); } /* Output the short branch form. */ output_asm_insn ((REG_P (addr) ? "jsr.n %0" : (flag_pic ? "bsr.n %0#plt" : "bsr.n %0")), operands); #ifdef USE_GAS last = (delta < 0 ? "subu %#r1,%#r1,.-%l0+4" : "addu %#r1,%#r1,%l0-.-4"); operands[0] = dest; #else operands[0] = gen_label_rtx (); operands[1] = gen_label_rtx (); if (delta < 0) { low = dest; high = operands[1]; last = "subu %#r1,%#r1,%l0\n%l1:"; } else { low = operands[1]; high = dest; last = "addu %#r1,%#r1,%l0\n%l1:"; } /* Record the values to be computed later as "def name,high-low". */ sb_name = gen_rtx (EXPR_LIST, VOIDmode, operands[0], sb_name); sb_high = gen_rtx (EXPR_LIST, VOIDmode, high, sb_high); sb_low = gen_rtx (EXPR_LIST, VOIDmode, low, sb_low); #endif /* Don't USE_GAS */ return last; } } return (REG_P (addr) ? "jsr%. %0" : (flag_pic ? "bsr%. %0#plt" : "bsr%. %0")); } static void output_short_branch_defs (stream) FILE *stream; { char name[256], high[256], low[256]; for (; sb_name && sb_high && sb_low; sb_name = XEXP (sb_name, 1), sb_high = XEXP (sb_high, 1), sb_low = XEXP (sb_low, 1)) { ASM_GENERATE_INTERNAL_LABEL (name, "L", CODE_LABEL_NUMBER (XEXP (sb_name, 0))); ASM_GENERATE_INTERNAL_LABEL (high, "L", CODE_LABEL_NUMBER (XEXP (sb_high, 0))); ASM_GENERATE_INTERNAL_LABEL (low, "L", CODE_LABEL_NUMBER (XEXP (sb_low, 0))); /* This will change as the assembler requirements become known. */ fprintf (stream, "\t%s\t %s,%s-%s\n", SET_ASM_OP, &name[1], &high[1], &low[1]); } if (sb_name || sb_high || sb_low) abort (); } /* Return truth value of the statement that this conditional branch is likely to fall through. CONDITION, is the condition that JUMP_INSN is testing. */ int mostly_false_jump (jump_insn, condition) rtx jump_insn, condition; { rtx target_label = JUMP_LABEL (jump_insn); rtx insnt, insnj; /* Much of this isn't computed unless we're optimizing. */ if (optimize == 0) return 0; /* Determine if one path or the other leads to a return. */ for (insnt = NEXT_INSN (target_label); insnt; insnt = NEXT_INSN (insnt)) { if (GET_CODE (insnt) == JUMP_INSN) break; else if (GET_CODE (insnt) == INSN && GET_CODE (PATTERN (insnt)) == SEQUENCE && GET_CODE (XVECEXP (PATTERN (insnt), 0, 0)) == JUMP_INSN) { insnt = XVECEXP (PATTERN (insnt), 0, 0); break; } } if (insnt && (GET_CODE (PATTERN (insnt)) == RETURN || (GET_CODE (PATTERN (insnt)) == SET && GET_CODE (SET_SRC (PATTERN (insnt))) == REG && REGNO (SET_SRC (PATTERN (insnt))) == 1))) insnt = 0; for (insnj = NEXT_INSN (jump_insn); insnj; insnj = NEXT_INSN (insnj)) { if (GET_CODE (insnj) == JUMP_INSN) break; else if (GET_CODE (insnj) == INSN && GET_CODE (PATTERN (insnj)) == SEQUENCE && GET_CODE (XVECEXP (PATTERN (insnj), 0, 0)) == JUMP_INSN) { insnj = XVECEXP (PATTERN (insnj), 0, 0); break; } } if (insnj && (GET_CODE (PATTERN (insnj)) == RETURN || (GET_CODE (PATTERN (insnj)) == SET && GET_CODE (SET_SRC (PATTERN (insnj))) == REG && REGNO (SET_SRC (PATTERN (insnj))) == 1))) insnj = 0; /* Predict to not return. */ if ((insnt == 0) != (insnj == 0)) return (insnt == 0); /* Predict loops to loop. */ for (insnt = PREV_INSN (target_label); insnt && GET_CODE (insnt) == NOTE; insnt = PREV_INSN (insnt)) if (NOTE_LINE_NUMBER (insnt) == NOTE_INSN_LOOP_END) return 1; else if (NOTE_LINE_NUMBER (insnt) == NOTE_INSN_LOOP_BEG) return 0; else if (NOTE_LINE_NUMBER (insnt) == NOTE_INSN_LOOP_CONT) return 0; /* Predict backward branches usually take. */ if (final_sequence) insnj = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); else insnj = jump_insn; if (insn_addresses[INSN_UID (insnj)] > insn_addresses[INSN_UID (target_label)]) return 0; /* EQ tests are usually false and NE tests are usually true. Also, most quantities are positive, so we can make the appropriate guesses about signed comparisons against zero. Consider unsigned comparisons to be a range check and assume quantities to be in range. */ switch (GET_CODE (condition)) { case CONST_INT: /* Unconditional branch. */ return 0; case EQ: return 1; case NE: return 0; case LE: case LT: case GEU: case GTU: /* Must get casesi right at least. */ if (XEXP (condition, 1) == const0_rtx) return 1; break; case GE: case GT: case LEU: case LTU: if (XEXP (condition, 1) == const0_rtx) return 0; break; } return 0; } /* Return true if the operand is a power of two and is a floating point type (to optimize division by power of two into multiplication). */ int real_power_of_2_operand (op, mode) rtx op; enum machine_mode mode; { union { REAL_VALUE_TYPE d; int i[sizeof (REAL_VALUE_TYPE) / sizeof (int)]; struct { /* IEEE double precision format */ unsigned sign : 1; unsigned exponent : 11; unsigned mantissa1 : 20; unsigned mantissa2; } s; struct { /* IEEE double format to quick check */ unsigned sign : 1; /* if it fits in a float */ unsigned exponent1 : 4; unsigned exponent2 : 7; unsigned mantissa1 : 20; unsigned mantissa2; } s2; } u; if (GET_MODE (op) != DFmode && GET_MODE (op) != SFmode) return 0; if (GET_CODE (op) != CONST_DOUBLE) return 0; u.i[0] = CONST_DOUBLE_LOW (op); u.i[1] = CONST_DOUBLE_HIGH (op); if (u.s.mantissa1 != 0 || u.s.mantissa2 != 0 /* not a power of two */ || u.s.exponent == 0 /* constant 0.0 */ || u.s.exponent == 0x7ff /* NAN */ || (u.s2.exponent1 != 0x8 && u.s2.exponent1 != 0x7)) return 0; /* const won't fit in float */ return 1; } /* Make OP legitimate for mode MODE. Currently this only deals with DFmode operands, putting them in registers and making CONST_DOUBLE values SFmode where possible. */ struct rtx_def * legitimize_operand (op, mode) rtx op; enum machine_mode mode; { rtx temp; union { union real_extract r; struct { /* IEEE double precision format */ unsigned sign : 1; unsigned exponent : 11; unsigned mantissa1 : 20; unsigned mantissa2; } d; struct { /* IEEE double format to quick check */ unsigned sign : 1; /* if it fits in a float */ unsigned exponent1 : 4; unsigned exponent2 : 7; unsigned mantissa1 : 20; unsigned mantissa2; } s; } u; if (GET_CODE (op) == REG || mode != DFmode) return op; if (GET_CODE (op) == CONST_DOUBLE) { bcopy (&CONST_DOUBLE_LOW (op), &u.r, sizeof u); if (u.d.exponent != 0x7ff /* NaN */ && u.d.mantissa2 == 0 /* Mantissa fits */ && (u.s.exponent1 == 0x8 || u.s.exponent1 == 0x7) /* Exponent fits */ && (temp = simplify_unary_operation (FLOAT_TRUNCATE, SFmode, op, mode)) != 0) return gen_rtx (FLOAT_EXTEND, mode, force_reg (SFmode, temp)); } else if (register_operand (op, mode)) return op; return force_reg (mode, op); } /* Return true if OP is a suitable input for a move insn. */ int move_operand (op, mode) rtx op; enum machine_mode mode; { if (register_operand (op, mode)) return 1; if (GET_CODE (op) == CONST_INT) return (classify_integer (mode, INTVAL (op)) < m88k_oru_hi16); if (GET_MODE (op) != mode) return 0; if (GET_CODE (op) == SUBREG) op = SUBREG_REG (op); if (GET_CODE (op) != MEM) return 0; op = XEXP (op, 0); if (GET_CODE (op) == LO_SUM) return (REG_P (XEXP (op, 0)) && symbolic_address_p (XEXP (op, 1))); return memory_address_p (mode, op); } /* Return true if OP is suitable for a call insn. */ int call_address_operand (op, mode) rtx op; enum machine_mode mode; { return (REG_P (op) || symbolic_address_p (op)); } /* Returns true if OP is either a symbol reference or a sum of a symbol reference and a constant. */ int symbolic_address_p (op) register rtx op; { switch (GET_CODE (op)) { case SYMBOL_REF: case LABEL_REF: return 1; case CONST: op = XEXP (op, 0); return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF || GET_CODE (XEXP (op, 0)) == LABEL_REF) && GET_CODE (XEXP (op, 1)) == CONST_INT); default: return 0; } } /* Return true if OP is a register or const0_rtx. */ int reg_or_0_operand (op, mode) rtx op; enum machine_mode mode; { return (op == const0_rtx || register_operand (op, mode)); } /* Nonzero if OP is a valid second operand for an arithmetic insn. */ int arith_operand (op, mode) rtx op; enum machine_mode mode; { return (register_operand (op, mode) || (GET_CODE (op) == CONST_INT && SMALL_INT (op))); } /* Return true if OP is a register or 5 bit integer. */ int arith5_operand (op, mode) rtx op; enum machine_mode mode; { return (register_operand (op, mode) || (GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 32)); } int arith32_operand (op, mode) rtx op; enum machine_mode mode; { return (register_operand (op, mode) || GET_CODE (op) == CONST_INT); } int arith64_operand (op, mode) rtx op; enum machine_mode mode; { return (register_operand (op, mode) || GET_CODE (op) == CONST_INT || (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DImode)); } int int5_operand (op, mode) rtx op; enum machine_mode mode; { return (GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 32); } int int32_operand (op, mode) rtx op; enum machine_mode mode; { return (GET_CODE (op) == CONST_INT); } /* Return true if OP is a register or a valid immediate operand for addu or subu. */ int add_operand (op, mode) rtx op; enum machine_mode mode; { return (register_operand (op, mode) || (GET_CODE (op) == CONST_INT && ADD_INT (op))); } /* Nonzero if this is a bitmask filling the bottom bits, for optimizing and + shift left combinations into a single mak instruction. */ int mak_mask_p (value) int value; { return (value && POWER_OF_2_or_0 (value + 1)); } int reg_or_bbx_mask_operand (op, mode) rtx op; enum machine_mode mode; { int value; if (register_operand (op, mode)) return 1; if (GET_CODE (op) != CONST_INT) return 0; value = INTVAL (op); if (POWER_OF_2 (value)) return 1; return 0; } /* Return true if OP is valid to use in the context of a floating point operation. Special case 0.0, since we can use r0. */ int real_or_0_operand (op, mode) rtx op; enum machine_mode mode; { if (mode != SFmode && mode != DFmode) return 0; return (register_operand (op, mode) || (GET_CODE (op) == CONST_DOUBLE && op == CONST0_RTX (mode))); } /* Return true if OP is valid to use in the context of logic aritmethic on condition codes. */ int partial_ccmode_register_operand (op, mode) rtx op; enum machine_mode mode; { return register_operand (op, CCmode) || register_operand (op, CCEVENmode); } /* Return true if OP is a relational operator. */ int relop (op, mode) rtx op; enum machine_mode mode; { switch (GET_CODE (op)) { case EQ: case NE: case LT: case LE: case GE: case GT: case LTU: case LEU: case GEU: case GTU: return 1; default: return 0; } } int even_relop (op, mode) rtx op; enum machine_mode mode; { switch (GET_CODE (op)) { case EQ: case LT: case GT: case LTU: case GTU: return 1; default: return 0; } } int odd_relop (op, mode) rtx op; enum machine_mode mode; { switch (GET_CODE (op)) { case NE: case LE: case GE: case LEU: case GEU: return 1; default: return 0; } } /* Return true if OP is a relational operator, and is not an unsigned relational operator. */ int relop_no_unsigned (op, mode) rtx op; enum machine_mode mode; { switch (GET_CODE (op)) { case EQ: case NE: case LT: case LE: case GE: case GT: /* @@ What is this test doing? Why not use `mode'? */ if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT || GET_MODE (op) == DImode || GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_FLOAT || GET_MODE (XEXP (op, 0)) == DImode || GET_MODE_CLASS (GET_MODE (XEXP (op, 1))) == MODE_FLOAT || GET_MODE (XEXP (op, 1)) == DImode) return 0; return 1; default: return 0; } } /* Return true if the code of this rtx pattern is EQ or NE. */ int equality_op (op, mode) rtx op; enum machine_mode mode; { return (GET_CODE (op) == EQ || GET_CODE (op) == NE); } /* Return true if the code of this rtx pattern is pc or label_ref. */ int pc_or_label_ref (op, mode) rtx op; enum machine_mode mode; { return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF); } /* Output to FILE the start of the assembler file. */ struct option { char *string; int *variable; int on_value; }; static int output_option (file, sep, type, name, indent, pos, max) FILE *file; char *sep; char *type; char *name; char *indent; int pos; int max; { if (strlen (sep) + strlen (type) + strlen (name) + pos > max) { fprintf (file, indent); return fprintf (file, "%s%s", type, name); } return pos + fprintf (file, "%s%s%s", sep, type, name); } static struct { char *name; int value; } m_options[] = TARGET_SWITCHES; static void output_options (file, f_options, f_len, W_options, W_len, pos, max, sep, indent, term) FILE *file; struct option *f_options; struct option *W_options; int f_len, W_len; int pos; int max; char *indent; char *term; { register int j; if (optimize) pos = output_option (file, sep, "-O", "", indent, pos, max); if (write_symbols != NO_DEBUG) pos = output_option (file, sep, "-g", "", indent, pos, max); if (flag_traditional) pos = output_option (file, sep, "-traditional", "", indent, pos, max); if (profile_flag) pos = output_option (file, sep, "-p", "", indent, pos, max); if (profile_block_flag) pos = output_option (file, sep, "-a", "", indent, pos, max); for (j = 0; j < f_len; j++) if (*f_options[j].variable == f_options[j].on_value) pos = output_option (file, sep, "-f", f_options[j].string, indent, pos, max); for (j = 0; j < W_len; j++) if (*W_options[j].variable == W_options[j].on_value) pos = output_option (file, sep, "-W", W_options[j].string, indent, pos, max); for (j = 0; j < sizeof m_options / sizeof m_options[0]; j++) if (m_options[j].name[0] != '\0' && m_options[j].value > 0 && ((m_options[j].value & target_flags) == m_options[j].value)) pos = output_option (file, sep, "-m", m_options[j].name, indent, pos, max); if (m88k_short_data) pos = output_option (file, sep, "-mshort-data-", m88k_short_data, indent, pos, max); fprintf (file, term); } void output_file_start (file, f_options, f_len, W_options, W_len) FILE *file; struct option *f_options; struct option *W_options; int f_len, W_len; { register int pos; ASM_FIRST_LINE (file); if (TARGET_88110 && m88k_version != 0 && strcmp (m88k_version, "04.00") >= 0) fprintf (file, "\t%s\n", REQUIRES_88110_ASM_OP); output_file_directive (file, main_input_filename); /* Switch to the data section so that the coffsem symbol and the gcc2_compiled. symbol aren't in the text section. */ data_section (); ASM_COFFSEM (file); pos = fprintf (file, "\n; cc1 (%s) arguments:", VERSION_STRING); output_options (file, f_options, f_len, W_options, W_len, pos, 75, " ", "\n; ", "\n\n"); if (TARGET_IDENTIFY_REVISION) { char indent[256]; time_t now = time ((time_t *)0); sprintf (indent, "]\"\n\t%s\t \"@(#)%s [", IDENT_ASM_OP, main_input_filename); fprintf (file, indent+3); pos = fprintf (file, "gcc %s, %.24s,", VERSION_STRING, ctime (&now)); output_options (file, f_options, f_len, W_options, W_len, pos, 150 - strlen (indent), " ", indent, "]\"\n\n"); } } /* Output an ascii string. */ void output_ascii (file, opcode, max, p, size) FILE *file; char *opcode; int max; unsigned char *p; int size; { int i; int in_escape = 0; register int num = 0; fprintf (file, "\t%s\t \"", opcode); for (i = 0; i < size; i++) { register int c = p[i]; if (num > max) { fprintf (file, "\"\n\t%s\t \"", opcode); num = 0; } if (c == '\"' || c == '\\') { escape: putc ('\\', file); putc (c, file); num += 2; in_escape = 0; } else if (in_escape && c >= '0' && c <= '9') { /* If a digit follows an octal-escape, the Vax assembler fails to stop reading the escape after three digits. Continue to output the values as an octal-escape until a non-digit is found. */ fprintf (file, "\\%03o", c); num += 4; } else if (c >= ' ' && c < 0177) { putc (c, file); num++; in_escape = 0; } else { switch (c) { /* Some assemblers can't handle \a, \v, or \?. */ case '\t': c = 't'; goto escape; case '\f': c = 'f'; goto escape; case '\b': c = 'b'; goto escape; case '\r': c = 'r'; goto escape; case '\n': c = 'n'; goto escape; } fprintf (file, "\\%03o", c); num += 4; in_escape = 1; } } fprintf (file, "\"\n"); } /* Output a label (allows insn-output.c to be compiled without including m88k.c or needing to include stdio.h). */ void output_label (label_number) int label_number; { ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", label_number); } /* Generate the assembly code for function entry. The prologue is responsible for setting up the stack frame, initializing the frame pointer register, saving registers that must be saved, and allocating SIZE additional bytes of storage for the local variables. SIZE is an integer. FILE is a stdio stream to which the assembler code should be output. The label for the beginning of the function need not be output by this macro. That has already been done when the macro is run. To determine which registers to save, the macro can refer to the array `regs_ever_live': element R is nonzero if hard register R is used anywhere within the function. This implies the function prologue should save register R, but not if it is one of the call-used registers. On machines where functions may or may not have frame-pointers, the function entry code must vary accordingly; it must set up the frame pointer if one is wanted, and not otherwise. To determine whether a frame pointer is in wanted, the macro can refer to the variable `frame_pointer_needed'. The variable's value will be 1 at run time in a function that needs a frame pointer. On machines where an argument may be passed partly in registers and partly in memory, this macro must examine the variable `current_function_pretend_args_size', and allocate that many bytes of uninitialized space on the stack just underneath the first argument arriving on the stack. (This may not be at the very end of the stack, if the calling sequence has pushed anything else since pushing the stack arguments. But usually, on such machines, nothing else has been pushed yet, because the function prologue itself does all the pushing.) If `ACCUMULATE_OUTGOING_ARGS' is defined, the variable `current_function_outgoing_args_size' contains the size in bytes required for the outgoing arguments. This macro must add that amount of uninitialized space to very bottom of the stack. The stack frame we use looks like this: caller callee |==============================================| | caller's frame | |==============================================| | [caller's outgoing memory arguments] | |==============================================| | caller's outgoing argument area (32 bytes) | sp -> |==============================================| <- ap | [local variable space] | |----------------------------------------------| | [return address (r1)] | |----------------------------------------------| | [previous frame pointer (r30)] | |==============================================| <- fp | [preserved registers (r25..r14)] | |----------------------------------------------| | [preserved registers (x29..x22)] | |==============================================| | [dynamically allocated space (alloca)] | |==============================================| | [callee's outgoing memory arguments] | |==============================================| | [callee's outgoing argument area (32 bytes)] | |==============================================| <- sp Notes: r1 and r30 must be saved if debugging. fp (if present) is located two words down from the local variable space. */ static void emit_add (); static void preserve_registers (); static void emit_ldst (); static void output_tdesc (); static int nregs; static int nxregs; static char save_regs[FIRST_PSEUDO_REGISTER]; static int frame_laid_out; static int frame_size; static int variable_args_p; static int epilogue_marked; static int prologue_marked; extern char call_used_regs[]; extern int current_function_pretend_args_size; extern int current_function_outgoing_args_size; extern int frame_pointer_needed; #define FIRST_OCS_PRESERVE_REGISTER 14 #define LAST_OCS_PRESERVE_REGISTER 30 #define FIRST_OCS_EXTENDED_PRESERVE_REGISTER (32 + 22) #define LAST_OCS_EXTENDED_PRESERVE_REGISTER (32 + 31) #define STACK_UNIT_BOUNDARY (STACK_BOUNDARY / BITS_PER_UNIT) #define ROUND_CALL_BLOCK_SIZE(BYTES) \ (((BYTES) + (STACK_UNIT_BOUNDARY - 1)) & ~(STACK_UNIT_BOUNDARY - 1)) /* Establish the position of the FP relative to the SP. This is done either during FUNCTION_PROLOGUE or by INITIAL_ELIMINATION_OFFSET. */ void m88k_layout_frame () { int regno, sp_size; frame_laid_out++; bzero ((char *) &save_regs[0], sizeof (save_regs)); sp_size = nregs = nxregs = 0; frame_size = get_frame_size (); /* Since profiling requires a call, make sure r1 is saved. */ if (profile_flag || profile_block_flag) save_regs[1] = 1; /* If we are producing debug information, store r1 and r30 where the debugger wants to find them (r30 at r30+0, r1 at r30+4). Space has already been reserved for r1/r30 in STARTING_FRAME_OFFSET. */ if (write_symbols != NO_DEBUG && !TARGET_OCS_FRAME_POSITION) save_regs[1] = 1; /* If there is a call, alloca is used, __builtin_alloca is used, or a dynamic-sized object is defined, add the 8 additional words for the callee's argument area. The common denominator is that the FP is required. may_call_alloca only gets calls to alloca; current_function_calls_alloca gets alloca and __builtin_alloca. */ if (regs_ever_live[1] || frame_pointer_needed) { save_regs[1] = 1; sp_size += REG_PARM_STACK_SPACE (0); } /* If we are producing PIC, save the addressing base register and r1. */ if (flag_pic && current_function_uses_pic_offset_table) { save_regs[PIC_OFFSET_TABLE_REGNUM] = 1; nregs++; } /* If a frame is requested, save the previous FP, and the return address (r1), so that a traceback can be done without using tdesc information. Otherwise, simply save the FP if it is used as a preserve register. */ if (frame_pointer_needed) save_regs[FRAME_POINTER_REGNUM] = save_regs[1] = 1; else if (regs_ever_live[FRAME_POINTER_REGNUM]) save_regs[FRAME_POINTER_REGNUM] = 1; /* Figure out which extended register(s) needs to be saved. */ for (regno = FIRST_EXTENDED_REGISTER + 1; regno < FIRST_PSEUDO_REGISTER; regno++) if (regs_ever_live[regno] && ! call_used_regs[regno]) { save_regs[regno] = 1; nxregs++; } /* Figure out which normal register(s) needs to be saved. */ for (regno = 2; regno < FRAME_POINTER_REGNUM; regno++) if (regs_ever_live[regno] && ! call_used_regs[regno]) { save_regs[regno] = 1; nregs++; } /* Achieve greatest use of double memory ops. Either we end up saving r30 or we use that slot to align the registers we do save. */ if (nregs >= 2 && save_regs[1] && !save_regs[FRAME_POINTER_REGNUM]) sp_size += 4; nregs += save_regs[1] + save_regs[FRAME_POINTER_REGNUM]; /* if we need to align extended registers, add a word */ if (nxregs > 0 && (nregs & 1) != 0) sp_size +=4; sp_size += 4 * nregs; sp_size += 8 * nxregs; sp_size += current_function_outgoing_args_size; /* The first two saved registers are placed above the new frame pointer if any. In the only case this matters, they are r1 and r30. */ if (frame_pointer_needed || sp_size) m88k_fp_offset = ROUND_CALL_BLOCK_SIZE (sp_size - STARTING_FRAME_OFFSET); else m88k_fp_offset = -STARTING_FRAME_OFFSET; m88k_stack_size = m88k_fp_offset + STARTING_FRAME_OFFSET; /* First, combine m88k_stack_size and size. If m88k_stack_size is non-zero, align the frame size to 8 mod 16; otherwise align the frame size to 0 mod 16. (If stacks are 8 byte aligned, this ends up as a NOP. */ { int need = ((m88k_stack_size ? STACK_UNIT_BOUNDARY - STARTING_FRAME_OFFSET : 0) - (frame_size % STACK_UNIT_BOUNDARY)); if (need) { if (need < 0) need += STACK_UNIT_BOUNDARY; (void) assign_stack_local (BLKmode, need, BITS_PER_UNIT); frame_size = get_frame_size (); } m88k_stack_size = ROUND_CALL_BLOCK_SIZE (m88k_stack_size + frame_size + current_function_pretend_args_size); } } /* Return true if this function is known to have a null prologue. */ int null_prologue () { if (! reload_completed) return 0; if (! frame_laid_out) m88k_layout_frame (); return (! frame_pointer_needed && nregs == 0 && nxregs == 0 && m88k_stack_size == 0); } /* Determine if the current function has any references to the arg pointer. This is done indirectly by examining the DECL_ARGUMENTS' DECL_RTL. It is OK to return TRUE if there are no references, but FALSE must be correct. */ static int uses_arg_area_p () { register tree parm; if (current_function_decl == 0 || current_function_varargs || variable_args_p) return 1; for (parm = DECL_ARGUMENTS (current_function_decl); parm; parm = TREE_CHAIN (parm)) { if (DECL_RTL (parm) == 0 || GET_CODE (DECL_RTL (parm)) == MEM) return 1; if (DECL_INCOMING_RTL (parm) == 0 || GET_CODE (DECL_INCOMING_RTL (parm)) == MEM) return 1; } return 0; } void m88k_begin_prologue (stream, size) FILE *stream; int size; { m88k_prologue_done = 1; /* it's ok now to put out ln directives */ } void m88k_end_prologue (stream) FILE *stream; { if (TARGET_OCS_DEBUG_INFO && !prologue_marked) { PUT_OCS_FUNCTION_START (stream); prologue_marked = 1; /* If we've already passed the start of the epilogue, say that it starts here. This marks the function as having a null body, but at a point where the return address is in a known location. Originally, I thought this couldn't happen, but the pic prologue for leaf functions ends with the instruction that restores the return address from the temporary register. If the temporary register is never used, that instruction can float all the way to the end of the function. */ if (epilogue_marked) PUT_OCS_FUNCTION_END (stream); } } void m88k_expand_prologue () { m88k_layout_frame (); if (TARGET_OPTIMIZE_ARG_AREA && m88k_stack_size && ! uses_arg_area_p ()) { /* The incoming argument area is used for stack space if it is not used (or if -mno-optimize-arg-area is given). */ if ((m88k_stack_size -= REG_PARM_STACK_SPACE (0)) < 0) m88k_stack_size = 0; } if (m88k_stack_size) emit_add (stack_pointer_rtx, stack_pointer_rtx, -m88k_stack_size); if (nregs || nxregs) preserve_registers (m88k_fp_offset + 4, 1); if (frame_pointer_needed) emit_add (frame_pointer_rtx, stack_pointer_rtx, m88k_fp_offset); if (flag_pic && save_regs[PIC_OFFSET_TABLE_REGNUM]) { rtx return_reg = gen_rtx (REG, SImode, 1); rtx label = gen_label_rtx (); rtx temp_reg; if (! save_regs[1]) { temp_reg = gen_rtx (REG, SImode, TEMP_REGNUM); emit_move_insn (temp_reg, return_reg); } emit_insn (gen_locate1 (pic_offset_table_rtx, label)); emit_insn (gen_locate2 (pic_offset_table_rtx, label)); emit_insn (gen_addsi3 (pic_offset_table_rtx, pic_offset_table_rtx, return_reg)); if (! save_regs[1]) emit_move_insn (return_reg, temp_reg); } if (profile_flag || profile_block_flag) emit_insn (gen_blockage ()); } /* This function generates the assembly code for function exit, on machines that need it. Args are same as for FUNCTION_PROLOGUE. The function epilogue should not depend on the current stack pointer! It should use the frame pointer only, if there is a frame pointer. This is mandatory because of alloca; we also take advantage of it to omit stack adjustments before returning. */ void m88k_begin_epilogue (stream) FILE *stream; { if (TARGET_OCS_DEBUG_INFO && !epilogue_marked && prologue_marked) { PUT_OCS_FUNCTION_END (stream); } epilogue_marked = 1; } void m88k_end_epilogue (stream, size) FILE *stream; int size; { rtx insn = get_last_insn (); if (TARGET_OCS_DEBUG_INFO && !epilogue_marked) PUT_OCS_FUNCTION_END (stream); /* If the last insn isn't a BARRIER, we must write a return insn. This should only happen if the function has no prologe and no body. */ if (GET_CODE (insn) == NOTE) insn = prev_nonnote_insn (insn); if (insn == 0 || GET_CODE (insn) != BARRIER) fprintf (stream, "\tjmp\t %s\n", reg_names[1]); output_short_branch_defs (stream); fprintf (stream, "\n"); if (TARGET_OCS_DEBUG_INFO) output_tdesc (stream, m88k_fp_offset + 4); m88k_function_number++; m88k_prologue_done = 0; /* don't put out ln directives */ variable_args_p = 0; /* has variable args */ frame_laid_out = 0; epilogue_marked = 0; prologue_marked = 0; } void m88k_expand_epilogue () { #if (MONITOR_GCC & 0x4) /* What are interesting prologue/epilogue values? */ fprintf (stream, "; size = %d, m88k_fp_offset = %d, m88k_stack_size = %d\n", size, m88k_fp_offset, m88k_stack_size); #endif if (frame_pointer_needed) emit_add (stack_pointer_rtx, frame_pointer_rtx, -m88k_fp_offset); if (nregs || nxregs) preserve_registers (m88k_fp_offset + 4, 0); if (m88k_stack_size) emit_add (stack_pointer_rtx, stack_pointer_rtx, m88k_stack_size); } /* Emit insns to set DSTREG to SRCREG + AMOUNT during the prologue or epilogue. */ static void emit_add (dstreg, srcreg, amount) rtx dstreg; rtx srcreg; int amount; { rtx incr = gen_rtx (CONST_INT, VOIDmode, abs (amount)); if (! ADD_INTVAL (amount)) { rtx temp = gen_rtx (REG, SImode, TEMP_REGNUM); emit_move_insn (temp, incr); incr = temp; } emit_insn ((amount < 0 ? gen_subsi3 : gen_addsi3) (dstreg, srcreg, incr)); } /* Save/restore the preserve registers. base is the highest offset from r31 at which a register is stored. store_p is true if stores are to be done; otherwise loads. */ static void preserve_registers (base, store_p) int base; int store_p; { int regno, offset; struct mem_op { int regno; int nregs; int offset; } mem_op[FIRST_PSEUDO_REGISTER]; struct mem_op *mo_ptr = mem_op; /* The 88open OCS mandates that preserved registers be stored in increasing order. For compatibility with current practice, the order is r1, r30, then the preserve registers. */ offset = base; if (save_regs[1]) { /* An extra word is given in this case to make best use of double memory ops. */ if (nregs > 2 && !save_regs[FRAME_POINTER_REGNUM]) offset -= 4; emit_ldst (store_p, 1, SImode, offset); offset -= 4; base = offset; } /* Walk the registers to save recording all single memory operations. */ for (regno = FRAME_POINTER_REGNUM; regno > 1; regno--) if (save_regs[regno]) { if ((offset & 7) != 4 || (regno & 1) != 1 || !save_regs[regno-1]) { mo_ptr->nregs = 1; mo_ptr->regno = regno; mo_ptr->offset = offset; mo_ptr++; offset -= 4; } else { regno--; offset -= 2*4; } } /* Walk the registers to save recording all double memory operations. This avoids a delay in the epilogue (ld.d/ld). */ offset = base; for (regno = FRAME_POINTER_REGNUM; regno > 1; regno--) if (save_regs[regno]) { if ((offset & 7) != 4 || (regno & 1) != 1 || !save_regs[regno-1]) { offset -= 4; } else { mo_ptr->nregs = 2; mo_ptr->regno = regno-1; mo_ptr->offset = offset-4; mo_ptr++; regno--; offset -= 2*4; } } /* Walk the extended registers to record all memory operations. */ /* Be sure the offset is double word aligned. */ offset = (offset - 1) & ~7; for (regno = FIRST_PSEUDO_REGISTER - 1; regno > FIRST_EXTENDED_REGISTER; regno--) if (save_regs[regno]) { mo_ptr->nregs = 2; mo_ptr->regno = regno; mo_ptr->offset = offset; mo_ptr++; offset -= 2*4; } mo_ptr->regno = 0; /* Output the memory operations. */ for (mo_ptr = mem_op; mo_ptr->regno; mo_ptr++) { if (mo_ptr->nregs) emit_ldst (store_p, mo_ptr->regno, (mo_ptr->nregs > 1 ? DImode : SImode), mo_ptr->offset); } } static void emit_ldst (store_p, regno, mode, offset) int store_p; int regno; enum machine_mode mode; int offset; { rtx reg = gen_rtx (REG, mode, regno); rtx mem; if (SMALL_INTVAL (offset)) { mem = gen_rtx (MEM, mode, plus_constant (stack_pointer_rtx, offset)); } else { /* offset is too large for immediate index must use register */ rtx disp = gen_rtx (CONST_INT, VOIDmode, offset); rtx temp = gen_rtx (REG, SImode, TEMP_REGNUM); rtx regi = gen_rtx (PLUS, SImode, stack_pointer_rtx, temp); emit_move_insn (temp, disp); mem = gen_rtx (MEM, mode, regi); } if (store_p) emit_move_insn (mem, reg); else emit_move_insn (reg, mem); } /* Convert the address expression REG to a CFA offset. */ int m88k_debugger_offset (reg, offset) register rtx reg; register int offset; { if (GET_CODE (reg) == PLUS) { offset = INTVAL (XEXP (reg, 1)); reg = XEXP (reg, 0); } /* Put the offset in terms of the CFA (arg pointer). */ if (reg == frame_pointer_rtx) offset += m88k_fp_offset - m88k_stack_size; else if (reg == stack_pointer_rtx) offset -= m88k_stack_size; else if (reg != arg_pointer_rtx) { #if (MONITOR_GCC & 0x10) /* Watch for suspicious symbolic locations. */ if (! (GET_CODE (reg) == REG && REGNO (reg) >= FIRST_PSEUDO_REGISTER)) warning ("Internal gcc error: Can't express symbolic location"); #endif return 0; } return offset; } /* Output the 88open OCS proscribed text description information. The information is: 0 8: zero 0 22: info-byte-length (16 or 20 bytes) 0 2: info-alignment (word 2) 1 32: info-protocol (version 1 or 2(pic)) 2 32: starting-address (inclusive, not counting prologue) 3 32: ending-address (exclusive, not counting epilog) 4 8: info-variant (version 1 or 3(extended registers)) 4 17: register-save-mask (from register 14 to 30) 4 1: zero 4 1: return-address-info-discriminant 4 5: frame-address-register 5 32: frame-address-offset 6 32: return-address-info 7 32: register-save-offset 8 16: extended-register-save-mask (x16 - x31) 8 16: extended-register-save-offset (WORDS from register-save-offset) */ static void output_tdesc (file, offset) FILE *file; int offset; { int regno, i, j; long mask, return_address_info, register_save_offset; long xmask, xregister_save_offset; char buf[256]; for (mask = 0, i = 0, regno = FIRST_OCS_PRESERVE_REGISTER; regno <= LAST_OCS_PRESERVE_REGISTER; regno++) { mask <<= 1; if (save_regs[regno]) { mask |= 1; i++; } } for (xmask = 0, j = 0, regno = FIRST_OCS_EXTENDED_PRESERVE_REGISTER; regno <= LAST_OCS_EXTENDED_PRESERVE_REGISTER; regno++) { xmask <<= 1; if (save_regs[regno]) { xmask |= 1; j++; } } if (save_regs[1]) { if ((nxregs > 0 || nregs > 2) && !save_regs[FRAME_POINTER_REGNUM]) offset -= 4; return_address_info = - m88k_stack_size + offset; register_save_offset = return_address_info - i*4; } else { return_address_info = 1; register_save_offset = - m88k_stack_size + offset + 4 - i*4; } xregister_save_offset = - (j * 2 + ((register_save_offset >> 2) & 1)); tdesc_section (); fprintf (file, "\t%s\t %d,%d", INT_ASM_OP, /* 8:0,22:(20 or 16),2:2 */ (((xmask != 0) ? 20 : 16) << 2) | 2, flag_pic ? 2 : 1); ASM_GENERATE_INTERNAL_LABEL (buf, OCS_START_PREFIX, m88k_function_number); fprintf (file, ",%s%s", buf+1, flag_pic ? "#rel" : ""); ASM_GENERATE_INTERNAL_LABEL (buf, OCS_END_PREFIX, m88k_function_number); fprintf (file, ",%s%s", buf+1, flag_pic ? "#rel" : ""); fprintf (file, ",0x%x,0x%x,0x%x,0x%x", /* 8:1,17:0x%.3x,1:0,1:%d,5:%d */ (((xmask ? 3 : 1) << (17+1+1+5)) | (mask << (1+1+5)) | ((!!save_regs[1]) << 5) | (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM)), (m88k_stack_size - (frame_pointer_needed ? m88k_fp_offset : 0)), return_address_info, register_save_offset); if (xmask) fprintf (file, ",0x%x%04x", xmask, (0xffff & xregister_save_offset)); fputc ('\n', file); text_section (); } /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. NAME is the mcount function name (varies), SAVEP indicates whether the parameter registers need to be saved and restored. */ void output_function_profiler (file, labelno, name, savep) FILE *file; int labelno; char *name; int savep; { char label[256]; char dbi[256]; char *temp = (savep ? reg_names[2] : reg_names[10]); /* Remember to update FUNCTION_PROFILER_LENGTH. */ if (savep) { fprintf (file, "\tsubu\t %s,%s,64\n", reg_names[31], reg_names[31]); fprintf (file, "\tst.d\t %s,%s,32\n", reg_names[2], reg_names[31]); fprintf (file, "\tst.d\t %s,%s,40\n", reg_names[4], reg_names[31]); fprintf (file, "\tst.d\t %s,%s,48\n", reg_names[6], reg_names[31]); fprintf (file, "\tst.d\t %s,%s,56\n", reg_names[8], reg_names[31]); } ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno); if (flag_pic == 2) { fprintf (file, "\tor.u\t %s,%s,%shi16(%s#got_rel)\n", temp, reg_names[0], m88k_pound_sign, &label[1]); fprintf (file, "\tor\t %s,%s,%slo16(%s#got_rel)\n", temp, temp, m88k_pound_sign, &label[1]); sprintf (dbi, "\tld\t %s,%s,%s\n", temp, reg_names[PIC_OFFSET_TABLE_REGNUM], temp); } else if (flag_pic) { sprintf (dbi, "\tld\t %s,%s,%s#got_rel\n", temp, reg_names[PIC_OFFSET_TABLE_REGNUM], &label[1]); } else { fprintf (file, "\tor.u\t %s,%s,%shi16(%s)\n", temp, reg_names[0], m88k_pound_sign, &label[1]); sprintf (dbi, "\tor\t %s,%s,%slo16(%s)\n", temp, temp, m88k_pound_sign, &label[1]); } if (flag_pic) fprintf (file, "\tbsr.n\t %s#plt\n", name); else fprintf (file, "\tbsr.n\t %s\n", name); fputs (dbi, file); if (savep) { fprintf (file, "\tld.d\t %s,%s,32\n", reg_names[2], reg_names[31]); fprintf (file, "\tld.d\t %s,%s,40\n", reg_names[4], reg_names[31]); fprintf (file, "\tld.d\t %s,%s,48\n", reg_names[6], reg_names[31]); fprintf (file, "\tld.d\t %s,%s,56\n", reg_names[8], reg_names[31]); fprintf (file, "\taddu\t %s,%s,64\n", reg_names[31], reg_names[31]); } } /* Output assembler code to FILE to initialize basic-block profiling for the current module. LABELNO is unique to each instance. */ void output_function_block_profiler (file, labelno) FILE *file; int labelno; { char block[256]; char label[256]; /* Remember to update FUNCTION_BLOCK_PROFILER_LENGTH. */ ASM_GENERATE_INTERNAL_LABEL (block, "LPBX", 0); ASM_GENERATE_INTERNAL_LABEL (label, "LPY", labelno); /* @@ Need to deal with PIC. I'm not sure what the requirements are on register usage, so I used r26/r27 to be safe. */ fprintf (file, "\tor.u\t %s,%s,%shi16(%s)\n", reg_names[27], reg_names[0], m88k_pound_sign, &block[1]); fprintf (file, "\tld\t %s,%s,%slo16(%s)\n", reg_names[26], reg_names[27], m88k_pound_sign, &block[1]); fprintf (file, "\tbcnd\t %sne0,%s,%s\n", m88k_pound_sign, reg_names[26], &label[1]); fprintf (file, "\tsubu\t %s,%s,64\n", reg_names[31], reg_names[31]); fprintf (file, "\tst.d\t %s,%s,32\n", reg_names[2], reg_names[31]); fprintf (file, "\tst.d\t %s,%s,40\n", reg_names[4], reg_names[31]); fprintf (file, "\tst.d\t %s,%s,48\n", reg_names[6], reg_names[31]); fprintf (file, "\tst.d\t %s,%s,56\n", reg_names[8], reg_names[31]); fputs ("\tbsr.n\t ", file); ASM_OUTPUT_LABELREF (file, "__bb_init_func"); putc ('\n', file); fprintf (file, "\tor\t %s,%s,%slo16(%s)\n", reg_names[2], reg_names[27], m88k_pound_sign, &block[1]); fprintf (file, "\tld.d\t %s,%s,32\n", reg_names[2], reg_names[31]); fprintf (file, "\tld.d\t %s,%s,40\n", reg_names[4], reg_names[31]); fprintf (file, "\tld.d\t %s,%s,48\n", reg_names[6], reg_names[31]); fprintf (file, "\tld.d\t %s,%s,56\n", reg_names[8], reg_names[31]); fprintf (file, "\taddu\t %s,%s,64\n", reg_names[31], reg_names[31]); ASM_OUTPUT_INTERNAL_LABEL (file, "LPY", labelno); } /* Output assembler code to FILE to increment the count associated with the basic block number BLOCKNO. */ void output_block_profiler (file, blockno) FILE *file; int blockno; { char block[256]; /* Remember to update BLOCK_PROFILER_LENGTH. */ ASM_GENERATE_INTERNAL_LABEL (block, "LPBX", 2); /* @@ Need to deal with PIC. I'm not sure what the requirements are on register usage, so I used r26/r27 to be safe. */ fprintf (file, "\tor.u\t %s,%s,%shi16(%s+%d)\n", reg_names[27], reg_names[0], m88k_pound_sign, &block[1], 4 * blockno); fprintf (file, "\tld\t %s,%s,%slo16(%s+%d)\n", reg_names[26], reg_names[27], m88k_pound_sign, &block[1], 4 * blockno); fprintf (file, "\taddu\t %s,%s,1\n", reg_names[26], reg_names[26]); fprintf (file, "\tst\t %s,%s,%slo16(%s+%d)\n", reg_names[26], reg_names[27], m88k_pound_sign, &block[1], 4 * blockno); } /* Determine whether a function argument is passed in a register, and which register. The arguments are CUM, which summarizes all the previous arguments; MODE, the machine mode of the argument; TYPE, the data type of the argument as a tree node or 0 if that is not known (which happens for C support library functions); and NAMED, which is 1 for an ordinary argument and 0 for nameless arguments that correspond to `...' in the called function's prototype. The value of the expression should either be a `reg' RTX for the hard register in which to pass the argument, or zero to pass the argument on the stack. On the m88000 the first eight words of args are normally in registers and the rest are pushed. Double precision floating point must be double word aligned (and if in a register, starting on an even register). Structures and unions which are not 4 byte, and word aligned are passed in memory rather than registers, even if they would fit completely in the registers under OCS rules. Note that FUNCTION_ARG and FUNCTION_INCOMING_ARG were different. For structures that are passed in memory, but could have been passed in registers, we first load the structure into the register, and then when the last argument is passed, we store the registers into the stack locations. This fixes some bugs where GCC did not expect to have register arguments, followed by stack arguments, followed by register arguments. */ struct rtx_def * m88k_function_arg (args_so_far, mode, type, named) CUMULATIVE_ARGS args_so_far; enum machine_mode mode; tree type; int named; { int bytes, words; if (type != 0 /* undo putting struct in register */ && (TREE_CODE (type) == RECORD_TYPE || TREE_CODE (type) == UNION_TYPE)) mode = BLKmode; if (mode == BLKmode && TARGET_WARN_PASS_STRUCT) warning ("argument #%d is a structure", args_so_far + 1); if ((args_so_far & 1) != 0 && (mode == DImode || mode == DFmode || (type != 0 && TYPE_ALIGN (type) > 32))) args_so_far++; #ifdef ESKIT if (no_reg_params) return (rtx) 0; /* don't put args in registers */ #endif if (type == 0 && mode == BLKmode) abort (); /* m88k_function_arg argument `type' is NULL for BLKmode. */ bytes = (mode != BLKmode) ? GET_MODE_SIZE (mode) : int_size_in_bytes (type); words = (bytes + 3) / 4; if (args_so_far + words > 8) return (rtx) 0; /* args have exhausted registers */ else if (mode == BLKmode && (TYPE_ALIGN (type) != BITS_PER_WORD || bytes != UNITS_PER_WORD)) return (rtx) 0; return gen_rtx (REG, ((mode == BLKmode) ? TYPE_MODE (type) : mode), 2 + args_so_far); } /* Do what is necessary for `va_start'. The argument is ignored; We look at the current function to determine if stdargs or varargs is used and fill in an initial va_list. A pointer to this constructor is returned. */ struct rtx_def * m88k_builtin_saveregs (arglist) tree arglist; { rtx block, addr, argsize; tree fntype = TREE_TYPE (current_function_decl); int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))) ? -UNITS_PER_WORD : 0) + UNITS_PER_WORD - 1; int fixed; variable_args_p = 1; if (CONSTANT_P (current_function_arg_offset_rtx)) { fixed = (XINT (current_function_arg_offset_rtx, 0) + argadj) / UNITS_PER_WORD; argsize = gen_rtx (CONST_INT, VOIDmode, fixed); } else { fixed = 0; argsize = plus_constant (current_function_arg_offset_rtx, argadj); argsize = expand_shift (RSHIFT_EXPR, Pmode, argsize, build_int_2 (2, 0), argsize, 0); } /* Allocate the va_list constructor */ block = assign_stack_local (BLKmode, 3 * UNITS_PER_WORD, BITS_PER_WORD); RTX_UNCHANGING_P (block) = 1; RTX_UNCHANGING_P (XEXP (block, 0)) = 1; /* Store the argsize as the __va_arg member. */ emit_move_insn (change_address (block, SImode, XEXP (block, 0)), argsize); /* Store the arg pointer in the __va_stk member. */ emit_move_insn (change_address (block, Pmode, plus_constant (XEXP (block, 0), UNITS_PER_WORD)), copy_to_reg (virtual_incoming_args_rtx)); /* Allocate the register space, and store it as the __va_reg member. */ addr = assign_stack_local (BLKmode, 8 * UNITS_PER_WORD, -1); MEM_IN_STRUCT_P (addr) = 1; RTX_UNCHANGING_P (addr) = 1; RTX_UNCHANGING_P (XEXP (addr, 0)) = 1; emit_move_insn (change_address (block, Pmode, plus_constant (XEXP (block, 0), 2 * UNITS_PER_WORD)), copy_to_reg (XEXP (addr, 0))); /* Now store the incoming registers. */ if (fixed < 8) move_block_from_reg (2 + fixed, change_address (addr, Pmode, plus_constant (XEXP (addr, 0), fixed * UNITS_PER_WORD)), 8 - fixed, (8 - fixed) * UNITS_PER_WORD); /* Return the address of the va_list constructor, but don't put it in a register. This fails when not optimizing and produces worse code when optimizing. */ return XEXP (block, 0); } /* If cmpsi has not been generated, emit code to do the test. Return the expression describing the test of operator OP. */ rtx emit_test (op, mode) enum rtx_code op; enum machine_mode mode; { if (m88k_compare_reg == 0) emit_insn (gen_test (m88k_compare_op0, m88k_compare_op1)); return (gen_rtx (op, mode, m88k_compare_reg, const0_rtx)); } /* Determine how to best perform cmpsi/bxx, where cmpsi has a constant operand. All tests with zero (albeit swapped) and all equality tests with a constant are done with bcnd. The remaining cases are swapped as needed. */ void emit_bcnd (op, label) enum rtx_code op; rtx label; { if (m88k_compare_op1 == const0_rtx) emit_jump_insn (optimize ? gen_bxx (emit_test (op, VOIDmode), label) : gen_bcnd (gen_rtx (op, VOIDmode, m88k_compare_op0, const0_rtx), label)); else if (m88k_compare_op0 == const0_rtx) emit_jump_insn (optimize ? gen_bxx (emit_test (op, VOIDmode), label) : gen_bcnd (gen_rtx (swap_condition (op), VOIDmode, m88k_compare_op1, const0_rtx), label)); else if (op != EQ && op != NE) emit_jump_insn (gen_bxx (emit_test (op, VOIDmode), label)); else { rtx zero = gen_reg_rtx (SImode); rtx reg, constant; int value; if (GET_CODE (m88k_compare_op1) == CONST_INT) { reg = force_reg (SImode, m88k_compare_op0); constant = m88k_compare_op1; } else { reg = force_reg (SImode, m88k_compare_op1); constant = m88k_compare_op0; } value = INTVAL (constant); /* Perform an arithmetic computation to make the compared-to value zero, but avoid loosing if the bcnd is later changed into sxx. */ if (SMALL_INTVAL (value)) emit_jump_insn (gen_bxx (emit_test (op, VOIDmode), label)); else { if (SMALL_INTVAL (-value)) emit_insn (gen_addsi3 (zero, reg, gen_rtx (CONST_INT, VOIDmode, -value))); else emit_insn (gen_xorsi3 (zero, reg, constant)); emit_jump_insn (gen_bcnd (gen_rtx (op, VOIDmode, zero, const0_rtx), label)); } } } /* Print an operand. Recognize special options, documented below. */ void print_operand (file, x, code) FILE *file; rtx x; char code; { enum rtx_code xc = (x ? GET_CODE (x) : UNKNOWN); register int value = (xc == CONST_INT ? INTVAL (x) : 0); static int sequencep; static int reversep; if (sequencep) { if (code < 'B' || code > 'E') output_operand_lossage ("%R not followed by %B/C/D/E"); if (reversep) xc = reverse_condition (xc); sequencep = 0; } switch (code) { case '*': /* addressing base register for PIC */ fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file); return; case '#': /* SVR4 pound-sign syntax character (empty if SVR3) */ fputs (m88k_pound_sign, file); return; case 'V': /* Output a serializing instruction as needed if the operand (assumed to be a MEM) is a volatile load. */ case 'v': /* ditto for a volatile store. */ if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE) { /* The m88110 implements two FIFO queues, one for loads and one for stores. These queues mean that loads complete in their issue order as do stores. An interaction between the history buffer and the store reservation station ensures that a store will not bypass load. Finally, a load will not bypass store, but only when they reference the same address. To avoid this reordering (a load bypassing a store) for volatile references, a serializing instruction is output. We choose the fldcr instruction as it does not serialize on the m88100 so that -m88000 code will not be degraded. The mechanism below is completed by having CC_STATUS_INIT set the code to the unknown value. */ /* hassey 6/30/93 A problem with 88110 4.1 & 4.2 makes the use of fldcr for this purpose undesirable. Instead we will use tb1, this will cause serialization on the 88100 but such is life. */ static rtx last_addr = 0; if (code == 'V' /* Only need to serialize before a load. */ && m88k_volatile_code != 'V' /* Loads complete in FIFO order. */ && !(m88k_volatile_code == 'v' && GET_CODE (XEXP (x, 0)) == LO_SUM && rtx_equal_p (XEXP (XEXP (x, 0), 1), last_addr))) fprintf (file, #if 0 #ifdef AS_BUG_FLDCR "fldcr\t %s,%scr63\n\t", #else "fldcr\t %s,%sfcr63\n\t", #endif reg_names[0], m88k_pound_sign); #else /* 0 */ "tb1\t 1,%s,0xff\n\t", reg_names[0]); #endif /* 0 */ m88k_volatile_code = code; last_addr = (GET_CODE (XEXP (x, 0)) == LO_SUM ? XEXP (XEXP (x, 0), 1) : 0); } return; case 'X': /* print the upper 16 bits... */ value >>= 16; case 'x': /* print the lower 16 bits of the integer constant in hex */ if (xc != CONST_INT) output_operand_lossage ("invalid %x/X value"); fprintf (file, "0x%x", value & 0xffff); return; case 'H': /* print the low 16 bits of the negated integer constant */ if (xc != CONST_INT) output_operand_lossage ("invalid %H value"); value = -value; case 'h': /* print the register or low 16 bits of the integer constant */ if (xc == REG) goto reg; if (xc != CONST_INT) output_operand_lossage ("invalid %h value"); fprintf (file, "%d", value & 0xffff); return; case 'Q': /* print the low 8 bits of the negated integer constant */ if (xc != CONST_INT) output_operand_lossage ("invalid %Q value"); value = -value; case 'q': /* print the register or low 8 bits of the integer constant */ if (xc == REG) goto reg; if (xc != CONST_INT) output_operand_lossage ("invalid %q value"); fprintf (file, "%d", value & 0xff); return; case 'w': /* print the integer constant (X == 32 ? 0 : 32 - X) */ if (xc != CONST_INT) output_operand_lossage ("invalid %o value"); fprintf (file, "%d", value == 32 ? 0 : 32 - value); return; case 'p': /* print the logarithm of the integer constant */ if (xc != CONST_INT || (value = exact_log2 (value)) < 0) output_operand_lossage ("invalid %p value"); fprintf (file, "%d", value); return; case 'S': /* compliment the value and then... */ value = ~value; case 's': /* print the width and offset values forming the integer constant with a SET instruction. See integer_ok_for_set. */ { register unsigned mask, uval = value; register int top, bottom; if (xc != CONST_INT) output_operand_lossage ("invalid %s/S value"); /* All the "one" bits must be contiguous. If so, MASK will be a power of two or zero. */ mask = (uval | (uval - 1)) + 1; if (!(uval && POWER_OF_2_or_0 (mask))) output_operand_lossage ("invalid %s/S value"); top = mask ? exact_log2 (mask) : 32; bottom = exact_log2 (uval & ~(uval - 1)); fprintf (file,"%d<%d>", top - bottom, bottom); return; } case 'P': /* print nothing if pc_rtx; output label_ref */ if (xc == LABEL_REF) output_addr_const (file, x); else if (xc != PC) output_operand_lossage ("invalid %P operand"); return; case 'L': /* print 0 or 1 if operand is label_ref and then... */ fputc (xc == LABEL_REF ? '1' : '0', file); case '.': /* print .n if delay slot is used */ fputs ((final_sequence && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))) ? ".n\t" : "\t", file); return; case '!': /* Reverse the following condition. */ sequencep++; reversep = 1; return; case 'R': /* reverse the condition of the next print_operand if operand is a label_ref. */ sequencep++; reversep = (xc == LABEL_REF); return; case 'B': /* bcnd branch values */ fputs (m88k_pound_sign, file); switch (xc) { case EQ: fputs ("eq0", file); return; case NE: fputs ("ne0", file); return; case GT: fputs ("gt0", file); return; case LE: fputs ("le0", file); return; case LT: fputs ("lt0", file); return; case GE: fputs ("ge0", file); return; default: output_operand_lossage ("invalid %B value"); } case 'C': /* bb0/bb1 branch values for comparisons */ fputs (m88k_pound_sign, file); switch (xc) { case EQ: fputs ("eq", file); return; case NE: fputs ("ne", file); return; case GT: fputs ("gt", file); return; case LE: fputs ("le", file); return; case LT: fputs ("lt", file); return; case GE: fputs ("ge", file); return; case GTU: fputs ("hi", file); return; case LEU: fputs ("ls", file); return; case LTU: fputs ("lo", file); return; case GEU: fputs ("hs", file); return; default: output_operand_lossage ("invalid %C value"); } case 'D': /* bcnd branch values for float comparisons */ switch (xc) { case EQ: fputs ("0xa", file); return; case NE: fputs ("0x5", file); return; case GT: fputs (m88k_pound_sign, file); fputs ("gt0", file); return; case LE: fputs ("0xe", file); return; case LT: fputs ("0x4", file); return; case GE: fputs ("0xb", file); return; default: output_operand_lossage ("invalid %D value"); } case 'E': /* bcnd branch values for special integers */ switch (xc) { case EQ: fputs ("0x8", file); return; case NE: fputs ("0x7", file); return; default: output_operand_lossage ("invalid %E value"); } case 'd': /* second register of a two register pair */ if (xc != REG) output_operand_lossage ("`%d' operand isn't a register"); fputs (reg_names[REGNO (x) + 1], file); return; case 'r': /* an immediate 0 should be represented as `r0' */ if (x == const0_rtx) { fputs (reg_names[0], file); return; } else if (xc != REG) output_operand_lossage ("invalid %r value"); case 0: name: if (xc == REG) { reg: if (REGNO (x) == ARG_POINTER_REGNUM) output_operand_lossage ("operand is r0"); else fputs (reg_names[REGNO (x)], file); } else if (xc == PLUS) output_address (x); else if (xc == MEM) output_address (XEXP (x, 0)); else if (xc == CONST_DOUBLE) output_operand_lossage ("operand is const_double"); else output_addr_const (file, x); return; case 'g': /* append #got_rel as needed */ if (flag_pic && (xc == SYMBOL_REF || xc == LABEL_REF)) { output_addr_const (file, x); fputs ("#got_rel", file); return; } goto name; case 'a': /* (standard), assume operand is an address */ case 'c': /* (standard), assume operand is an immediate value */ case 'l': /* (standard), assume operand is a label_ref */ case 'n': /* (standard), like %c, except negate first */ default: output_operand_lossage ("invalid code"); } } void print_operand_address (file, addr) FILE *file; rtx addr; { register rtx reg0, reg1, temp; switch (GET_CODE (addr)) { case REG: if (REGNO (addr) == ARG_POINTER_REGNUM) abort (); else fprintf (file, "%s,%s", reg_names[0], reg_names [REGNO (addr)]); break; case LO_SUM: fprintf (file, "%s,%slo16(", reg_names[REGNO (XEXP (addr, 0))], m88k_pound_sign); output_addr_const (file, XEXP (addr, 1)); fputc (')', file); break; case PLUS: reg0 = XEXP (addr, 0); reg1 = XEXP (addr, 1); if (GET_CODE (reg0) == MULT || GET_CODE (reg0) == CONST_INT) { rtx tmp = reg0; reg0 = reg1; reg1 = tmp; } if ((REG_P (reg0) && REGNO (reg0) == ARG_POINTER_REGNUM) || (REG_P (reg1) && REGNO (reg1) == ARG_POINTER_REGNUM)) abort (); else if (REG_P (reg0)) { if (REG_P (reg1)) fprintf (file, "%s,%s", reg_names [REGNO (reg0)], reg_names [REGNO (reg1)]); else if (GET_CODE (reg1) == CONST_INT) fprintf (file, "%s,%d", reg_names [REGNO (reg0)], INTVAL (reg1)); else if (GET_CODE (reg1) == MULT) { rtx mreg = XEXP (reg1, 0); if (REGNO (mreg) == ARG_POINTER_REGNUM) abort (); fprintf (file, "%s[%s]", reg_names[REGNO (reg0)], reg_names[REGNO (mreg)]); } else if (GET_CODE (reg1) == ZERO_EXTRACT) { fprintf (file, "%s,%slo16(", reg_names[REGNO (reg0)], m88k_pound_sign); output_addr_const (file, XEXP (reg1, 0)); fputc (')', file); } else if (flag_pic) { fprintf (file, "%s,", reg_names[REGNO (reg0)]); output_addr_const (file, reg1); fputs ("#got_rel", file); } else abort (); } else abort (); break; case MULT: if (REGNO (XEXP (addr, 0)) == ARG_POINTER_REGNUM) abort (); fprintf (file, "%s[%s]", reg_names[0], reg_names[REGNO (XEXP (addr, 0))]); break; case LSHIFT: fprintf (file, "%s,%shi16(", reg_names[0], m88k_pound_sign); output_addr_const (file, XEXP (addr, 0)); fputc (')', file); break; case CONST_INT: fprintf (file, "%s,%d", reg_names[0], INTVAL (addr)); break; default: fprintf (file, "%s,", reg_names[0]); if (SHORT_ADDRESS_P (addr, temp)) { fprintf (file, "%siw16(", m88k_pound_sign); output_addr_const (file, addr); fputc (')', file); } else output_addr_const (file, addr); } } gcc-2.5.8/config/m88k/m88k.h100444 22011 13 304724 5467074413 14043 0ustar kenneruser/* Definitions of target machine for GNU compiler. Motorola m88100 in an 88open OCS/BCS environment. Copyright (C) 1988, 1989, 1990, 1991, 1993 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@mcc.com) Enhanced by Michael Meissner (meissner@osf.org) Version 2 port by Tom Wood (Tom_Wood@NeXT.com) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* The m88100 port of GNU CC adheres to the various standards from 88open. These documents are available by writing: 88open Consortium Ltd. 100 Homeland Court, Suite 800 San Jose, CA 95112 (408) 436-6600 In brief, the current standards are: Binary Compatibility Standard, Release 1.1A, May 1991 This provides for portability of application-level software at the executable level for AT&T System V Release 3.2. Object Compatibility Standard, Release 1.1A, May 1991 This provides for portability of application-level software at the object file and library level for C, Fortran, and Cobol, and again, largely for SVR3. Under development are standards for AT&T System V Release 4, based on the [generic] System V Application Binary Interface from AT&T. These include: System V Application Binary Interface, Motorola 88000 Processor Supplement Another document from AT&T for SVR4 specific to the m88100. Available from Prentice Hall. System V Application Binary Interface, Motorola 88000 Processor Supplement, Release 1.1, Draft H, May 6, 1991 A proposed update to the AT&T document from 88open. System V ABI Implementation Guide for the M88000 Processor, Release 1.0, January 1991 A companion ABI document from 88open. */ /* Other m88k*.h files include this one and override certain items. At present, these are m88kv3.h, m88kv4.h, m88kdgux.h, and m88kluna.h. Additionally, m88kv4.h and m88kdgux.h include svr4.h first. All other m88k targets except m88kluna.h are based on svr3.h. */ /* Choose SVR3 as the default. */ #if !defined(DBX_DEBUGGING_INFO) && !defined(DWARF_DEBUGGING_INFO) #include "svr3.h" #endif /* External types used. */ /* What instructions are needed to manufacture an integer constant. */ enum m88k_instruction { m88k_zero, m88k_or, m88k_subu, m88k_or_lo16, m88k_or_lo8, m88k_set, m88k_oru_hi16, m88k_oru_or }; /* External variables/functions defined in m88k.c. */ extern char *m88k_pound_sign; extern char *m88k_short_data; extern char *m88k_version; extern char m88k_volatile_code; extern int m88k_gp_threshold; extern int m88k_prologue_done; extern int m88k_function_number; extern int m88k_fp_offset; extern int m88k_stack_size; extern int m88k_case_index; extern int m88k_version_0300; extern struct rtx_def *m88k_compare_reg; extern struct rtx_def *m88k_compare_op0; extern struct rtx_def *m88k_compare_op1; extern enum attr_cpu m88k_cpu; extern int null_prologue (); extern int integer_ok_for_set (); extern int m88k_debugger_offset (); extern void emit_bcnd (); extern void expand_block_move (); extern void m88k_layout_frame (); extern void m88k_expand_prologue (); extern void m88k_begin_prologue (); extern void m88k_end_prologue (); extern void m88k_expand_epilogue (); extern void m88k_begin_epilogue (); extern void m88k_end_epilogue (); extern void output_function_profiler (); extern void output_function_block_profiler (); extern void output_block_profiler (); extern void output_file_start (); extern void output_ascii (); extern void output_label (); extern void print_operand (); extern void print_operand_address (); extern char *output_load_const_int (); extern char *output_load_const_float (); extern char *output_load_const_double (); extern char *output_load_const_dimode (); extern char *output_and (); extern char *output_ior (); extern char *output_xor (); extern char *output_call (); extern struct rtx_def *emit_test (); extern struct rtx_def *legitimize_address (); extern struct rtx_def *legitimize_operand (); extern struct rtx_def *m88k_function_arg (); extern struct rtx_def *m88k_builtin_saveregs (); extern enum m88k_instruction classify_integer (); /* external variables defined elsewhere in the compiler */ extern int target_flags; /* -m compiler switches */ extern int frame_pointer_needed; /* current function has a FP */ extern int current_function_pretend_args_size; /* args size without ... */ extern int flag_delayed_branch; /* -fdelayed-branch */ extern int flag_pic; /* -fpic */ extern char * reg_names[]; /* Specify the default monitors. The meaning of these values can be obtained by doing "grep MONITOR_GCC *m88k*". Generally, the values downward from 0x8000 are tests that will soon go away. values upward from 0x1 are generally useful tests that will remain. */ #ifndef MONITOR_GCC #define MONITOR_GCC 0 #endif /*** Controlling the Compilation Driver, `gcc' ***/ /* Some machines may desire to change what optimizations are performed for various optimization levels. This macro, if defined, is executed once just after the optimization level is determined and before the remainder of the command options have been parsed. Values set in this macro are used as the default values for the other command line options. LEVEL is the optimization level specified; 2 if -O2 is specified, 1 if -O is specified, and 0 if neither is specified. */ /* This macro used to store 0 in flag_signed_bitfields. Not only is that misuse of this macro; the whole idea is wrong. The GNU C dialect makes bitfields signed by default, regardless of machine type. Making any machine inconsistent in this regard is bad for portability. I chose to make bitfields signed by default because this is consistent with the way ordinary variables are handled: `int' equals `signed int'. If there is a good reason to prefer making bitfields unsigned by default, it cannot have anything to do with the choice of machine. If the reason is good enough, we should change the convention for all machines. -- rms, 20 July 1991. */ #define OPTIMIZATION_OPTIONS(LEVEL) \ do { \ if (LEVEL) \ { \ flag_omit_frame_pointer = 1; \ } \ } while (0) /* If -m88100 is in effect, add -D__m88100__; similarly for -m88110. Here, the CPU_DEFAULT is assumed to be -m88100. */ #undef CPP_SPEC #define CPP_SPEC "%{!m88000:%{!m88100:%{m88110:-D__m88110__}}} \ %{!m88000:%{!m88110:-D__m88100__}}" /* LIB_SPEC, LINK_SPEC, and STARTFILE_SPEC defined in svr3.h. ASM_SPEC, ASM_FINAL_SPEC, LIB_SPEC, LINK_SPEC, and STARTFILE_SPEC redefined in svr4.h. CPP_SPEC, ASM_SPEC, ASM_FINAL_SPEC, LIB_SPEC, LINK_SPEC, and STARTFILE_SPEC redefined in m88kdgux.h. */ /*** Run-time Target Specification ***/ /* Names to predefine in the preprocessor for this target machine. Redefined in m88kv3.h, m88kv4.h, m88kdgux.h, and m88kluna.h. */ #define CPP_PREDEFINES "-Dm88000 -Dm88k -Dunix -D__CLASSIFY_TYPE__=2 -Asystem(unix) -Acpu(m88k) -Amachine(m88k)" #define TARGET_VERSION fprintf (stderr, " (%s%s)", \ VERSION_INFO1, VERSION_INFO2) /* Print subsidiary information on the compiler version in use. Redefined in m88kv4.h, and m88kluna.h. */ #define VERSION_INFO1 "88open OCS/BCS, " #define VERSION_INFO2 "12/16/92" #define VERSION_STRING version_string #define TM_SCCS_ID "@(#)m88k.h 2.3.3.2 12/16/92 08:26:09" /* Run-time compilation parameters selecting different hardware subsets. */ /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */ #define MASK_88100 0x00000001 /* Target m88100 */ #define MASK_88110 0x00000002 /* Target m88110 */ #define MASK_OCS_DEBUG_INFO 0x00000004 /* Emit .tdesc info */ #define MASK_OCS_FRAME_POSITION 0x00000008 /* Debug frame = CFA, not r30 */ #define MASK_SVR4 0x00000010 /* Target is AT&T System V.4 */ #define MASK_NO_UNDERSCORES 0x00000040 /* Don't emit a leading `_' */ #define MASK_BIG_PIC 0x00000080 /* PIC with large got-rel's -fPIC */ #define MASK_TRAP_LARGE_SHIFT 0x00000100 /* Trap if shift not <= 31 */ #define MASK_HANDLE_LARGE_SHIFT 0x00000200 /* Handle shift count >= 32 */ #define MASK_CHECK_ZERO_DIV 0x00000400 /* Check for int div. by 0 */ #define MASK_USE_DIV 0x00000800 /* No signed div. checks */ #define MASK_IDENTIFY_REVISION 0x00001000 /* Emit ident, with GCC rev */ #define MASK_WARN_PASS_STRUCT 0x00002000 /* Warn about passed structs */ #define MASK_OPTIMIZE_ARG_AREA 0x00004000 /* Save stack space */ #define MASK_NO_SERIALIZE_VOLATILE 0x00008000 /* Serialize volatile refs */ #define MASK_88000 (MASK_88100 | MASK_88110) #define MASK_EITHER_LARGE_SHIFT (MASK_TRAP_LARGE_SHIFT | \ MASK_HANDLE_LARGE_SHIFT) #define TARGET_88100 ((target_flags & MASK_88000) == MASK_88100) #define TARGET_88110 ((target_flags & MASK_88000) == MASK_88110) #define TARGET_88000 ((target_flags & MASK_88000) == MASK_88000) #define TARGET_OCS_DEBUG_INFO (target_flags & MASK_OCS_DEBUG_INFO) #define TARGET_OCS_FRAME_POSITION (target_flags & MASK_OCS_FRAME_POSITION) #define TARGET_SVR4 (target_flags & MASK_SVR4) #define TARGET_NO_UNDERSCORES (target_flags & MASK_NO_UNDERSCORES) #define TARGET_BIG_PIC (target_flags & MASK_BIG_PIC) #define TARGET_TRAP_LARGE_SHIFT (target_flags & MASK_TRAP_LARGE_SHIFT) #define TARGET_HANDLE_LARGE_SHIFT (target_flags & MASK_HANDLE_LARGE_SHIFT) #define TARGET_CHECK_ZERO_DIV (target_flags & MASK_CHECK_ZERO_DIV) #define TARGET_USE_DIV (target_flags & MASK_USE_DIV) #define TARGET_IDENTIFY_REVISION (target_flags & MASK_IDENTIFY_REVISION) #define TARGET_WARN_PASS_STRUCT (target_flags & MASK_WARN_PASS_STRUCT) #define TARGET_OPTIMIZE_ARG_AREA (target_flags & MASK_OPTIMIZE_ARG_AREA) #define TARGET_SERIALIZE_VOLATILE (!(target_flags & MASK_NO_SERIALIZE_VOLATILE)) #define TARGET_EITHER_LARGE_SHIFT (target_flags & MASK_EITHER_LARGE_SHIFT) /* Redefined in m88kv3.h,m88kv4.h, and m88kdgux.h. */ #define TARGET_DEFAULT (MASK_CHECK_ZERO_DIV) #define CPU_DEFAULT MASK_88100 #define TARGET_SWITCHES \ { \ { "88110", MASK_88110 }, \ { "88100", MASK_88100 }, \ { "88000", MASK_88000 }, \ { "ocs-debug-info", MASK_OCS_DEBUG_INFO }, \ { "no-ocs-debug-info", -MASK_OCS_DEBUG_INFO }, \ { "ocs-frame-position", MASK_OCS_FRAME_POSITION }, \ { "no-ocs-frame-position", -MASK_OCS_FRAME_POSITION }, \ { "svr4", MASK_SVR4 }, \ { "svr3", -MASK_SVR4 }, \ { "no-underscores", MASK_NO_UNDERSCORES }, \ { "big-pic", MASK_BIG_PIC }, \ { "trap-large-shift", MASK_TRAP_LARGE_SHIFT }, \ { "handle-large-shift", MASK_HANDLE_LARGE_SHIFT }, \ { "check-zero-division", MASK_CHECK_ZERO_DIV }, \ { "no-check-zero-division", -MASK_CHECK_ZERO_DIV }, \ { "use-div-instruction", MASK_USE_DIV }, \ { "identify-revision", MASK_IDENTIFY_REVISION }, \ { "warn-passed-structs", MASK_WARN_PASS_STRUCT }, \ { "optimize-arg-area", MASK_OPTIMIZE_ARG_AREA }, \ { "no-optimize-arg-area", -MASK_OPTIMIZE_ARG_AREA }, \ { "no-serialize-volatile", MASK_NO_SERIALIZE_VOLATILE }, \ { "serialize-volatile", -MASK_NO_SERIALIZE_VOLATILE }, \ SUBTARGET_SWITCHES \ /* Default switches */ \ { "", TARGET_DEFAULT }, \ } /* Redefined in m88kdgux.h. */ #define SUBTARGET_SWITCHES /* Macro to define table for command options with values. */ #define TARGET_OPTIONS { { "short-data-", &m88k_short_data }, \ { "version-", &m88k_version } } /* Do any checking or such that is needed after processing the -m switches. */ #define OVERRIDE_OPTIONS \ do { \ register int i; \ \ if ((target_flags & MASK_88000) == 0) \ target_flags |= CPU_DEFAULT; \ \ m88k_cpu = (TARGET_88000 ? CPU_M88000 \ : (TARGET_88100 ? CPU_M88100 : CPU_M88110)); \ \ if (TARGET_BIG_PIC) \ flag_pic = 2; \ \ if ((target_flags & MASK_EITHER_LARGE_SHIFT) == MASK_EITHER_LARGE_SHIFT) \ error ("-mtrap-large-shift and -mhandle-large-shift are incompatible");\ \ m88k_version_0300 = (m88k_version != 0 \ && strcmp (m88k_version, "03.00") >= 0); \ \ if (VERSION_0300_SYNTAX) \ { \ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ reg_names[i]--; \ m88k_pound_sign = "#"; \ if (m88k_version == 0) \ m88k_version = VERSION_0400_SYNTAX ? "04.00" : "03.00"; \ else if (strcmp (m88k_version, "03.00") < 0) \ error ("Specified assembler version (%s) is less that 03.00", \ m88k_version); \ } \ \ m88k_version_0300 = (m88k_version != 0 \ && strcmp (m88k_version, "03.00") >= 0); \ \ if (m88k_short_data) \ { \ char *p = m88k_short_data; \ while (*p) \ if (*p >= '0' && *p <= '9') \ p++; \ else \ { \ error ("Invalid option `-mshort-data-%s'", m88k_short_data); \ break; \ } \ m88k_gp_threshold = atoi (m88k_short_data); \ if (flag_pic) \ error ("-mshort-data-%s and PIC are incompatible", m88k_short_data); \ } \ } while (0) /*** Storage Layout ***/ /* Sizes in bits of the various types. */ #define CHAR_TYPE_SIZE 8 #define SHORT_TYPE_SIZE 16 #define INT_TYPE_SIZE 32 #define LONG_TYPE_SIZE 32 #define LONG_LONG_TYPE_SIZE 64 #define FLOAT_TYPE_SIZE 32 #define DOUBLE_TYPE_SIZE 64 #define LONG_DOUBLE_TYPE_SIZE 64 /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. Somewhat arbitrary. It matches the bit field patterns. */ #define BITS_BIG_ENDIAN 1 /* Define this if most significant byte of a word is the lowest numbered. That is true on the m88000. */ #define BYTES_BIG_ENDIAN 1 /* Define this if most significant word of a multiword number is the lowest numbered. For the m88000 we can decide arbitrarily since there are no machine instructions for them. */ #define WORDS_BIG_ENDIAN 1 /* Number of bits in an addressable storage unit */ #define BITS_PER_UNIT 8 /* Width in bits of a "word", which is the contents of a machine register. Note that this is not necessarily the width of data type `int'; if using 16-bit ints on a 68000, this would still be 32. But on a machine with 16-bit registers, this would be 16. */ #define BITS_PER_WORD 32 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 4 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ #define POINTER_SIZE 32 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ #define PARM_BOUNDARY 32 /* Largest alignment for stack parameters (if greater than PARM_BOUNDARY). */ #define MAX_PARM_BOUNDARY 64 /* Boundary (in *bits*) on which stack pointer should be aligned. */ #define STACK_BOUNDARY 128 /* Allocation boundary (in *bits*) for the code of a function. On the m88100, it is desirable to align to a cache line. However, SVR3 targets only provided 8 byte alignment. The m88110 cache is small, so align to an 8 byte boundary. Pack code tightly when compiling crtstuff.c. */ #define FUNCTION_BOUNDARY (flag_inhibit_size_directive ? 32 : \ (TARGET_88100 && TARGET_SVR4 ? 128 : 64)) /* No data type wants to be aligned rounder than this. */ #define BIGGEST_ALIGNMENT 64 /* The best alignment to use in cases where we have a choice. */ #define FASTEST_ALIGNMENT (TARGET_88100 ? 32 : 64) /* Make strings 4/8 byte aligned so strcpy from constants will be faster. */ #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ ((TREE_CODE (EXP) == STRING_CST \ && (ALIGN) < FASTEST_ALIGNMENT) \ ? FASTEST_ALIGNMENT : (ALIGN)) /* Make arrays of chars 4/8 byte aligned for the same reasons. */ #define DATA_ALIGNMENT(TYPE, ALIGN) \ (TREE_CODE (TYPE) == ARRAY_TYPE \ && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) /* Alignment of field after `int : 0' in a structure. Ignored with PCC_BITFIELD_TYPE_MATTERS. */ /* #define EMPTY_FIELD_BOUNDARY 8 */ /* Every structure's size must be a multiple of this. */ #define STRUCTURE_SIZE_BOUNDARY 8 /* Set this nonzero if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 1 /* A bitfield declared as `int' forces `int' alignment for the struct. */ #define PCC_BITFIELD_TYPE_MATTERS 1 /* Maximum size (in bits) to use for the largest integral type that replaces a BLKmode type. */ /* #define MAX_FIXED_MODE_SIZE 0 */ /* Check a `double' value for validity for a particular machine mode. This is defined to avoid crashes outputting certain constants. Since we output the number in hex, the assembler won't choke on it. */ /* #define CHECK_FLOAT_VALUE(MODE,VALUE) */ /* A code distinguishing the floating point format of the target machine. */ /* #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT */ /*** Register Usage ***/ /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. The m88100 has a General Register File (GRF) of 32 32-bit registers. The m88110 adds an Extended Register File (XRF) of 32 80-bit registers. */ #define FIRST_PSEUDO_REGISTER 64 #define FIRST_EXTENDED_REGISTER 32 /* General notes on extended registers, their use and misuse. Possible good uses: spill area instead of memory. -waste if only used once floating point calculations -probably a waste unless we have run out of general purpose registers freeing up general purpose registers -e.g. may be able to have more loop invariants if floating point is moved into extended registers. I've noticed wasteful moves into and out of extended registers; e.g. a load into x21, then inside a loop a move into r24, then r24 used as input to an fadd. Why not just load into r24 to begin with? Maybe the new cse.c will address this. This wastes a move, but the load,store and move could have been saved had extended registers been used throughout. E.g. in the code following code, if z and xz are placed in extended registers, there is no need to save preserve registers. long c=1,d=1,e=1,f=1,g=1,h=1,i=1,j=1,k; double z=0,xz=4.5; foo(a,b) long a,b; { while (a < b) { k = b + c + d + e + f + g + h + a + i + j++; z += xz; a++; } printf("k= %d; z=%f;\n", k, z); } I've found that it is possible to change the constraints (putting * before the 'r' constraints int the fadd.ddd instruction) and get the entire addition and store to go into extended registers. However, this also forces simple addition and return of floating point arguments to a function into extended registers. Not the correct solution. Found the following note in local-alloc.c which may explain why I can't get both registers to be in extended registers since two are allocated in local-alloc and one in global-alloc. Doesn't explain (I don't believe) why an extended register is used instead of just using the preserve register. from local-alloc.c: We have provision to exempt registers, even when they are contained within the block, that can be tied to others that are not contained in it. This is so that global_alloc could process them both and tie them then. But this is currently disabled since tying in global_alloc is not yet implemented. The explanation of why the preserved register is not used is as follows, I believe. The registers are being allocated in order. Tying is not done so efficiently, so when it comes time to do the first allocation, there are no registers left to use without spilling except extended registers. Then when the next pseudo register needs a hard reg, there are still no registers to be had for free, but this one must be a GRF reg instead of an extended reg, so a preserve register is spilled. Thus the move from extended to GRF is necessitated. I do not believe this can be 'fixed' through the config/*m88k* files. gcc seems to sometimes make worse use of register allocation -- not counting moves -- whenever extended registers are present. For example in the whetstone, the simple for loop (slightly modified) for(i = 1; i <= n1; i++) { x1 = (x1 + x2 + x3 - x4) * t; x2 = (x1 + x2 - x3 + x4) * t; x3 = (x1 - x2 + x3 + x4) * t; x4 = (x1 + x2 + x3 + x4) * t; } in general loads the high bits of the addresses of x2-x4 and i into registers outside the loop. Whenever extended registers are used, it loads all of these inside the loop. My conjecture is that since the 88110 has so many registers, and gcc makes no distinction at this point -- just that they are not fixed, that in loop.c it believes it can expect a number of registers to be available. Then it allocates 'too many' in local-alloc which causes problems later. 'Too many' are allocated because a large portion of the registers are extended registers and cannot be used for certain purposes ( e.g. hold the address of a variable). When this loop is compiled on its own, the problem does not occur. I don't know the solution yet, though it is probably in the base sources. Possibly a different way to calculate "threshold". */ /* 1 for registers that have pervasive standard uses and are not available for the register allocator. Registers r14-r25 and x22-x29 are expected to be preserved across function calls. On the 88000, the standard uses of the General Register File (GRF) are: Reg 0 = Pseudo argument pointer (hardware fixed to 0). Reg 1 = Subroutine return pointer (hardware). Reg 2-9 = Parameter registers (OCS). Reg 10 = OCS reserved temporary. Reg 11 = Static link if needed [OCS reserved temporary]. Reg 12 = Address of structure return (OCS). Reg 13 = OCS reserved temporary. Reg 14-25 = Preserved register set. Reg 26-29 = Reserved by OCS and ABI. Reg 30 = Frame pointer (Common use). Reg 31 = Stack pointer. The following follows the current 88open UCS specification for the Extended Register File (XRF): Reg 32 = x0 Always equal to zero Reg 33-53 = x1-x21 Temporary registers (Caller Save) Reg 54-61 = x22-x29 Preserver registers (Callee Save) Reg 62-63 = x30-x31 Reserved for future ABI use. Note: The current 88110 extended register mapping is subject to change. The bias towards caller-save registers is based on the presumption that memory traffic can potentially be reduced by allowing the "caller" to save only that part of the register which is actually being used. (i.e. don't do a st.x if a st.d is sufficient). Also, in scientific code (a.k.a. Fortran), the large number of variables defined in common blocks may require that almost all registers be saved across calls anyway. */ #define FIXED_REGISTERS \ {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1} /* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. */ #define CALL_USED_REGISTERS \ {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1} /* Macro to conditionally modify fixed_regs/call_used_regs. */ #define CONDITIONAL_REGISTER_USAGE \ { \ if (! TARGET_88110) \ { \ register int i; \ for (i = FIRST_EXTENDED_REGISTER; i < FIRST_PSEUDO_REGISTER; i++) \ { \ fixed_regs[i] = 1; \ call_used_regs[i] = 1; \ } \ } \ if (flag_pic) \ { \ /* Current hack to deal with -fpic -O2 problems. */ \ fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ global_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ } \ } /* These interfaces that don't apply to the m88000. */ /* OVERLAPPING_REGNO_P(REGNO) 0 */ /* INSN_CLOBBERS_REGNO_P(INSN, REGNO) 0 */ /* PRESERVE_DEATH_INFO_REGNO_P(REGNO) 0 */ /* True if register is an extended register. */ #define XRF_REGNO_P(N) ((N) < FIRST_PSEUDO_REGISTER && (N) >= FIRST_EXTENDED_REGISTER) /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. On the m88000, GRF registers hold 32-bits and XRF registers hold 80-bits. An XRF register can hold any mode, but two GRF registers are required for larger modes. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ (XRF_REGNO_P (REGNO) \ ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. For double integers, we never put the value into an odd register so that the operators don't run into the situation where the high part of one of the inputs is the low part of the result register. (It's ok if the output registers are the same as the input registers.) The XRF registers can hold all modes, but only DF and SF modes can be manipulated in these registers. The compiler should be allowed to use these as a fast spill area. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ (XRF_REGNO_P(REGNO) \ ? (TARGET_88110 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ : (((MODE) != DImode && (MODE) != DFmode && (MODE) != DCmode) \ || ((REGNO) & 1) == 0)) /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. */ #define MODES_TIEABLE_P(MODE1, MODE2) \ (((MODE1) == DFmode || (MODE1) == DCmode || (MODE1) == DImode \ || (TARGET_88110 && GET_MODE_CLASS (MODE1) == MODE_FLOAT)) \ == ((MODE2) == DFmode || (MODE2) == DCmode || (MODE2) == DImode \ || (TARGET_88110 && GET_MODE_CLASS (MODE2) == MODE_FLOAT))) /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ /* the m88000 pc isn't overloaded on a register that the compiler knows about. */ /* #define PC_REGNUM */ /* Register to use for pushing function arguments. */ #define STACK_POINTER_REGNUM 31 /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM 30 /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM 0 /* Register used in cases where a temporary is known to be safe to use. */ #define TEMP_REGNUM 10 /* Register in which static-chain is passed to a function. */ #define STATIC_CHAIN_REGNUM 11 /* Register in which address to store a structure value is passed to a function. */ #define STRUCT_VALUE_REGNUM 12 /* Register to hold the addressing base for position independent code access to data items. */ #define PIC_OFFSET_TABLE_REGNUM 25 /* Order in which registers are preferred (most to least). Use temp registers, then param registers top down. Preserve registers are top down to maximize use of double memory ops for register save. The 88open reserved registers (r26-r29 and x30-x31) may commonly be used in most environments with the -fcall-used- or -fcall-saved- options. */ #define REG_ALLOC_ORDER \ { \ 13, 12, 11, 10, 29, 28, 27, 26, \ 62, 63, 9, 8, 7, 6, 5, 4, \ 3, 2, 1, 53, 52, 51, 50, 49, \ 48, 47, 46, 45, 44, 43, 42, 41, \ 40, 39, 38, 37, 36, 35, 34, 33, \ 25, 24, 23, 22, 21, 20, 19, 18, \ 17, 16, 15, 14, 61, 60, 59, 58, \ 57, 56, 55, 54, 30, 31, 0, 32} /* Order for leaf functions. */ #define REG_LEAF_ALLOC_ORDER \ { \ 9, 8, 7, 6, 13, 12, 11, 10, \ 29, 28, 27, 26, 62, 63, 5, 4, \ 3, 2, 0, 53, 52, 51, 50, 49, \ 48, 47, 46, 45, 44, 43, 42, 41, \ 40, 39, 38, 37, 36, 35, 34, 33, \ 25, 24, 23, 22, 21, 20, 19, 18, \ 17, 16, 15, 14, 61, 60, 59, 58, \ 57, 56, 55, 54, 30, 31, 1, 32} /* Switch between the leaf and non-leaf orderings. The purpose is to avoid write-over scoreboard delays between caller and callee. */ #define ORDER_REGS_FOR_LOCAL_ALLOC \ { \ static int leaf[] = REG_LEAF_ALLOC_ORDER; \ static int nonleaf[] = REG_ALLOC_ORDER; \ \ bcopy (regs_ever_live[1] ? nonleaf : leaf, reg_alloc_order, \ FIRST_PSEUDO_REGISTER * sizeof (int)); \ } /*** Register Classes ***/ /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. One of the classes must always be named ALL_REGS and include all hard regs. If there is more than one class, another class must be named NO_REGS and contain no registers. The name GENERAL_REGS must be the name of a class (or an alias for another name such as ALL_REGS). This is the class of registers that is allowed by "g" or "r" in a register constraint. Also, registers outside this class are allocated only when instructions express preferences for them. The classes must be numbered in nondecreasing order; that is, a larger-numbered class must never be contained completely in a smaller-numbered class. For any two classes, it is very desirable that there be another class that represents their union. */ /* The m88000 hardware has two kinds of registers. In addition, we denote the arg pointer as a separate class. */ enum reg_class { NO_REGS, AP_REG, XRF_REGS, GENERAL_REGS, AGRF_REGS, XGRF_REGS, ALL_REGS, LIM_REG_CLASSES }; #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES {"NO_REGS", "AP_REG", "XRF_REGS", "GENERAL_REGS", \ "AGRF_REGS", "XGRF_REGS", "ALL_REGS" } /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS {{0x00000000, 0x00000000}, \ {0x00000001, 0x00000000}, \ {0x00000000, 0xffffffff}, \ {0xfffffffe, 0x00000000}, \ {0xffffffff, 0x00000000}, \ {0xfffffffe, 0xffffffff}, \ {0xffffffff, 0xffffffff}} /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ #define REGNO_REG_CLASS(REGNO) \ ((REGNO) ? ((REGNO < 32) ? GENERAL_REGS : XRF_REGS) : AP_REG) /* The class value for index registers, and the one for base regs. */ #define BASE_REG_CLASS AGRF_REGS #define INDEX_REG_CLASS GENERAL_REGS /* Get reg_class from a letter such as appears in the machine description. For the 88000, the following class/letter is defined for the XRF: x - Extended register file */ #define REG_CLASS_FROM_LETTER(C) \ (((C) == 'x') ? XRF_REGS : NO_REGS) /* Macros to check register numbers against specific register classes. These assume that REGNO is a hard or pseudo reg number. They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. Since they use reg_renumber, they are safe only once reg_renumber has been allocated, which happens in local-alloc.c. */ #define REGNO_OK_FOR_BASE_P(REGNO) \ ((REGNO) < FIRST_EXTENDED_REGISTER \ || (unsigned) reg_renumber[REGNO] < FIRST_EXTENDED_REGISTER) #define REGNO_OK_FOR_INDEX_P(REGNO) \ (((REGNO) && (REGNO) < FIRST_EXTENDED_REGISTER) \ || (unsigned) reg_renumber[REGNO] < FIRST_EXTENDED_REGISTER) /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines in some cases it is preferable to use a more restrictive class. Double constants should be in a register iff they can be made cheaply. */ #define PREFERRED_RELOAD_CLASS(X,CLASS) \ (CONSTANT_P(X) && (CLASS == XRF_REGS) ? NO_REGS : (CLASS)) /* Return the register class of a scratch register needed to load IN into a register of class CLASS in MODE. On the m88k, when PIC, we need a temporary when loading some addresses into a register. */ #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ ((flag_pic \ && GET_CODE (IN) == CONST \ && GET_CODE (XEXP (IN, 0)) == PLUS \ && GET_CODE (XEXP (XEXP (IN, 0), 0)) == CONST_INT \ && ! SMALL_INT (XEXP (XEXP (IN, 0), 1))) ? GENERAL_REGS : NO_REGS) /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ ((((CLASS) == XRF_REGS) ? 1 \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) /* Letters in the range `I' through `P' in a register constraint string can be used to stand for particular ranges of immediate operands. The C expression is true iff C is a known letter and VALUE is appropriate for that letter. For the m88000, the following constants are used: `I' requires a non-negative 16-bit value. `J' requires a non-positive 16-bit value. `K' requires a non-negative value < 32. `L' requires a constant with only the upper 16-bits set. `M' requires constant values that can be formed with `set'. `N' requires a negative value. `O' requires zero. `P' requires a non-negative value. */ /* Quick tests for certain values. */ #define SMALL_INT(X) (SMALL_INTVAL (INTVAL (X))) #define SMALL_INTVAL(I) ((unsigned) (I) < 0x10000) #define ADD_INT(X) (ADD_INTVAL (INTVAL (X))) #define ADD_INTVAL(I) ((unsigned) (I) + 0xffff < 0x1ffff) #define POWER_OF_2(I) ((I) && POWER_OF_2_or_0(I)) #define POWER_OF_2_or_0(I) (((I) & ((unsigned)(I) - 1)) == 0) #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? SMALL_INTVAL (VALUE) \ : (C) == 'J' ? SMALL_INTVAL (-(VALUE)) \ : (C) == 'K' ? (unsigned)(VALUE) < 32 \ : (C) == 'L' ? ((VALUE) & 0xffff) == 0 \ : (C) == 'M' ? integer_ok_for_set (VALUE) \ : (C) == 'N' ? (VALUE) < 0 \ : (C) == 'O' ? (VALUE) == 0 \ : (C) == 'P' ? (VALUE) >= 0 \ : 0) /* Similar, but for floating constants, and defining letters G and H. Here VALUE is the CONST_DOUBLE rtx itself. For the m88000, the constraints are: `G' requires zero, and `H' requires one or two. */ #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'G' ? (CONST_DOUBLE_HIGH (VALUE) == 0 \ && CONST_DOUBLE_LOW (VALUE) == 0) \ : 0) /* Letters in the range `Q' through `U' in a register constraint string may be defined in a machine-dependent fashion to stand for arbitrary operand types. For the m88k, `Q' handles addresses in a call context. */ #define EXTRA_CONSTRAINT(OP, C) \ ((C) == 'Q' ? symbolic_address_p (OP) : 0) /*** Describing Stack Layout ***/ /* Define this if pushing a word on the stack moves the stack pointer to a smaller address. */ #define STACK_GROWS_DOWNWARD /* Define this if the addresses of local variable slots are at negative offsets from the frame pointer. */ /* #define FRAME_GROWS_DOWNWARD */ /* Offset from the frame pointer to the first local variable slot to be allocated. For the m88k, the debugger wants the return address (r1) stored at location r30+4, and the previous frame pointer stored at location r30. */ #define STARTING_FRAME_OFFSET 8 /* If we generate an insn to push BYTES bytes, this says how many the stack pointer really advances by. The m88k has no push instruction. */ /* #define PUSH_ROUNDING(BYTES) */ /* If defined, the maximum amount of space required for outgoing arguments will be computed and placed into the variable `current_function_outgoing_args_size'. No space will be pushed onto the stack for each call; instead, the function prologue should increase the stack frame size by this amount. */ #define ACCUMULATE_OUTGOING_ARGS /* Offset from the stack pointer register to the first location at which outgoing arguments are placed. Use the default value zero. */ /* #define STACK_POINTER_OFFSET 0 */ /* Offset of first parameter from the argument pointer register value. Using an argument pointer, this is 0 for the m88k. GCC knows how to eliminate the argument pointer references if necessary. */ #define FIRST_PARM_OFFSET(FNDECL) 0 /* Define this if functions should assume that stack space has been allocated for arguments even when their values are passed in registers. The value of this macro is the size, in bytes, of the area reserved for arguments passed in registers. This space can either be allocated by the caller or be a part of the machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says which. */ #define REG_PARM_STACK_SPACE(FNDECL) 32 /* Define this macro if REG_PARM_STACK_SPACE is defined but stack parameters don't skip the area specified by REG_PARM_STACK_SPACE. Normally, when a parameter is not passed in registers, it is placed on the stack beyond the REG_PARM_STACK_SPACE area. Defining this macro suppresses this behavior and causes the parameter to be passed on the stack in its natural location. */ #define STACK_PARMS_IN_REG_PARM_AREA /* Define this if it is the responsibility of the caller to allocate the area reserved for arguments passed in registers. If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect of this macro is to determine whether the space is included in `current_function_outgoing_args_size'. */ /* #define OUTGOING_REG_PARM_STACK_SPACE */ /* Offset from the stack pointer register to an item dynamically allocated on the stack, e.g., by `alloca'. The default value for this macro is `STACK_POINTER_OFFSET' plus the length of the outgoing arguments. The default is correct for most machines. See `function.c' for details. */ /* #define STACK_DYNAMIC_OFFSET(FUNDECL) ... */ /* Value is the number of bytes of arguments automatically popped when returning from a subroutine call. FUNTYPE is the data type of the function (as a tree), or for a library call it is an identifier node for the subroutine name. SIZE is the number of bytes of arguments passed on the stack. */ #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0 /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ gen_rtx (REG, \ TYPE_MODE (VALTYPE) == BLKmode ? SImode : TYPE_MODE (VALTYPE), \ 2) /* Define this if it differs from FUNCTION_VALUE. */ /* #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) ... */ /* Disable the promotion of some structures and unions to registers. */ #define RETURN_IN_MEMORY(TYPE) \ (TYPE_MODE (TYPE) == BLKmode \ || ((TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE(TYPE) == UNION_TYPE) \ && !(TYPE_MODE (TYPE) == SImode \ || (TYPE_MODE (TYPE) == BLKmode \ && TYPE_ALIGN (TYPE) == BITS_PER_WORD \ && int_size_in_bytes (TYPE) == UNITS_PER_WORD)))) /* Don't default to pcc-struct-return, because we have already specified exactly how to return structures in the RETURN_IN_MEMORY macro. */ #define DEFAULT_PCC_STRUCT_RETURN 0 /* Define how to find the value returned by a library function assuming the value has mode MODE. */ #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 2) /* True if N is a possible register number for a function value as seen by the caller. */ #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2) /* Determine whether a function argument is passed in a register, and which register. See m88k.c. */ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ m88k_function_arg (CUM, MODE, TYPE, NAMED) /* Define this if it differs from FUNCTION_ARG. */ /* #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) ... */ /* A C expression for the number of words, at the beginning of an argument, must be put in registers. The value must be zero for arguments that are passed entirely in registers or that are entirely pushed on the stack. */ #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0) /* A C expression that indicates when an argument must be passed by reference. If nonzero for an argument, a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself. The pointer is passed in whatever way is appropriate for passing a pointer to that type. */ #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) (0) /* A C type for declaring a variable that is used as the first argument of `FUNCTION_ARG' and other related values. It suffices to count the number of words of argument so far. */ #define CUMULATIVE_ARGS int /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0) /* A C statement (sans semicolon) to update the summarizer variable CUM to advance past an argument in the argument list. The values MODE, TYPE and NAMED describe that argument. Once this is done, the variable CUM is suitable for analyzing the *following* argument with `FUNCTION_ARG', etc. (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ do { \ enum machine_mode __mode = (TYPE) ? TYPE_MODE (TYPE) : (MODE); \ if ((CUM & 1) \ && (__mode == DImode || __mode == DFmode \ || ((TYPE) && TYPE_ALIGN (TYPE) > BITS_PER_WORD))) \ CUM++; \ CUM += (((__mode != BLKmode) \ ? GET_MODE_SIZE (MODE) : int_size_in_bytes (TYPE)) \ + 3) / 4; \ } while (0) /* True if N is a possible register number for function argument passing. On the m88000, these are registers 2 through 9. */ #define FUNCTION_ARG_REGNO_P(N) ((N) <= 9 && (N) >= 2) /* A C expression which determines whether, and in which direction, to pad out an argument with extra space. The value should be of type `enum direction': either `upward' to pad above the argument, `downward' to pad below, or `none' to inhibit padding. This macro does not control the *amount* of padding; that is always just enough to reach the next multiple of `FUNCTION_ARG_BOUNDARY'. */ #define FUNCTION_ARG_PADDING(MODE, TYPE) \ ((MODE) == BLKmode \ || ((TYPE) && (TREE_CODE (TYPE) == RECORD_TYPE \ || TREE_CODE (TYPE) == UNION_TYPE)) \ ? upward : GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY ? downward : none) /* If defined, a C expression that gives the alignment boundary, in bits, of an argument with the specified mode and type. If it is not defined, `PARM_BOUNDARY' is used for all arguments. */ #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_SIZE (MODE)) <= PARM_BOUNDARY \ ? PARM_BOUNDARY : 2 * PARM_BOUNDARY) /* Generate necessary RTL for __builtin_saveregs(). ARGLIST is the argument list; see expr.c. */ #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) m88k_builtin_saveregs (ARGLIST) /* Generate the assembly code for function entry. */ #define FUNCTION_PROLOGUE(FILE, SIZE) m88k_begin_prologue(FILE, SIZE) /* Perform special actions at the point where the prologue ends. */ #define FUNCTION_END_PROLOGUE(FILE) m88k_end_prologue(FILE) /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. Redefined in m88kv3.h, m88kv4.h and m88kdgux.h. */ #define FUNCTION_PROFILER(FILE, LABELNO) \ output_function_profiler (FILE, LABELNO, "mcount", 1) /* Maximum length in instructions of the code output by FUNCTION_PROFILER. */ #define FUNCTION_PROFILER_LENGTH (5+3+1+5) /* Output assembler code to FILE to initialize basic-block profiling for the current module. LABELNO is unique to each instance. */ #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ output_function_block_profiler (FILE, LABELNO) /* Maximum length in instructions of the code output by FUNCTION_BLOCK_PROFILER. */ #define FUNCTION_BLOCK_PROFILER_LENGTH (3+5+2+5) /* Output assembler code to FILE to increment the count associated with the basic block number BLOCKNO. */ #define BLOCK_PROFILER(FILE, BLOCKNO) output_block_profiler (FILE, BLOCKNO) /* Maximum length in instructions of the code output by BLOCK_PROFILER. */ #define BLOCK_PROFILER_LENGTH 4 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, the stack pointer does not matter. The value is tested only in functions that have frame pointers. No definition is equivalent to always zero. */ #define EXIT_IGNORE_STACK (1) /* Generate the assembly code for function exit. */ #define FUNCTION_EPILOGUE(FILE, SIZE) m88k_end_epilogue(FILE, SIZE) /* Perform special actions at the point where the epilogue begins. */ #define FUNCTION_BEGIN_EPILOGUE(FILE) m88k_begin_epilogue(FILE) /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */ #define FRAME_POINTER_REQUIRED \ (frame_pointer_needed \ || (write_symbols != NO_DEBUG && !TARGET_OCS_FRAME_POSITION)) /* Definitions for register eliminations. We have two registers that can be eliminated on the m88k. First, the frame pointer register can often be eliminated in favor of the stack pointer register. Secondly, the argument pointer register can always be eliminated; it is replaced with either the stack or frame pointer. */ /* This is an array of structures. Each structure initializes one pair of eliminable registers. The "from" register number is given first, followed by "to". Eliminations of the same "from" register are listed in order of preference. */ #define ELIMINABLE_REGS \ {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} /* Given FROM and TO register numbers, say whether this elimination is allowed. */ #define CAN_ELIMINATE(FROM, TO) \ (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)) /* Define the offset between two registers, one to be eliminated, and the other its replacement, at the start of a routine. */ #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ { m88k_layout_frame (); \ if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ (OFFSET) = m88k_fp_offset; \ else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ (OFFSET) = m88k_stack_size - m88k_fp_offset; \ else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ (OFFSET) = m88k_stack_size; \ else \ abort (); \ } /*** Trampolines for Nested Functions ***/ /* Output assembler code for a block containing the constant parts of a trampoline, leaving space for the variable parts. This block is placed on the stack and filled in. It is aligned 0 mod 128 and those portions that are executed are constant. This should work for instruction caches that have cache lines up to the aligned amount (128 is arbitrary), provided no other code producer is attempting to play the same game. This of course is in violation of any number of 88open standards. */ #define TRAMPOLINE_TEMPLATE(FILE) \ { \ char buf[256]; \ static int labelno = 0; \ labelno++; \ ASM_GENERATE_INTERNAL_LABEL (buf, "LTRMP", labelno); \ /* Save the return address (r1) in the static chain reg (r11). */ \ fprintf (FILE, "\tor\t %s,%s,0\n", reg_names[11], reg_names[1]); \ /* Locate this block; transfer to the next instruction. */ \ fprintf (FILE, "\tbsr\t %s\n", &buf[1]); \ ASM_OUTPUT_INTERNAL_LABEL (FILE, "LTRMP", labelno); \ /* Save r10; use it as the relative pointer; restore r1. */ \ fprintf (FILE, "\tst\t %s,%s,24\n", reg_names[10], reg_names[1]); \ fprintf (FILE, "\tor\t %s,%s,0\n", reg_names[10], reg_names[1]); \ fprintf (FILE, "\tor\t %s,%s,0\n", reg_names[1], reg_names[11]); \ /* Load the function's address and go there. */ \ fprintf (FILE, "\tld\t %s,%s,32\n", reg_names[11], reg_names[10]); \ fprintf (FILE, "\tjmp.n\t %s\n", reg_names[11]); \ /* Restore r10 and load the static chain register. */ \ fprintf (FILE, "\tld.d\t %s,%s,24\n", reg_names[10], reg_names[10]); \ /* Storage: r10 save area, static chain, function address. */ \ ASM_OUTPUT_INT (FILE, const0_rtx); \ ASM_OUTPUT_INT (FILE, const0_rtx); \ ASM_OUTPUT_INT (FILE, const0_rtx); \ } /* Length in units of the trampoline for entering a nested function. This is really two components. The first 32 bytes are fixed and must be copied; the last 12 bytes are just storage that's filled in later. So for allocation purposes, it's 32+12 bytes, but for initialization purposes, it's 32 bytes. */ #define TRAMPOLINE_SIZE (32+12) /* Alignment required for a trampoline. 128 is used to find the beginning of a line in the instruction cache and to allow for instruction cache lines of up to 128 bytes. */ #define TRAMPOLINE_ALIGNMENT 128 /* Emit RTL insns to initialize the variable parts of a trampoline. FNADDR is an RTX for the address of the function's pure code. CXT is an RTX for the static chain value for the function. */ #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 40)), FNADDR); \ emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 36)), CXT); \ } /*** Library Subroutine Names ***/ /* Define this macro if GNU CC should generate calls to the System V (and ANSI C) library functions `memcpy' and `memset' rather than the BSD functions `bcopy' and `bzero'. */ #define TARGET_MEM_FUNCTIONS /*** Addressing Modes ***/ #define EXTRA_CC_MODES CCEVENmode #define EXTRA_CC_NAMES "CCEVEN" #define SELECT_CC_MODE(OP,X,Y) CCmode /* #define HAVE_POST_INCREMENT */ /* #define HAVE_POST_DECREMENT */ /* #define HAVE_PRE_DECREMENT */ /* #define HAVE_PRE_INCREMENT */ /* Recognize any constant value that is a valid address. */ #define CONSTANT_ADDRESS_P(X) \ (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ || GET_CODE (X) == HIGH) /* Maximum number of registers that can appear in a valid memory address. */ #define MAX_REGS_PER_ADDRESS 2 /* The condition for memory shift insns. */ #define SCALED_ADDRESS_P(ADDR) \ (GET_CODE (ADDR) == PLUS \ && (GET_CODE (XEXP (ADDR, 0)) == MULT \ || GET_CODE (XEXP (ADDR, 1)) == MULT)) /* Can the reference to X be made short? */ #define SHORT_ADDRESS_P(X,TEMP) \ ((TEMP) = (GET_CODE (X) == CONST ? get_related_value (X) : X), \ ((TEMP) && GET_CODE (TEMP) == SYMBOL_REF && SYMBOL_REF_FLAG (TEMP))) /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. On the m88000, a legitimate address has the form REG, REG+REG, REG+SMALLINT, REG+(REG*modesize) (REG[REG]), or SMALLINT. The register elimination process should deal with the argument pointer and frame pointer changing to REG+SMALLINT. */ #define LEGITIMATE_INDEX_P(X, MODE) \ ((GET_CODE (X) == CONST_INT \ && SMALL_INT (X)) \ || (REG_P (X) \ && REG_OK_FOR_INDEX_P (X)) \ || (GET_CODE (X) == MULT \ && REG_P (XEXP (X, 0)) \ && REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ && GET_CODE (XEXP (X, 1)) == CONST_INT \ && INTVAL (XEXP (X, 1)) == GET_MODE_SIZE (MODE))) #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { \ register rtx _x; \ if (REG_P (X)) \ { \ if (REG_OK_FOR_BASE_P (X)) \ goto ADDR; \ } \ else if (GET_CODE (X) == PLUS) \ { \ register rtx _x0 = XEXP (X, 0); \ register rtx _x1 = XEXP (X, 1); \ if ((flag_pic \ && _x0 == pic_offset_table_rtx \ && (flag_pic == 2 \ ? REG_P (_x1) \ : (GET_CODE (_x1) == SYMBOL_REF \ || GET_CODE (_x1) == LABEL_REF))) \ || (REG_P (_x0) \ && (REG_OK_FOR_BASE_P (_x0) \ && LEGITIMATE_INDEX_P (_x1, MODE))) \ || (REG_P (_x1) \ && (REG_OK_FOR_BASE_P (_x1) \ && LEGITIMATE_INDEX_P (_x0, MODE)))) \ goto ADDR; \ } \ else if (GET_CODE (X) == LO_SUM) \ { \ register rtx _x0 = XEXP (X, 0); \ register rtx _x1 = XEXP (X, 1); \ if (((REG_P (_x0) \ && REG_OK_FOR_BASE_P (_x0)) \ || (GET_CODE (_x0) == SUBREG \ && REG_P (SUBREG_REG (_x0)) \ && REG_OK_FOR_BASE_P (SUBREG_REG (_x0)))) \ && CONSTANT_P (_x1)) \ goto ADDR; \ } \ else if (GET_CODE (X) == CONST_INT \ && SMALL_INT (X)) \ goto ADDR; \ else if (SHORT_ADDRESS_P (X, _x)) \ goto ADDR; \ } /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions for each of them. The usual definition accepts all pseudo regs; the other rejects them unless they have been allocated suitable hard regs. The symbol REG_OK_STRICT causes the latter definition to be used. Most source files want to accept pseudo regs in the hope that they will get allocated to the class that the insn wants them to be in. Source files for reload pass need to be strict. After reload, it makes no difference, since pseudo regs have been eliminated by then. */ #ifndef REG_OK_STRICT /* Nonzero if X is a hard reg that can be used as an index or if it is a pseudo reg. Not the argument pointer. */ #define REG_OK_FOR_INDEX_P(X) \ (!XRF_REGNO_P(REGNO (X))) /* Nonzero if X is a hard reg that can be used as a base reg or if it is a pseudo reg. */ #define REG_OK_FOR_BASE_P(X) (REG_OK_FOR_INDEX_P (X)) #else /* Nonzero if X is a hard reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) /* Nonzero if X is a hard reg that can be used as a base reg. */ #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) #endif /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. OLDX is the address as it was before break_out_memory_refs was called. In some cases it is useful to look at this to decide what needs to be done. MODE and WIN are passed so that this macro can use GO_IF_LEGITIMATE_ADDRESS. It is always safe for this macro to do nothing. It exists to recognize opportunities to optimize the output. */ /* On the m88000, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ { \ if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \ copy_to_mode_reg (SImode, XEXP (X, 1))); \ if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \ copy_to_mode_reg (SImode, XEXP (X, 0))); \ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \ force_operand (XEXP (X, 0), 0)); \ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \ (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \ force_operand (XEXP (X, 1), 0)); \ if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ || GET_CODE (X) == LABEL_REF) \ (X) = legitimize_address (flag_pic, X, 0, 0); \ if (memory_address_p (MODE, X)) \ goto WIN; } /* Go to LABEL if ADDR (a legitimate address expression) has an effect that depends on the machine mode it is used for. On the the m88000 this is never true. */ #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) /* Nonzero if the constant value X is a legitimate general operand. It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ #define LEGITIMATE_CONSTANT_P(X) (1) /*** Condition Code Information ***/ /* C code for a data type which is used for declaring the `mdep' component of `cc_status'. It defaults to `int'. */ /* #define CC_STATUS_MDEP int */ /* A C expression to initialize the `mdep' field to "empty". */ /* #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0) */ /* Macro to zap the normal portions of CC_STATUS, but leave the machine dependent parts (ie, literal synthesis) alone. */ /* #define CC_STATUS_INIT_NO_MDEP \ (cc_status.flags = 0, cc_status.value1 = 0, cc_status.value2 = 0) */ /* When using a register to hold the condition codes, the cc_status mechanism cannot be used. */ #define NOTICE_UPDATE_CC(EXP, INSN) (0) /*** Miscellaneous Parameters ***/ /* Define the codes that are matched by predicates in m88k.c. */ #define PREDICATE_CODES \ {"move_operand", {SUBREG, REG, CONST_INT, LO_SUM, MEM}}, \ {"call_address_operand", {SUBREG, REG, SYMBOL_REF, LABEL_REF, CONST}}, \ {"arith_operand", {SUBREG, REG, CONST_INT}}, \ {"arith5_operand", {SUBREG, REG, CONST_INT}}, \ {"arith32_operand", {SUBREG, REG, CONST_INT}}, \ {"arith64_operand", {SUBREG, REG, CONST_INT}}, \ {"int5_operand", {CONST_INT}}, \ {"int32_operand", {CONST_INT}}, \ {"add_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_bbx_mask_operand", {SUBREG, REG, CONST_INT}}, \ {"real_or_0_operand", {SUBREG, REG, CONST_DOUBLE}}, \ {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ {"relop", {EQ, NE, LT, LE, GE, GT, LTU, LEU, GEU, GTU}}, \ {"even_relop", {EQ, LT, GT, LTU, GTU}}, \ {"odd_relop", { NE, LE, GE, LEU, GEU}}, \ {"partial_ccmode_register_operand", { SUBREG, REG}}, \ {"relop_no_unsigned", {EQ, NE, LT, LE, GE, GT}}, \ {"equality_op", {EQ, NE}}, \ {"pc_or_label_ref", {PC, LABEL_REF}}, /* The case table contains either words or branch instructions. This says which. We always claim that the vector is PC-relative. It is position independent when -fpic is used. */ #define CASE_VECTOR_INSNS (TARGET_88100 || flag_pic) /* An alias for a machine mode name. This is the machine mode that elements of a jump-table should have. */ #define CASE_VECTOR_MODE SImode /* Define this macro if jump-tables should contain relative addresses. */ #define CASE_VECTOR_PC_RELATIVE /* Define this if control falls through a `case' insn when the index value is out of range. This means the specified default-label is actually ignored by the `case' insn proper. */ /* #define CASE_DROPS_THROUGH */ /* Define this to be the smallest number of different values for which it is best to use a jump-table instead of a tree of conditional branches. The default is 4 for machines with a casesi instruction and 5 otherwise. The best 88110 number is around 7, though the exact number isn't yet known. A third alternative for the 88110 is to use a binary tree of bb1 instructions on bits 2/1/0 if the range is dense. This may not win very much though. */ #define CASE_VALUES_THRESHOLD (TARGET_88100 ? 4 : 7) /* Specify the tree operation to be used to convert reals to integers. */ #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR /* This is the kind of divide that is easiest to do in the general case. */ #define EASY_DIV_EXPR TRUNC_DIV_EXPR /* Define this as 1 if `char' should by default be signed; else as 0. */ #define DEFAULT_SIGNED_CHAR 1 /* The 88open ABI says size_t is unsigned int. */ #define SIZE_TYPE "unsigned int" /* Allow and ignore #sccs directives */ #define SCCS_DIRECTIVE /* Handle #pragma pack and sometimes #pragma weak. */ #define HANDLE_SYSV_PRAGMA /* Tell when to handle #pragma weak. This is only done for V.4. */ #define HANDLE_PRAGMA_WEAK TARGET_SVR4 /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ #define MOVE_MAX 8 /* Define if operations between registers always perform the operation on the full register even if a narrower mode is specified. */ #define WORD_REGISTER_OPERATIONS /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD will either zero-extend or sign-extend. The value of this macro should be the code that says which one of the two operations is implicitly done, NIL if none. */ #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Zero if access to memory by bytes is faster. */ #define SLOW_BYTE_ACCESS 1 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 /* Define this if addresses of constant functions shouldn't be put through pseudo regs where they can be cse'd. Desirable on machines where ordinary constants are expensive but a CALL with constant address is cheap. */ #define NO_FUNCTION_CSE /* Define this macro if an argument declared as `char' or `short' in a prototype should actually be passed as an `int'. In addition to avoiding errors in certain cases of mismatch, it also makes for better code on certain machines. */ #define PROMOTE_PROTOTYPES /* Define this macro if a float function always returns float (even in traditional mode). Redefined in m88kluna.h. */ #define TRADITIONAL_RETURN_FLOAT /* We assume that the store-condition-codes instructions store 0 for false and some other value for true. This is the value stored for true. */ #define STORE_FLAG_VALUE -1 /* Specify the machine mode that pointers have. After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ #define Pmode SImode /* A function address in a call instruction is a word address (for indexing purposes) so give the MEM rtx word mode. */ #define FUNCTION_MODE SImode /* A barrier will be aligned so account for the possible expansion. A volatile load may be preceded by a serializing instruction. Account for profiling code output at NOTE_INSN_PROLOGUE_END. Account for block profiling code at basic block boundaries. */ #define ADJUST_INSN_LENGTH(RTX, LENGTH) \ if (GET_CODE (RTX) == BARRIER \ || (TARGET_SERIALIZE_VOLATILE \ && GET_CODE (RTX) == INSN \ && GET_CODE (PATTERN (RTX)) == SET \ && ((GET_CODE (SET_SRC (PATTERN (RTX))) == MEM \ && MEM_VOLATILE_P (SET_SRC (PATTERN (RTX))))))) \ LENGTH += 1; \ else if (GET_CODE (RTX) == NOTE \ && NOTE_LINE_NUMBER (RTX) == NOTE_INSN_PROLOGUE_END) \ { \ if (profile_block_flag) \ LENGTH += FUNCTION_BLOCK_PROFILER_LENGTH; \ if (profile_flag) \ LENGTH += (FUNCTION_PROFILER_LENGTH + REG_PUSH_LENGTH \ + REG_POP_LENGTH); \ } \ else if (profile_block_flag \ && (GET_CODE (RTX) == CODE_LABEL \ || GET_CODE (RTX) == JUMP_INSN \ || (GET_CODE (RTX) == INSN \ && GET_CODE (PATTERN (RTX)) == SEQUENCE \ && GET_CODE (XVECEXP (PATTERN (RTX), 0, 0)) == JUMP_INSN)))\ LENGTH += BLOCK_PROFILER_LENGTH; /* Track the state of the last volatile memory reference. Clear the state with CC_STATUS_INIT for now. */ #define CC_STATUS_INIT m88k_volatile_code = '\0' /* Compute the cost of computing a constant rtl expression RTX whose rtx-code is CODE. The body of this macro is a portion of a switch statement. If the code is computed here, return it with a return statement. Otherwise, break from the switch. We assume that any 16 bit integer can easily be recreated, so we indicate 0 cost, in an attempt to get GCC not to optimize things like comparison against a constant. The cost of CONST_DOUBLE is zero (if it can be placed in an insn, it is as good as a register; since it can't be placed in any insn, it won't do anything in cse, but it will cause expand_binop to pass the constant to the define_expands). */ #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ case CONST_INT: \ if (SMALL_INT (RTX)) \ return 0; \ else if (SMALL_INTVAL (- INTVAL (RTX))) \ return 2; \ else if (classify_integer (SImode, INTVAL (RTX)) != m88k_oru_or) \ return 4; \ return 7; \ case HIGH: \ return 2; \ case CONST: \ case LABEL_REF: \ case SYMBOL_REF: \ if (flag_pic) \ return (flag_pic == 2) ? 11 : 8; \ return 5; \ case CONST_DOUBLE: \ return 0; /* Provide the costs of an addressing mode that contains ADDR. If ADDR is not a valid address, its cost is irrelevant. REG+REG is made slightly more expensive because it might keep a register live for longer than we might like. */ #define ADDRESS_COST(ADDR) \ (GET_CODE (ADDR) == REG ? 1 : \ GET_CODE (ADDR) == LO_SUM ? 1 : \ GET_CODE (ADDR) == HIGH ? 2 : \ GET_CODE (ADDR) == MULT ? 1 : \ GET_CODE (ADDR) != PLUS ? 4 : \ (REG_P (XEXP (ADDR, 0)) && REG_P (XEXP (ADDR, 1))) ? 2 : 1) /* Provide the costs of a rtl expression. This is in the body of a switch on CODE. */ #define RTX_COSTS(X,CODE,OUTER_CODE) \ case MEM: \ return COSTS_N_INSNS (2); \ case MULT: \ return COSTS_N_INSNS (3); \ case DIV: \ case UDIV: \ case MOD: \ case UMOD: \ return COSTS_N_INSNS (38); /* A C expressions returning the cost of moving data of MODE from a register to or from memory. This is more costly than between registers. */ #define MEMORY_MOVE_COST(MODE) 4 /* Provide the cost of a branch. Exact meaning under development. */ #define BRANCH_COST (TARGET_88100 ? 1 : 2) /* A C statement (sans semicolon) to update the integer variable COST based on the relationship between INSN that is dependent on DEP_INSN through the dependence LINK. The default is to make no adjustment to COST. On the m88k, ignore the cost of anti- and output-dependencies. On the m88100, a store can issue two cycles before the value (not the address) has finished computing. */ #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \ do { \ if (REG_NOTE_KIND (LINK) != 0) \ (COST) = 0; /* Anti or output dependence. */ \ else if (! TARGET_88100 \ && recog_memoized (INSN) >= 0 \ && get_attr_type (INSN) == TYPE_STORE \ && SET_SRC (PATTERN (INSN)) == SET_DEST (PATTERN (DEP_INSN))) \ (COST) -= 4; /* 88110 store reservation station. */ \ } while (0) /* Define this to be nonzero if the character `$' should be allowed by default in identifier names. */ #define DOLLARS_IN_IDENTIFIERS 1 /* Do not break .stabs pseudos into continuations. */ #define DBX_CONTIN_LENGTH 0 /*** Output of Assembler Code ***/ /* Control the assembler format that we output. */ /* Which assembler syntax. Redefined in m88kdgux.h. */ #define VERSION_0300_SYNTAX TARGET_SVR4 /* At some point, m88kv4.h will redefine this. */ #define VERSION_0400_SYNTAX 0 /* Allow pseudo-ops to be overridden. Override these in svr[34].h. */ #undef INT_ASM_OP #undef ASCII_DATA_ASM_OP #undef CONST_SECTION_ASM_OP #undef CTORS_SECTION_ASM_OP #undef DTORS_SECTION_ASM_OP #undef INIT_SECTION_ASM_OP #undef FINI_SECTION_ASM_OP #undef TYPE_ASM_OP #undef SIZE_ASM_OP #undef WEAK_ASM_OP #undef SET_ASM_OP #undef SKIP_ASM_OP #undef COMMON_ASM_OP #undef ALIGN_ASM_OP #undef IDENT_ASM_OP /* These are used in varasm.c as well. */ #define TEXT_SECTION_ASM_OP "text" #define DATA_SECTION_ASM_OP "data" /* Other sections. */ #define CONST_SECTION_ASM_OP (VERSION_0300_SYNTAX \ ? "section\t .rodata,\"a\"" \ : "section\t .rodata,\"x\"") #define TDESC_SECTION_ASM_OP (VERSION_0300_SYNTAX \ ? "section\t .tdesc,\"a\"" \ : "section\t .tdesc,\"x\"") /* These must be constant strings for crtstuff.c. */ #define CTORS_SECTION_ASM_OP "section\t .ctors,\"d\"" #define DTORS_SECTION_ASM_OP "section\t .dtors,\"d\"" #define INIT_SECTION_ASM_OP "section\t .init,\"x\"" #define FINI_SECTION_ASM_OP "section\t .fini,\"x\"" /* These are pretty much common to all assemblers. */ #define IDENT_ASM_OP "ident" #define FILE_ASM_OP "file" #define SECTION_ASM_OP "section" #define SET_ASM_OP "def" #define GLOBAL_ASM_OP "global" #define ALIGN_ASM_OP "align" #define SKIP_ASM_OP "zero" #define COMMON_ASM_OP "comm" #define BSS_ASM_OP "bss" #define FLOAT_ASM_OP "float" #define DOUBLE_ASM_OP "double" #define INT_ASM_OP "word" #define ASM_LONG INT_ASM_OP #define SHORT_ASM_OP "half" #define CHAR_ASM_OP "byte" #define ASCII_DATA_ASM_OP "string" /* These are particular to the global pool optimization. */ #define SBSS_ASM_OP "sbss" #define SCOMM_ASM_OP "scomm" #define SDATA_SECTION_ASM_OP "sdata" /* These are specific to PIC. */ #define TYPE_ASM_OP "type" #define SIZE_ASM_OP "size" #define WEAK_ASM_OP "weak" #ifndef AS_BUG_POUND_TYPE /* Faulty assemblers require @ rather than #. */ #undef TYPE_OPERAND_FMT #define TYPE_OPERAND_FMT "#%s" #endif /* These are specific to version 03.00 assembler syntax. */ #define INTERNAL_ASM_OP "local" #define VERSION_ASM_OP "version" #define UNALIGNED_SHORT_ASM_OP "uahalf" #define UNALIGNED_INT_ASM_OP "uaword" #define PUSHSECTION_ASM_OP "section" #define POPSECTION_ASM_OP "previous" /* These are specific to the version 04.00 assembler syntax. */ #define REQUIRES_88110_ASM_OP "requires_88110" /* Output any initial stuff to the assembly file. Always put out a file directive, even if not debugging. Immediately after putting out the file, put out a "sem." declaration. This should be harmless on other systems, and is used in DG/UX by the debuggers to supplement COFF. The fields in the integer value are as follows: Bits Value Meaning ---- ----- ------- 0-1 0 No information about stack locations 1 Auto/param locations are based on r30 2 Auto/param locations are based on CFA 3-2 0 No information on dimension order 1 Array dims in sym table matches source language 2 Array dims in sym table is in reverse order 5-4 0 No information about the case of global names 1 Global names appear in the symbol table as in the source 2 Global names have been converted to lower case 3 Global names have been converted to upper case. */ #ifdef SDB_DEBUGGING_INFO #define ASM_COFFSEM(FILE) \ if (write_symbols == SDB_DEBUG) \ { \ fprintf (FILE, "\nsem.%x:\t\t; %s\n", \ (((TARGET_OCS_FRAME_POSITION) ? 2 : 1) << 0) + (1 << 2) + (1 << 4),\ (TARGET_OCS_FRAME_POSITION) \ ? "frame is CFA, normal array dims, case unchanged" \ : "frame is r30, normal array dims, case unchanged"); \ } #else #define ASM_COFFSEM(FILE) #endif /* Output the first line of the assembly file. Redefined in m88kdgux.h. */ #define ASM_FIRST_LINE(FILE) \ do { \ if (m88k_version) \ fprintf (FILE, "\t%s\t \"%s\"\n", VERSION_ASM_OP, m88k_version); \ } while (0) /* Override svr[34].h. */ #undef ASM_FILE_START #define ASM_FILE_START(FILE) \ output_file_start (FILE, f_options, sizeof f_options / sizeof f_options[0], \ W_options, sizeof W_options / sizeof W_options[0]) #undef ASM_FILE_END #define ASM_OUTPUT_SOURCE_FILENAME(FILE, NAME) \ do { fprintf (FILE, "\t%s\t ", FILE_ASM_OP); \ output_quoted_string (FILE, NAME); \ fprintf (FILE, "\n"); \ } while (0) #ifdef SDB_DEBUGGING_INFO #define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \ if (m88k_prologue_done) \ fprintf (FILE, "\n\tln\t %d\t\t\t\t; Real source line %d\n",\ LINE - sdb_begin_function_line, LINE) #endif /* Code to handle #ident directives. Override svr[34].h definition. */ #undef ASM_OUTPUT_IDENT #ifdef DBX_DEBUGGING_INFO #define ASM_OUTPUT_IDENT(FILE, NAME) #else #define ASM_OUTPUT_IDENT(FILE, NAME) \ output_ascii (FILE, IDENT_ASM_OP, 4000, NAME, strlen (NAME)); #endif /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ #define ASM_APP_ON "" /* Output to assembler file text saying following lines no longer contain unusual constructs. */ #define ASM_APP_OFF "" /* Format the assembly opcode so that the arguments are all aligned. The maximum instruction size is 8 characters (fxxx.xxx), so a tab and a space will do to align the output. Abandon the output if a `%' is encountered. */ #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ { \ int ch; \ char *orig_ptr; \ \ for (orig_ptr = (PTR); \ (ch = *(PTR)) && ch != ' ' && ch != '\t' && ch != '\n' && ch != '%'; \ (PTR)++) \ putc (ch, STREAM); \ \ if (ch == ' ' && orig_ptr != (PTR) && (PTR) - orig_ptr < 8) \ putc ('\t', STREAM); \ } /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number. Updated by OVERRIDE_OPTIONS to include the # for version 03.00 syntax. */ #define REGISTER_NAMES \ {"#r0"+1, "#r1"+1, "#r2"+1, "#r3"+1, "#r4"+1, "#r5"+1, "#r6"+1, "#r7"+1, \ "#r8"+1, "#r9"+1, "#r10"+1,"#r11"+1,"#r12"+1,"#r13"+1,"#r14"+1,"#r15"+1,\ "#r16"+1,"#r17"+1,"#r18"+1,"#r19"+1,"#r20"+1,"#r21"+1,"#r22"+1,"#r23"+1,\ "#r24"+1,"#r25"+1,"#r26"+1,"#r27"+1,"#r28"+1,"#r29"+1,"#r30"+1,"#r31"+1,\ "#x0"+1, "#x1"+1, "#x2"+1, "#x3"+1, "#x4"+1, "#x5"+1, "#x6"+1, "#x7"+1, \ "#x8"+1, "#x9"+1, "#x10"+1,"#x11"+1,"#x12"+1,"#x13"+1,"#x14"+1,"#x15"+1,\ "#x16"+1,"#x17"+1,"#x18"+1,"#x19"+1,"#x20"+1,"#x21"+1,"#x22"+1,"#x23"+1,\ "#x24"+1,"#x25"+1,"#x26"+1,"#x27"+1,"#x28"+1,"#x29"+1,"#x30"+1,"#x31"+1} /* Define additional names for use in asm clobbers and asm declarations. We define the fake Condition Code register as an alias for reg 0 (which is our `condition code' register), so that condition codes can easily be clobbered by an asm. The carry bit in the PSR is now used. */ #define ADDITIONAL_REGISTER_NAMES {"psr", 0, "cc", 0} /* How to renumber registers for dbx and gdb. */ #define DBX_REGISTER_NUMBER(REGNO) (REGNO) /* Tell when to declare ASM names. Override svr4.h to provide this hook. */ #undef DECLARE_ASM_NAME #define DECLARE_ASM_NAME TARGET_SVR4 /* Write the extra assembler code needed to declare a function properly. */ #undef ASM_DECLARE_FUNCTION_NAME #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ do { \ if (DECLARE_ASM_NAME) \ { \ fprintf (FILE, "\t%s\t ", TYPE_ASM_OP); \ assemble_name (FILE, NAME); \ putc (',', FILE); \ fprintf (FILE, TYPE_OPERAND_FMT, "function"); \ putc ('\n', FILE); \ } \ ASM_OUTPUT_LABEL(FILE, NAME); \ } while (0) /* Write the extra assembler code needed to declare an object properly. */ #undef ASM_DECLARE_OBJECT_NAME #define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \ do { \ if (DECLARE_ASM_NAME) \ { \ fprintf (FILE, "\t%s\t ", TYPE_ASM_OP); \ assemble_name (FILE, NAME); \ putc (',', FILE); \ fprintf (FILE, TYPE_OPERAND_FMT, "object"); \ putc ('\n', FILE); \ size_directive_output = 0; \ if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \ { \ size_directive_output = 1; \ fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ assemble_name (FILE, NAME); \ fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ } \ } \ ASM_OUTPUT_LABEL(FILE, NAME); \ } while (0) /* Output the size directive for a decl in rest_of_decl_compilation in the case where we did not do so before the initializer. Once we find the error_mark_node, we know that the value of size_directive_output was set by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */ #undef ASM_FINISH_DECLARE_OBJECT #define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ do { \ char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \ && DECLARE_ASM_NAME \ && ! AT_END && TOP_LEVEL \ && DECL_INITIAL (DECL) == error_mark_node \ && !size_directive_output) \ { \ fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ assemble_name (FILE, name); \ fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ } \ } while (0) /* This is how to declare the size of a function. */ #undef ASM_DECLARE_FUNCTION_SIZE #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ do { \ if (DECLARE_ASM_NAME) \ { \ if (!flag_inhibit_size_directive) \ { \ char label[256]; \ static int labelno = 0; \ labelno++; \ ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \ ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno); \ fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ assemble_name (FILE, (FNAME)); \ fprintf (FILE, ",%s-", &label[1]); \ assemble_name (FILE, (FNAME)); \ putc ('\n', FILE); \ } \ } \ } while (0) /* This is how to output the definition of a user-level label named NAME, such as the label on a static function or variable NAME. */ #define ASM_OUTPUT_LABEL(FILE,NAME) \ do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) /* This is how to output a command to make the user-level label named NAME defined for reference from other files. */ #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ do { \ fprintf (FILE, "\t%s\t ", GLOBAL_ASM_OP); \ assemble_name (FILE, NAME); \ putc ('\n', FILE); \ } while (0) /* This is how to output a reference to a user-level label named NAME. Override svr[34].h. */ #undef ASM_OUTPUT_LABELREF #define ASM_OUTPUT_LABELREF(FILE,NAME) \ { \ if (! TARGET_NO_UNDERSCORES && ! VERSION_0300_SYNTAX) \ fputc ('_', FILE); \ fputs (NAME, FILE); \ } /* This is how to output an internal numbered label where PREFIX is the class of label and NUM is the number within the class. For V.4, labels use `.' rather than `@'. */ #undef ASM_OUTPUT_INTERNAL_LABEL #ifdef AS_BUG_DOT_LABELS /* The assembler requires a declaration of local. */ #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, VERSION_0300_SYNTAX ? ".%s%d:\n\t%s\t .%s%d\n" : "@%s%d:\n", \ PREFIX, NUM, INTERNAL_ASM_OP, PREFIX, NUM) #else #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ fprintf (FILE, VERSION_0300_SYNTAX ? ".%s%d:\n" : "@%s%d:\n", PREFIX, NUM) #endif /* AS_BUG_DOT_LABELS */ /* This is how to store into the string LABEL the symbol_ref name of an internal numbered label where PREFIX is the class of label and NUM is the number within the class. This is suitable for output with `assemble_name'. This must agree with ASM_OUTPUT_INTERNAL_LABEL above, except for being prefixed with an `*'. */ #undef ASM_GENERATE_INTERNAL_LABEL #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ sprintf (LABEL, VERSION_0300_SYNTAX ? "*.%s%d" : "*@%s%d", PREFIX, NUM) /* Internal macro to get a single precision floating point value into an int, so we can print it's value in hex. */ #define FLOAT_TO_INT_INTERNAL( FVALUE, IVALUE ) \ { union { \ REAL_VALUE_TYPE d; \ struct { \ unsigned sign : 1; \ unsigned exponent1 : 1; \ unsigned exponent2 : 3; \ unsigned exponent3 : 7; \ unsigned mantissa1 : 20; \ unsigned mantissa2 : 3; \ unsigned mantissa3 : 29; \ } s; \ } _u; \ \ union { \ int i; \ struct { \ unsigned sign : 1; \ unsigned exponent1 : 1; \ unsigned exponent3 : 7; \ unsigned mantissa1 : 20; \ unsigned mantissa2 : 3; \ } s; \ } _u2; \ \ _u.d = REAL_VALUE_TRUNCATE (SFmode, FVALUE); \ _u2.s.sign = _u.s.sign; \ _u2.s.exponent1 = _u.s.exponent1; \ _u2.s.exponent3 = _u.s.exponent3; \ _u2.s.mantissa1 = _u.s.mantissa1; \ _u2.s.mantissa2 = _u.s.mantissa2; \ IVALUE = _u2.i; \ } /* This is how to output an assembler line defining a `double' constant. Use "word" pseudos to avoid printing NaNs, infinity, etc. */ #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ do { \ union { REAL_VALUE_TYPE d; long l[2]; } x; \ x.d = (VALUE); \ fprintf (FILE, "\t%s\t 0x%.8x, 0x%.8x\n", INT_ASM_OP, \ x.l[0], x.l[1]); \ } while (0) /* This is how to output an assembler line defining a `float' constant. */ #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ do { \ int i; \ FLOAT_TO_INT_INTERNAL (VALUE, i); \ fprintf (FILE, "\t%s\t 0x%.8x\n", INT_ASM_OP, i); \ } while (0) /* Likewise for `int', `short', and `char' constants. */ #define ASM_OUTPUT_INT(FILE,VALUE) \ ( fprintf (FILE, "\t%s\t ", INT_ASM_OP), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ( fprintf (FILE, "\t%s\t ", SHORT_ASM_OP), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ( fprintf (FILE, "\t%s\t ", CHAR_ASM_OP), \ output_addr_const (FILE, (VALUE)), \ fprintf (FILE, "\n")) /* This is how to output an assembler line for a numeric constant byte. */ #define ASM_OUTPUT_BYTE(FILE,VALUE) \ fprintf (FILE, "\t%s\t 0x%x\n", CHAR_ASM_OP, (VALUE)) /* The single-byte pseudo-op is the default. Override svr[34].h. */ #undef ASM_BYTE_OP #define ASM_BYTE_OP "byte" #undef ASM_OUTPUT_ASCII #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \ output_ascii (FILE, ASCII_DATA_ASM_OP, 48, P, SIZE) /* Override svr4.h. Change to the readonly data section for a table of addresses. final_scan_insn changes back to the text section. */ #undef ASM_OUTPUT_CASE_LABEL #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, TABLE) \ do { \ if (! CASE_VECTOR_INSNS) \ { \ readonly_data_section (); \ ASM_OUTPUT_ALIGN (FILE, 2); \ } \ ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \ } while (0) /* Epilogue for case labels. This jump instruction is called by casesi to transfer to the appropriate branch instruction within the table. The label `@Le' is coined to mark the end of the table. */ #define ASM_OUTPUT_CASE_END(FILE, NUM, TABLE) \ do { \ if (CASE_VECTOR_INSNS) \ { \ char label[256]; \ ASM_GENERATE_INTERNAL_LABEL (label, "L", NUM); \ fprintf (FILE, "%se:\n", &label[1]); \ if (! flag_delayed_branch) \ fprintf (FILE, "\tlda\t %s,%s[%s]\n", reg_names[1], \ reg_names[1], reg_names[m88k_case_index]); \ fprintf (FILE, "\tjmp\t %s\n", reg_names[1]); \ } \ } while (0) /* This is how to output an element of a case-vector that is absolute. */ #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ do { \ char buffer[256]; \ ASM_GENERATE_INTERNAL_LABEL (buffer, "L", VALUE); \ fprintf (FILE, CASE_VECTOR_INSNS ? "\tbr\t %s\n" : "\tword\t %s\n", \ &buffer[1]); \ } while (0) /* This is how to output an element of a case-vector that is relative. */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ ASM_OUTPUT_ADDR_VEC_ELT (FILE, VALUE) /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ #define ASM_OUTPUT_ALIGN(FILE,LOG) \ if ((LOG) != 0) \ fprintf (FILE, "\t%s\t %d\n", ALIGN_ASM_OP, 1<<(LOG)) /* On the m88100, align the text address to half a cache boundary when it can only be reached by jumping. Pack code tightly when compiling crtstuff.c. */ #define ASM_OUTPUT_ALIGN_CODE(FILE) \ ASM_OUTPUT_ALIGN (FILE, \ (TARGET_88100 && !flag_inhibit_size_directive ? 3 : 2)) /* Override svr[34].h. */ #undef ASM_OUTPUT_SKIP #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t%s\t %u\n", SKIP_ASM_OP, (SIZE)) /* Override svr4.h. */ #undef ASM_OUTPUT_EXTERNAL_LIBCALL /* This says how to output an assembler line to define a global common symbol. Size can be zero for the unusual case of a `struct { int : 0; }'. Override svr[34].h. */ #undef ASM_OUTPUT_COMMON #undef ASM_OUTPUT_ALIGNED_COMMON #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ( fprintf ((FILE), "\t%s\t ", \ ((SIZE) ? (SIZE) : 1) <= m88k_gp_threshold ? SCOMM_ASM_OP : COMMON_ASM_OP), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u\n", (SIZE) ? (SIZE) : 1)) /* This says how to output an assembler line to define a local common symbol. Override svr[34].h. */ #undef ASM_OUTPUT_LOCAL #undef ASM_OUTPUT_ALIGNED_LOCAL #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ ( fprintf ((FILE), "\t%s\t ", \ ((SIZE) ? (SIZE) : 1) <= m88k_gp_threshold ? SBSS_ASM_OP : BSS_ASM_OP), \ assemble_name ((FILE), (NAME)), \ fprintf ((FILE), ",%u,%d\n", (SIZE) ? (SIZE) : 1, (SIZE) <= 4 ? 4 : 8)) /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) /* This is how to output an insn to push a register on the stack. It need not be very fast code. */ #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ fprintf (FILE, "\tsubu\t %s,%s,%d\n\tst\t %s,%s,0\n", \ reg_names[STACK_POINTER_REGNUM], \ reg_names[STACK_POINTER_REGNUM], \ (STACK_BOUNDARY / BITS_PER_UNIT), \ reg_names[REGNO], \ reg_names[STACK_POINTER_REGNUM]) /* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */ #define REG_PUSH_LENGTH 2 /* This is how to output an insn to pop a register from the stack. */ #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ fprintf (FILE, "\tld\t %s,%s,0\n\taddu\t %s,%s,%d\n", \ reg_names[REGNO], \ reg_names[STACK_POINTER_REGNUM], \ reg_names[STACK_POINTER_REGNUM], \ reg_names[STACK_POINTER_REGNUM], \ (STACK_BOUNDARY / BITS_PER_UNIT)) /* Length in instructions of the code output by ASM_OUTPUT_REG_POP. */ #define REG_POP_LENGTH 2 /* Define the parentheses used to group arithmetic operations in assembler code. */ #define ASM_OPEN_PAREN "(" #define ASM_CLOSE_PAREN ")" /* Define results of standard character escape sequences. */ #define TARGET_BELL 007 #define TARGET_BS 010 #define TARGET_TAB 011 #define TARGET_NEWLINE 012 #define TARGET_VT 013 #define TARGET_FF 014 #define TARGET_CR 015 /* Macros to deal with OCS debug information */ #define OCS_START_PREFIX "Ltb" #define OCS_END_PREFIX "Lte" #define PUT_OCS_FUNCTION_START(FILE) \ { ASM_OUTPUT_INTERNAL_LABEL (FILE, OCS_START_PREFIX, m88k_function_number); } #define PUT_OCS_FUNCTION_END(FILE) \ { ASM_OUTPUT_INTERNAL_LABEL (FILE, OCS_END_PREFIX, m88k_function_number); } /* Macros for debug information */ #define DEBUGGER_AUTO_OFFSET(X) \ (m88k_debugger_offset (X, 0) \ + (TARGET_OCS_FRAME_POSITION ? 0 : m88k_stack_size - m88k_fp_offset)) #define DEBUGGER_ARG_OFFSET(OFFSET, X) \ (m88k_debugger_offset (X, OFFSET) \ + (TARGET_OCS_FRAME_POSITION ? 0 : m88k_stack_size - m88k_fp_offset)) /* Macros to deal with SDB debug information */ #ifdef SDB_DEBUGGING_INFO /* Output structure tag names even when it causes a forward reference. */ #define SDB_ALLOW_FORWARD_REFERENCES /* Print out extra debug information in the assembler file */ #define PUT_SDB_SCL(a) \ do { \ register int s = (a); \ register char *scl; \ switch (s) \ { \ case C_EFCN: scl = "end of function"; break; \ case C_NULL: scl = "NULL storage class"; break; \ case C_AUTO: scl = "automatic"; break; \ case C_EXT: scl = "external"; break; \ case C_STAT: scl = "static"; break; \ case C_REG: scl = "register"; break; \ case C_EXTDEF: scl = "external definition"; break; \ case C_LABEL: scl = "label"; break; \ case C_ULABEL: scl = "undefined label"; break; \ case C_MOS: scl = "structure member"; break; \ case C_ARG: scl = "argument"; break; \ case C_STRTAG: scl = "structure tag"; break; \ case C_MOU: scl = "union member"; break; \ case C_UNTAG: scl = "union tag"; break; \ case C_TPDEF: scl = "typedef"; break; \ case C_USTATIC: scl = "uninitialized static"; break; \ case C_ENTAG: scl = "enumeration tag"; break; \ case C_MOE: scl = "member of enumeration"; break; \ case C_REGPARM: scl = "register parameter"; break; \ case C_FIELD: scl = "bit field"; break; \ case C_BLOCK: scl = "block start/end"; break; \ case C_FCN: scl = "function start/end"; break; \ case C_EOS: scl = "end of structure"; break; \ case C_FILE: scl = "filename"; break; \ case C_LINE: scl = "line"; break; \ case C_ALIAS: scl = "duplicated tag"; break; \ case C_HIDDEN: scl = "hidden"; break; \ default: scl = "unknown"; break; \ } \ \ fprintf(asm_out_file, "\tscl\t %d\t\t\t\t; %s\n", s, scl); \ } while (0) #define PUT_SDB_TYPE(a) \ do { \ register int t = (a); \ static char buffer[100]; \ register char *p = buffer, *q; \ register int typ = t; \ register int i,d; \ \ for (i = 0; i <= 5; i++) \ { \ switch ((typ >> ((i*N_TSHIFT) + N_BTSHFT)) & 03) \ { \ case DT_PTR: \ strcpy (p, "ptr to "); \ p += sizeof("ptr to"); \ break; \ \ case DT_ARY: \ strcpy (p, "array of "); \ p += sizeof("array of"); \ break; \ \ case DT_FCN: \ strcpy (p, "func ret "); \ p += sizeof("func ret"); \ break; \ } \ } \ \ switch (typ & N_BTMASK) \ { \ case T_NULL: q = ""; break; \ case T_CHAR: q = "char"; break; \ case T_SHORT: q = "short"; break; \ case T_INT: q = "int"; break; \ case T_LONG: q = "long"; break; \ case T_FLOAT: q = "float"; break; \ case T_DOUBLE: q = "double"; break; \ case T_STRUCT: q = "struct"; break; \ case T_UNION: q = "union"; break; \ case T_ENUM: q = "enum"; break; \ case T_MOE: q = "enum member"; break; \ case T_UCHAR: q = "unsigned char"; break; \ case T_USHORT: q = "unsigned short"; break; \ case T_UINT: q = "unsigned int"; break; \ case T_ULONG: q = "unsigned long"; break; \ default: q = "void"; break; \ } \ \ strcpy (p, q); \ fprintf(asm_out_file, "\ttype\t %d\t\t\t\t; %s\n", \ t, buffer); \ } while (0) #define PUT_SDB_INT_VAL(a) \ fprintf (asm_out_file, "\tval\t %d\n", (a)) #define PUT_SDB_VAL(a) \ ( fprintf (asm_out_file, "\tval\t "), \ output_addr_const (asm_out_file, (a)), \ fputc ('\n', asm_out_file)) #define PUT_SDB_DEF(a) \ do { fprintf (asm_out_file, "\tsdef\t "); \ ASM_OUTPUT_LABELREF (asm_out_file, a); \ fputc ('\n', asm_out_file); \ } while (0) #define PUT_SDB_PLAIN_DEF(a) \ fprintf(asm_out_file,"\tsdef\t .%s\n", a) /* Simply and endef now. */ #define PUT_SDB_ENDEF \ fputs("\tendef\n\n", asm_out_file) #define PUT_SDB_SIZE(a) \ fprintf (asm_out_file, "\tsize\t %d\n", (a)) /* Max dimensions to store for debug information (limited by COFF). */ #define SDB_MAX_DIM 6 /* New method for dim operations. */ #define PUT_SDB_START_DIM \ fputs("\tdim\t ", asm_out_file) /* How to end the DIM sequence. */ #define PUT_SDB_LAST_DIM(a) \ fprintf(asm_out_file, "%d\n", a) #define PUT_SDB_TAG(a) \ do { \ fprintf (asm_out_file, "\ttag\t "); \ ASM_OUTPUT_LABELREF (asm_out_file, a); \ fputc ('\n', asm_out_file); \ } while( 0 ) #define PUT_SDB_BLOCK_OR_FUNCTION(NAME, SCL, LINE) \ do { \ fprintf (asm_out_file, "\n\tsdef\t %s\n\tval\t .\n", \ NAME); \ PUT_SDB_SCL( SCL ); \ fprintf (asm_out_file, "\tline\t %d\n\tendef\n\n", \ (LINE)); \ } while (0) #define PUT_SDB_BLOCK_START(LINE) \ PUT_SDB_BLOCK_OR_FUNCTION (".bb", C_BLOCK, (LINE)) #define PUT_SDB_BLOCK_END(LINE) \ PUT_SDB_BLOCK_OR_FUNCTION (".eb", C_BLOCK, (LINE)) #define PUT_SDB_FUNCTION_START(LINE) \ do { \ fprintf (asm_out_file, "\tln\t 1\n"); \ PUT_SDB_BLOCK_OR_FUNCTION (".bf", C_FCN, (LINE)); \ } while (0) #define PUT_SDB_FUNCTION_END(LINE) \ do { \ PUT_SDB_BLOCK_OR_FUNCTION (".ef", C_FCN, (LINE)); \ } while (0) #define PUT_SDB_EPILOGUE_END(NAME) \ do { \ text_section (); \ fprintf (asm_out_file, "\n\tsdef\t "); \ ASM_OUTPUT_LABELREF(asm_out_file, (NAME)); \ fputc('\n', asm_out_file); \ PUT_SDB_SCL( C_EFCN ); \ fprintf (asm_out_file, "\tendef\n\n"); \ } while (0) #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \ sprintf ((BUFFER), ".%dfake", (NUMBER)); #endif /* SDB_DEBUGGING_INFO */ /* Support const and tdesc sections. Generally, a const section will be distinct from the text section whenever we do V.4-like things and so follows DECLARE_ASM_NAME. Note that strings go in text rather than const. Override svr[34].h. */ #undef USE_CONST_SECTION #undef EXTRA_SECTIONS #define USE_CONST_SECTION DECLARE_ASM_NAME #if defined(USING_SVR4_H) #define EXTRA_SECTIONS in_const, in_tdesc, in_sdata, in_ctors, in_dtors #define INIT_SECTION_FUNCTION #define FINI_SECTION_FUNCTION #else #if defined(USING_SVR3_H) #define EXTRA_SECTIONS in_const, in_tdesc, in_sdata, in_ctors, in_dtors, \ in_init, in_fini #else /* m88kluna or other not based on svr[34].h. */ #undef INIT_SECTION_ASM_OP #define EXTRA_SECTIONS in_const, in_tdesc, in_sdata #define CONST_SECTION_FUNCTION \ void \ const_section () \ { \ text_section(); \ } #define CTORS_SECTION_FUNCTION #define DTORS_SECTION_FUNCTION #define INIT_SECTION_FUNCTION #define FINI_SECTION_FUNCTION #endif /* USING_SVR3_H */ #endif /* USING_SVR4_H */ #undef EXTRA_SECTION_FUNCTIONS #define EXTRA_SECTION_FUNCTIONS \ CONST_SECTION_FUNCTION \ \ void \ tdesc_section () \ { \ if (in_section != in_tdesc) \ { \ fprintf (asm_out_file, "%s\n", TDESC_SECTION_ASM_OP); \ in_section = in_tdesc; \ } \ } \ \ void \ sdata_section () \ { \ if (in_section != in_sdata) \ { \ fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \ in_section = in_sdata; \ } \ } \ \ CTORS_SECTION_FUNCTION \ DTORS_SECTION_FUNCTION \ INIT_SECTION_FUNCTION \ FINI_SECTION_FUNCTION /* A C statement or statements to switch to the appropriate section for output of DECL. DECL is either a `VAR_DECL' node or a constant of some sort. RELOC indicates whether forming the initial value of DECL requires link-time relocations. For strings, the section is selected before the segment info is encoded. */ #undef SELECT_SECTION #define SELECT_SECTION(DECL,RELOC) \ { \ if (TREE_CODE (DECL) == STRING_CST) \ { \ if (! flag_writable_strings) \ const_section (); \ else if (m88k_gp_threshold > 0 \ && TREE_STRING_LENGTH (DECL) <= m88k_gp_threshold) \ sdata_section (); \ else \ data_section (); \ } \ else if (TREE_CODE (DECL) == VAR_DECL) \ { \ if (SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0))) \ sdata_section (); \ else if ((flag_pic && RELOC) \ || !TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL)) \ data_section (); \ else \ const_section (); \ } \ else \ const_section (); \ } /* Jump tables consist of branch instructions and should be output in the text section. When we use a table of addresses, we explicitly change to the readonly data section. */ #define JUMP_TABLES_IN_TEXT_SECTION 1 /* Define this macro if references to a symbol must be treated differently depending on something about the variable or function named by the symbol (such as what section it is in). The macro definition, if any, is executed immediately after the rtl for DECL has been created and stored in `DECL_RTL (DECL)'. The value of the rtl will be a `mem' whose address is a `symbol_ref'. For the m88k, determine if the item should go in the global pool. */ #define ENCODE_SECTION_INFO(DECL) \ do { \ if (m88k_gp_threshold > 0) \ if (TREE_CODE (DECL) == VAR_DECL) \ { \ if (!TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL)) \ { \ int size = int_size_in_bytes (TREE_TYPE (DECL)); \ \ if (size > 0 && size <= m88k_gp_threshold) \ SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \ } \ } \ else if (TREE_CODE (DECL) == STRING_CST \ && flag_writable_strings \ && TREE_STRING_LENGTH (DECL) <= m88k_gp_threshold) \ SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \ } while (0) /* Print operand X (an rtx) in assembler syntax to file FILE. CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. For `%' followed by punctuation, CODE is the punctuation and X is null. */ #define PRINT_OPERAND_PUNCT_VALID_P(c) \ ((c) == '#' || (c) == '.' || (c) == '!' || (c) == '*' || (c) == ';') #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) /* Print a memory address as an operand to reference that memory location. */ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) gcc-2.5.8/config/m88k/m88k.md100444 22011 13 353035 5467761045 14217 0ustar kenneruser;;- Machine description for the Motorola 88000 for GNU C compiler ;; Copyright (C) 1988, 1989, 1990, 1991, 1993 Free Software Foundation, Inc. ;; Contributed by Michael Tiemann (tiemann@mcc.com) ;; Additional changes by Michael Meissner (meissner@osf.org) ;; Version 2 port by Tom Wood (Tom_Wood@NeXT.com) ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 2, or (at your option) ;; any later version. ;; GNU CC is distributed in the hope that it will be useful, ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU General Public License for more details. ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ;; SCCS rev field. This is a NOP, just to get the SCCS id into the ;; program image. (define_expand "m88k_sccs_id" [(match_operand:SI 0 "" "")] "" "{ static char sccs_id[] = \"@(#)m88k.md 2.3.3.2 12/16/92 08:26:12\"; FAIL; }") ;; Attribute specifications ; Target CPU. (define_attr "cpu" "m88100,m88110,m88000" (const (symbol_ref "m88k_cpu"))) ; Type of each instruction. Default is arithmetic. ; I'd like to write the list as this, but genattrtab won't accept it. ; ; "branch,jump,call, ; flow-control instructions ; load,store,loadd,loada, ; data unit instructions ; spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv, ; FPU add instructions ; spmul,dpmul,imul, ; FPU multiply instructions ; arith,bit,mov ; integer unit instructions ; marith,weird" ; multi-word instructions ; Classification of each insn. Some insns of TYPE_BRANCH are multi-word. (define_attr "type" "branch,jump,call,load,store,loadd,loada,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv,spmul,dpmul,imul,arith,bit,mov,marith,weird" (const_string "arith")) (define_attr "fpu" "yes,no" (if_then_else (eq_attr "type" "spmul,dpmul,imul,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv") (const_string "yes") (const_string "no"))) ; Length in # of instructions of each insn. The values are not exact, but ; are safe. (define_attr "length" "" (cond [(eq_attr "type" "marith,weird,branch") (const_int 2)] (const_int 1))) ; Describe a user's asm statement. (define_asm_attributes [(set_attr "type" "weird")]) ; Define the delay slot requirements for branches and calls. ; The m88100 annuls instructions if a conditional branch is taken. ; For insns of TYPE_BRANCH that are multi-word instructions, the ; delay slot applies to the first instruction. ; @@ For the moment, reorg.c requires that the delay slot of a branch not ; be a call or branch. (define_delay (eq_attr "type" "branch,jump") [(and (and (eq_attr "type" "!branch,jump,call,marith,weird") ; required. (eq_attr "type" "!load,loadd")) ; issue as-soon-as-possible. (eq_attr "fpu" "no")) ; issue as-soon-as-possible. (eq_attr "type" "!call,branch,jump") (nil)]) ; @@ was (const_int 1) ; output_call supports an unconditional branch in the delay slot of ; a call. (@@ Support for this case is expected in reorg.c soon.) (define_delay (eq_attr "type" "call") [(eq_attr "type" "!branch,call,marith,weird") ; required. (nil) (nil)]) ; An abstract block diagram of the function units for the m88100. ; ; * ; | ; +---v----+ ; | decode | ; +-vv-v-v-+ fpu ; ,----------'| | `----------------------. ; | | | | ,-----. ; load | store | | arith | | | ; | | | +-v-v-+ | dp source ; | | | | fp1 |---' ; store | | | div +-v-v-+ ; ,------. | | | ,-----. ,-----------' `-----------. ; | | | | | | | | | ; | +--v---v--+ ,---' | | +-v-v---+ +---v---+ ; | | stage 2 | | | `---| add 2 | | mul 2 | ; | +---------+ | +--v--+ +-------+ imul +-------+ ; | | stage 1 | | | alu | | add 3 | ,--------| mul 3 | ; | +---------+ | +--v--+ +-------+ | +-------+ ; | | stage 0 | | | | add 4 | | | mul 4 | ; | +--v---v--+ | | +---v---+ | +-------+ ; | | | | | | | | mul 5 | ; | * | | | | | +---v---+ ; | | | | | +----v----+ | ; | load | | | fp add `------>| fp last |<------' fp mul ; | | | | +---v-v--^+ ; | | | | | | | ; | | | | | `--' dp dest ; | | +--v-----v--+ | ; | `--->| writeback |<--------------------' ; | +--v-----v--+ ; | | | ; `------------------' * ; ; The decode unit need not be specified. ; Consideration of writeback contention is critical to superb scheduling. ; ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) ; Describing the '100 alu is currently not useful. ;(define_function_unit "alu" 1 0 (eq_attr "type" ; "!store,marith,weird") 1 0) ;(define_function_unit "alu" 1 0 (eq_attr "type" "marith,weird") 2 0) (define_function_unit "alu" 1 0 (and (eq_attr "type" "loada,arith,mov") (eq_attr "cpu" "!m88100")) 2 0) (define_function_unit "alu" 1 0 (and (eq_attr "type" "marith,weird") (eq_attr "cpu" "!m88100")) 4 0) (define_function_unit "bit" 1 0 (and (eq_attr "type" "bit") (eq_attr "cpu" "!m88100")) 2 2) (define_function_unit "mem100" 1 0 (and (eq_attr "type" "store,loada") (eq_attr "cpu" "m88100")) 1 0) (define_function_unit "mem100" 1 0 (and (eq_attr "type" "load") (eq_attr "cpu" "m88100")) 3 0) (define_function_unit "mem100" 1 0 (and (eq_attr "type" "loadd") (eq_attr "cpu" "m88100")) 3 2) (define_function_unit "mem110" 1 0 (and (eq_attr "type" "load,loadd") (eq_attr "cpu" "!m88100")) 3 2) (define_function_unit "mem110" 1 0 (and (eq_attr "type" "store") (eq_attr "cpu" "!m88100")) 1 2) ; The times are adjusted to include fp1 and fplast, but then are further ; adjusted based on the actual generated code. The notation to the right ; is the total latency. A range denotes a group of instructions and/or ; conditions (the extra clock of fplast time with some sequences). (define_function_unit "fpmul100" 1 0 (and (eq_attr "type" "spmul") (eq_attr "cpu" "m88100")) 4 0) ; 6-8 (define_function_unit "fpmul100" 1 0 (and (eq_attr "type" "dpmul") (eq_attr "cpu" "m88100")) 7 0) ; 9-10 (define_function_unit "fpmul100" 1 0 (and (eq_attr "type" "imul") (eq_attr "cpu" "m88100")) 3 0) ; 4 (define_function_unit "fpmul110" 1 0 (and (eq_attr "type" "imul,spmul,dpmul") (eq_attr "cpu" "!m88100")) 5 2) ; 3 (define_function_unit "fpadd100" 1 5 (and (eq_attr "type" "spadd,spcmp") (eq_attr "cpu" "m88100")) 3 0) ; 5-6 (define_function_unit "fpadd100" 1 5 (and (eq_attr "type" "dpadd,dpcmp") (eq_attr "cpu" "m88100")) 4 0) ; 6-7 (define_function_unit "fpadd110" 1 0 (and (eq_attr "type" "spadd,dpadd") (eq_attr "cpu" "!m88100")) 5 2) ; 3 (define_function_unit "fpadd110" 1 0 (and (eq_attr "type" "spcmp,dpcmp") (eq_attr "cpu" "!m88100")) 2 2) ; 1 (define_function_unit "fpadd100" 1 5 (and (eq_attr "type" "spdiv") (eq_attr "cpu" "m88100")) 30 0) ; 30-31 (define_function_unit "fpadd100" 1 5 (and (eq_attr "type" "dpdiv") (eq_attr "cpu" "m88100")) 60 0) ; 60-61 (define_function_unit "fpadd100" 1 5 (and (eq_attr "type" "idiv") (eq_attr "cpu" "m88100")) 38 0) ; 38 (define_function_unit "div" 1 1 (and (eq_attr "type" "spdiv") (eq_attr "cpu" "!m88100")) 25 2) ; 13 (define_function_unit "div" 1 1 (and (eq_attr "type" "dpdiv") (eq_attr "cpu" "!m88100")) 45 2) ; 23 (define_function_unit "div" 1 1 (and (eq_attr "type" "idiv") (eq_attr "cpu" "!m88100")) 35 2) ; 18 ;; Superoptimizer sequences ;; geu+: { r = ((unsigned_word) v0 >= (unsigned_word) v1) + v2; } ;; subu.co r5,r2,r3 ;; addu.cio r6,r4,r0 (define_split [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 1 "register_operand" "r") (geu:SI (match_operand:SI 2 "register_operand" "r") (match_operand:SI 3 "register_operand" "r"))))] "" [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1)) (set (match_dup 0) (plus:SI (match_dup 1) (unspec:SI [(const_int 0) (reg:CC 0)] 0)))] "") ;; leu+: { r = ((unsigned_word) v0 <= (unsigned_word) v1) + v2; } ;; subu.co r5,r3,r2 ;; addu.cio r6,r4,r0 (define_split [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 1 "register_operand" "r") (leu:SI (match_operand:SI 3 "register_operand" "r") (match_operand:SI 2 "register_operand" "r"))))] "" [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1)) (set (match_dup 0) (plus:SI (match_dup 1) (unspec:SI [(const_int 0) (reg:CC 0)] 0)))] "") ;; eq0+: { r = (v0 == 0) + v1; } ;; subu.co r4,r0,r2 ;; addu.cio r5,r3,r0 (define_split [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 1 "register_operand" "r") (eq:SI (match_operand:SI 2 "register_operand" "r") (const_int 0))))] "" [(set (reg:CC 0) (unspec:CC [(const_int 0) (match_dup 2)] 1)) (set (match_dup 0) (plus:SI (match_dup 1) (unspec:SI [(const_int 0) (reg:CC 0)] 0)))] "") ;; ltu-: { r = v2 - ((unsigned_word) v0 < (unsigned_word) v1); } ;; subu.co r5,r2,r3 ;; subu.cio r6,r4,r0 (define_split [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (ltu:SI (match_operand:SI 2 "register_operand" "r") (match_operand:SI 3 "register_operand" "r")) (match_operand:SI 1 "register_operand" "r")))] "" [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1)) (set (match_dup 0) (minus:SI (match_dup 1) (unspec:SI [(const_int 0) (reg:CC 0)] 1)))] "") ;; gtu-: { r = v2 - ((unsigned_word) v0 > (unsigned_word) v1); } ;; subu.co r5,r3,r2 ;; subu.cio r6,r4,r0 (define_split [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (gtu:SI (match_operand:SI 3 "register_operand" "r") (match_operand:SI 2 "register_operand" "r")) (match_operand:SI 1 "register_operand" "r")))] "" [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 3)] 1)) (set (match_dup 0) (minus:SI (match_dup 1) (unspec:SI [(const_int 0) (reg:CC 0)] 1)))] "") ;; ne0-: { r = v1 - (v0 != 0); } ;; subu.co r4,r0,r2 ;; subu.cio r5,r3,r0 (define_split [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (ne:SI (match_operand:SI 2 "register_operand" "r") (const_int 0)) (match_operand:SI 1 "register_operand" "r")))] "" [(set (reg:CC 0) (unspec:CC [(const_int 0) (match_dup 2)] 1)) (set (match_dup 0) (minus:SI (match_dup 1) (unspec:SI [(const_int 0) (reg:CC 0)] 1)))] "") ;; ges0-: { r = v1 - ((signed_word) v0 >= 0); } ;; addu.co r4,r2,r2 ;; subu.cio r5,r3,r0 (define_split [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 1 "register_operand" "r") (xor:SI (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") (const_int 31)) (const_int 1))))] "" [(set (reg:CC 0) (unspec:CC [(match_dup 2) (match_dup 2)] 0)) (set (match_dup 0) (minus:SI (match_dup 1) (unspec:SI [(const_int 0) (reg:CC 0)] 1)))] "") ;; This rich set of complex patterns are mostly due to Torbjorn Granlund ;; (tege@sics.se). They've changed since then, so don't complain to him ;; if they don't work right. ;; Regarding shifts, gen_lshlsi3 generates ASHIFT. LSHIFT opcodes are ;; not produced and should not normally occur. Also, the gen functions ;; produce the necessary insns to support TARGET_*_LARGE_SHIFT, so nothing ;; special needs to be done here. ;; Optimize possible cases of the set instruction. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ashift:SI (const_int -1) (match_operand:SI 1 "register_operand" "r")))] "" "set %0,%#r0,%1" [(set_attr "type" "bit")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (ashift:SI (const_int -1) (match_operand:SI 1 "register_operand" "r")) (match_operand:SI 2 "register_operand" "r")))] "" "set %0,%2,%1" [(set_attr "type" "bit")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (match_operand:SI 1 "register_operand" "r") (ashift:SI (const_int -1) (match_operand:SI 2 "register_operand" "r"))))] "" "set %0,%1,%2" [(set_attr "type" "bit")]) ;; Optimize possible cases of the mak instruction. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "int5_operand" "")) (match_operand:SI 3 "immediate_operand" "n")))] "mak_mask_p (INTVAL (operands[3]) >> INTVAL (operands[2]))" "* { operands[4] = gen_rtx (CONST_INT, SImode, exact_log2 (1 + (INTVAL (operands[3]) >> INTVAL(operands[2])))); return \"mak %0,%1,%4<%2>\"; }" [(set_attr "type" "bit")]) ;; Optimize possible cases of output_and. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ashift:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "int5_operand" "") (match_operand:SI 3 "int5_operand" "")) (match_operand:SI 4 "int5_operand" "")))] "INTVAL (operands[2]) + INTVAL (operands[3]) + INTVAL (operands[4]) == 32" "* { operands[2] = gen_rtx (CONST_INT, SImode, ((1 << INTVAL (operands[2])) - 1) << INTVAL (operands[4])); return output_and (operands); }" [(set_attr "type" "marith")]) ; arith,bit,marith. length is 1 or 2. ;; Improve logical operations on compare words ;; ;; We define all logical operations on CCmode values to preserve the pairwise ;; relationship of the compare bits. This allows a future branch prediction ;; pass the degree of freedom needed to change and/bb0-le into or/bb1-gt. ;; THIS IS CURRENTLY FALSE! ;; ;; Opportunities arise when conditional expressions using && and || are made ;; unconditional. When these are used to branch, the sequence is ;; cmp/cmp/extu/extu/{and,or}/bcnd-{eq0,ne0}. When these are used to create ;; a value, the sequence is cmp/cmp/extu/extu/{and,or} for 1 or 0 or ;; cmp/cmp/ext/ext/{and,or} for -1 or 0. ;; ;; When the extracted conditions are the same, the define_split patterns ;; below change extu/extu/{and,or} into {and,or}/extu. If the reversed ;; conditions match, one compare word can be complimented, resulting in ;; {and.c,or.c}/extu. These changes are done for ext/ext/{and,or} as well. ;; If the conditions don't line up, one can be rotated. To keep the pairwise ;; relationship, it may be necessary to both rotate and compliment. Rotating ;; makes branching cheaper, but doesn't help (or hurt) creating a value, so ;; we don't do this for ext/ext/{and,or}. ;; ;; These changes result in the sequence extu/bcnd-{eq0,ne0} which is combined ;; into an alternate form of bb0 and bb1. (define_split [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (neg:SI (match_operator 1 "even_relop" [(match_operand 2 "partial_ccmode_register_operand" "%r") (const_int 0)])) (neg:SI (match_operator 3 "relop" [(match_operand 4 "partial_ccmode_register_operand" "r") (const_int 0)])))) (clobber (match_operand:SI 5 "register_operand" "=r"))] "" [(set (match_dup 5) (ior:CCEVEN (match_dup 4) (match_dup 2))) (set (match_dup 0) (neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))] "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0); if (GET_CODE (operands[1]) == GET_CODE (operands[3])) ; /* The conditions match. */ else if (GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))) /* Reverse the condition by complimenting the compare word. */ operands[4] = gen_rtx (NOT, CCmode, operands[4]); else { /* Make the condition pairs line up by rotating the compare word. */ int cv1 = condition_value (operands[1]); int cv2 = condition_value (operands[3]); operands[4] = gen_rtx (ROTATE, CCmode, operands[4], gen_rtx (CONST_INT, VOIDmode, ((cv2 & ~1) - (cv1 & ~1)) & 0x1f)); /* Reverse the condition if needed. */ if ((cv1 & 1) != (cv2 & 1)) operands[4] = gen_rtx (NOT, CCmode, operands[4]); }") (define_split [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (neg:SI (match_operator 1 "odd_relop" [(match_operand 2 "partial_ccmode_register_operand" "%r") (const_int 0)])) (neg:SI (match_operator 3 "odd_relop" [(match_operand 4 "partial_ccmode_register_operand" "r") (const_int 0)])))) (clobber (match_operand:SI 5 "register_operand" "=r"))] "" [(set (match_dup 5) (and:CCEVEN (match_dup 4) (match_dup 2))) (set (match_dup 0) (neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))] "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0); if (GET_CODE (operands[1]) == GET_CODE (operands[3])) ; /* The conditions match. */ else { /* Make the condition pairs line up by rotating the compare word. */ int cv1 = condition_value (operands[1]); int cv2 = condition_value (operands[3]); operands[4] = gen_rtx (ROTATE, CCmode, operands[4], gen_rtx (CONST_INT, VOIDmode, (cv2 - cv1) & 0x1f)); }") (define_split [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (neg:SI (match_operator 1 "odd_relop" [(match_operand 2 "partial_ccmode_register_operand" "%r") (const_int 0)])) (neg:SI (match_operator 3 "even_relop" [(match_operand 4 "partial_ccmode_register_operand" "r") (const_int 0)])))) (clobber (match_operand:SI 5 "register_operand" "=r"))] "" [(set (match_dup 5) (ior:CCEVEN (not:CC (match_dup 2)) (match_dup 4))) (set (match_dup 0) (neg:SI (match_op_dup 3 [(match_dup 5) (const_int 0)])))] "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0); if (GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))) ; else { /* Make the condition pairs line up by rotating the compare word. */ int cv1 = condition_value (operands[1]); int cv2 = condition_value (operands[3]); operands[2] = gen_rtx (ROTATE, CCmode, operands[2], gen_rtx (CONST_INT, VOIDmode, ((cv1 & ~1) - (cv2 & ~1)) & 0x1f)); }") (define_split [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (match_operator 1 "even_relop" [(match_operand 2 "partial_ccmode_register_operand" "%r") (const_int 0)]) (match_operator 3 "relop" [(match_operand 4 "partial_ccmode_register_operand" "r") (const_int 0)]))) (clobber (match_operand:SI 5 "register_operand" "=r"))] "GET_CODE (operands[1]) == GET_CODE (operands[3]) || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))" [(set (match_dup 5) (ior:CCEVEN (match_dup 4) (match_dup 2))) (set (match_dup 0) (match_op_dup 1 [(match_dup 5) (const_int 0)]))] "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0); /* Reverse the condition by complimenting the compare word. */ if (GET_CODE (operands[1]) != GET_CODE (operands[3])) operands[4] = gen_rtx (NOT, CCmode, operands[4]);") (define_split [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (match_operator 1 "odd_relop" [(match_operand 2 "partial_ccmode_register_operand" "%r") (const_int 0)]) (match_operator 3 "odd_relop" [(match_operand 4 "partial_ccmode_register_operand" "r") (const_int 0)]))) (clobber (match_operand:SI 5 "register_operand" "=r"))] "GET_CODE (operands[1]) == GET_CODE (operands[3])" [(set (match_dup 5) (and:CCEVEN (match_dup 4) (match_dup 2))) (set (match_dup 0) (match_op_dup 1 [(match_dup 5) (const_int 0)]))] "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);") (define_split [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (match_operator 1 "odd_relop" [(match_operand 2 "partial_ccmode_register_operand" "%r") (const_int 0)]) (match_operator 3 "even_relop" [(match_operand 4 "partial_ccmode_register_operand" "r") (const_int 0)]))) (clobber (match_operand:SI 5 "register_operand" "=r"))] "GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))" [(set (match_dup 5) (ior:CCEVEN (not:CC (match_dup 4)) (match_dup 2))) (set (match_dup 0) (match_op_dup 1 [(match_dup 5) (const_int 0)]))] "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);") (define_split [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (neg:SI (match_operator 1 "even_relop" [(match_operand 2 "partial_ccmode_register_operand" "%r") (const_int 0)])) (neg:SI (match_operator 3 "relop" [(match_operand 4 "partial_ccmode_register_operand" "r") (const_int 0)])))) (clobber (match_operand:SI 5 "register_operand" "=r"))] "" [(set (match_dup 5) (and:CCEVEN (match_dup 4) (match_dup 2))) (set (match_dup 0) (neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))] "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0); if (GET_CODE (operands[1]) == GET_CODE (operands[3])) ; /* The conditions match. */ else if (GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))) /* Reverse the condition by complimenting the compare word. */ operands[4] = gen_rtx (NOT, CCmode, operands[4]); else { /* Make the condition pairs line up by rotating the compare word. */ int cv1 = condition_value (operands[1]); int cv2 = condition_value (operands[3]); operands[4] = gen_rtx (ROTATE, CCmode, operands[4], gen_rtx (CONST_INT, VOIDmode, ((cv2 & ~1) - (cv1 & ~1)) & 0x1f)); /* Reverse the condition if needed. */ if ((cv1 & 1) != (cv2 & 1)) operands[4] = gen_rtx (NOT, CCmode, operands[4]); }") (define_split [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (neg:SI (match_operator 1 "odd_relop" [(match_operand 2 "partial_ccmode_register_operand" "%r") (const_int 0)])) (neg:SI (match_operator 3 "odd_relop" [(match_operand 4 "partial_ccmode_register_operand" "r") (const_int 0)])))) (clobber (match_operand:SI 5 "register_operand" "=r"))] "" [(set (match_dup 5) (ior:CCEVEN (match_dup 4) (match_dup 2))) (set (match_dup 0) (neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))] "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0); if (GET_CODE (operands[1]) == GET_CODE (operands[3])) ; /* The conditions match. */ else { /* Make the condition pairs line up by rotating the compare word. */ int cv1 = condition_value (operands[1]); int cv2 = condition_value (operands[3]); operands[4] = gen_rtx (ROTATE, CCmode, operands[4], gen_rtx (CONST_INT, VOIDmode, (cv2 - cv1) & 0x1f)); }") (define_split [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (neg:SI (match_operator 1 "odd_relop" [(match_operand 2 "partial_ccmode_register_operand" "%r") (const_int 0)])) (neg:SI (match_operator 3 "even_relop" [(match_operand 4 "partial_ccmode_register_operand" "r") (const_int 0)])))) (clobber (match_operand:SI 5 "register_operand" "=r"))] "" [(set (match_dup 5) (and:CCEVEN (not:CC (match_dup 2)) (match_dup 4))) (set (match_dup 0) (neg:SI (match_op_dup 3 [(match_dup 5) (const_int 0)])))] "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0); if (GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))) ; else { /* Make the condition pairs line up by rotating the compare word. */ int cv1 = condition_value (operands[1]); int cv2 = condition_value (operands[3]); operands[2] = gen_rtx (ROTATE, CCmode, operands[2], gen_rtx (CONST_INT, VOIDmode, ((cv1 & ~1) - (cv2 & ~1)) & 0x1f)); }") (define_split [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (match_operator 1 "even_relop" [(match_operand 2 "partial_ccmode_register_operand" "%r") (const_int 0)]) (match_operator 3 "relop" [(match_operand 4 "partial_ccmode_register_operand" "r") (const_int 0)]))) (clobber (match_operand:SI 5 "register_operand" "=r"))] "GET_CODE (operands[1]) == GET_CODE (operands[3]) || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))" [(set (match_dup 5) (and:CCEVEN (match_dup 4) (match_dup 2))) (set (match_dup 0) (match_op_dup 1 [(match_dup 5) (const_int 0)]))] "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0); /* Reverse the condition by complimenting the compare word. */ if (GET_CODE (operands[1]) != GET_CODE (operands[3])) operands[4] = gen_rtx (NOT, CCmode, operands[4]);") (define_split [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (match_operator 1 "odd_relop" [(match_operand 2 "partial_ccmode_register_operand" "%r") (const_int 0)]) (match_operator 3 "odd_relop" [(match_operand 4 "partial_ccmode_register_operand" "r") (const_int 0)]))) (clobber (match_operand:SI 5 "register_operand" "=r"))] "GET_CODE (operands[1]) == GET_CODE (operands[3])" [(set (match_dup 5) (ior:CCEVEN (match_dup 4) (match_dup 2))) (set (match_dup 0) (match_op_dup 1 [(match_dup 5) (const_int 0)]))] "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);") (define_split [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (match_operator 1 "odd_relop" [(match_operand 2 "partial_ccmode_register_operand" "%r") (const_int 0)]) (match_operator 3 "even_relop" [(match_operand 4 "partial_ccmode_register_operand" "r") (const_int 0)]))) (clobber (match_operand:SI 5 "register_operand" "=r"))] "GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))" [(set (match_dup 5) (and:CCEVEN (not:CC (match_dup 2)) (match_dup 4))) (set (match_dup 0) (match_op_dup 3 [(match_dup 5) (const_int 0)]))] "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);") ;; Logical operations on compare words. (define_insn "" [(set (match_operand:CCEVEN 0 "register_operand" "=r") (and:CCEVEN (not:CC (match_operand 1 "partial_ccmode_register_operand" "r")) (match_operand 2 "partial_ccmode_register_operand" "r")))] "" "and.c %0,%2,%1") (define_insn "" [(set (match_operand:CCEVEN 0 "register_operand" "=r") (and:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "%r") (match_operand 2 "partial_ccmode_register_operand" "r")))] "" "and %0,%1,%2") (define_insn "" [(set (match_operand:CCEVEN 0 "register_operand" "=r") (ior:CCEVEN (not:CC (match_operand 1 "partial_ccmode_register_operand" "r")) (match_operand 2 "partial_ccmode_register_operand" "r")))] "" "or.c %0,%2,%1") (define_insn "" [(set (match_operand:CCEVEN 0 "register_operand" "=r") (ior:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "%r") (match_operand 2 "partial_ccmode_register_operand" "r")))] "" "or %0,%1,%2") (define_insn "" [(set (match_operand:CC 0 "register_operand" "=r") (rotate:CC (match_operand:CC 1 "register_operand" "r") (match_operand:CC 2 "int5_operand" "")))] "" "rot %0,%1,%2" [(set_attr "type" "bit")]) (define_insn "" [(set (match_operand:CCEVEN 0 "register_operand" "=r") (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") (match_operand:CC 2 "int5_operand" "")))] "" "rot %0,%1,%2" [(set_attr "type" "bit")]) ;; rotate/and[.c] and rotate/ior[.c] (define_split [(set (match_operand:CCEVEN 0 "register_operand" "=r") (ior:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") (match_operand:CC 2 "int5_operand" "")) (match_operand 3 "partial_ccmode_register_operand" "r"))) (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))] "" [(set (match_dup 4) (rotate:CC (match_dup 1) (match_dup 2))) (set (match_dup 0) (ior:CCEVEN (match_dup 4) (match_dup 3)))] "") (define_insn "" [(set (match_operand:CCEVEN 0 "register_operand" "=r") (ior:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") (match_operand:CC 2 "int5_operand" "")) (match_operand 3 "partial_ccmode_register_operand" "r"))) (clobber (match_scratch:CCEVEN 4 "=r"))] "" "#") (define_split [(set (match_operand:CCEVEN 0 "register_operand" "=r") (ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") (match_operand:CC 2 "int5_operand" ""))) (match_operand 3 "partial_ccmode_register_operand" "r"))) (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))] "" [(set (match_dup 4) (rotate:CC (match_dup 1) (match_dup 2))) (set (match_dup 0) (ior:CCEVEN (not:CC (match_dup 4)) (match_dup 3)))] "") (define_insn "" [(set (match_operand:CCEVEN 0 "register_operand" "=r") (ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") (match_operand:CC 2 "int5_operand" ""))) (match_operand 3 "partial_ccmode_register_operand" "r"))) (clobber (match_scratch:CCEVEN 4 "=r"))] "" "#") (define_split [(set (match_operand:CCEVEN 0 "register_operand" "=r") (and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") (match_operand:CC 2 "int5_operand" "")) (match_operand 3 "partial_ccmode_register_operand" "r"))) (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))] "" [(set (match_dup 4) (rotate:CC (match_dup 1) (match_dup 2))) (set (match_dup 0) (and:CCEVEN (match_dup 4) (match_dup 3)))] "") (define_insn "" [(set (match_operand:CCEVEN 0 "register_operand" "=r") (and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") (match_operand:CC 2 "int5_operand" "")) (match_operand 3 "partial_ccmode_register_operand" "r"))) (clobber (match_scratch:CCEVEN 4 "=r"))] "" "#") (define_split [(set (match_operand:CCEVEN 0 "register_operand" "=r") (and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") (match_operand:CC 2 "int5_operand" ""))) (match_operand 3 "partial_ccmode_register_operand" "r"))) (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))] "" [(set (match_dup 4) (rotate:CC (match_dup 1) (match_dup 2))) (set (match_dup 0) (and:CCEVEN (not:CC (match_dup 4)) (match_dup 3)))] "") (define_insn "" [(set (match_operand:CCEVEN 0 "register_operand" "=r") (and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r") (match_operand:CC 2 "int5_operand" ""))) (match_operand 3 "partial_ccmode_register_operand" "r"))) (clobber (match_scratch:CCEVEN 4 "=r"))] "" "#") ;; Recognize bcnd instructions for integer values. This is distinguished ;; from a conditional branch instruction (below) with SImode instead of ;; CCmode. (define_insn "" [(set (pc) (if_then_else (match_operator 0 "relop_no_unsigned" [(match_operand:SI 1 "register_operand" "r") (const_int 0)]) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bcnd%. %R3%B0,%1,%P2%P3" [(set_attr "type" "branch")]) ;; Recognize tests for sign and zero. (define_insn "" [(set (pc) (if_then_else (match_operator 0 "equality_op" [(match_operand:SI 1 "register_operand" "r") (const_int -2147483648)]) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bcnd%. %R3%E0,%1,%P2%P3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (match_operator 0 "equality_op" [(zero_extract:SI (match_operand:SI 1 "register_operand" "r") (const_int 31) (const_int 1)) (const_int 0)]) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bcnd%. %R3%D0,%1,%P2%P3" [(set_attr "type" "branch")]) ;; Recognize bcnd instructions for double integer values (define_insn "" [(set (pc) (if_then_else (match_operator 0 "relop_no_unsigned" [(sign_extend:DI (match_operand:SI 1 "register_operand" "r")) (const_int 0)]) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bcnd%. %R3%B0,%1,%P2%P3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (match_operator 0 "equality_op" [(zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (const_int 0)]) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bcnd%. %R3%B0,%1,%P2%P3" [(set_attr "type" "branch")]) ; @@ I doubt this is interesting until cmpdi is provided. Anyway, it needs ; to be reworked. ; ;(define_insn "" ; [(set (pc) ; (if_then_else ; (match_operator 0 "relop_no_unsigned" ; [(match_operand:DI 1 "register_operand" "r") ; (const_int 0)]) ; (match_operand 2 "pc_or_label_ref" "") ; (match_operand 3 "pc_or_label_ref" "")))] ; "" ; "* ;{ ; switch (GET_CODE (operands[0])) ; { ; case EQ: ; case NE: ; /* I'm not sure if it's safe to use .n here. */ ; return \"or %!,%1,%d1\;bcnd %R3%B0,%!,%P2%P3\"; ; case GE: ; case LT: ; return \"bcnd%. %R3%B0,%1,%P2%P3\"; ; case GT: ; { ; rtx op2 = operands[2]; ; operands[2] = operands[3]; ; operands[3] = op2; ; } ; case LE: ; if (GET_CODE (operands[3]) == LABEL_REF) ; { ; int label_num; ; operands[2] = gen_label_rtx (); ; label_num = XINT (operands[2], 3); ; output_asm_insn ; (\"bcnd%. %#lt0,%1,%2\;or %!,%1,%d1\;bcnd %#ne0,%!,%3\", operands); ; output_label (label_num); ; return \"\"; ; } ; else ; return \"bcnd%. %#lt0,%1,%2\;or %!,%1,%d1\;bcnd %#eq0,%!,%2\"; ; } ;}") ;; Recognize bcnd instructions for single precision float values ;; Exclude relational operations as they must signal NaNs. ;; @@ These bcnd insns for float and double values don't seem to be recognized. (define_insn "" [(set (pc) (if_then_else (match_operator 0 "equality_op" [(float_extend:DF (match_operand:SF 1 "register_operand" "r")) (const_int 0)]) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bcnd%. %R3%D0,%1,%P2%P3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (match_operator 0 "equality_op" [(match_operand:SF 1 "register_operand" "r") (const_int 0)]) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bcnd%. %R3%D0,%1,%P2%P3" [(set_attr "type" "branch")]) ;; Recognize bcnd instructions for double precision float values ;; Exclude relational operations as they must signal NaNs. (define_insn "" [(set (pc) (if_then_else (match_operator 0 "equality_op" [(match_operand:DF 1 "register_operand" "r") (const_int 0)]) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "* { int label_num; if (GET_CODE (operands[0]) == NE) { rtx op2 = operands[2]; operands[2] = operands[3]; operands[3] = op2; } if (GET_CODE (operands[3]) == LABEL_REF) return \"bcnd 0x5,%1,%3\;bcnd %#ne0,%d1,%3\"; operands[3] = gen_label_rtx (); label_num = XINT (operands[3], 3); output_asm_insn (\"bcnd 0x5,%1,%3\;bcnd %#eq0,%d1,%2\", operands); output_label (label_num); return \"\"; }" [(set_attr "type" "weird") (set_attr "length" "3")]) ;; Recognize bb0 and bb1 instructions. These use two unusual template ;; patterns, %Lx and %Px. %Lx outputs a 1 if operand `x' is a LABEL_REF ;; otherwise it outputs a 0. It then may print ".n" if the delay slot ;; is used. %Px does noting if `x' is PC and outputs the operand if `x' ;; is a LABEL_REF. (define_insn "" [(set (pc) (if_then_else (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r") (const_int 1) (match_operand:SI 1 "int5_operand" "")) (const_int 0)) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bb%L2 (31-%1),%0,%P2%P3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r") (const_int 1) (match_operand:SI 1 "int5_operand" "")) (const_int 0)) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bb%L3 (31-%1),%0,%P2%P3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r") (const_int 1) (match_operand:SI 1 "int5_operand" "")) (const_int 0)) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bb%L2 (31-%1),%0,%P2%P3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r") (const_int 1) (match_operand:SI 1 "int5_operand" "")) (const_int 0)) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bb%L3 (31-%1),%0,%P2%P3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (eq (and:SI (match_operand:SI 0 "reg_or_bbx_mask_operand" "%r") (match_operand:SI 1 "reg_or_bbx_mask_operand" "n")) (const_int 0)) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "(GET_CODE (operands[0]) == CONST_INT) != (GET_CODE (operands[1]) == CONST_INT)" "bb%L3 %p1,%0,%P2%P3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (ne (and:SI (match_operand:SI 0 "reg_or_bbx_mask_operand" "%r") (match_operand:SI 1 "reg_or_bbx_mask_operand" "n")) (const_int 0)) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "(GET_CODE (operands[0]) == CONST_INT) != (GET_CODE (operands[1]) == CONST_INT)" "bb%L2 %p1,%0,%P2%P3" [(set_attr "type" "branch")]) ;; The comparison operations store the comparison into a register and ;; record that register. The following Bxx or Sxx insn uses that ;; register as an input. To facilitate use of bcnd instead of cmp/bb1, ;; cmpsi records it's operands and produces no code when any operand ;; is constant. In this case, the Bxx insns use gen_bcnd and the ;; Sxx insns use gen_test to ensure a cmp has been emitted. ;; ;; This could also be done for SFmode and DFmode having only beq and bne ;; use gen_bcnd. The others must signal NaNs. It seems though that zero ;; has already been copied into a register. ;; ;; cmpsi/beq and cmpsi/bne can always be done with bcnd if any operand ;; is a constant. (This idea is due to Torbjorn Granlund.) Others can ;; use bcnd only if an operand is zero. ;; ;; It is necessary to distinguish a register holding condition codes. ;; This is done by context. (define_expand "test" [(set (match_dup 2) (compare:CC (match_operand 0 "" "") (match_operand 1 "" "")))] "" " { if (m88k_compare_reg) abort (); if (GET_CODE (operands[0]) == CONST_INT && ! SMALL_INT (operands[0])) operands[0] = force_reg (SImode, operands[0]); if (GET_CODE (operands[1]) == CONST_INT && ! SMALL_INT (operands[1])) operands[1] = force_reg (SImode, operands[1]); operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode); }") ; @@ The docs say don't do this. It's probably a nop since the insn looks ; identical to cmpsi against zero. Is there an advantage to providing ; this, perhaps with a different form? ;(define_expand "tstsi" ; [(set (match_dup 1) ; (compare:CC (match_operand:SI 0 "register_operand" "") ; (const_int 0)))] ; "" ; " ;{ ; m88k_compare_reg = 0; ; m88k_compare_op0 = operands[0]; ; m88k_compare_op1 = const0_rtx; ; DONE; ;}") (define_expand "cmpsi" [(set (match_dup 2) (compare:CC (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "arith32_operand" "")))] "" " { if (GET_CODE (operands[0]) == CONST_INT || GET_CODE (operands[1]) == CONST_INT) { m88k_compare_reg = 0; m88k_compare_op0 = operands[0]; m88k_compare_op1 = operands[1]; DONE; } operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode); }") (define_expand "cmpsf" [(set (match_dup 2) (compare:CC (match_operand:SF 0 "register_operand" "") (match_operand:SF 1 "register_operand" "")))] "" "operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode);") (define_expand "cmpdf" [(set (match_dup 2) (compare:CC (match_operand:DF 0 "general_operand" "") (match_operand:DF 1 "general_operand" "")))] "" " { operands[0] = legitimize_operand (operands[0], DFmode); operands[1] = legitimize_operand (operands[1], DFmode); operands[2] = m88k_compare_reg = gen_reg_rtx (CCmode); }") ; @@ Get back to this later on. ; ;(define_insn "cmpdi" ; [(set (cc0) ; (compare:CC (match_operand:DI 0 "register_operand" "r") ; (match_operand:DI 1 "register_operand" "r")))] ; "" ; "* ;{ ; if ((cc_status.mdep & MDEP_LS_CHANGE) != 0) ; abort (); /* output_move_double MDEP_LS_CHANGE bits were set. */ ; ; cc_status.mdep &= ~ MDEP_LS_MASK; ; ; operands[2] = gen_label_rtx (); ; /* Remember, %! is the condition code register and %@ is the ; literal synthesis register. */ ; ; output_asm_insn (\"cmp %!,%0,%1\;bb0 %#eq,%!,%l2\;cmp %!,%d0,%d1\", ; operands); ; ; output_asm_insn (\"extu %@,%!,4<8>\;clr %!,%!,4<4>\", operands); ; output_asm_insn (\"mak %@,%@,4<4>\;or %!,%!,%@\", operands); ; output_label (XINT (operands[2], 3)); ; return \"\"; ;}" ;; The actual compare instructions. (define_insn "" [(set (match_operand:CC 0 "register_operand" "=r") (compare:CC (match_operand:SI 1 "register_operand" "rO") (match_operand:SI 2 "arith_operand" "rI")))] "" "cmp %0,%r1,%2") (define_insn "" [(set (match_operand:CC 0 "register_operand" "=r,r,r,r") (compare:CC (match_operand:SF 1 "register_operand" "r,r,x,x") (match_operand:SF 2 "real_or_0_operand" "r,G,x,G")))] "" "@ fcmp.sss %0,%1,%2 fcmp.sss %0,%1,%#r0 fcmp.sss %0,%1,%2 fcmp.sss %0,%1,%#x0" [(set_attr "type" "spcmp")]) (define_insn "" [(set (match_operand:CC 0 "register_operand" "=r,r") (compare:CC (match_operand:DF 1 "register_operand" "r,x") (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fcmp.sds %0,%1,%2" [(set_attr "type" "dpcmp")]) (define_insn "" [(set (match_operand:CC 0 "register_operand" "=r,r") (compare:CC (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) (match_operand:DF 2 "register_operand" "r,x")))] "" "fcmp.ssd %0,%1,%2" [(set_attr "type" "dpcmp")]) (define_insn "" [(set (match_operand:CC 0 "register_operand" "=r,r,r,r") (compare:CC (match_operand:DF 1 "register_operand" "r,r,x,x") (match_operand:DF 2 "real_or_0_operand" "r,G,x,G")))] "" "@ fcmp.sdd %0,%1,%2 fcmp.sds %0,%1,%#r0 fcmp.sdd %0,%1,%2 fcmp.sds %0,%1,%#x0" [(set_attr "type" "dpcmp")]) ;; Store condition code insns. The compare insns set a register ;; rather than cc0 and record that register for use here. See above ;; for the special treatment of cmpsi with a constant operand. ;; @@ For the m88110, use fcmpu for bxx sxx inequality comparisons. (define_expand "seq" [(set (match_operand:SI 0 "register_operand" "") (match_dup 1))] "" "operands[1] = emit_test (EQ, SImode);") (define_expand "sne" [(set (match_operand:SI 0 "register_operand" "") (match_dup 1))] "" "operands[1] = emit_test (NE, SImode);") (define_expand "sgt" [(set (match_operand:SI 0 "register_operand" "") (match_dup 1))] "" "operands[1] = emit_test (GT, SImode);") (define_expand "sgtu" [(set (match_operand:SI 0 "register_operand" "") (match_dup 1))] "" "operands[1] = emit_test (GTU, SImode);") (define_expand "slt" [(set (match_operand:SI 0 "register_operand" "") (match_dup 1))] "" "operands[1] = emit_test (LT, SImode);") (define_expand "sltu" [(set (match_operand:SI 0 "register_operand" "") (match_dup 1))] "" "operands[1] = emit_test (LTU, SImode);") (define_expand "sge" [(set (match_operand:SI 0 "register_operand" "") (match_dup 1))] "" "operands[1] = emit_test (GE, SImode);") (define_expand "sgeu" [(set (match_operand:SI 0 "register_operand" "") (match_dup 1))] "" "operands[1] = emit_test (GEU, SImode);") (define_expand "sle" [(set (match_operand:SI 0 "register_operand" "") (match_dup 1))] "" "operands[1] = emit_test (LE, SImode);") (define_expand "sleu" [(set (match_operand:SI 0 "register_operand" "") (match_dup 1))] "" "operands[1] = emit_test (LEU, SImode);") ;; The actual set condition code instruction. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (match_operator:SI 1 "relop" [(match_operand:CC 2 "register_operand" "r") (const_int 0)]))] "" "ext %0,%2,1<%C1>" [(set_attr "type" "bit")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (match_operator:SI 1 "even_relop" [(match_operand:CCEVEN 2 "register_operand" "r") (const_int 0)]))] "" "ext %0,%2,1<%C1>" [(set_attr "type" "bit")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (not:SI (match_operator:SI 1 "odd_relop" [(match_operand:CCEVEN 2 "register_operand" "r") (const_int 0)])))] "" "ext %0,%2,1<%!%C1>" [(set_attr "type" "bit")]) (define_split [(set (match_operand:SI 0 "register_operand" "=r") (match_operator:SI 1 "odd_relop" [(match_operand:CCEVEN 2 "register_operand" "r") (const_int 0)])) (clobber (match_operand:SI 3 "register_operand" "=r"))] "" [(set (match_dup 3) (not:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]))) (set (match_dup 0) (not:SI (match_dup 3)))] "") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (match_operator:SI 1 "odd_relop" [(match_operand:CCEVEN 2 "register_operand" "r") (const_int 0)])) (clobber (match_scratch:SI 3 "=r"))] "" "#") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operator:SI 1 "relop" [(match_operand:CC 2 "register_operand" "r") (const_int 0)])))] "" "extu %0,%2,1<%C1>" [(set_attr "type" "bit")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operator:SI 1 "even_relop" [(match_operand:CCEVEN 2 "register_operand" "r") (const_int 0)])))] "" "extu %0,%2,1<%C1>" [(set_attr "type" "bit")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (not:SI (match_operator:SI 1 "odd_relop" [(match_operand:CCEVEN 2 "register_operand" "r") (const_int 0)]))))] "" "extu %0,%2,1<%!%C1>" [(set_attr "type" "bit")]) (define_split [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operator:SI 1 "odd_relop" [(match_operand:CCEVEN 2 "register_operand" "r") (const_int 0)]))) (clobber (match_operand:SI 3 "register_operand" "=r"))] "" [(set (match_dup 3) (neg:SI (not:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])))) (set (match_dup 0) (xor:SI (match_dup 3) (const_int 1)))] "") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operator:SI 1 "odd_relop" [(match_operand:CCEVEN 2 "register_operand" "r") (const_int 0)]))) (clobber (match_scratch:SI 3 "=r"))] "" "#") ;; Conditional branch insns. The compare insns set a register ;; rather than cc0 and record that register for use here. See above ;; for the special case of cmpsi with a constant operand. (define_expand "bcnd" [(set (pc) (if_then_else (match_operand 0 "" "") (label_ref (match_operand 1 "" "")) (pc)))] "" "if (m88k_compare_reg) abort ();") (define_expand "bxx" [(set (pc) (if_then_else (match_operand 0 "" "") (label_ref (match_operand 1 "" "")) (pc)))] "" "if (m88k_compare_reg == 0) abort ();") (define_expand "beq" [(set (pc) (if_then_else (eq (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "if (m88k_compare_reg == 0) { emit_bcnd (EQ, operands[0]); DONE; } operands[1] = m88k_compare_reg;") (define_expand "bne" [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "if (m88k_compare_reg == 0) { emit_bcnd (NE, operands[0]); DONE; } operands[1] = m88k_compare_reg;") (define_expand "bgt" [(set (pc) (if_then_else (gt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "if (m88k_compare_reg == 0) { emit_bcnd (GT, operands[0]); DONE; } operands[1] = m88k_compare_reg;") (define_expand "bgtu" [(set (pc) (if_then_else (gtu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "if (m88k_compare_reg == 0) { emit_jump_insn (gen_bxx (emit_test (GTU, VOIDmode), operands[0])); DONE; } operands[1] = m88k_compare_reg;") (define_expand "blt" [(set (pc) (if_then_else (lt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "if (m88k_compare_reg == 0) { emit_bcnd (LT, operands[0]); DONE; } operands[1] = m88k_compare_reg;") (define_expand "bltu" [(set (pc) (if_then_else (ltu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "if (m88k_compare_reg == 0) { emit_jump_insn (gen_bxx (emit_test (LTU, VOIDmode), operands[0])); DONE; } operands[1] = m88k_compare_reg;") (define_expand "bge" [(set (pc) (if_then_else (ge (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "if (m88k_compare_reg == 0) { emit_bcnd (GE, operands[0]); DONE; } operands[1] = m88k_compare_reg;") (define_expand "bgeu" [(set (pc) (if_then_else (geu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "if (m88k_compare_reg == 0) { emit_jump_insn (gen_bxx (emit_test (GEU, VOIDmode), operands[0])); DONE; } operands[1] = m88k_compare_reg;") (define_expand "ble" [(set (pc) (if_then_else (le (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "if (m88k_compare_reg == 0) { emit_bcnd (LE, operands[0]); DONE; } operands[1] = m88k_compare_reg;") (define_expand "bleu" [(set (pc) (if_then_else (leu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "if (m88k_compare_reg == 0) { emit_jump_insn (gen_bxx (emit_test (LEU, VOIDmode), operands[0])); DONE; } operands[1] = m88k_compare_reg;") ;; The actual conditional branch instruction (both directions). This ;; uses two unusual template patterns, %Rx and %Px. %Rx is a prefix code ;; for the immediately following condition and reverses the condition iff ;; operand `x' is a LABEL_REF. %Px does nothing if `x' is PC and outputs ;; the operand if `x' is a LABEL_REF. (define_insn "" [(set (pc) (if_then_else (match_operator 0 "relop" [(match_operand:CC 1 "register_operand" "r") (const_int 0)]) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "* { if (mostly_false_jump (insn, operands[0])) return \"bb0%. %R2%C0,%1,%P2%P3\"; else return \"bb1%. %R3%C0,%1,%P2%P3\"; }" [(set_attr "type" "branch")]) ;; ;; Here branch prediction is sacrificed. To get it back, you need ;; - CCODD (CC mode where the ODD bits are valid) ;; - several define_split that can apply De Morgan's Law. ;; - transformations between CCEVEN and CCODD modes. ;; (define_insn "" [(set (pc) (if_then_else (match_operator 0 "even_relop" [(match_operand:CCEVEN 1 "register_operand" "r") (const_int 0)]) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bb%L2%. %C0,%1,%P2%P3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (match_operator 0 "odd_relop" [(match_operand:CCEVEN 1 "register_operand" "r") (const_int 0)]) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bb%L3%. %!%C0,%1,%P2%P3" [(set_attr "type" "branch")]) ;; Branch conditional on scc values. These arise from manipulations on ;; compare words above. ;; Are these really used ? (define_insn "" [(set (pc) (if_then_else (ne (match_operator 0 "relop" [(match_operand:CC 1 "register_operand" "r") (const_int 0)]) (const_int 0)) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bb%L2 %C0,%1,%P2%P3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (ne (match_operator 0 "even_relop" [(match_operand:CCEVEN 1 "register_operand" "r") (const_int 0)]) (const_int 0)) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bb%L2 %C0,%1,%P2%P3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (ne (match_operator 0 "odd_relop" [(match_operand:CCEVEN 1 "register_operand" "r") (const_int 0)]) (const_int 0)) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bb%L3 %!%C0,%1,%P2%P3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (eq (match_operator 0 "relop" [(match_operand:CC 1 "register_operand" "r") (const_int 0)]) (const_int 0)) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bb%L3 %C0,%1,%P2%P3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (eq (match_operator 0 "even_relop" [(match_operand:CCEVEN 1 "register_operand" "r") (const_int 0)]) (const_int 0)) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bb%L3 %C0,%1,%P2%P3" [(set_attr "type" "branch")]) (define_insn "" [(set (pc) (if_then_else (eq (match_operator 0 "odd_relop" [(match_operand:CCEVEN 1 "register_operand" "r") (const_int 0)]) (const_int 0)) (match_operand 2 "pc_or_label_ref" "") (match_operand 3 "pc_or_label_ref" "")))] "" "bb%L2 %!%C0,%1,%P2%P3" [(set_attr "type" "branch")]) (define_insn "locate1" [(set (match_operand:SI 0 "register_operand" "=r") (high:SI (unspec:SI [(label_ref (match_operand 1 "" ""))] 0)))] "" "or.u %0,%#r0,%#hi16(%1#abdiff)") (define_insn "locate2" [(parallel [(set (reg:SI 1) (pc)) (set (match_operand:SI 0 "register_operand" "=r") (lo_sum:SI (match_dup 0) (unspec:SI [(label_ref (match_operand 1 "" ""))] 0)))])] "" "bsr.n %1\;or %0,%0,%#lo16(%1#abdiff)\\n%1:" [(set_attr "length" "2")]) ;; SImode move instructions (define_expand "movsi" [(set (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))] "" " { if (emit_move_sequence (operands, SImode, 0)) DONE; }") (define_expand "reload_insi" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "general_operand" "")) (clobber (match_operand:SI 2 "register_operand" "=&r"))] "" " { if (emit_move_sequence (operands, SImode, operands[2])) DONE; /* We don't want the clobber emitted, so handle this ourselves. */ emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1])); DONE; }") (define_insn "" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,x,x,x,m") (match_operand:SI 1 "move_operand" "rI,m,rO,J,M,x,r,x,m,x"))] "(register_operand (operands[0], SImode) || register_operand (operands[1], SImode) || operands[1] == const0_rtx)" "@ or %0,%#r0,%1 %V1ld\\t %0,%1 %v0st\\t %r1,%0 subu %0,%#r0,%n1 set %0,%#r0,%s1 mov.s %0,%1 mov.s %0,%1 mov %0,%1 %V1ld\\t %0,%1 %v0st\\t %1,%0" [(set_attr "type" "arith,load,store,arith,bit,mov,mov,mov,load,store")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") (match_operand:SI 1 "arith32_operand" "rI,J,L,M,n"))] "" "@ or %0,%#r0,%1 subu %0,%#r0,%n1 or.u %0,%#r0,%X1 set %0,%#r0,%s1 or.u %0,%#r0,%X1\;or %0,%0,%x1" [(set_attr "type" "arith,arith,arith,bit,marith")]) ;; @@ Why the constraint "in"? Doesn't `i' include `n'? (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "in")))] "" "or %0,%1,%#lo16(%g2)") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (high:SI (match_operand 1 "" "")))] "" "or.u %0,%#r0,%#hi16(%g1)") ;; HImode move instructions (define_expand "movhi" [(set (match_operand:HI 0 "general_operand" "") (match_operand:HI 1 "general_operand" ""))] "" " { if (emit_move_sequence (operands, HImode, 0)) DONE; }") (define_insn "" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r") (match_operand:HI 1 "move_operand" "rP,m,rO,N"))] "(register_operand (operands[0], HImode) || register_operand (operands[1], HImode) || operands[1] == const0_rtx)" "@ or %0,%#r0,%h1 %V1ld.hu\\t %0,%1 %v0st.h\\t %r1,%0 subu %0,%#r0,%H1" [(set_attr "type" "arith,load,store,arith")]) (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (subreg:HI (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "in")) 0))] "!flag_pic" "or %0,%1,%#lo16(%2)") ;; QImode move instructions (define_expand "movqi" [(set (match_operand:QI 0 "general_operand" "") (match_operand:QI 1 "general_operand" ""))] "" " { if (emit_move_sequence (operands, QImode, 0)) DONE; }") (define_insn "" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r") (match_operand:QI 1 "move_operand" "rP,m,rO,N"))] "(register_operand (operands[0], QImode) || register_operand (operands[1], QImode) || operands[1] == const0_rtx)" "@ or %0,%#r0,%q1 %V1ld.bu\\t %0,%1 %v0st.b\\t %r1,%0 subu %r0,%#r0,%Q1" [(set_attr "type" "arith,load,store,arith")]) (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") (subreg:QI (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "in")) 0))] "!flag_pic" "or %0,%1,%#lo16(%2)") ;; DImode move instructions (define_expand "movdi" [(set (match_operand:DI 0 "general_operand" "") (match_operand:DI 1 "general_operand" ""))] "" " { if (emit_move_sequence (operands, DImode, 0)) DONE; }") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r,x") (const_int 0))] "" "@ or %0,%#r0,0\;or %d0,%#r0,0 mov %0,%#x0" [(set_attr "type" "marith,mov")]) (define_insn "" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,x,x,x,m") (match_operand:DI 1 "nonimmediate_operand" "r,m,r,x,r,x,m,x"))] "" "@ or %0,%#r0,%1\;or %d0,%#r0,%d1 %V1ld.d\\t %0,%1 %v0st.d\\t %1,%0 mov.d %0,%1 mov.d %0,%1 mov %0,%1 %V1ld.d\\t %0,%1 %v0st.d\\t %1,%0" [(set_attr "type" "marith,loadd,store,mov,mov,mov,loadd,store")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (subreg:DI (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "in")) 0))] "!flag_pic" "or %0,%1,%#lo16(%2)") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "immediate_operand" "n"))] "" "* return output_load_const_dimode (operands);" [(set_attr "type" "marith") (set_attr "length" "4")]) ; length is 2, 3 or 4. ;; DFmode move instructions (define_expand "movdf" [(set (match_operand:DF 0 "general_operand" "") (match_operand:DF 1 "general_operand" ""))] "" " { if (emit_move_sequence (operands, DFmode, 0)) DONE; }") ;; @@ This pattern is incomplete and doesn't appear necessary. ;; ;; This pattern forces (set (reg:DF ...) (const_double ...)) ;; to be reloaded by putting the constant into memory. ;; It must come before the more general movdf pattern. ;(define_insn "" ; [(set (match_operand:DF 0 "general_operand" "=r,o") ; (match_operand:DF 1 "" "G,G"))] ; "GET_CODE (operands[1]) == CONST_DOUBLE" ; "* ;{ ; switch (which_alternative) ; { ; case 0: ; return \"or %0,%#r0,0\;or %d0,%#r0,0\"; ; case 1: ; operands[1] = adj_offsettable_operand (operands[0], 4); ; return \"%v0st\\t %#r0,%0\;st %#r0,%1\"; ; } ;}") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (const_int 0))] "" "@ or %0,%#r0,0\;or %d0,%#r0,0 mov %0,%#x0" [(set_attr "type" "marith,mov")]) (define_insn "" [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,x,r,x,x,m") (match_operand:DF 1 "nonimmediate_operand" "r,m,r,r,x,x,m,x"))] "" "@ or %0,%#r0,%1\;or %d0,%#r0,%d1 %V1ld.d\\t %0,%1 %v0st.d\\t %1,%0 mov.d %0,%1 mov.d %0,%1 mov %0,%1 %V1ld.d\\t %0,%1 %v0st.d\\t %1,%0" [(set_attr "type" "marith,loadd,store,mov,mov,mov,loadd,store")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r") (subreg:DF (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "in")) 0))] "!flag_pic" "or %0,%1,%#lo16(%2)") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r") (match_operand:DF 1 "immediate_operand" "F"))] "" "* return output_load_const_double (operands);" [(set_attr "type" "marith") (set_attr "length" "4")]) ; length is 2, 3, or 4. ;; SFmode move instructions (define_expand "movsf" [(set (match_operand:SF 0 "general_operand" "") (match_operand:SF 1 "general_operand" ""))] "" " { if (emit_move_sequence (operands, SFmode, 0)) DONE; }") ;; @@ What happens to fconst0_rtx? (define_insn "" [(set (match_operand:SF 0 "register_operand" "=r,x") (const_int 0))] "" "@ or %0,%#r0,0 mov %0,%#x0" [(set_attr "type" "arith,mov")]) (define_insn "" [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,x,r,x,x,m") (match_operand:SF 1 "nonimmediate_operand" "r,m,r,r,x,x,m,x"))] "" "@ or %0,%#r0,%1 %V1ld\\t %0,%1 %v0st\\t %r1,%0 mov.s %0,%1 mov.s %0,%1 mov %0,%1 %V1ld\\t %0,%1 %v0st\\t %r1,%0" [(set_attr "type" "arith,load,store,mov,mov,mov,load,store")]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=r") (subreg:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "in")) 0))] "!flag_pic" "or %0,%1,%#lo16(%2)") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=r") (match_operand:SF 1 "immediate_operand" "F"))] "operands[1] != const0_rtx" "* return output_load_const_float (operands);" [(set_attr "type" "marith")]) ; length is 1 or 2. ;; String/block move insn. See m88k.c for details. (define_expand "movstrsi" [(parallel [(set (mem:BLK (match_operand:BLK 0 "" "")) (mem:BLK (match_operand:BLK 1 "" ""))) (use (match_operand:SI 2 "arith32_operand" "")) (use (match_operand:SI 3 "immediate_operand" ""))])] "" " { rtx dest_mem = operands[0]; rtx src_mem = operands[1]; operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); expand_block_move (dest_mem, src_mem, operands); DONE; }") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") (match_operand:BLK 1 "memory_operand" "m"))] "" "%V1ld.bu\\t %0,%1" [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (match_operand:BLK 1 "memory_operand" "m"))] "" "%V1ld.hu\\t %0,%1" [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:BLK 1 "memory_operand" "m"))] "" "%V1ld\\t %0,%1" [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:BLK 1 "memory_operand" "m"))] "" "%V1ld.d\\t %0,%1" [(set_attr "type" "loadd")]) (define_insn "" [(set (match_operand:BLK 0 "memory_operand" "=m") (match_operand:QI 1 "register_operand" "r"))] "" "%v0st.b\\t %1,%0" [(set_attr "type" "store")]) (define_insn "" [(set (match_operand:BLK 0 "memory_operand" "=m") (match_operand:HI 1 "register_operand" "r"))] "" "%v0st.h\\t %1,%0" [(set_attr "type" "store")]) (define_insn "" [(set (match_operand:BLK 0 "memory_operand" "=m") (match_operand:SI 1 "register_operand" "r"))] "" "%v0st\\t %1,%0" [(set_attr "type" "store")]) (define_insn "" [(set (match_operand:BLK 0 "memory_operand" "=m") (match_operand:DI 1 "register_operand" "r"))] "" "%v0st.d\\t %1,%0" [(set_attr "type" "store")]) ;; Call a non-looping block move library function (e.g. __movstrSI96x64). ;; operand 0 is the function name ;; operand 1 is the destination pointer ;; operand 2 is the source pointer ;; operand 3 is the offset for the source and destination pointers ;; operand 4 is the first value to be loaded ;; operand 5 is the register to hold the value (r4 or r5) (define_expand "call_block_move" [(set (reg:SI 3) (minus:SI (match_operand:SI 2 "register_operand" "") (match_operand:SI 3 "immediate_operand" ""))) (set (match_operand 5 "register_operand" "") (match_operand 4 "memory_operand" "")) (set (reg:SI 2) (minus:SI (match_operand:SI 1 "register_operand" "") (match_dup 3))) (use (reg:SI 2)) (use (reg:SI 3)) (use (match_dup 5)) (parallel [(set (reg:DI 2) (call (mem:SI (match_operand 0 "" "")) (const_int 0))) (clobber (reg:SI 1))])] "" "") ;; Call an SImode looping block move library function (e.g. __movstrSI64n68). ;; operands 0-5 as in the non-looping interface ;; operand 6 is the loop count (define_expand "call_movstrsi_loop" [(set (reg:SI 3) (minus:SI (match_operand:SI 2 "register_operand" "") (match_operand:SI 3 "immediate_operand" ""))) (set (match_operand:SI 5 "register_operand" "") (match_operand 4 "memory_operand" "")) (set (reg:SI 2) (minus:SI (match_operand:SI 1 "register_operand" "") (match_dup 3))) (set (reg:SI 6) (match_operand:SI 6 "immediate_operand" "")) (use (reg:SI 2)) (use (reg:SI 3)) (use (match_dup 5)) (use (reg:SI 6)) (parallel [(set (reg:DI 2) (call (mem:SI (match_operand 0 "" "")) (const_int 0))) (clobber (reg:SI 1))])] "" "") ;;- zero extension instructions (define_expand "zero_extendhisi2" [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] "" " { if (GET_CODE (operands[1]) == MEM && symbolic_address_p (XEXP (operands[1], 0))) operands[1] = legitimize_address (flag_pic, operands[1], 0, 0); }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (zero_extend:SI (match_operand:HI 1 "move_operand" "!r,n,m")))] "GET_CODE (operands[1]) != CONST_INT" "@ mask %0,%1,0xffff or %0,%#r0,%h1 %V1ld.hu\\t %0,%1" [(set_attr "type" "arith,arith,load")]) (define_expand "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] "" " { if (GET_CODE (operands[1]) == MEM && symbolic_address_p (XEXP (operands[1], 0))) operands[1] = legitimize_address (flag_pic, operands[1], 0, 0); }") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r,r,r") (zero_extend:HI (match_operand:QI 1 "move_operand" "r,n,m")))] "GET_CODE (operands[1]) != CONST_INT" "@ mask %0,%1,0xff or %0,%#r0,%q1 %V1ld.bu\\t %0,%1" [(set_attr "type" "arith,arith,load")]) (define_expand "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] "" " { if (GET_CODE (operands[1]) == MEM && symbolic_address_p (XEXP (operands[1], 0))) { operands[1] = legitimize_address (flag_pic, operands[1], 0, 0); emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (ZERO_EXTEND, SImode, operands[1]))); DONE; } }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (zero_extend:SI (match_operand:QI 1 "move_operand" "r,n,m")))] "GET_CODE (operands[1]) != CONST_INT" "@ mask %0,%1,0xff or %0,%#r0,%q1 %V1ld.bu\\t %0,%1" [(set_attr "type" "arith,arith,load")]) ;;- sign extension instructions (define_expand "extendsidi2" [(set (subreg:SI (match_operand:DI 0 "register_operand" "=r") 1) (match_operand:SI 1 "general_operand" "g")) (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 0) 1) (const_int 31)))] "" "") (define_expand "extendhisi2" [(set (match_operand:SI 0 "register_operand" "") (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] "" " { if (GET_CODE (operands[1]) == MEM && symbolic_address_p (XEXP (operands[1], 0))) operands[1] = legitimize_address (flag_pic, operands[1], 0, 0); }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (sign_extend:SI (match_operand:HI 1 "move_operand" "!r,P,N,m")))] "GET_CODE (operands[1]) != CONST_INT" "@ ext %0,%1,16<0> or %0,%#r0,%h1 subu %0,%#r0,%H1 %V1ld.h\\t %0,%1" [(set_attr "type" "bit,arith,arith,load")]) (define_expand "extendqihi2" [(set (match_operand:HI 0 "register_operand" "") (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] "" " { if (GET_CODE (operands[1]) == MEM && symbolic_address_p (XEXP (operands[1], 0))) operands[1] = legitimize_address (flag_pic, operands[1], 0, 0); }") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") (sign_extend:HI (match_operand:QI 1 "move_operand" "!r,P,N,m")))] "GET_CODE (operands[1]) != CONST_INT" "@ ext %0,%1,8<0> or %0,%#r0,%q1 subu %0,%#r0,%Q1 %V1ld.b\\t %0,%1" [(set_attr "type" "bit,arith,arith,load")]) (define_expand "extendqisi2" [(set (match_operand:SI 0 "register_operand" "") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] "" " { if (GET_CODE (operands[1]) == MEM && symbolic_address_p (XEXP (operands[1], 0))) operands[1] = legitimize_address (flag_pic, operands[1], 0, 0); }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (sign_extend:SI (match_operand:QI 1 "move_operand" "!r,P,N,m")))] "GET_CODE (operands[1]) != CONST_INT" "@ ext %0,%1,8<0> or %0,%#r0,%q1 subu %0,%#r0,%Q1 %V1ld.b\\t %0,%1" [(set_attr "type" "bit,arith,arith,load")]) ;; Conversions between float and double. ;; The fadd instruction does not conform to IEEE 754 when used to ;; convert between float and double. In particular, the sign of -0 is ;; not preserved. Interestingly, fsub does conform. (define_expand "extendsfdf2" [(set (match_operand:DF 0 "register_operand" "=r") (float_extend:DF (match_operand:SF 1 "register_operand" "r")))] "" "") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r") (float_extend:DF (match_operand:SF 1 "register_operand" "r")))] "! TARGET_88110" "fsub.dss %0,%1,%#r0" [(set_attr "type" "spadd")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")))] "TARGET_88110" "fcvt.ds %0,%1" [(set_attr "type" "spadd")]) (define_expand "truncdfsf2" [(set (match_operand:SF 0 "register_operand" "=r") (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))] "" "") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=r") (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))] "! TARGET_88110" "fsub.sds %0,%1,%#r0" [(set_attr "type" "dpadd")]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=r,x") (float_truncate:SF (match_operand:DF 1 "register_operand" "r,x")))] "TARGET_88110" "fcvt.sd %0,%1" [(set_attr "type" "dpadd")]) ;; Conversions between floating point and integer (define_insn "floatsidf2" [(set (match_operand:DF 0 "register_operand" "=r,x") (float:DF (match_operand:SI 1 "register_operand" "r,r")))] "" "flt.ds %0,%1" [(set_attr "type" "spadd,dpadd")]) (define_insn "floatsisf2" [(set (match_operand:SF 0 "register_operand" "=r,x") (float:SF (match_operand:SI 1 "register_operand" "r,r")))] "" "flt.ss %0,%1" [(set_attr "type" "spadd,spadd")]) (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (fix:SI (match_operand:DF 1 "register_operand" "r,x")))] "" "trnc.sd %0,%1" [(set_attr "type" "dpadd,dpadd")]) (define_insn "fix_truncsfsi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (fix:SI (match_operand:SF 1 "register_operand" "r,x")))] "" "trnc.ss %0,%1" [(set_attr "type" "spadd,dpadd")]) ;;- arithmetic instructions ;;- add instructions (define_insn "addsi3" [(set (match_operand:SI 0 "register_operand" "=r,r") (plus:SI (match_operand:SI 1 "add_operand" "%r,r") (match_operand:SI 2 "add_operand" "rI,J")))] "" "@ addu %0,%1,%2 subu %0,%1,%n2") ;; patterns for mixed mode floating point. ;; Do not define patterns that utilize mixed mode arithmetic that result ;; in narrowing the precision, because it loses accuracy, since the standard ;; requires double rounding, whereas the 88000 instruction only rounds once. (define_expand "adddf3" [(set (match_operand:DF 0 "register_operand" "=r,x") (plus:DF (match_operand:DF 1 "general_operand" "%r,x") (match_operand:DF 2 "general_operand" "r,x")))] "" " { operands[1] = legitimize_operand (operands[1], DFmode); operands[2] = legitimize_operand (operands[2], DFmode); }") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fadd.dss %0,%1,%2" [(set_attr "type" "spadd")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (plus:DF (match_operand:DF 1 "register_operand" "r,x") (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fadd.dds %0,%1,%2" [(set_attr "type" "dpadd")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) (match_operand:DF 2 "register_operand" "r,x")))] "" "fadd.dsd %0,%1,%2" [(set_attr "type" "dpadd")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (plus:DF (match_operand:DF 1 "register_operand" "%r,x") (match_operand:DF 2 "register_operand" "r,x")))] "" "fadd.ddd %0,%1,%2" [(set_attr "type" "dpadd")]) (define_insn "addsf3" [(set (match_operand:SF 0 "register_operand" "=r,x") (plus:SF (match_operand:SF 1 "register_operand" "%r,x") (match_operand:SF 2 "register_operand" "r,x")))] "" "fadd.sss %0,%1,%2" [(set_attr "type" "spadd")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (match_operand:DI 1 "register_operand" "r") (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))) (clobber (reg:CC 0))] "" "addu.co %d0,%d1,%2\;addu.ci %0,%1,%#r0" [(set_attr "type" "marith")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (match_operand:DI 2 "register_operand" "r"))) (clobber (reg:CC 0))] "" "addu.co %d0,%1,%d2\;addu.ci %0,%#r0,%2" [(set_attr "type" "marith")]) (define_insn "adddi3" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (match_operand:DI 1 "register_operand" "%r") (match_operand:DI 2 "register_operand" "r"))) (clobber (reg:CC 0))] "" "addu.co %d0,%d1,%d2\;addu.ci %0,%1,%2" [(set_attr "type" "marith")]) ;; Add with carry insns. (define_insn "" [(parallel [(set (match_operand:SI 0 "reg_or_0_operand" "=r") (plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO") (match_operand:SI 2 "reg_or_0_operand" "rO"))) (set (reg:CC 0) (unspec:CC [(match_dup 1) (match_dup 2)] 0))])] "" "addu.co %r0,%r1,%r2") (define_insn "" [(set (reg:CC 0) (unspec:CC [(match_operand:SI 0 "reg_or_0_operand" "rO") (match_operand:SI 1 "reg_or_0_operand" "rO")] 0))] "" "addu.co %#r0,%r0,%r1") (define_insn "" [(set (match_operand:SI 0 "reg_or_0_operand" "=r") (plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO") (unspec:SI [(match_operand:SI 2 "reg_or_0_operand" "rO") (reg:CC 0)] 0)))] "" "addu.ci %r0,%r1,%r2") ;;- subtract instructions (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith32_operand" "rI")))] "" "subu %0,%1,%2") ;; patterns for mixed mode floating point ;; Do not define patterns that utilize mixed mode arithmetic that result ;; in narrowing the precision, because it loses accuracy, since the standard ;; requires double rounding, whereas the 88000 instruction only rounds once. (define_expand "subdf3" [(set (match_operand:DF 0 "register_operand" "=r,x") (minus:DF (match_operand:DF 1 "general_operand" "r,x") (match_operand:DF 2 "general_operand" "r,x")))] "" " { operands[1] = legitimize_operand (operands[1], DFmode); operands[2] = legitimize_operand (operands[2], DFmode); }") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (minus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fsub.dss %0,%1,%2" [(set_attr "type" "spadd")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (minus:DF (match_operand:DF 1 "register_operand" "r,x") (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fsub.dds %0,%1,%2" [(set_attr "type" "dpadd")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (minus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) (match_operand:DF 2 "register_operand" "r,x")))] "" "fsub.dsd %0,%1,%2" [(set_attr "type" "dpadd")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (minus:DF (match_operand:DF 1 "register_operand" "r,x") (match_operand:DF 2 "register_operand" "r,x")))] "" "fsub.ddd %0,%1,%2" [(set_attr "type" "dpadd")]) (define_insn "subsf3" [(set (match_operand:SF 0 "register_operand" "=r,x") (minus:SF (match_operand:SF 1 "register_operand" "r,x") (match_operand:SF 2 "register_operand" "r,x")))] "" "fsub.sss %0,%1,%2" [(set_attr "type" "spadd")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (minus:DI (match_operand:DI 1 "register_operand" "r") (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))) (clobber (reg:CC 0))] "" "subu.co %d0,%d1,%2\;subu.ci %0,%1,%#r0" [(set_attr "type" "marith")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (minus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (match_operand:DI 2 "register_operand" "r"))) (clobber (reg:CC 0))] "" "subu.co %d0,%1,%d2\;subu.ci %0,%#r0,%2" [(set_attr "type" "marith")]) (define_insn "subdi3" [(set (match_operand:DI 0 "register_operand" "=r") (minus:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "register_operand" "r"))) (clobber (reg:CC 0))] "" "subu.co %d0,%d1,%d2\;subu.ci %0,%1,%2" [(set_attr "type" "marith")]) ;; Subtract with carry insns. (define_insn "" [(parallel [(set (match_operand:SI 0 "reg_or_0_operand" "=r") (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO") (match_operand:SI 2 "reg_or_0_operand" "rO"))) (set (reg:CC 0) (unspec:CC [(match_dup 1) (match_dup 2)] 1))])] "" "subu.co %r0,%r1,%r2") (define_insn "" [(set (reg:CC 0) (unspec:CC [(match_operand:SI 0 "reg_or_0_operand" "rO") (match_operand:SI 1 "reg_or_0_operand" "rO")] 1))] "" "subu.co %#r0,%r0,%r1") (define_insn "" [(set (match_operand:SI 0 "reg_or_0_operand" "=r") (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO") (unspec:SI [(match_operand:SI 2 "reg_or_0_operand" "rO") (reg:CC 0)] 1)))] "" "subu.ci %r0,%r1,%r2") ;;- multiply instructions ;; ;; There is an unfounded silicon eratta for E.1 requiring that an ;; immediate constant value in div/divu/mul instructions be less than ;; 0x800. This is no longer provided for. (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_operand:SI 1 "arith32_operand" "%r") (match_operand:SI 2 "arith32_operand" "rI")))] "" "mul %0,%1,%2" [(set_attr "type" "imul")]) (define_insn "umulsidi3" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r")) (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))] "TARGET_88110" "mulu.d %0,%1,%2" [(set_attr "type" "imul")]) ;; patterns for mixed mode floating point ;; Do not define patterns that utilize mixed mode arithmetic that result ;; in narrowing the precision, because it loses accuracy, since the standard ;; requires double rounding, whereas the 88000 instruction only rounds once. (define_expand "muldf3" [(set (match_operand:DF 0 "register_operand" "=r,x") (mult:DF (match_operand:DF 1 "general_operand" "%r,x") (match_operand:DF 2 "general_operand" "r,x")))] "" " { operands[1] = legitimize_operand (operands[1], DFmode); operands[2] = legitimize_operand (operands[2], DFmode); }") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fmul.dss %0,%1,%2" [(set_attr "type" "spmul")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (mult:DF (match_operand:DF 1 "register_operand" "r,x") (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fmul.dds %0,%1,%2" [(set_attr "type" "spmul")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) (match_operand:DF 2 "register_operand" "r,x")))] "" "fmul.dsd %0,%1,%2" [(set_attr "type" "spmul")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (mult:DF (match_operand:DF 1 "register_operand" "%r,x") (match_operand:DF 2 "register_operand" "r,x")))] "" "fmul.ddd %0,%1,%2" [(set_attr "type" "dpmul")]) (define_insn "mulsf3" [(set (match_operand:SF 0 "register_operand" "=r,x") (mult:SF (match_operand:SF 1 "register_operand" "%r,x") (match_operand:SF 2 "register_operand" "r,x")))] "" "fmul.sss %0,%1,%2" [(set_attr "type" "spmul")]) ;;- divide instructions ;; ;; The 88k div and divu instructions don't reliably trap on ;; divide-by-zero. A trap to vector 503 asserts divide-by-zero. The ;; general scheme for doing divide is to do a 4-way split based on the ;; sign of the two operand and do the appropriate negates. ;; ;; The conditional trap instruction is not used as this serializes the ;; processor. Instead a conditional branch and an unconditional trap ;; are used, but after the divu. Since the divu takes up to 38 cycles, ;; the conditional branch is essentially free. ;; ;; Two target options control how divide is done. One options selects ;; whether to do the branch and negate scheme instead of using the div ;; instruction; the other option selects whether to explicitly check ;; for divide-by-zero or take your chances. If the div instruction is ;; used, the O/S must complete the operation if the operands are ;; negative. The O/S will signal an overflow condition if the most ;; negative number (-214783648) is divided by negative 1. ;; ;; There is an unfounded silicon eratta for E.1 requiring that an ;; immediate constant value in div/divu/mul instructions be less than ;; 0x800. This is no longer provided for. ;; Division by 0 trap (define_insn "trap_divide_by_zero" [(trap_if (const_int 1) 503)] "" "tb0 0,%#r0,503" [(set_attr "type" "weird")]) ;; Conditional division by 0 trap. (define_expand "tcnd_divide_by_zero" [(set (pc) (if_then_else (eq (match_operand:SI 0 "register_operand" "") (const_int 0)) (pc) (match_operand 1 "" ""))) (trap_if (const_int 1) 503)] "" " { emit_insn (gen_cmpsi (operands[0], const0_rtx)); emit_jump_insn (gen_bne (operands[1])); emit_insn (gen_trap_divide_by_zero ()); DONE; }") (define_expand "divsi3" [(set (match_operand:SI 0 "register_operand" "") (div:SI (match_operand:SI 1 "arith32_operand" "") (match_operand:SI 2 "arith32_operand" "")))] "" " { rtx op0 = operands[0]; rtx op1 = operands[1]; rtx op2 = operands[2]; rtx join_label; /* @@ This needs to be reworked. Torbjorn Granlund has suggested making it a runtime (perhaps quite special). */ if (GET_CODE (op1) == CONST_INT) op1 = force_reg (SImode, op1); else if (GET_CODE (op2) == CONST_INT && ! SMALL_INT (operands[2])) op2 = force_reg (SImode, op2); if (op2 == const0_rtx) { emit_insn (gen_trap_divide_by_zero ()); emit_insn (gen_dummy (op0)); DONE; } if (TARGET_USE_DIV) { emit_move_insn (op0, gen_rtx (DIV, SImode, op1, op2)); if (TARGET_CHECK_ZERO_DIV && GET_CODE (op2) != CONST_INT) { rtx label = gen_label_rtx (); emit_insn (gen_tcnd_divide_by_zero (op2, label)); emit_label (label); emit_insn (gen_dummy (op0)); } DONE; } join_label = gen_label_rtx (); if (GET_CODE (op1) == CONST_INT) { int neg = FALSE; rtx neg_op2 = gen_reg_rtx (SImode); rtx label1 = gen_label_rtx (); if (INTVAL (op1) < 0) { neg = TRUE; op1 = gen_rtx (CONST_INT, VOIDmode, -INTVAL (op1)); } op1 = force_reg (SImode, op1); emit_insn (gen_negsi2 (neg_op2, op2)); emit_insn (gen_cmpsi (op2, const0_rtx)); emit_jump_insn (gen_bgt (label1)); /* constant / 0-or-negative */ emit_move_insn (op0, gen_rtx (UDIV, SImode, op1, neg_op2)); if (!neg) emit_insn (gen_negsi2 (op0, op0)); if (TARGET_CHECK_ZERO_DIV) emit_insn (gen_tcnd_divide_by_zero (op2, join_label)); emit_jump_insn (gen_jump (join_label)); emit_barrier (); emit_label (label1); /* constant / positive */ emit_move_insn (op0, gen_rtx (UDIV, SImode, op1, op2)); if (neg) emit_insn (gen_negsi2 (op0, op0)); } else if (GET_CODE (op2) == CONST_INT) { int neg = FALSE; rtx neg_op1 = gen_reg_rtx (SImode); rtx label1 = gen_label_rtx (); if (INTVAL (op2) < 0) { neg = TRUE; op2 = gen_rtx (CONST_INT, VOIDmode, -INTVAL (op2)); } else if (! SMALL_INT (operands[2])) op2 = force_reg (SImode, op2); emit_insn (gen_negsi2 (neg_op1, op1)); emit_insn (gen_cmpsi (op1, const0_rtx)); emit_jump_insn (gen_bge (label1)); /* 0-or-negative / constant */ emit_move_insn (op0, gen_rtx (UDIV, SImode, neg_op1, op2)); if (!neg) emit_insn (gen_negsi2 (op0, op0)); emit_jump_insn (gen_jump (join_label)); emit_barrier (); emit_label (label1); /* positive / constant */ emit_move_insn (op0, gen_rtx (UDIV, SImode, op1, op2)); if (neg) emit_insn (gen_negsi2 (op0, op0)); } else { rtx neg_op1 = gen_reg_rtx (SImode); rtx neg_op2 = gen_reg_rtx (SImode); rtx label1 = gen_label_rtx (); rtx label2 = gen_label_rtx (); rtx label3 = gen_label_rtx (); rtx label4; emit_insn (gen_negsi2 (neg_op2, op2)); emit_insn (gen_cmpsi (op2, const0_rtx)); emit_jump_insn (gen_bgt (label1)); emit_insn (gen_negsi2 (neg_op1, op1)); emit_insn (gen_cmpsi (op1, const0_rtx)); emit_jump_insn (gen_bge (label2)); /* negative / negative-or-0 */ emit_move_insn (op0, gen_rtx (UDIV, SImode, neg_op1, neg_op2)); if (TARGET_CHECK_ZERO_DIV) { label4 = gen_label_rtx (); emit_insn (gen_cmpsi (op2, const0_rtx)); emit_jump_insn (gen_bne (join_label)); emit_label (label4); emit_insn (gen_trap_divide_by_zero ()); } emit_jump_insn (gen_jump (join_label)); emit_barrier (); emit_label (label2); /* pos.-or-0 / neg.-or-0 */ emit_move_insn (op0, gen_rtx (UDIV, SImode, op1, neg_op2)); if (TARGET_CHECK_ZERO_DIV) { emit_insn (gen_cmpsi (op2, const0_rtx)); emit_jump_insn (gen_beq (label4)); } emit_insn (gen_negsi2 (op0, op0)); emit_jump_insn (gen_jump (join_label)); emit_barrier (); emit_label (label1); emit_insn (gen_negsi2 (neg_op1, op1)); emit_insn (gen_cmpsi (op1, const0_rtx)); emit_jump_insn (gen_bge (label3)); /* negative / positive */ emit_move_insn (op0, gen_rtx (UDIV, SImode, neg_op1, op2)); emit_insn (gen_negsi2 (op0, op0)); emit_jump_insn (gen_jump (join_label)); emit_barrier (); emit_label (label3); /* positive-or-0 / positive */ emit_move_insn (op0, gen_rtx (UDIV, SImode, op1, op2)); } emit_label (join_label); emit_insn (gen_dummy (op0)); DONE; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (div:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "" "div %0,%1,%2" [(set_attr "type" "idiv")]) (define_expand "udivsi3" [(set (match_operand:SI 0 "register_operand" "") (udiv:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "arith32_operand" "")))] "" " { rtx op2 = operands[2]; if (op2 == const0_rtx) { emit_insn (gen_trap_divide_by_zero ()); emit_insn (gen_dummy (operands[0])); DONE; } else if (GET_CODE (op2) != CONST_INT && TARGET_CHECK_ZERO_DIV) { rtx label = gen_label_rtx (); emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (UDIV, SImode, operands[1], op2))); emit_insn (gen_tcnd_divide_by_zero (op2, label)); emit_label (label); emit_insn (gen_dummy (operands[0])); DONE; } }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (udiv:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith32_operand" "rI")))] "operands[2] != const0_rtx" "divu %0,%1,%2" [(set_attr "type" "idiv")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (udiv:SI (match_operand:SI 1 "register_operand" "r") (const_int 0)))] "" "tb0 0,%#r0,503" [(set_attr "type" "weird")]) ;; patterns for mixed mode floating point. ;; Do not define patterns that utilize mixed mode arithmetic that result ;; in narrowing the precision, because it loses accuracy, since the standard ;; requires double rounding, whereas the 88000 instruction only rounds once. (define_expand "divdf3" [(set (match_operand:DF 0 "register_operand" "=r,x") (div:DF (match_operand:DF 1 "general_operand" "r,x") (match_operand:DF 2 "general_operand" "r,x")))] "" " { operands[1] = legitimize_operand (operands[1], DFmode); if (real_power_of_2_operand (operands[2])) { union real_extract u; bcopy (&CONST_DOUBLE_LOW (operands[2]), &u, sizeof u); emit_insn (gen_muldf3 (operands[0], operands[1], CONST_DOUBLE_FROM_REAL_VALUE (1.0/u.d, DFmode))); DONE; } else if (! register_operand (operands[2], DFmode)) operands[2] = force_reg (DFmode, operands[2]); }") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (div:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fdiv.dss %0,%1,%2" [(set_attr "type" "dpdiv")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (div:DF (match_operand:DF 1 "register_operand" "r,x") (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))] "" "fdiv.dds %0,%1,%2" [(set_attr "type" "dpdiv")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (div:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")) (match_operand:DF 2 "register_operand" "r,x")))] "" "fdiv.dsd %0,%1,%2" [(set_attr "type" "dpdiv")]) (define_insn "divsf3" [(set (match_operand:SF 0 "register_operand" "=r,x") (div:SF (match_operand:SF 1 "register_operand" "r,x") (match_operand:SF 2 "register_operand" "r,x")))] "" "fdiv.sss %0,%1,%2" [(set_attr "type" "spdiv")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=r,x") (div:DF (match_operand:DF 1 "register_operand" "r,x") (match_operand:DF 2 "register_operand" "r,x")))] "" "fdiv.ddd %0,%1,%2" [(set_attr "type" "dpdiv")]) ;; - remainder instructions, don't define, since the hardware doesn't have any ;; direct support, and GNU can synthesis them out of div/mul just fine. ;;- load effective address, must come after add, so that we favor using ;; addu reg,reg,reg instead of: lda reg,reg,reg (addu doesn't require ;; the data unit), and also future 88k chips might not support unscaled ;; lda instructions. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "address_operand" "p"))] "m88k_gp_threshold > 0 && symbolic_address_p (operands[1])" "addu %0,%a1") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:HI 1 "address_operand" "p"))] "" "lda.h %0,%a1" [(set_attr "type" "loada")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "address_operand" "p"))] "" "lda %0,%a1" [(set_attr "type" "loada")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:DI 1 "address_operand" "p"))] "" "lda.d %0,%a1" [(set_attr "type" "loada")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SF 1 "address_operand" "p"))] "" "lda %0,%a1" [(set_attr "type" "loada")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:DF 1 "address_operand" "p"))] "" "lda.d %0,%a1" [(set_attr "type" "loada")]) ;;- and instructions (with complement also) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (not:SI (match_operand:SI 1 "register_operand" "r")) (match_operand:SI 2 "register_operand" "r")))] "" "and.c %0,%2,%1") ;; If the operation is being performed on a 32-bit constant such that ;; it cannot be done in one insn, do it in two. We may lose a bit on ;; CSE in pathological cases, but it seems better doing it this way. (define_expand "andsi3" [(set (match_operand:SI 0 "register_operand" "") (and:SI (match_operand:SI 1 "arith32_operand" "") (match_operand:SI 2 "arith32_operand" "")))] "" " { if (GET_CODE (operands[2]) == CONST_INT) { int value = INTVAL (operands[2]); if (! (SMALL_INTVAL (value) || (value & 0xffff0000) == 0xffff0000 || (value & 0xffff) == 0xffff || (value & 0xffff) == 0 || integer_ok_for_set (~value))) { emit_insn (gen_andsi3 (operands[0], operands[1], gen_rtx (CONST_INT, VOIDmode, value | 0xffff))); operands[1] = operands[0]; operands[2] = gen_rtx (CONST_INT, VOIDmode, value | 0xffff0000); } } }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r") (and:SI (match_operand:SI 1 "arith32_operand" "%r,r") (match_operand:SI 2 "arith32_operand" "rIJL,rn")))] "" "* return output_and (operands);" [(set_attr "type" "arith,marith")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (and:DI (not:DI (match_operand:DI 1 "register_operand" "r")) (match_operand:DI 2 "register_operand" "r")))] "" "and.c %d0,%d2,%d1\;and.c %0,%2,%1" [(set_attr "type" "marith")]) (define_insn "anddi3" [(set (match_operand:DI 0 "register_operand" "=r") (and:DI (match_operand:DI 1 "arith64_operand" "%r") (match_operand:DI 2 "arith64_operand" "rn")))] "" "* { rtx xoperands[10]; xoperands[0] = operand_subword (operands[0], 1, 0, DImode); xoperands[1] = operand_subword (operands[1], 1, 0, DImode); xoperands[2] = operand_subword (operands[2], 1, 0, DImode); output_asm_insn (output_and (xoperands), xoperands); operands[0] = operand_subword (operands[0], 0, 0, DImode); operands[1] = operand_subword (operands[1], 0, 0, DImode); operands[2] = operand_subword (operands[2], 0, 0, DImode); return output_and (operands); }" [(set_attr "type" "marith") (set_attr "length" "4")]) ; length is 2, 3, or 4. ;;- Bit set (inclusive or) instructions (with complement also) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (not:SI (match_operand:SI 1 "register_operand" "r")) (match_operand:SI 2 "register_operand" "r")))] "" "or.c %0,%2,%1") (define_expand "iorsi3" [(set (match_operand:SI 0 "register_operand" "") (ior:SI (match_operand:SI 1 "arith32_operand" "") (match_operand:SI 2 "arith32_operand" "")))] "" " { if (GET_CODE (operands[2]) == CONST_INT) { int value = INTVAL (operands[2]); if (! (SMALL_INTVAL (value) || (value & 0xffff) == 0 || integer_ok_for_set (value))) { emit_insn (gen_iorsi3 (operands[0], operands[1], gen_rtx (CONST_INT, VOIDmode, value & 0xffff0000))); operands[1] = operands[0]; operands[2] = gen_rtx (CONST_INT, VOIDmode, value & 0xffff); } } }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (ior:SI (match_operand:SI 1 "arith32_operand" "%r,r,r,r") (match_operand:SI 2 "arith32_operand" "rI,L,M,n")))] "" "@ or %0,%1,%2 or.u %0,%1,%X2 set %0,%1,%s2 or.u %0,%1,%X2\;or %0,%0,%x2" [(set_attr "type" "arith,arith,bit,marith")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ior:DI (not:DI (match_operand:DI 1 "register_operand" "r")) (match_operand:DI 2 "register_operand" "r")))] "" "or.c %d0,%d2,%d1\;or.c %0,%2,%1" [(set_attr "type" "marith")]) (define_insn "iordi3" [(set (match_operand:DI 0 "register_operand" "=r") (ior:DI (match_operand:DI 1 "arith64_operand" "%r") (match_operand:DI 2 "arith64_operand" "rn")))] "" "* { rtx xoperands[10]; xoperands[0] = operand_subword (operands[0], 1, 0, DImode); xoperands[1] = operand_subword (operands[1], 1, 0, DImode); xoperands[2] = operand_subword (operands[2], 1, 0, DImode); output_asm_insn (output_ior (xoperands), xoperands); operands[0] = operand_subword (operands[0], 0, 0, DImode); operands[1] = operand_subword (operands[1], 0, 0, DImode); operands[2] = operand_subword (operands[2], 0, 0, DImode); return output_ior (operands); }" [(set_attr "type" "marith") (set_attr "length" "4")]) ; length is 2, 3, or 4. ;;- xor instructions (with complement also) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (not:SI (xor:SI (match_operand:SI 1 "register_operand" "%r") (match_operand:SI 2 "register_operand" "r"))))] "" "xor.c %0,%1,%2") (define_expand "xorsi3" [(set (match_operand:SI 0 "register_operand" "") (xor:SI (match_operand:SI 1 "arith32_operand" "") (match_operand:SI 2 "arith32_operand" "")))] "" " { if (GET_CODE (operands[2]) == CONST_INT) { int value = INTVAL (operands[2]); if (! (SMALL_INTVAL (value) || (value & 0xffff) == 0)) { emit_insn (gen_xorsi3 (operands[0], operands[1], gen_rtx (CONST_INT, VOIDmode, value & 0xffff0000))); operands[1] = operands[0]; operands[2] = gen_rtx (CONST_INT, VOIDmode, value & 0xffff); } } }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (xor:SI (match_operand:SI 1 "arith32_operand" "%r,r,r") (match_operand:SI 2 "arith32_operand" "rI,L,n")))] "" "@ xor %0,%1,%2 xor.u %0,%1,%X2 xor.u %0,%1,%X2\;xor %0,%0,%x2" [(set_attr "type" "arith,arith,marith")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (not:DI (xor:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "register_operand" "r"))))] "" "xor.c %d0,%d1,%d2\;xor.c %0,%1,%2" [(set_attr "type" "marith")]) (define_insn "xordi3" [(set (match_operand:DI 0 "register_operand" "=r") (xor:DI (match_operand:DI 1 "arith64_operand" "%r") (match_operand:DI 2 "arith64_operand" "rn")))] "" "* { rtx xoperands[10]; xoperands[0] = operand_subword (operands[0], 1, 0, DImode); xoperands[1] = operand_subword (operands[1], 1, 0, DImode); xoperands[2] = operand_subword (operands[2], 1, 0, DImode); output_asm_insn (output_xor (xoperands), xoperands); operands[0] = operand_subword (operands[0], 0, 0, DImode); operands[1] = operand_subword (operands[1], 0, 0, DImode); operands[2] = operand_subword (operands[2], 0, 0, DImode); return output_xor (operands); }" [(set_attr "type" "marith") (set_attr "length" "4")]) ; length is 2, 3, or 4. ;;- ones complement instructions (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "=r") (not:SI (match_operand:SI 1 "register_operand" "r")))] "" "xor.c %0,%1,%#r0") (define_insn "one_cmpldi2" [(set (match_operand:DI 0 "register_operand" "=r") (not:DI (match_operand:DI 1 "register_operand" "r")))] "" "xor.c %d0,%d1,%#r0\;xor.c %0,%1,%#r0" [(set_attr "type" "marith")]) ;; Optimized special cases of shifting. ;; Must precede the general case. ;; @@ What about HImode shifted by 8? (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m") (const_int 24)))] "! SCALED_ADDRESS_P (XEXP (operands[1], 0))" "%V1ld.b\\t %0,%1" [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") (const_int 24)))] "! SCALED_ADDRESS_P (XEXP (operands[1], 0))" "%V1ld.bu\\t %0,%1" [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m") (const_int 16)))] "! SCALED_ADDRESS_P (XEXP (operands[1], 0))" "%V1ld.h\\t %0,%1" [(set_attr "type" "load")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") (const_int 16)))] "! SCALED_ADDRESS_P (XEXP (operands[1], 0))" "%V1ld.hu\\t %0,%1" [(set_attr "type" "load")]) ;;- arithmetic shift instructions. ;; @@ Do the optimized patterns with -1 get used? Perhaps operand 1 should ;; be arith32_operand? ;; Use tbnd to support TARGET_TRAP_LARGE_SHIFT. (define_insn "tbnd" [(trap_if (gtu (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "arith_operand" "rI")) 7)] "" "tbnd %r0,%1" [(set_attr "type" "weird")]) ;; Just in case the optimizer decides to fold away the test. (define_insn "" [(trap_if (const_int 1) 7)] "" "tbnd %#r31,0" [(set_attr "type" "weird")]) (define_expand "ashlsi3" [(set (match_operand:SI 0 "register_operand" "") (ashift:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "arith32_operand" "")))] "" " { if (GET_CODE (operands[2]) == CONST_INT) { if ((unsigned) INTVAL (operands[2]) > 31) { if (TARGET_TRAP_LARGE_SHIFT) emit_insn (gen_tbnd (force_reg (SImode, operands[2]), gen_rtx (CONST_INT, VOIDmode, 31))); else emit_move_insn (operands[0], const0_rtx); DONE; } } else if (TARGET_TRAP_LARGE_SHIFT) emit_insn (gen_tbnd (operands[2], gen_rtx (CONST_INT, VOIDmode, 31))); else if (TARGET_HANDLE_LARGE_SHIFT) { rtx reg = gen_reg_rtx (SImode); emit_insn (gen_cmpsi (operands[2], gen_rtx (CONST_INT, VOIDmode, 31))); emit_insn (gen_sleu (reg)); emit_insn (gen_andsi3 (reg, operands[1], reg)); operands[1] = reg; } }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r") (ashift:SI (match_operand:SI 1 "register_operand" "r,r") (match_operand:SI 2 "arith5_operand" "r,K")))] "" "@ mak %0,%1,%2 mak %0,%1,0<%2>" [(set_attr "type" "bit")]) (define_expand "ashrsi3" [(set (match_operand:SI 0 "register_operand" "") (ashiftrt:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "arith32_operand" "")))] "" " { if (GET_CODE (operands[2]) == CONST_INT) { if ((unsigned) INTVAL (operands[2]) > 31) { if (TARGET_TRAP_LARGE_SHIFT) { emit_insn (gen_tbnd (force_reg (SImode, operands[2]), gen_rtx (CONST_INT, VOIDmode, 31))); DONE; } else operands[2] = gen_rtx (CONST_INT, VOIDmode, 31); } } else if (TARGET_TRAP_LARGE_SHIFT) emit_insn (gen_tbnd (operands[2], gen_rtx (CONST_INT, VOIDmode, 31))); else if (TARGET_HANDLE_LARGE_SHIFT) { rtx reg = gen_reg_rtx (SImode); emit_insn (gen_cmpsi (operands[2], gen_rtx (CONST_INT, VOIDmode, 31))); emit_insn (gen_sgtu (reg)); emit_insn (gen_iorsi3 (reg, operands[2], reg)); operands[2] = reg; } }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r") (ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r") (match_operand:SI 2 "arith5_operand" "r,K")))] "" "@ ext %0,%1,%2 ext %0,%1,0<%2>" [(set_attr "type" "bit")]) ;;- logical shift instructions. Logical shift left becomes arithmetic ;; shift left. LSHIFT is not normally produced, but is supported. (define_expand "lshlsi3" [(set (match_operand:SI 0 "register_operand" "") (lshift:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "arith32_operand" "")))] "" " { emit_insn (gen_ashlsi3 (operands[0], operands[1], operands[2])); DONE; }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r") (lshift:SI (match_operand:SI 1 "register_operand" "r,r") (match_operand:SI 2 "arith5_operand" "r,K")))] "" "@ mak %0,%1,%2 mak %0,%1,0<%2>" [(set_attr "type" "bit")]) (define_expand "lshrsi3" [(set (match_operand:SI 0 "register_operand" "") (lshiftrt:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "arith32_operand" "")))] "" " { if (GET_CODE (operands[2]) == CONST_INT) { if ((unsigned) INTVAL (operands[2]) > 31) { if (TARGET_TRAP_LARGE_SHIFT) emit_insn (gen_tbnd (force_reg (SImode, operands[2]), gen_rtx (CONST_INT, VOIDmode, 31))); else emit_move_insn (operands[0], const0_rtx); DONE; } } else if (TARGET_TRAP_LARGE_SHIFT) emit_insn (gen_tbnd (operands[2], gen_rtx (CONST_INT, VOIDmode, 31))); else if (TARGET_HANDLE_LARGE_SHIFT) { rtx reg = gen_reg_rtx (SImode); emit_insn (gen_cmpsi (operands[2], gen_rtx (CONST_INT, VOIDmode, 31))); emit_insn (gen_sleu (reg)); emit_insn (gen_andsi3 (reg, operands[1], reg)); operands[1] = reg; } }") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r") (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r") (match_operand:SI 2 "arith5_operand" "r,K")))] "" "@ extu %0,%1,%2 extu %0,%1,0<%2>" [(set_attr "type" "bit")]) ;;- rotate instructions (define_expand "rotlsi3" [(set (match_operand:SI 0 "register_operand" "") (rotatert:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "arith32_operand" "")))] "" " { if (GET_CODE (operands[2]) == CONST_INT && (unsigned) INTVAL (operands[2]) >= 32) operands[2] = gen_rtx (CONST_INT, VOIDmode, (32 - INTVAL (operands[2])) % 32); else { rtx op = gen_reg_rtx (SImode); emit_insn (gen_negsi2 (op, operands[2])); operands[2] = op; } }") (define_insn "rotrsi3" [(set (match_operand:SI 0 "register_operand" "=r") (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "" "rot %0,%1,%2" [(set_attr "type" "bit")]) ;; find first set. ;; The ff1 instruction searches from the most significant bit while ffs ;; searches from the least significant bit. The bit index and treatment of ;; zero also differ. This amazing sequence was discovered using the GNU ;; Superoptimizer. (define_insn "ffssi2" [(set (match_operand:SI 0 "register_operand" "=r,&r") (ffs:SI (match_operand:SI 1 "register_operand" "0,r"))) (clobber (reg:CC 0)) (clobber (match_scratch:SI 2 "=r,X"))] "" "@ subu.co %2,%#r0,%1\;and %2,%2,%1\;addu.ci %2,%2,%2\;ff1 %0,%2 subu.co %0,%#r0,%1\;and %0,%0,%1\;addu.ci %0,%0,%0\;ff1 %0,%0" [(set_attr "type" "marith") (set_attr "length" "4")]) ;; Bit field instructions. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (sign_extract:SI (match_operand:SI 1 "register_operand" "r") (const_int 32) (const_int 0)))] "" "or %0,%#r0,%1") (define_insn "extv" [(set (match_operand:SI 0 "register_operand" "=r") (sign_extract:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "int5_operand" "") (match_operand:SI 3 "int5_operand" "")))] "" "* { operands[4] = gen_rtx (CONST_INT, SImode, (32 - INTVAL (operands[2])) - INTVAL (operands[3])); return \"ext %0,%1,%2<%4>\"; /* <(32-%2-%3)> */ }" [(set_attr "type" "bit")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extract:SI (match_operand:SI 1 "register_operand" "r") (const_int 32) (const_int 0)))] "" "or %0,%#r0,%1") (define_insn "extzv" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extract:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "int5_operand" "") (match_operand:SI 3 "int5_operand" "")))] "" "* { operands[4] = gen_rtx (CONST_INT, SImode, (32 - INTVAL (operands[2])) - INTVAL (operands[3])); return \"extu %0,%1,%2<%4>\"; /* <(32-%2-%3)> */ }" [(set_attr "type" "bit")]) (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") (match_operand:SI 1 "int5_operand" "") (match_operand:SI 2 "int5_operand" "")) (const_int 0))] "" "* { operands[3] = gen_rtx (CONST_INT, SImode, (32 - INTVAL (operands[1])) - INTVAL (operands[2])); return \"clr %0,%0,%1<%3>\"; /* <(32-%1-%2)> */ }" [(set_attr "type" "bit")]) (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") (match_operand:SI 1 "int5_operand" "") (match_operand:SI 2 "int5_operand" "")) (const_int -1))] "" "* { operands[3] = gen_rtx (CONST_INT, SImode, (32 - INTVAL (operands[1])) - INTVAL (operands[2])); return \"set %0,%0,%1<%3>\"; /* <(32-%1-%2)> */ }" [(set_attr "type" "bit")]) (define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") (match_operand:SI 1 "int5_operand" "") (match_operand:SI 2 "int5_operand" "")) (match_operand:SI 3 "int32_operand" "n"))] "" "* { int value = INTVAL (operands[3]); if (INTVAL (operands[1]) < 32) value &= (1 << INTVAL (operands[1])) - 1; operands[2] = gen_rtx (CONST_INT, VOIDmode, 32 - (INTVAL(operands[1]) + INTVAL(operands[2]))); value <<= INTVAL (operands[2]); operands[3] = gen_rtx (CONST_INT, VOIDmode, value); if (SMALL_INTVAL (value)) return \"clr %0,%0,%1<%2>\;or %0,%0,%3\"; else if ((value & 0x0000ffff) == 0) return \"clr %0,%0,%1<%2>\;or.u %0,%0,%X3\"; else return \"clr %0,%0,%1<%2>\;or.u %0,%0,%X3\;or %0,%0,%x3\"; }" [(set_attr "type" "marith") (set_attr "length" "3")]) ; may be 2 or 3. ;; negate insns (define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operand:SI 1 "arith_operand" "rI")))] "" "subu %0,%#r0,%1") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=r,x") (float_truncate:SF (neg:DF (match_operand:DF 1 "register_operand" "r,x"))))] "" "@ fsub.ssd %0,%#r0,%1 fsub.ssd %0,%#x0,%1" [(set_attr "type" "dpadd")]) (define_insn "negdf2" [(set (match_operand:DF 0 "register_operand" "=&r,r") (neg:DF (match_operand:DF 1 "register_operand" "r,0")))] "" "@ xor.u %0,%1,0x8000\;or %d0,%#r0,%d1 xor.u %0,%0,0x8000" [(set_attr "type" "marith,arith")]) (define_insn "negsf2" [(set (match_operand:SF 0 "register_operand" "=r") (neg:SF (match_operand:SF 1 "register_operand" "r")))] "" "xor.u %0,%1,0x8000") ;; absolute value insns for floating-point (integer abs can be done using the ;; machine-independent sequence). (define_insn "absdf2" [(set (match_operand:DF 0 "register_operand" "=&r,r") (abs:DF (match_operand:DF 1 "register_operand" "r,0")))] "" "@ and.u %0,%1,0x7fff\;or %d0,%#r0,%d1 and.u %0,%0,0x7fff" [(set_attr "type" "marith,arith")]) (define_insn "abssf2" [(set (match_operand:SF 0 "register_operand" "=r") (abs:SF (match_operand:SF 1 "register_operand" "r")))] "" "and.u %0,%1,0x7fff") ;; Subroutines of "casesi". ;; Operand 0 is index ;; operand 1 is the minimum bound ;; operand 2 is the maximum bound - minimum bound + 1 ;; operand 3 is CODE_LABEL for the table; ;; operand 4 is the CODE_LABEL to go to if index out of range. (define_expand "casesi" ;; We don't use these for generating the RTL, but we must describe ;; the operands here. [(match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "immediate_operand" "") (match_operand:SI 2 "immediate_operand" "") (match_operand 3 "" "") (match_operand 4 "" "")] "" " { register rtx index_diff = gen_reg_rtx (SImode); register rtx low = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[1])); register rtx label = gen_rtx (LABEL_REF, VOIDmode, operands[3]); register rtx base; if (! CASE_VECTOR_INSNS) /* These instructions are likely to be scheduled and made loop invariant. This decreases the cost of the dispatch at the expense of the default case. */ base = force_reg (SImode, memory_address_noforce (SImode, label)); /* Compute the index difference and handle the default case. */ emit_insn (gen_addsi3 (index_diff, force_reg (SImode, operands[0]), ADD_INT (low) ? low : force_reg (SImode, low))); emit_insn (gen_cmpsi (index_diff, operands[2])); /* It's possible to replace this branch with sgtu/iorsi3 and adding a -1 entry to the table. However, that doesn't seem to win on the m88110. */ emit_jump_insn (gen_bgtu (operands[4])); if (CASE_VECTOR_INSNS) /* Call the jump that will branch to the appropriate case. */ emit_jump_insn (gen_casesi_enter (label, index_diff, operands[3])); else /* Load the table entry and jump to it. */ emit_jump_insn (gen_casesi_jump (gen_reg_rtx (SImode), base, index_diff)); /* Claim that flow drops into the table so it will be adjacent by not emitting a barrier. */ DONE; }") (define_expand "casesi_jump" [(set (match_operand:SI 0 "" "") (mem:SI (plus:SI (match_operand:SI 1 "" "") (mult:SI (match_operand:SI 2 "" "") (const_int 4))))) (set (pc) (match_dup 0))] "" "") ;; The bsr.n instruction is directed to the END of the table. See ;; ASM_OUTPUT_CASE_END. (define_insn "casesi_enter" [(set (pc) (match_operand 0 "" "")) (use (match_operand:SI 1 "register_operand" "r")) ;; The USE here is so that at least one jump-insn will refer to the label, ;; to keep it alive in jump_optimize. (use (label_ref (match_operand 2 "" ""))) (clobber (reg:SI 1))] "" "* { if (flag_delayed_branch) return \"bsr.n %0e\;lda %#r1,%#r1[%1]\"; m88k_case_index = REGNO (operands[1]); return \"bsr %0e\"; }" [(set_attr "type" "weird") (set_attr "length" "3")]) ; Including the "jmp r1". ;;- jump to subroutine (define_expand "call" [(parallel [(call (match_operand:SI 0 "" "") (match_operand 1 "" "")) (clobber (reg:SI 1))])] "" " { if (GET_CODE (operands[0]) == MEM && ! call_address_operand (XEXP (operands[0], 0), SImode)) operands[0] = gen_rtx (MEM, GET_MODE (operands[0]), force_reg (Pmode, XEXP (operands[0], 0))); }") (define_insn "" [(parallel [(call (mem:SI (match_operand:SI 0 "call_address_operand" "rQ")) (match_operand 1 "" "")) (clobber (reg:SI 1))])] "" "* return output_call (operands, operands[0]);" [(set_attr "type" "call")]) (define_expand "call_value" [(parallel [(set (match_operand 0 "register_operand" "") (call (match_operand:SI 1 "" "") (match_operand 2 "" ""))) (clobber (reg:SI 1))])] "" " { if (GET_CODE (operands[1]) == MEM && ! call_address_operand (XEXP (operands[1], 0), SImode)) operands[1] = gen_rtx (MEM, GET_MODE (operands[1]), force_reg (Pmode, XEXP (operands[1], 0))); }") (define_insn "" [(parallel [(set (match_operand 0 "register_operand" "=r") (call (mem:SI (match_operand:SI 1 "call_address_operand" "rQ")) (match_operand 2 "" ""))) (clobber (reg:SI 1))])] "" "* return output_call (operands, operands[1]);" [(set_attr "type" "call")]) ;; Nop instruction and others (define_insn "nop" [(const_int 0)] "" "ff0 %#r0,%#r0" [(set_attr "type" "bit")]) (define_insn "return" [(return)] "reload_completed" "jmp%. %#r1" [(set_attr "type" "jump")]) (define_expand "prologue" [(const_int 0)] "" "m88k_expand_prologue (); DONE;") (define_expand "epilogue" [(return)] "! null_prologue ()" "m88k_expand_epilogue ();") (define_insn "blockage" [(unspec_volatile [(const_int 0)] 0)] "" "" [(set_attr "length" "0")]) (define_insn "indirect_jump" [(set (pc) (match_operand:SI 0 "register_operand" "r"))] "" "jmp%. %0" [(set_attr "type" "jump")]) (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "br%. %l0" [(set_attr "type" "jump")]) ;; This insn is used for some loop tests, typically loops reversed when ;; strength reduction is used. It is actually created when the instruction ;; combination phase combines the special loop test. Since this insn ;; is both a jump insn and has an output, it must deal with it's own ;; reloads, hence the `m' constraints. The `!' constraints direct reload ;; to not choose the register alternatives in the event a reload is needed. (define_insn "decrement_and_branch_until_zero" [(set (pc) (if_then_else (match_operator 0 "relop_no_unsigned" [(match_operand:SI 1 "register_operand" "+!r,!r,m,m") (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc))) (set (match_dup 1) (plus:SI (match_dup 1) (match_operand:SI 3 "add_operand" "rI,J,rI,J"))) (clobber (match_scratch:SI 4 "=X,X,&r,&r")) (clobber (match_scratch:SI 5 "=X,X,&r,&r"))] "find_reg_note (insn, REG_NONNEG, 0)" "@ bcnd.n %B0,%1,%2\;addu %1,%1,%3 bcnd.n %B0,%1,%2\;subu %1,%1,%n3 ld %4,%1\;addu %5,%4,%3\;bcnd.n %B0,%4,%2\;st %5,%1 ld %4,%1\;subu %5,%4,%n3\;bcnd.n %B0,%4,%2\;st %5,%1" [(set_attr "type" "weird") (set_attr "length" "2,2,4,4")]) ;; Special insn to serve as the last insn of a define_expand. This insn ;; will generate no code. (define_expand "dummy" [(set (match_operand 0 "" "") (match_dup 0))] "" "") gcc-2.5.8/config/m88k/mot-sysv4.h100444 22011 13 3333 5436764201 15066 0ustar kenneruser/* Definitions of target machine for GNU compiler. Motorola 88100 Delta machine running SVR4 Copyright (C) 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m88k/sysv4.h" /* The .init section preamble code on the svr4 m88k Delta system looks like: _init: subu r31, r31, 0x30 st r1, r31, 0x20 do_global_ctors_aux in crtstuff.c emits do_global_ctors which is put into the .init section. However, this function has its own prolog which allocates more of the stack. The epilogue of do_global_ctors only knows about its own stack allocation, not that in the .init section preamble. So we must undo the allocation performed by the .init section preamble. We use the following instruction: addu r31, r31, 0x30 which is placed immediately after the two instructions shown above and before do_global_ctors. Note that this is a kludge since it depends on knowing the constant 0x30 above. However, no better fix is known at this time. */ #undef INIT_SECTION_PREAMBLE #define INIT_SECTION_PREAMBLE asm ("\taddu\t #r31,#r31,0x30") gcc-2.5.8/config/m88k/sysv3.h100444 22011 13 12167 5453234770 14317 0ustar kenneruser/* Definitions of target machine for GNU compiler. Motorola m88100 running the AT&T/Unisoft/Motorola V.3 reference port. Copyright (C) 1990, 1991 Free Software Foundation, Inc. Contributed by Ray Essick (ressick@mot.com) Enhanced by Tom Wood (Tom_Wood@NeXT.com) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m88k/m88k.h" /* Default switches */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_CHECK_ZERO_DIV | \ MASK_OCS_DEBUG_INFO | \ MASK_OCS_FRAME_POSITION) /* Macros to be automatically defined. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES "-Dm88000 -Dm88k -Dunix -DsysV88 -D__CLASSIFY_TYPE__=2 -Asystem(unix) -Asystem(svr3) -Acpu(m88k) -Amachine(m88k)" /* Override svr3.h to link with ?crt0.o instead of ?crt1.o and ?crtn.o. From arul@sdsu.edu. */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}} crtbegin.o%s" /* Profiled libraries live in a different directory but keep the same names other than that. arul@sdsu.edu says -lg is always needed. */ #undef LIB_SPEC #define LIB_SPEC "%{p:-L/lib/libp}%{pg:%{!p:-L/lib/libp}} -lg -lc crtend.o%s" /* Hot version of the profiler that uses r10 to pass the address of the counter. the _gcc_mcount routine knows not to screw with the parameter registers. DG/UX does this; i wrote a gnu-c/88k specific version and put it in libgcc2.c -- RBE; this macro knows about the leading underscore convention. */ #undef FUNCTION_PROFILER #define FUNCTION_PROFILER(FILE, LABELNO) \ output_function_profiler (FILE, LABELNO, "_gcc_mcount", 0) /* Various other changes that we want to have in place without too many changes to the m88k.h file. */ #undef USE_LIBG #define USE_LIBG /* Define a few machine-specific details of the implementation of constructors. */ /* Although the .init section is used, it is not automatically invoked. */ #define INVOKE__main /* State that atexit exists so __do_global_ctors will register __do_global_dtors. */ #define HAVE_ATEXIT #define CTOR_LIST_BEGIN \ asm (INIT_SECTION_ASM_OP); \ asm ("\tsubu\t r31,r31,16"); /* (STACK_BOUNDARY / BITS_PER_UNIT) == 16 */ \ asm ("\tst\t r0,r31,32"); /* REG_PARM_STACK_SPACE (0) == 32 */ #define CTOR_LIST_END /* ASM_OUTPUT_CONSTRUCTOR outputs code into the .init section to push the address of the constructor. This becomes the body of __do_global_ctors in crtstuff.c. r13 is a temporary register. */ #undef ASM_OUTPUT_CONSTRUCTOR #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ do { \ init_section (); \ fprintf (FILE, "\tor.u\t r13,r0,hi16("); \ assemble_name (FILE, NAME); \ fprintf (FILE, ")\n\tor\t r13,r13,lo16("); \ assemble_name (FILE, NAME); \ fprintf (FILE, ")\n\tsubu\t r31,r31,%d\n\tst\t r13,r31,%d\n", \ STACK_BOUNDARY / BITS_PER_UNIT, REG_PARM_STACK_SPACE (0)); \ } while (0) #undef DO_GLOBAL_CTORS_BODY #define DO_GLOBAL_CTORS_BODY \ do { \ func_ptr *__CTOR_LIST__ = __builtin_alloca (0), *p; \ for (p = __CTOR_LIST__; *p; p += 4) \ (*p) (); \ } while (0) #define DTOR_LIST_BEGIN \ asm (FINI_SECTION_ASM_OP); \ func_ptr __DTOR_LIST__[4] = { (func_ptr) (-1), (func_ptr) (-1), \ (func_ptr) (-1), (func_ptr) (-1) } #define DTOR_LIST_END \ asm (FINI_SECTION_ASM_OP); \ func_ptr __DTOR_END__[4] = { (func_ptr) 0, (func_ptr) 0, \ (func_ptr) 0, (func_ptr) 0 } /* A C statement (sans semicolon) to output an element in the table of global destructors. The table is constructed in the .fini section so that an explicit linker script is not required. The complication is that this section is padded with NOP instructions and to either 8 or 16 byte alignment depending on the specific system. A clever way to avoid trouble is to output a block of 16 bytes where the extra words are known values (-1). */ #undef ASM_OUTPUT_DESTRUCTOR #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ do { \ register int i; \ fini_section (); \ fprintf (FILE, "\t%s\t ", ASM_LONG); \ assemble_name (FILE,NAME); \ fprintf (FILE, "\n"); \ for (i = 1; i < 4; i++) \ fprintf (FILE, "\t%s\t -1\n", ASM_LONG); \ } while (0) /* Walk the list looking for the terminating zero and ignoring all values of -1. */ #undef DO_GLOBAL_DTORS_BODY #define DO_GLOBAL_DTORS_BODY \ do { \ int i; \ for (i = 0; __DTOR_LIST__[i] != 0; i++) \ if (((int *)__DTOR_LIST__)[i] != -1) \ __DTOR_LIST__[i] (); \ } while (0) gcc-2.5.8/config/m88k/sysv4.h100444 22011 13 4347 5453234773 14304 0ustar kenneruser/* Definitions of target machine for GNU compiler. Motorola 88100 in an 88open ABI environment. Copyright (C) 1990, 1991 Free Software Foundation, Inc. Written by Ron Guilmette (rfg@ncd.com). Contributed to FSF by Network Computing Devices. Other contributions by Vince Guarna (vguarna@urbana.mcd.mot.com), Ray Essick (essick@i88.isc.com), Wilson Tien (wtien@urbana.mcd.mot.com), and Tom Wood (Tom_Wood@NeXT.com) This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* DWARF_DEBUGGING_INFO defined in svr4.h. */ #ifndef NO_BUGS #define AS_BUG_DOT_LABELS #define AS_BUG_POUND_TYPE #endif #include "svr4.h" #include "m88k/m88k.h" /* Identify the compiler. */ #undef VERSION_INFO1 #define VERSION_INFO1 "88open ABI, " /* Default switches */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_CHECK_ZERO_DIV | \ MASK_OCS_DEBUG_INFO | \ MASK_SVR4) /* Cpp spec. These pre-assertions are needed for SVR4 as they occur often in the system header files. __svr4__ is our extension. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES \ "-Dm88000 -Dm88k -Dunix -D__svr4__ -Amachine(m88k) -Acpu(m88k) -Asystem(unix) -Asystem(svr4)" /* For the AT&T SVR4 port, the function is _mcount. */ #undef FUNCTION_PROFILER #define FUNCTION_PROFILER(FILE, LABELNO) \ output_function_profiler (FILE, LABELNO, "_mcount", 1) /* Override svr4.h and m88k.h. */ #undef INIT_SECTION_ASM_OP #define INIT_SECTION_ASM_OP "section\t.init,\"xa\",#progbits" #undef CTORS_SECTION_ASM_OP #define CTORS_SECTION_ASM_OP "section\t.ctors,\"a\",#progbits" #undef DTORS_SECTION_ASM_OP #define DTORS_SECTION_ASM_OP "section\t.dtors,\"a\",#progbits" gcc-2.5.8/config/m88k/t-dgux100444 22011 13 1307 5443705723 14164 0ustar kenneruser# Specify how to create the *.asm files MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \ moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \ moveDI96x.asm $(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh $(srcdir)/config/m88k/m88k-move.sh LIB2FUNCS_EXTRA = $(MOVE_ASM) LIBGCC1 = libgcc1.null CROSS_LIBGCC1 = libgcc1.null # For DG/UX we build crtbegin.o and crtend.o which serve to add begin and # end labels to the .ctors and .dtors section when we link using gcc. # In a coff environment, a link script is required. EXTRA_PARTS=crtbegin.o crtend.o m88kdgux.ld m88kdgux.ld: $(srcdir)/config/m88k/dgux.ld rm -f m88kdgux.ld; cp $(srcdir)/config/m88k/dgux.ld ./m88kdgux.ld gcc-2.5.8/config/m88k/t-dgux-gas100444 22011 13 1336 5443705724 14737 0ustar kenneruser# Specify how to create the *.asm files MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \ moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \ moveDI96x.asm $(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh $(srcdir)/config/m88k/m88k-move.sh LIB2FUNCS_EXTRA = $(MOVE_ASM) LIBGCC1 = libgcc1.null CROSS_LIBGCC1 = libgcc1.null T_CPPFLAGS = -DUSE_GAS # For DG/UX we build crtbegin.o and crtend.o which serve to add begin and # end labels to the .ctors and .dtors section when we link using gcc. # In a coff environment, a link script is required. EXTRA_PARTS=crtbegin.o crtend.o m88kdgux.ld m88kdgux.ld: $(srcdir)/config/m88k/dgux.ld rm -f m88kdgux.ld; cp $(srcdir)/config/m88k/dgux.ld ./m88kdgux.ld gcc-2.5.8/config/m88k/t-luna100444 22011 13 565 5443705723 14141 0ustar kenneruser# Specify how to create the *.asm files MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \ moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \ moveDI96x.asm $(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh bash $(srcdir)/config/m88k/m88k-move.sh -no-tdesc LIB2FUNCS_EXTRA = $(MOVE_ASM) LIBGCC1 = libgcc1.null CROSS_LIBGCC1 = libgcc1.null gcc-2.5.8/config/m88k/t-luna-gas100444 22011 13 614 5443705725 14706 0ustar kenneruser# Specify how to create the *.asm files MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \ moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \ moveDI96x.asm $(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh bash $(srcdir)/config/m88k/m88k-move.sh -no-tdesc LIB2FUNCS_EXTRA = $(MOVE_ASM) LIBGCC1 = libgcc1.null CROSS_LIBGCC1 = libgcc1.null T_CPPFLAGS = -DUSE_GAS gcc-2.5.8/config/m88k/t-m88k100444 22011 13 1104 5473747414 14005 0ustar kenneruser# Specify how to create the *.asm files MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \ moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \ moveDI96x.asm $(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh $(srcdir)/config/m88k/m88k-move.sh LIB2FUNCS_EXTRA = $(MOVE_ASM) LIBGCC1 = libgcc1.null CROSS_LIBGCC1 = libgcc1.null # For svr4 we build crtbegin.o and crtend.o which serve to add begin and # end labels to the .ctors and .dtors section when we link using gcc. EXTRA_PARTS=crtbegin.o crtend.o # Clean up. realclean:: rm -f $(MOVE_ASM) gcc-2.5.8/config/m88k/t-m88k-gas100444 22011 13 1056 5443705730 14553 0ustar kenneruser# Specify how to create the *.asm files MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \ moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \ moveDI96x.asm $(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh $(srcdir)/config/m88k/m88k-move.sh LIB2FUNCS_EXTRA = $(MOVE_ASM) LIBGCC1 = libgcc1.null CROSS_LIBGCC1 = libgcc1.null T_CPPFLAGS = -DUSE_GAS # For svr4 we build crtbegin.o and crtend.o which serve to add begin and # end labels to the .ctors and .dtors section when we link using gcc. EXTRA_PARTS=crtbegin.o crtend.o gcc-2.5.8/config/m88k/t-sysv4100444 22011 13 1115 5443705732 14302 0ustar kenneruser# Specify how to create the *.asm files MOVE_ASM = moveHI15x.asm moveQI16x.asm moveSI46x.asm moveSI64n.asm \ moveHI48x.asm moveSI45x.asm moveSI47x.asm moveSI96x.asm \ moveDI96x.asm # Use the -abi option for version 03.00 syntax. $(MOVE_ASM): $(srcdir)/config/m88k/m88k-move.sh $(srcdir)/config/m88k/m88k-move.sh -abi LIB2FUNCS_EXTRA = $(MOVE_ASM) LIBGCC1 = libgcc1.null CROSS_LIBGCC1 = libgcc1.null # For svr4 we build crtbegin.o and crtend.o which serve to add begin and # end labels to the .ctors and .dtors section when we link using gcc. EXTRA_PARTS=crtbegin.o crtend.o gcc-2.5.8/config/m88k/tekXD88.h100444 22011 13 3506 5373072444 14403 0ustar kenneruser/* Tektronix XD88 UTekV 3.2e (svr3 derived from UniSoft System V/88) Copyright (C) 1993 Free Software Foundation, Inc. Contributed by Kaveh R. Ghazi (ghazi@caip.rutgers.edu) 2/22/93. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m88k/sysv3.h" /* Don't output structure tag names when it causes a forward reference. Symptom: Error messages like as: "/usr/tmp/cca22733.s": cannot reduce symbol table, unused symbols remain when compiling some programs. example program (C++): struct bad { bad(); }; bad::bad() {} This problem seems to have gone away, perhaps with release 3.6 of the O/S from Dolphin. */ /* #undef SDB_ALLOW_FORWARD_REFERENCES */ /* I don't know if this SDB thing is needed or not --KRG */ /* Use T_ARG as T_VOID. T_VOID is not defined in as it should be. */ #define T_VOID T_ARG /* The bundled ld program needs link editor directives which normally reside in /lib/default.ld. We'll pass our own copy during the link phase because additioal information about extra sections must be added so that gcc generated files will link properly. --KRG. */ #undef LINK_SPEC #define LINK_SPEC "gcc.ld%s" gcc-2.5.8/config/m88k/tekXD88.ld100444 22011 13 2510 5373072445 14546 0ustar kenneruser/* gcc.ld - COFF linker directives for the Tektronix XD88. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. This file does the following: - Sets VIRTUAL addr of .text to 0x10200 Sets FILE addr of .text to 0x200 (BLOCK directive) - Depending on size of .text section rounds up to next 4 MG boundary, adds (size of .text and vaddr of .text) mod 64K This is to handle sections larger than 4 MG. */ SECTIONS { .text 0x10200 BLOCK (0x200): { *(.init) *(.text) *(.rodata) *(.tdesc) *(.fini)} GROUP BIND( ((SIZEOF(.text) / 0x400000 * 0x400000) + 0x400000) + ((SIZEOF(.text) + ADDR(.text)) % 0x10000) ) : { .data : { } .bss : { } } } gcc-2.5.8/config/m88k/x-dgux100444 22011 13 74 5427612644 14131 0ustar kenneruserCC = /bin/gcc BISONFLAGS = -l X_CFLAGS = -D_M88KBCS_TARGET gcc-2.5.8/config/m88k/x-dolph100444 22011 13 1154 5473747430 14333 0ustar kenneruser# Use link editor directives to make NULL pointers point to # illegal addresses. EXTRA_PARTS=crtbegin.o crtend.o gcc.ld gcc.ld: $(srcdir)/config/m88k/dolphin.ld rm -f gcc.ld; cp $(srcdir)/config/m88k/dolphin.ld gcc.ld # Green Hills C on Dolphin UNIX System V/88 Release 3.2 Version 3.6/5.86 does # not provide alloca. It does not harm to have it defined on version 3.8.alfa # even though it's not needed there. ALLOCA=alloca.o # Under DolphinOS 3.8.alfa, /bin/cc defines __GNUC__, but not __m88k__, # causing gdstarg.h to fail. Defining __m88k__ does probably not hurt on # DolphinOS 3.6. X_CFLAGS =-D__m88k__ gcc-2.5.8/config/m88k/x-sysv3100444 22011 13 151 5425501123 14250 0ustar kenneruser# this is m88k/x-sysv3 # native compiler does not provide alloca ALLOCA = alloca.o # end m88k/x-sysv3 gcc-2.5.8/config/m88k/x-sysv4100444 22011 13 601 5223343770 14261 0ustar kenneruser# Problems in early version of the assembler have been fixed (-DNO_BUGS). # There are peculiar problems with the include files that require __STDC__ # to be defined as 0. This results in sigset_t being defined which otherwise # results in a problem when includes . X_CFLAGS = -DNO_BUGS -D__STDC__=0 # The CI5 compiler does not provide alloca. ALLOCA = alloca.o gcc-2.5.8/config/m88k/x-tekXD88100444 22011 13 572 5377601113 14375 0ustar kenneruser# Install the custom Tektronix XD88 link editor directives file. EXTRA_PARTS=crtbegin.o crtend.o gcc.ld gcc.ld: $(srcdir)/config/m88k/tekXD88.ld rm -f gcc.ld; cp $(srcdir)/config/m88k/tekXD88.ld ./gcc.ld # Green Hills C on the Tektronix XD88 does not provide alloca. ALLOCA=alloca.o # rc is cleaner, but the ar program sometimes crashes. # This is a workaround. AR_FLAGS=qc gcc-2.5.8/config/m88k/xm-m88k.h100444 22011 13 4015 5413066215 14403 0ustar kenneruser/* Configuration for GNU compiler. Motorola m88100 in an 88open OCS/BCS environment. Copyright (C) 1988, 1989, 1990, 1991, 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* #defines that need visibility everywhere. */ #define FALSE 0 #define TRUE 1 /* This describes the machine the compiler is hosted on. */ #define HOST_BITS_PER_CHAR 8 #define HOST_BITS_PER_SHORT 16 #define HOST_BITS_PER_INT 32 #define HOST_BITS_PER_LONG 32 #define HOST_BITS_PER_LONGLONG 64 #define HOST_WORDS_BIG_ENDIAN /* Arguments to use with `exit'. */ #define SUCCESS_EXIT_CODE 0 #define FATAL_EXIT_CODE 33 /* Use System V memory functions. */ #define bcopy(a,b,c) memcpy (b,a,c) #define bzero(a,b) memset (a,0,b) #define bcmp(a,b,c) memcmp (a,b,c) #define rindex strrchr #define index strchr /* The 88open BCS (and ABI) environment doesn't support BSD features (vfork, getrusage), so use USG. The Omron Luna/88k is BSD though. */ #ifndef luna88k #define USG #define NO_SYS_SIGLIST #endif /* Define HAVE_VPRINTF if it is available on host system. */ #define HAVE_VPRINTF /* If not compiled with GNU C, use the C alloca */ #ifndef __GNUC__ #define USE_C_ALLOCA #endif /* For DG/UX, the best size is different. */ #ifdef __DGUX__ #define OBSTACK_CHUNK_SIZE (8192-16) #endif /* target machine dependencies. tm.h is a symbolic link to the actual target specific file. */ #include "tm.h" gcc-2.5.8/config/m88k/xm-sysv3.h100444 22011 13 1744 5321035337 14710 0ustar kenneruser/* Configuration for GNU C-compiler. Motorola m88100 running the AT&T/Unisoft/Motorola V.3 reference port. Copyright (C) 1990 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "m88k/xm-m88k.h" #define R_OK 4 #define W_OK 2 #define X_OK 1 #define F_OK 0 /* for the emacs version of alloca */ #define STACK_DIRECTION -1 gcc-2.5.8/config/mips/ 40777 22011 13 0 5502603037 13111 5ustar kennerusergcc-2.5.8/config/mips/bsd-4-gdb.h100444 22011 13 1602 5322365266 15024 0ustar kenneruser/* Definitions of target machine for GNU compiler. Mips BSD version using encapsulated stabs. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG #include "mips/bsd-4.h" gcc-2.5.8/config/mips/bsd-4.h100444 22011 13 4247 5453234776 14310 0ustar kenneruser/* Definitions of target machine for GNU compiler. MIPS RISC-OS BSD version. Copyright (C) 1991 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define MIPS_BSD43 #define CPP_PREDEFINES "\ -Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \ -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \ -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)" #define STANDARD_INCLUDE_DIR "/bsd43/usr/include" #define CPP_SPEC "\ %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \ %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \ %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \ %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C} \ %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ %{!.S:%{!.s: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}" #define LINK_SPEC "\ %{G*} \ %{!mgas: \ %{EB} %{!EB: -EB} \ %{EL: %e-EL not supported} \ %{bestGnum} %{shared} %{non_shared} \ %{mips1} %{mips2} %{mips3} \ -systype /bsd43/ }" #define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc" #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}" #define MACHINE_TYPE "RISC-OS BSD Mips" /* Generate calls to memcpy, etc., not bcopy, etc. */ #define TARGET_MEM_FUNCTIONS /* Override defaults for finding the MIPS tools. */ #define MD_STARTFILE_PREFIX "/bsd43/usr/lib/cmplrs/cc/" #define MD_EXEC_PREFIX "/bsd43/usr/lib/cmplrs/cc/" #include "mips/mips.h" gcc-2.5.8/config/mips/bsd-5-gdb.h100444 22011 13 1616 5322365267 15033 0ustar kenneruser/* Definitions of target machine for GNU compiler. Mips RISC-OS 5.0 BSD version using encapsulated stabs. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG #include "mips/bsd-5.h" gcc-2.5.8/config/mips/bsd-5.h100444 22011 13 4426 5453235001 14266 0ustar kenneruser/* Definitions of target machine for GNU compiler. MIPS RISC-OS, 5.0 BSD version. Copyright (C) 1991 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define MIPS_BSD43 #define CPP_PREDEFINES "\ -Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \ -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \ -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)" #define STANDARD_INCLUDE_DIR "/bsd43/usr/include" #define CPP_SPEC "\ %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \ %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \ %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \ %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C} \ %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ %{!.S:%{!.s: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}" #define LINK_SPEC "\ %{G*} \ %{!mgas: \ %{EB} %{!EB: -EB} \ %{EL: %e-EL not supported} \ %{mips1} %{mips2} %{mips3} %{bestGnum} \ %{shared} %{non_shared} %{call_shared} %{no_archive} %{exact_version} \ %{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \ -systype /bsd43/ }" #define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc" #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}" #define MACHINE_TYPE "RISC-OS BSD Mips" /* Generate calls to memcpy, etc., not bcopy, etc. */ #define TARGET_MEM_FUNCTIONS /* Override defaults for finding the MIPS tools. */ #define MD_STARTFILE_PREFIX "/bsd43/usr/lib/cmplrs/cc/" #define MD_EXEC_PREFIX "/bsd43/usr/lib/cmplrs/cc/" #include "mips/mips.h" gcc-2.5.8/config/mips/dec-bsd.h100666 22011 13 4244 5461146116 14670 0ustar kenneruser/* Definitions for DECstation running BSD as target machine for GNU compiler. Copyright (C) 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define DECSTATION #ifndef CPP_PREDEFINES #define CPP_PREDEFINES "-D__ANSI_COMPAT \ -DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD -Dbsd4_4 -Dhost_mips -Dmips \ -Dunix -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 \ -Asystem(unix) -Asystem(bsd) -Amachine(mips)" #endif #ifndef ASM_SPEC #define ASM_SPEC "%{G*}" #endif #ifndef CPP_SPEC #define CPP_SPEC "\ %{.S: -D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ %{.cc: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS} \ %{.cxx: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS} \ %{.C: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS} \ %{.m: -D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C} \ %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ %{!.S:%{!.s: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}" #endif #ifndef LINK_SPEC #define LINK_SPEC "%{G*}" #endif #define LIB_SPEC "" #define STARTFILE_SPEC "" /* For compatibility with types.h. */ #ifndef SIZE_TYPE #define SIZE_TYPE "unsigned int" #endif #ifndef MACHINE_TYPE #define MACHINE_TYPE "DECstation running BSD 4.4" #endif #define TARGET_DEFAULT MASK_GAS #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG #include "mips/mips.h" /* Since gas and gld are standard on 4.4 BSD, we don't need these */ #undef MD_EXEC_PREFIX #undef MD_STARTFILE_PREFIX #undef ASM_FINAL_SPEC #undef LIB_SPEC #undef STARTFILE_SPEC gcc-2.5.8/config/mips/dec-gosf1.h100444 22011 13 1661 5322365270 15131 0ustar kenneruser/* Definitions of target machine for GNU compiler. DECstation (OSF/1) version with stabs. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Use stabs instead of ECOFF debug format. */ #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG #include "mips/dec-osf1.h" gcc-2.5.8/config/mips/dec-osf1.h100444 22011 13 3350 5453235003 14752 0ustar kenneruser/* Definitions of target machine for GNU compiler. DECstation (OSF/1) version. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define DEC_OSF1 #define CPP_PREDEFINES "\ -D__ANSI_COMPAT -DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD \ -Dbsd4_2 -Dhost_mips -Dmips -Dosf -Dunix \ -Asystem(unix) -Asystem(xpg4) -Acpu(mips) -Amachine(mips)" #define LINK_SPEC "\ %{G*} \ %{!mgas: \ %{EL} %{!EL: -EL} \ %{EB: %e-EB not supported} \ %{mips1} %{mips2} %{mips3} %{bestGnum} \ %{shared} %{non_shared} %{call_shared} %{no_archive} %{exact_version} \ %{!shared: %{!non_shared: %{!call_shared: -non_shared}}}}" #include "mips/ultrix.h" /* Specify size_t, ptrdiff_t, and wchar_t types. */ #undef SIZE_TYPE #undef PTRDIFF_TYPE #undef WCHAR_TYPE #undef WCHAR_TYPE_SIZE #define SIZE_TYPE "long unsigned int" #define PTRDIFF_TYPE "int" #define WCHAR_TYPE "short unsigned int" #define WCHAR_TYPE_SIZE SHORT_TYPE_SIZE /* turn off collect2 COFF support, since ldfcn now has elf declaration */ #undef OBJECT_FORMAT_COFF #undef MACHINE_TYPE #define MACHINE_TYPE "DECstation running DEC OSF/1" gcc-2.5.8/config/mips/iris3-gdb.h100444 22011 13 1576 5322365271 15152 0ustar kenneruser/* Definitions of target machine for GNU compiler. Iris version using encapsulated stabs. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG #include "mips/iris3.h" gcc-2.5.8/config/mips/iris3.h100444 22011 13 7576 5454353634 14434 0ustar kenneruser/* Definitions of target machine for GNU compiler. Iris version. Copyright (C) 1991 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define SGI_TARGET 1 /* inform other mips files this is SGI */ /* Names to predefine in the preprocessor for this target machine. */ #define CPP_PREDEFINES "\ -Dunix -Dmips -Dsgi -DSVR3 -Dhost_mips -DMIPSEB -DSYSTYPE_SYSV \ -Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)" #define STARTFILE_SPEC "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}" #define CPP_SPEC "\ %{!ansi:-D__EXTENSIONS__} -D_MIPSEB -D_SYSTYPE_SYSV \ %{.S: -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ %{.s: -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ %{.cc: -D_LANGUAGE_C_PLUS_PLUS} \ %{.cxx: -D_LANGUAGE_C_PLUS_PLUS} \ %{.C: -D_LANGUAGE_C_PLUS_PLUS} \ %{.m: -D_LANGUAGE_OBJECTIVE_C} \ %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}" #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} crtn.o%s" #define MACHINE_TYPE "Silicon Graphics Mips" /* SGI Iris doesn't support -EB/-EL like other MIPS processors. */ #define ASM_SPEC "\ %{!mgas: \ %{!mrnames: %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}}} \ %{pipe: %e-pipe is not supported.} \ %{mips1} %{mips2} %{mips3} \ %{noasmopt:-O0} \ %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}} \ %{g} %{g0} %{g1} %{g2} %{g3} %{v} %{K} \ %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \ %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \ %{gcoff:-g} %{gstabs0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}} \ %{G*}" #define LINK_SPEC "\ %{G*} \ %{!mgas: %{mips1} %{mips2} %{mips3} \ %{bestGnum} %{shared} %{non_shared}}" /* Always use 1 for .file number. I [meissner@osf.org] wonder why IRIS needs this. */ #define SET_FILE_NUMBER() num_source_filenames = 1 /* Put out a label after a .loc. I [meissner@osf.org] wonder why IRIS needs this. */ #define LABEL_AFTER_LOC(STREAM) fprintf (STREAM, "LM%d:\n", ++sym_lineno) #define STACK_ARGS_ADJUST(SIZE) \ { \ SIZE.constant += 4; \ if (SIZE.constant < 32) \ SIZE.constant = 32; \ } /* Define this macro to control use of the character `$' in identifier names. The value should be 0, 1, or 2. 0 means `$' is not allowed by default; 1 means it is allowed by default if `-traditional' is used; 2 means it is allowed by default provided `-ansi' is not used. 1 is the default; there is no need to define this macro in that case. */ #define DOLLARS_IN_IDENTIFIERS 0 /* Tell G++ not to create constructors or destructors with $'s in them. */ #define NO_DOLLAR_IN_LABEL 1 /* Specify size_t, ptrdiff_t, and wchar_t types. */ #define SIZE_TYPE "unsigned int" #define PTRDIFF_TYPE "int" #define WCHAR_TYPE "unsigned char" #define WCHAR_TYPE_SIZE BITS_PER_UNIT /* Generate calls to memcpy, etc., not bcopy, etc. */ #define TARGET_MEM_FUNCTIONS /* Plain char is unsigned in the SGI compiler. */ #define DEFAULT_SIGNED_CHAR 0 #include "mips/mips.h" gcc-2.5.8/config/mips/iris4-gdb.h100444 22011 13 1625 5322365272 15147 0ustar kenneruser/* Definitions of target machine for GNU compiler. Iris version 4. Copyright (C) 1991 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Use stabs instead of ECOFF debug format. */ #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG #include "mips/iris4.h" gcc-2.5.8/config/mips/iris4.h100444 22011 13 2661 5375756373 14434 0ustar kenneruser/* Definitions of target machine for GNU compiler. Iris version 4. Copyright (C) 1991 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Use atexit for static constructors/destructors, instead of defining our own exit function. */ #define HAVE_ATEXIT #include "mips/iris3.h" /* Assembler is said to have trouble with .ascii with escape chars. The quickest way to avoid the problem is not to use .ascii. */ #undef ASM_OUTPUT_ASCII #define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ { \ unsigned char *s; \ int i; \ for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++) \ { \ if ((i % 8) == 0) \ fputs ("\n\t.byte\t", (FILE)); \ fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \ } \ fputs ("\n", (FILE)); \ } gcc-2.5.8/config/mips/iris4gl.h100666 22011 13 1230 5400572363 14734 0ustar kenneruser/* Like iris4-gdb.h, but always inhibits assembler optimization. Use this via mips-sgi-iris4loser if you need it. */ #include "mips/iris4-gdb.h" #undef ASM_SPEC #define ASM_SPEC "\ %{!mgas: \ %{!mrnames: %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}}} \ %{pipe: %e-pipe is not supported.} \ %{mips1} %{mips2} %{mips3} \ %{g} %{g0} %{g1} %{g2} %{g3} %{v} %{K} \ %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \ %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \ %{gcoff:-g} %{gstabs0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}} \ %{G*}" gcc-2.5.8/config/mips/iris4loser.h100666 22011 13 1227 5402225331 15454 0ustar kenneruser/* Like iris4.h, but always inhibits assembler optimization. Use this via mips-sgi-iris4loser if you need it. */ #include "mips/iris4.h" #undef ASM_SPEC #define ASM_SPEC "\ %{!mgas: \ %{!mrnames: %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}}} \ %{pipe: %e-pipe is not supported.} \ %{mips1} %{mips2} %{mips3} \ -O0 \ %{g} %{g0} %{g1} %{g2} %{g3} %{v} %{K} \ %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \ %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \ %{gcoff:-g} %{gstabs0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}} \ %{G*}" gcc-2.5.8/config/mips/iris5.h100444 22011 13 5541 5464246304 14420 0ustar kenneruser/* Definitions of target machine for GNU compiler. Iris version 5. Copyright (C) 1993 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define TARGET_DEFAULT MASK_ABICALLS #define ABICALLS_ASM_OP ".option pic2" #define OBJECT_FORMAT_ELF #include "mips/iris4.h" /* Specify size_t, ptrdiff_t, and wchar_t types. */ #undef SIZE_TYPE #undef PTRDIFF_TYPE #undef WCHAR_TYPE #undef WCHAR_TYPE_SIZE #define SIZE_TYPE "unsigned int" #define PTRDIFF_TYPE "int" #define WCHAR_TYPE "long int" #define WCHAR_TYPE_SIZE LONG_TYPE_SIZE /* ??? _MIPS_SIM and _MIPS_SZPTR should eventually depend on options when options for them exist. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES \ "-Dunix -Dmips -Dsgi -Dhost_mips -DMIPSEB -DSYSTYPE_SVR4 \ -D_SVR4_SOURCE -D_MODERN_C -D__DSO__ \ -D_MIPS_SIM=_MIPS_SIM_ABI32 -D_MIPS_SZPTR=32 \ -Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(sgi)" #undef CPP_SPEC #define CPP_SPEC "\ %{!ansi:-D__EXTENSIONS__ -D_SGI_SOURCE -D_LONGLONG} \ %{.S: -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ %{.cc: -D_LANGUAGE_C_PLUS_PLUS} \ %{.cxx: -D_LANGUAGE_C_PLUS_PLUS} \ %{.C: -D_LANGUAGE_C_PLUS_PLUS} \ %{.m: -D_LANGUAGE_OBJECTIVE_C} \ %{!.S: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}\ %{!mfp64: -D_MIPS_FPSET=16}%{mfp64: -D_MIPS_FPSET=32} \ %{mips1: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \ %{mips2: -D_MIPS_ISA=_MIPS_ISA_MIPS2} \ %{mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \ %{!mips1: %{!mips2: %{!mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS1}}} \ %{!mint64: -D_MIPS_SZINT=32}%{mint64: -D_MIPS_SZINT=64} \ %{!mlong64: -D_MIPS_SZLONG=32}%{mlong64: -D_MIPS_SZLONG=64}" #undef LINK_SPEC #define LINK_SPEC "\ %{G*} \ %{!mgas: \ %{mips1} %{mips2} %{mips3} %{bestGnum} \ %{shared} %{non_shared} %{call_shared} %{no_archive} %{exact_version} \ %{!shared: %{!non_shared: \ %{!call_shared: -call_shared -no_unresolved}}} \ -_SYSTYPE_SVR4 }" #undef LIB_SPEC #define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s" /* We do not want to run mips-tfile! */ #undef ASM_FINAL_SPEC #undef OBJECT_FORMAT_COFF /* We don't support debugging info for now. */ #undef DBX_DEBUGGING_INFO #undef SDB_DEBUGGING_INFO #undef MIPS_DEBUGGING_INFO #undef MACHINE_TYPE #define MACHINE_TYPE "SGI running IRIX 5.0" gcc-2.5.8/config/mips/mips-4-gdb.h100444 22011 13 1605 5322365273 15225 0ustar kenneruser/* Definitions of target machine for GNU compiler. MIPS default version using encapsulated stabs. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG #include "mips/mips.h" gcc-2.5.8/config/mips/mips-5-gdb.h100444 22011 13 1623 5322365273 15226 0ustar kenneruser/* Definitions of target machine for GNU compiler. MIPS RISC-OS 5.0 default version using encapsulated stabs. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG #include "mips/mips-5.h" gcc-2.5.8/config/mips/mips-5.h100444 22011 13 2256 5425535505 14500 0ustar kenneruser/* Definitions of target machine for GNU compiler. MIPS RISC-OS 5.0 default version. Copyright (C) 1992 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #define LINK_SPEC "\ %{G*} \ %{!mgas: \ %{EB} %{!EB: -EB} \ %{EL: %e-EL not supported} \ %{mips1} %{mips2} %{mips3} %{bestGnum} \ %{shared} %{non_shared} %{call_shared} %{no_archive} %{exact_version} \ %{!shared: %{!non_shared: %{!call_shared: -non_shared}}}}" #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}" #include "mips/mips.h" gcc-2.5.8/config/mips/mips.c100444 22011 13 372326 5471330034 14370 0ustar kenneruser/* Subroutines for insn-output.c for MIPS Contributed by A. Lichnewsky, lich@inria.inria.fr. Changes by Michael Meissner, meissner@osf.org. Copyright (C) 1989, 1990, 1991 Free Software Foundation, Inc. This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "config.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "insn-attr.h" #include "insn-codes.h" #include "recog.h" #include "output.h" #undef MAX /* sys/param.h may also define these */ #undef MIN #include #include #include #include #include #include "tree.h" #include "expr.h" #include "flags.h" #ifndef R_OK #define R_OK 4 #define W_OK 2 #define X_OK 1 #endif #if defined(USG) || defined(NO_STAB_H) #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */ #else #include /* On BSD, use the system's stab.h. */ #endif /* not USG */ #ifdef __GNU_STAB__ #define STAB_CODE_TYPE enum __stab_debug_code #else #define STAB_CODE_TYPE int #endif extern void abort (); extern int atoi (); extern char *getenv (); extern char *mktemp (); extern rtx adj_offsettable_operand (); extern rtx copy_to_reg (); extern void error (); extern void fatal (); extern tree lookup_name (); extern void pfatal_with_name (); extern void warning (); extern tree current_function_decl; extern FILE *asm_out_file; /* Enumeration for all of the relational tests, so that we can build arrays indexed by the test type, and not worry about the order of EQ, NE, etc. */ enum internal_test { ITEST_EQ, ITEST_NE, ITEST_GT, ITEST_GE, ITEST_LT, ITEST_LE, ITEST_GTU, ITEST_GEU, ITEST_LTU, ITEST_LEU, ITEST_MAX }; /* Global variables for machine-dependent things. */ /* Threshold for data being put into the small data/bss area, instead of the normal data area (references to the small data/bss area take 1 instruction, and use the global pointer, references to the normal data area takes 2 instructions). */ int mips_section_threshold = -1; /* Count the number of .file directives, so that .loc is up to date. */ int num_source_filenames = 0; /* Count the number of sdb related labels are generated (to find block start and end boundaries). */ int sdb_label_count = 0; /* Next label # for each statment for Silicon Graphics IRIS systems. */ int sym_lineno = 0; /* Non-zero if inside of a function, because the stupid MIPS asm can't handle .files inside of functions. */ int inside_function = 0; /* Files to separate the text and the data output, so that all of the data can be emitted before the text, which will mean that the assembler will generate smaller code, based on the global pointer. */ FILE *asm_out_data_file; FILE *asm_out_text_file; /* Linked list of all externals that are to be emitted when optimizing for the global pointer if they haven't been declared by the end of the program with an appropriate .comm or initialization. */ struct extern_list { struct extern_list *next; /* next external */ char *name; /* name of the external */ int size; /* size in bytes */ } *extern_head = 0; /* Name of the file containing the current function. */ char *current_function_file = ""; /* Warning given that Mips ECOFF can't support changing files within a function. */ int file_in_function_warning = FALSE; /* Whether to suppress issuing .loc's because the user attempted to change the filename within a function. */ int ignore_line_number = FALSE; /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */ int set_noreorder; int set_noat; int set_nomacro; int set_volatile; /* The next branch instruction is a branch likely, not branch normal. */ int mips_branch_likely; /* Count of delay slots and how many are filled. */ int dslots_load_total; int dslots_load_filled; int dslots_jump_total; int dslots_jump_filled; /* # of nops needed by previous insn */ int dslots_number_nops; /* Number of 1/2/3 word references to data items (ie, not jal's). */ int num_refs[3]; /* registers to check for load delay */ rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4; /* Cached operands, and operator to compare for use in set/branch on condition codes. */ rtx branch_cmp[2]; /* what type of branch to use */ enum cmp_type branch_type; /* Number of previously seen half-pic pointers and references. */ static int prev_half_pic_ptrs = 0; static int prev_half_pic_refs = 0; /* which cpu are we scheduling for */ enum processor_type mips_cpu; /* which instruction set architecture to use. */ int mips_isa; /* Strings to hold which cpu and instruction set architecture to use. */ char *mips_cpu_string; /* for -mcpu= */ char *mips_isa_string; /* for -mips{1,2,3} */ /* Generating calls to position independent functions? */ enum mips_abicalls_type mips_abicalls; /* Array to RTX class classification. At present, we care about whether the operator is an add-type operator, or a divide/modulus, and if divide/modulus, whether it is unsigned. This is for the peephole code. */ char mips_rtx_classify[NUM_RTX_CODE]; /* Array giving truth value on whether or not a given hard register can support a given mode. */ char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; /* Current frame information calculated by compute_frame_size. */ struct mips_frame_info current_frame_info; /* Zero structure to initialize current_frame_info. */ struct mips_frame_info zero_frame_info; /* Temporary filename used to buffer .text until end of program for -mgpopt. */ static char *temp_filename; /* List of all MIPS punctuation characters used by print_operand. */ char mips_print_operand_punct[256]; /* Map GCC register number to debugger register number. */ int mips_dbx_regno[FIRST_PSEUDO_REGISTER]; /* Buffer to use to enclose a load/store operation with %{ %} to turn on .set volatile. */ static char volatile_buffer[60]; /* Hardware names for the registers. If -mrnames is used, this will be overwritten with mips_sw_reg_names. */ char mips_reg_names[][8] = { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", "hi", "lo", "$fcr31" }; /* Mips software names for the registers, used to overwrite the mips_reg_names array. */ char mips_sw_reg_names[][8] = { "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", "hi", "lo", "$fcr31" }; /* Map hard register number to register class */ enum reg_class mips_regno_to_class[] = { GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, HI_REG, LO_REG, ST_REGS }; /* Map register constraint character to register class. */ enum reg_class mips_char_to_class[256] = { NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, NO_REGS, }; /* Return truth value of whether OP can be used as an operands where a register or 16 bit unsigned integer is needed. */ int uns_arith_operand (op, mode) rtx op; enum machine_mode mode; { if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op)) return TRUE; return register_operand (op, mode); } /* Return truth value of whether OP can be used as an operands where a 16 bit integer is needed */ int arith_operand (op, mode) rtx op; enum machine_mode mode; { if (GET_CODE (op) == CONST_INT && SMALL_INT (op)) return TRUE; return register_operand (op, mode); } /* Return truth value of whether OP can be used as an operand in a two address arithmetic insn (such as set 123456,%o4) of mode MODE. */ int arith32_operand (op, mode) rtx op; enum machine_mode mode; { if (GET_CODE (op) == CONST_INT) return TRUE; return register_operand (op, mode); } /* Return truth value of whether OP is a integer which fits in 16 bits */ int small_int (op, mode) rtx op; enum machine_mode mode; { return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); } /* Return truth value of whether OP is an integer which is too big to be loaded with one instruction. */ int large_int (op, mode) rtx op; enum machine_mode mode; { HOST_WIDE_INT value; if (GET_CODE (op) != CONST_INT) return FALSE; value = INTVAL (op); if ((value & ~0x0000ffff) == 0) /* ior reg,$r0,value */ return FALSE; if (((unsigned long)(value + 32768)) <= 32767) /* subu reg,$r0,value */ return FALSE; if ((value & 0xffff0000) == value) /* lui reg,value>>16 */ return FALSE; return TRUE; } /* Return truth value of whether OP is a register or the constant 0. */ int reg_or_0_operand (op, mode) rtx op; enum machine_mode mode; { switch (GET_CODE (op)) { default: break; case CONST_INT: return (INTVAL (op) == 0); case CONST_DOUBLE: if (CONST_DOUBLE_HIGH (op) != 0 || CONST_DOUBLE_LOW (op) != 0) return FALSE; return TRUE; case REG: case SUBREG: return register_operand (op, mode); } return FALSE; } /* Return truth value of whether OP is one of the special multiply/divide registers (hi, lo). */ int md_register_operand (op, mode) rtx op; enum machine_mode mode; { return (GET_MODE_CLASS (mode) == MODE_INT && GET_CODE (op) == REG && MD_REG_P (REGNO (op))); } /* Return truth value of whether OP is the FP status register. */ int fpsw_register_operand (op, mode) rtx op; enum machine_mode mode; { return (GET_CODE (op) == REG && ST_REG_P (REGNO (op))); } /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */ int mips_const_double_ok (op, mode) rtx op; enum machine_mode mode; { if (GET_CODE (op) != CONST_DOUBLE) return FALSE; if (mode == DImode) return TRUE; if (mode != SFmode && mode != DFmode) return FALSE; if (CONST_DOUBLE_HIGH (op) == 0 && CONST_DOUBLE_LOW (op) == 0) return TRUE; #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT if (TARGET_MIPS_AS) /* gas doesn't like li.d/li.s yet */ { union { double d; int i[2]; } u; double d; u.i[0] = CONST_DOUBLE_LOW (op); u.i[1] = CONST_DOUBLE_HIGH (op); d = u.d; if (d != d) return FALSE; /* NAN */ if (d < 0.0) d = - d; /* Rather than trying to get the accuracy down to the last bit, just use approximate ranges. */ if (mode == DFmode && d > 1.0e-300 && d < 1.0e300) return TRUE; if (mode == SFmode && d > 1.0e-38 && d < 1.0e+38) return TRUE; } #endif return FALSE; } /* Return truth value if a memory operand fits in a single instruction (ie, register + small offset). */ int simple_memory_operand (op, mode) rtx op; enum machine_mode mode; { rtx addr, plus0, plus1; /* Eliminate non-memory operations */ if (GET_CODE (op) != MEM) return FALSE; /* dword operations really put out 2 instructions, so eliminate them. */ if (GET_MODE_SIZE (GET_MODE (op)) > (HAVE_64BIT_P () ? 8 : 4)) return FALSE; /* Decode the address now. */ addr = XEXP (op, 0); switch (GET_CODE (addr)) { default: break; case REG: return TRUE; case CONST_INT: return SMALL_INT (op); case PLUS: plus0 = XEXP (addr, 0); plus1 = XEXP (addr, 1); if (GET_CODE (plus0) == REG && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)) return TRUE; else if (GET_CODE (plus1) == REG && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)) return TRUE; else return FALSE; #if 0 /* We used to allow small symbol refs here (ie, stuff in .sdata or .sbss), but this causes some bugs in G++. Also, it won't interfere if the MIPS linker rewrites the store instruction because the function is PIC. */ case LABEL_REF: /* never gp relative */ break; case CONST: /* If -G 0, we can never have a GP relative memory operation. Also, save some time if not optimizing. */ if (mips_section_threshold == 0 || !optimize || !TARGET_GP_OPT) return FALSE; { rtx offset = const0_rtx; addr = eliminate_constant_term (addr, &offset); if (GET_CODE (op) != SYMBOL_REF) return FALSE; /* let's be paranoid.... */ if (INTVAL (offset) < 0 || INTVAL (offset) > 0xffff) return FALSE; } /* fall through */ case SYMBOL_REF: return SYMBOL_REF_FLAG (addr); #endif } return FALSE; } /* Return true if the code of this rtx pattern is EQ or NE. */ int equality_op (op, mode) rtx op; enum machine_mode mode; { if (mode != GET_MODE (op)) return FALSE; return (classify_op (op, mode) & CLASS_EQUALITY_OP) != 0; } /* Return true if the code is a relational operations (EQ, LE, etc.) */ int cmp_op (op, mode) rtx op; enum machine_mode mode; { if (mode != GET_MODE (op)) return FALSE; return (classify_op (op, mode) & CLASS_CMP_OP) != 0; } /* Genrecog does not take the type of match_operator into consideration, and would complain about two patterns being the same if the same function is used, so make it believe they are different. */ int cmp2_op (op, mode) rtx op; enum machine_mode mode; { if (mode != GET_MODE (op)) return FALSE; return (classify_op (op, mode) & CLASS_CMP_OP) != 0; } /* Return true if the code is an unsigned relational operations (LEU, etc.) */ int uns_cmp_op (op,mode) rtx op; enum machine_mode mode; { if (mode != GET_MODE (op)) return FALSE; return (classify_op (op, mode) & CLASS_UNS_CMP_OP) == CLASS_UNS_CMP_OP; } /* Return true if the code is a relational operation FP can use. */ int fcmp_op (op, mode) rtx op; enum machine_mode mode; { if (mode != GET_MODE (op)) return FALSE; return (classify_op (op, mode) & CLASS_FCMP_OP) != 0; } /* Return true if the operand is either the PC or a label_ref. */ int pc_or_label_operand (op, mode) rtx op; enum machine_mode mode; { if (op == pc_rtx) return TRUE; if (GET_CODE (op) == LABEL_REF) return TRUE; return FALSE; } /* Test for a valid operand for a call instruction. Don't allow the arg pointer register or virtual regs since they may change into reg + const, which the patterns can't handle yet. */ int call_insn_operand (op, mode) rtx op; enum machine_mode mode; { if (GET_CODE (op) == MEM && (CONSTANT_ADDRESS_P (XEXP (op, 0)) || (GET_CODE (XEXP (op, 0)) == REG && XEXP (op, 0) != arg_pointer_rtx && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) return 1; return 0; } /* Return an operand string if the given instruction's delay slot or wrap it in a .set noreorder section. This is for filling delay slots on load type instructions under GAS, which does no reordering on its own. For the MIPS assembler, all we do is update the filled delay slot statistics. We assume that operands[0] is the target register that is set. In order to check the next insn, most of this functionality is moved to FINAL_PRESCAN_INSN, and we just set the global variables that it needs. */ char * mips_fill_delay_slot (ret, type, operands, cur_insn) char *ret; /* normal string to return */ enum delay_type type; /* type of delay */ rtx operands[]; /* operands to use */ rtx cur_insn; /* current insn */ { register rtx set_reg; register enum machine_mode mode; register rtx next_insn = (cur_insn) ? NEXT_INSN (cur_insn) : (rtx)0; register int num_nops; if (type == DELAY_LOAD || type == DELAY_FCMP) num_nops = 1; else if (type == DELAY_HILO) num_nops = 2; else num_nops = 0; /* Make sure that we don't put nop's after labels. */ next_insn = NEXT_INSN (cur_insn); while (next_insn != (rtx)0 && GET_CODE (next_insn) == NOTE) next_insn = NEXT_INSN (next_insn); dslots_load_total += num_nops; if (TARGET_DEBUG_F_MODE || !optimize || type == DELAY_NONE || operands == (rtx *)0 || cur_insn == (rtx)0 || next_insn == (rtx)0 || GET_CODE (next_insn) == CODE_LABEL || (set_reg = operands[0]) == (rtx)0) { dslots_number_nops = 0; mips_load_reg = (rtx)0; mips_load_reg2 = (rtx)0; mips_load_reg3 = (rtx)0; mips_load_reg4 = (rtx)0; return ret; } set_reg = operands[0]; if (set_reg == (rtx)0) return ret; while (GET_CODE (set_reg) == SUBREG) set_reg = SUBREG_REG (set_reg); mode = GET_MODE (set_reg); dslots_number_nops = num_nops; mips_load_reg = set_reg; mips_load_reg2 = (mode == DImode || mode == DFmode) ? gen_rtx (REG, SImode, REGNO (set_reg) + 1) : (rtx)0; if (type == DELAY_HILO) { mips_load_reg3 = gen_rtx (REG, SImode, MD_REG_FIRST); mips_load_reg4 = gen_rtx (REG, SImode, MD_REG_FIRST+1); } else { mips_load_reg3 = 0; mips_load_reg4 = 0; } if (TARGET_GAS && set_noreorder++ == 0) fputs ("\t.set\tnoreorder\n", asm_out_file); return ret; } /* Determine whether a memory reference takes one (based off of the GP pointer), two (normal), or three (label + reg) instructions, and bump the appropriate counter for -mstats. */ void mips_count_memory_refs (op, num) rtx op; int num; { int additional = 0; int n_words = 0; rtx addr, plus0, plus1; enum rtx_code code0, code1; int looping; if (TARGET_DEBUG_B_MODE) { fprintf (stderr, "\n========== mips_count_memory_refs:\n"); debug_rtx (op); } /* Skip MEM if passed, otherwise handle movsi of address. */ addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0); /* Loop, going through the address RTL */ do { looping = FALSE; switch (GET_CODE (addr)) { default: break; case REG: case CONST_INT: break; case PLUS: plus0 = XEXP (addr, 0); plus1 = XEXP (addr, 1); code0 = GET_CODE (plus0); code1 = GET_CODE (plus1); if (code0 == REG) { additional++; addr = plus1; looping = TRUE; continue; } if (code0 == CONST_INT) { addr = plus1; looping = TRUE; continue; } if (code1 == REG) { additional++; addr = plus0; looping = TRUE; continue; } if (code1 == CONST_INT) { addr = plus0; looping = TRUE; continue; } if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST) { addr = plus0; looping = TRUE; continue; } if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST) { addr = plus1; looping = TRUE; continue; } break; case LABEL_REF: n_words = 2; /* always 2 words */ break; case CONST: addr = XEXP (addr, 0); looping = TRUE; continue; case SYMBOL_REF: n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2; break; } } while (looping); if (n_words == 0) return; n_words += additional; if (n_words > 3) n_words = 3; num_refs[n_words-1] += num; } /* Return the appropriate instructions to move one operand to another. */ char * mips_move_1word (operands, insn, unsignedp) rtx operands[]; rtx insn; int unsignedp; { char *ret = 0; rtx op0 = operands[0]; rtx op1 = operands[1]; enum rtx_code code0 = GET_CODE (op0); enum rtx_code code1 = GET_CODE (op1); enum machine_mode mode = GET_MODE (op0); int subreg_word0 = 0; int subreg_word1 = 0; enum delay_type delay = DELAY_NONE; while (code0 == SUBREG) { subreg_word0 += SUBREG_WORD (op0); op0 = SUBREG_REG (op0); code0 = GET_CODE (op0); } while (code1 == SUBREG) { subreg_word1 += SUBREG_WORD (op1); op1 = SUBREG_REG (op1); code1 = GET_CODE (op1); } if (code0 == REG) { int regno0 = REGNO (op0) + subreg_word0; if (code1 == REG) { int regno1 = REGNO (op1) + subreg_word1; /* Just in case, don't do anything for assigning a register to itself, unless we are filling a delay slot. */ if (regno0 == regno1 && set_nomacro == 0) ret = ""; else if (GP_REG_P (regno0)) { if (GP_REG_P (regno1)) ret = "move\t%0,%1"; else if (MD_REG_P (regno1)) { delay = DELAY_HILO; ret = "mf%1\t%0"; } else { delay = DELAY_LOAD; if (FP_REG_P (regno1)) ret = "mfc1\t%0,%1"; else if (regno1 == FPSW_REGNUM) ret = "cfc1\t%0,$31"; } } else if (FP_REG_P (regno0)) { if (GP_REG_P (regno1)) { delay = DELAY_LOAD; ret = "mtc1\t%1,%0"; } if (FP_REG_P (regno1)) ret = "mov.s\t%0,%1"; } else if (MD_REG_P (regno0)) { if (GP_REG_P (regno1)) { delay = DELAY_HILO; ret = "mt%0\t%1"; } } else if (regno0 == FPSW_REGNUM) { if (GP_REG_P (regno1)) { delay = DELAY_LOAD; ret = "ctc1\t%0,$31"; } } } else if (code1 == MEM) { delay = DELAY_LOAD; if (TARGET_STATS) mips_count_memory_refs (op1, 1); if (GP_REG_P (regno0)) { /* For loads, use the mode of the memory item, instead of the target, so zero/sign extend can use this code as well. */ switch (GET_MODE (op1)) { default: break; case SFmode: ret = "lw\t%0,%1"; break; case SImode: ret = "lw\t%0,%1"; break; case HImode: ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1"; break; case QImode: ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1"; break; } } else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode)) ret = "l.s\t%0,%1"; if (ret != (char *)0 && MEM_VOLATILE_P (op1)) { int i = strlen (ret); if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) abort (); sprintf (volatile_buffer, "%%{%s%%}", ret); ret = volatile_buffer; } } else if (code1 == CONST_INT) { if (INTVAL (op1) == 0) { if (GP_REG_P (regno0)) ret = "move\t%0,%z1"; else if (FP_REG_P (regno0)) { delay = DELAY_LOAD; ret = "mtc1\t%z1,%0"; } } else if (GP_REG_P (regno0)) ret = (INTVAL (op1) < 0) ? "li\t%0,%1\t\t\t# %X1" : "li\t%0,%X1\t\t# %1"; } else if (code1 == CONST_DOUBLE && mode == SFmode) { if (CONST_DOUBLE_HIGH (op1) == 0 && CONST_DOUBLE_LOW (op1) == 0) { if (GP_REG_P (regno0)) ret = "move\t%0,%."; else if (FP_REG_P (regno0)) { delay = DELAY_LOAD; ret = "mtc1\t%.,%0"; } } else { delay = DELAY_LOAD; ret = "li.s\t%0,%1"; } } else if (code1 == LABEL_REF) { if (TARGET_STATS) mips_count_memory_refs (op1, 1); ret = "la\t%0,%a1"; } else if (code1 == SYMBOL_REF || code1 == CONST) { if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1)) { rtx offset = const0_rtx; if (GET_CODE (op1) == CONST) op1 = eliminate_constant_term (XEXP (op1, 0), &offset); if (GET_CODE (op1) == SYMBOL_REF) { operands[2] = HALF_PIC_PTR (op1); if (TARGET_STATS) mips_count_memory_refs (operands[2], 1); if (INTVAL (offset) == 0) { delay = DELAY_LOAD; ret = "lw\t%0,%2"; } else { dslots_load_total++; operands[3] = offset; ret = (SMALL_INT (offset)) ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3" : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]"; } } } else { if (TARGET_STATS) mips_count_memory_refs (op1, 1); ret = "la\t%0,%a1"; } } else if (code1 == PLUS) { rtx add_op0 = XEXP (op1, 0); rtx add_op1 = XEXP (op1, 1); if (GET_CODE (XEXP (op1, 1)) == REG && GET_CODE (XEXP (op1, 0)) == CONST_INT) { add_op0 = XEXP (op1, 1); /* reverse operands */ add_op1 = XEXP (op1, 0); } operands[2] = add_op0; operands[3] = add_op1; ret = "add%:\t%0,%2,%3"; } } else if (code0 == MEM) { if (TARGET_STATS) mips_count_memory_refs (op0, 1); if (code1 == REG) { int regno1 = REGNO (op1) + subreg_word1; if (GP_REG_P (regno1)) { switch (mode) { default: break; case SFmode: ret = "sw\t%1,%0"; break; case SImode: ret = "sw\t%1,%0"; break; case HImode: ret = "sh\t%1,%0"; break; case QImode: ret = "sb\t%1,%0"; break; } } else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode)) ret = "s.s\t%1,%0"; } else if (code1 == CONST_INT && INTVAL (op1) == 0) { switch (mode) { default: break; case SFmode: ret = "sw\t%z1,%0"; break; case SImode: ret = "sw\t%z1,%0"; break; case HImode: ret = "sh\t%z1,%0"; break; case QImode: ret = "sb\t%z1,%0"; break; } } else if (code1 == CONST_DOUBLE && CONST_DOUBLE_HIGH (op1) == 0 && CONST_DOUBLE_LOW (op1) == 0) { switch (mode) { default: break; case SFmode: ret = "sw\t%.,%0"; break; case SImode: ret = "sw\t%.,%0"; break; case HImode: ret = "sh\t%.,%0"; break; case QImode: ret = "sb\t%.,%0"; break; } } if (ret != (char *)0 && MEM_VOLATILE_P (op0)) { int i = strlen (ret); if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) abort (); sprintf (volatile_buffer, "%%{%s%%}", ret); ret = volatile_buffer; } } if (ret == (char *)0) { abort_with_insn (insn, "Bad move"); return 0; } if (delay != DELAY_NONE) return mips_fill_delay_slot (ret, delay, operands, insn); return ret; } /* Return the appropriate instructions to move 2 words */ char * mips_move_2words (operands, insn) rtx operands[]; rtx insn; { char *ret = 0; rtx op0 = operands[0]; rtx op1 = operands[1]; enum rtx_code code0 = GET_CODE (operands[0]); enum rtx_code code1 = GET_CODE (operands[1]); int subreg_word0 = 0; int subreg_word1 = 0; enum delay_type delay = DELAY_NONE; while (code0 == SUBREG) { subreg_word0 += SUBREG_WORD (op0); op0 = SUBREG_REG (op0); code0 = GET_CODE (op0); } while (code1 == SUBREG) { subreg_word1 += SUBREG_WORD (op1); op1 = SUBREG_REG (op1); code1 = GET_CODE (op1); } if (code0 == REG) { int regno0 = REGNO (op0) + subreg_word0; if (code1 == REG) { int regno1 = REGNO (op1) + subreg_word1; /* Just in case, don't do anything for assigning a register to itself, unless we are filling a delay slot. */ if (regno0 == regno1 && set_nomacro == 0) ret = ""; else if (FP_REG_P (regno0)) { if (FP_REG_P (regno1)) ret = "mov.d\t%0,%1"; else { delay = DELAY_LOAD; ret = (TARGET_FLOAT64) ? "dmtc1\t%1,%0" : "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0"; } } else if (FP_REG_P (regno1)) { delay = DELAY_LOAD; ret = (TARGET_FLOAT64) ? "dmfc1\t%0,%1" : "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1"; } else if (MD_REG_P (regno0) && GP_REG_P (regno1)) { delay = DELAY_HILO; ret = "mthi\t%M1\n\tmtlo\t%L1"; } else if (GP_REG_P (regno0) && MD_REG_P (regno1)) { delay = DELAY_HILO; ret = "mfhi\t%M0\n\tmflo\t%L0"; } else if (regno0 != (regno1+1)) ret = "move\t%0,%1\n\tmove\t%D0,%D1"; else ret = "move\t%D0,%D1\n\tmove\t%0,%1"; } else if (code1 == CONST_DOUBLE) { if (CONST_DOUBLE_HIGH (op1) != 0 || CONST_DOUBLE_LOW (op1) != 0) { if (GET_MODE (op1) == DFmode) { delay = DELAY_LOAD; ret = "li.d\t%0,%1"; } else { operands[2] = GEN_INT (CONST_DOUBLE_LOW (op1)); operands[3] = GEN_INT (CONST_DOUBLE_HIGH (op1)); ret = "li\t%M0,%3\n\tli\t%L0,%2"; } } else { if (GP_REG_P (regno0)) ret = "move\t%0,%.\n\tmove\t%D0,%."; else if (FP_REG_P (regno0)) { delay = DELAY_LOAD; ret = (TARGET_FLOAT64) ? "dmtc1\t%.,%0" : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"; } } } else if (code1 == CONST_INT && INTVAL (op1) == 0) { if (GP_REG_P (regno0)) ret = "move\t%0,%.\n\tmove\t%D0,%."; else if (FP_REG_P (regno0)) { delay = DELAY_LOAD; ret = (TARGET_FLOAT64) ? "dmtc1\t%.,%0" : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"; } } else if (code1 == CONST_INT && GET_MODE (op0) == DImode && GP_REG_P (regno0)) { operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1); ret = "li\t%M0,%2\n\tli\t%L0,%1"; } else if (code1 == MEM) { delay = DELAY_LOAD; if (TARGET_STATS) mips_count_memory_refs (op1, 2); if (FP_REG_P (regno0)) ret = "l.d\t%0,%1"; else if (offsettable_address_p (1, DFmode, XEXP (op1, 0))) { operands[2] = adj_offsettable_operand (op1, 4); if (reg_mentioned_p (op0, op1)) ret = "lw\t%D0,%2\n\tlw\t%0,%1"; else ret = "lw\t%0,%1\n\tlw\t%D0,%2"; } if (ret != (char *)0 && MEM_VOLATILE_P (op1)) { int i = strlen (ret); if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) abort (); sprintf (volatile_buffer, "%%{%s%%}", ret); ret = volatile_buffer; } } } else if (code0 == MEM) { if (code1 == REG) { int regno1 = REGNO (op1) + subreg_word1; if (FP_REG_P (regno1)) ret = "s.d\t%1,%0"; else if (offsettable_address_p (1, DFmode, XEXP (op0, 0))) { operands[2] = adj_offsettable_operand (op0, 4); ret = "sw\t%1,%0\n\tsw\t%D1,%2"; } } else if (code1 == CONST_DOUBLE && CONST_DOUBLE_HIGH (op1) == 0 && CONST_DOUBLE_LOW (op1) == 0 && offsettable_address_p (1, DFmode, XEXP (op0, 0))) { if (TARGET_FLOAT64) ret = "sd\t%.,%0"; else { operands[2] = adj_offsettable_operand (op0, 4); ret = "sw\t%.,%0\n\tsw\t%.,%2"; } } if (TARGET_STATS) mips_count_memory_refs (op0, 2); if (ret != (char *)0 && MEM_VOLATILE_P (op0)) { int i = strlen (ret); if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) abort (); sprintf (volatile_buffer, "%%{%s%%}", ret); ret = volatile_buffer; } } if (ret == (char *)0) { abort_with_insn (insn, "Bad move"); return 0; } if (delay != DELAY_NONE) return mips_fill_delay_slot (ret, delay, operands, insn); return ret; } /* Provide the costs of an addressing mode that contains ADDR. If ADDR is not a valid address, its cost is irrelevant. */ int mips_address_cost (addr) rtx addr; { switch (GET_CODE (addr)) { default: break; case LO_SUM: case HIGH: return 1; case LABEL_REF: return 2; case CONST: { rtx offset = const0_rtx; addr = eliminate_constant_term (addr, &offset); if (GET_CODE (addr) == LABEL_REF) return 2; if (GET_CODE (addr) != SYMBOL_REF) return 4; if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) return 2; } /* fall through */ case SYMBOL_REF: return SYMBOL_REF_FLAG (addr) ? 1 : 2; case PLUS: { register rtx plus0 = XEXP (addr, 0); register rtx plus1 = XEXP (addr, 1); if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) { plus0 = XEXP (addr, 1); plus1 = XEXP (addr, 0); } if (GET_CODE (plus0) != REG) break; switch (GET_CODE (plus1)) { default: break; case CONST_INT: { int value = INTVAL (plus1); return (value < -32768 || value > 32767) ? 2 : 1; } case CONST: case SYMBOL_REF: case LABEL_REF: case HIGH: case LO_SUM: return mips_address_cost (plus1) + 1; } } } return 4; } /* Make normal rtx_code into something we can index from an array */ static enum internal_test map_test_to_internal_test (test_code) enum rtx_code test_code; { enum internal_test test = ITEST_MAX; switch (test_code) { default: break; case EQ: test = ITEST_EQ; break; case NE: test = ITEST_NE; break; case GT: test = ITEST_GT; break; case GE: test = ITEST_GE; break; case LT: test = ITEST_LT; break; case LE: test = ITEST_LE; break; case GTU: test = ITEST_GTU; break; case GEU: test = ITEST_GEU; break; case LTU: test = ITEST_LTU; break; case LEU: test = ITEST_LEU; break; } return test; } /* Generate the code to compare two integer values. The return value is: (reg:SI xx) The pseudo register the comparison is in (rtx)0 No register, generate a simple branch. */ rtx gen_int_relational (test_code, result, cmp0, cmp1, p_invert) enum rtx_code test_code; /* relational test (EQ, etc) */ rtx result; /* result to store comp. or 0 if branch */ rtx cmp0; /* first operand to compare */ rtx cmp1; /* second operand to compare */ int *p_invert; /* NULL or ptr to hold whether branch needs */ /* to reverse its test */ { struct cmp_info { enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */ int const_low; /* low bound of constant we can accept */ int const_high; /* high bound of constant we can accept */ int const_add; /* constant to add (convert LE -> LT) */ int reverse_regs; /* reverse registers in test */ int invert_const; /* != 0 if invert value if cmp1 is constant */ int invert_reg; /* != 0 if invert value if cmp1 is register */ int unsignedp; /* != 0 for unsigned comparisons. */ }; static struct cmp_info info[ (int)ITEST_MAX ] = { { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */ { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */ { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */ { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */ { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */ { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */ { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */ { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */ { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */ { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */ }; enum internal_test test; struct cmp_info *p_info; int branch_p; int eqne_p; int invert; rtx reg; rtx reg2; test = map_test_to_internal_test (test_code); if (test == ITEST_MAX) abort (); p_info = &info[ (int)test ]; eqne_p = (p_info->test_code == XOR); /* Eliminate simple branches */ branch_p = (result == (rtx)0); if (branch_p) { if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG) { /* Comparisons against zero are simple branches */ if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0) return (rtx)0; /* Test for beq/bne. */ if (eqne_p) return (rtx)0; } /* allocate a pseudo to calculate the value in. */ result = gen_reg_rtx (SImode); } /* Make sure we can handle any constants given to us. */ if (GET_CODE (cmp0) == CONST_INT) cmp0 = force_reg (SImode, cmp0); if (GET_CODE (cmp1) == CONST_INT) { HOST_WIDE_INT value = INTVAL (cmp1); if (value < p_info->const_low || value > p_info->const_high) cmp1 = force_reg (SImode, cmp1); } /* See if we need to invert the result. */ invert = (GET_CODE (cmp1) == CONST_INT) ? p_info->invert_const : p_info->invert_reg; if (p_invert != (int *)0) { *p_invert = invert; invert = FALSE; } /* Comparison to constants, may involve adding 1 to change a LT into LE. Comparison between two registers, may involve switching operands. */ if (GET_CODE (cmp1) == CONST_INT) { if (p_info->const_add != 0) { HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add; /* If modification of cmp1 caused overflow, we would get the wrong answer if we follow the usual path; thus, x > 0xffffffffu would turn into x > 0u. */ if ((p_info->unsignedp ? (unsigned HOST_WIDE_INT) new > INTVAL (cmp1) : new > INTVAL (cmp1)) != (p_info->const_add > 0)) { /* This test is always true, but if INVERT is true then the result of the test needs to be inverted so 0 should be returned instead. */ emit_move_insn (result, invert ? const0_rtx : const_true_rtx); return result; } else cmp1 = GEN_INT (new); } } else if (p_info->reverse_regs) { rtx temp = cmp0; cmp0 = cmp1; cmp1 = temp; } if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0) reg = cmp0; else { reg = (invert || eqne_p) ? gen_reg_rtx (SImode) : result; emit_move_insn (reg, gen_rtx (p_info->test_code, SImode, cmp0, cmp1)); } if (test == ITEST_NE) { emit_move_insn (result, gen_rtx (GTU, SImode, reg, const0_rtx)); invert = FALSE; } else if (test == ITEST_EQ) { reg2 = (invert) ? gen_reg_rtx (SImode) : result; emit_move_insn (reg2, gen_rtx (LTU, SImode, reg, const1_rtx)); reg = reg2; } if (invert) emit_move_insn (result, gen_rtx (XOR, SImode, reg, const1_rtx)); return result; } /* Emit the common code for doing conditional branches. operand[0] is the label to jump to. The comparison operands are saved away by cmp{si,sf,df}. */ void gen_conditional_branch (operands, test_code) rtx operands[]; enum rtx_code test_code; { static enum machine_mode mode_map[(int)CMP_MAX][(int)ITEST_MAX] = { { /* CMP_SI */ SImode, /* eq */ SImode, /* ne */ SImode, /* gt */ SImode, /* ge */ SImode, /* lt */ SImode, /* le */ SImode, /* gtu */ SImode, /* geu */ SImode, /* ltu */ SImode, /* leu */ }, { /* CMP_SF */ CC_FPmode, /* eq */ CC_REV_FPmode, /* ne */ CC_FPmode, /* gt */ CC_FPmode, /* ge */ CC_FPmode, /* lt */ CC_FPmode, /* le */ VOIDmode, /* gtu */ VOIDmode, /* geu */ VOIDmode, /* ltu */ VOIDmode, /* leu */ }, { /* CMP_DF */ CC_FPmode, /* eq */ CC_REV_FPmode, /* ne */ CC_FPmode, /* gt */ CC_FPmode, /* ge */ CC_FPmode, /* lt */ CC_FPmode, /* le */ VOIDmode, /* gtu */ VOIDmode, /* geu */ VOIDmode, /* ltu */ VOIDmode, /* leu */ }, }; enum machine_mode mode; enum cmp_type type = branch_type; rtx cmp0 = branch_cmp[0]; rtx cmp1 = branch_cmp[1]; rtx label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]); rtx label2 = pc_rtx; rtx reg = (rtx)0; int invert = 0; enum internal_test test = map_test_to_internal_test (test_code); if (test == ITEST_MAX) { mode = SImode; goto fail; } /* Get the machine mode to use (CCmode, CC_EQmode, CC_FPmode, or CC_REV_FPmode). */ mode = mode_map[(int)type][(int)test]; if (mode == VOIDmode) goto fail; switch (branch_type) { default: goto fail; case CMP_SI: reg = gen_int_relational (test_code, (rtx)0, cmp0, cmp1, &invert); if (reg != (rtx)0) { cmp0 = reg; cmp1 = const0_rtx; test_code = NE; } /* Make sure not non-zero constant if ==/!= */ else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0) cmp1 = force_reg (SImode, cmp1); break; case CMP_DF: case CMP_SF: { rtx reg = gen_rtx (REG, mode, FPSW_REGNUM); emit_insn (gen_rtx (SET, VOIDmode, reg, gen_rtx (test_code, mode, cmp0, cmp1))); cmp0 = reg; cmp1 = const0_rtx; test_code = NE; } break; } /* Generate the jump */ if (invert) { label2 = label1; label1 = pc_rtx; } emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (test_code, mode, cmp0, cmp1), label1, label2))); return; fail: abort_with_insn (gen_rtx (test_code, mode, cmp0, cmp1), "bad test"); } #define UNITS_PER_SHORT (SHORT_TYPE_SIZE / BITS_PER_UNIT) /* Internal code to generate the load and store of one word/short/byte. The load is emitted directly, and the store insn is returned. */ #if 0 static rtx block_move_load_store (dest_reg, src_reg, p_bytes, p_offset, align, orig_src) rtx src_reg; /* register holding source memory address */ rtx dest_reg; /* register holding dest. memory address */ int *p_bytes; /* pointer to # bytes remaining */ int *p_offset; /* pointer to current offset */ int align; /* alignment */ rtx orig_src; /* original source for making a reg note */ { int bytes; /* # bytes remaining */ int offset; /* offset to use */ int size; /* size in bytes of load/store */ enum machine_mode mode; /* mode to use for load/store */ rtx reg; /* temporary register */ rtx src_addr; /* source address */ rtx dest_addr; /* destination address */ rtx insn; /* insn of the load */ rtx orig_src_addr; /* original source address */ rtx (*load_func)(); /* function to generate load insn */ rtx (*store_func)(); /* function to generate destination insn */ bytes = *p_bytes; if (bytes <= 0 || align <= 0) abort (); if (bytes >= UNITS_PER_WORD && align >= UNITS_PER_WORD) { mode = SImode; size = UNITS_PER_WORD; load_func = gen_movsi; store_func = gen_movsi; } #if 0 /* Don't generate unaligned moves here, rather defer those to the general movestrsi_internal pattern. */ else if (bytes >= UNITS_PER_WORD) { mode = SImode; size = UNITS_PER_WORD; load_func = gen_movsi_ulw; store_func = gen_movsi_usw; } #endif else if (bytes >= UNITS_PER_SHORT && align >= UNITS_PER_SHORT) { mode = HImode; size = UNITS_PER_SHORT; load_func = gen_movhi; store_func = gen_movhi; } else { mode = QImode; size = 1; load_func = gen_movqi; store_func = gen_movqi; } offset = *p_offset; *p_offset = offset + size; *p_bytes = bytes - size; if (offset == 0) { src_addr = src_reg; dest_addr = dest_reg; } else { src_addr = gen_rtx (PLUS, Pmode, src_reg, GEN_INT (offset)); dest_addr = gen_rtx (PLUS, Pmode, dest_reg, GEN_INT (offset)); } reg = gen_reg_rtx (mode); insn = emit_insn ((*load_func) (reg, gen_rtx (MEM, mode, src_addr))); orig_src_addr = XEXP (orig_src, 0); if (CONSTANT_P (orig_src_addr)) REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUIV, plus_constant (orig_src_addr, offset), REG_NOTES (insn)); return (*store_func) (gen_rtx (MEM, mode, dest_addr), reg); } #endif /* Write a series of loads/stores to move some bytes. Generate load/stores as follows: load 1 load 2 load 3 store 1 load 4 store 2 load 5 store 3 ... This way, no NOP's are needed, except at the end, and only two temp registers are needed. Two delay slots are used in deference to the R4000. */ #if 0 static void block_move_sequence (dest_reg, src_reg, bytes, align, orig_src) rtx dest_reg; /* register holding destination address */ rtx src_reg; /* register holding source address */ int bytes; /* # bytes to move */ int align; /* max alignment to assume */ rtx orig_src; /* original source for making a reg note */ { int offset = 0; rtx prev2_store = (rtx)0; rtx prev_store = (rtx)0; rtx cur_store = (rtx)0; while (bytes > 0) { /* Is there a store to do? */ if (prev2_store) emit_insn (prev2_store); prev2_store = prev_store; prev_store = cur_store; cur_store = block_move_load_store (dest_reg, src_reg, &bytes, &offset, align, orig_src); } /* Finish up last three stores. */ if (prev2_store) emit_insn (prev2_store); if (prev_store) emit_insn (prev_store); if (cur_store) emit_insn (cur_store); } #endif /* Write a loop to move a constant number of bytes. Generate load/stores as follows: do { temp1 = src[0]; temp2 = src[1]; ... temp = src[MAX_MOVE_REGS-1]; dest[0] = temp1; dest[1] = temp2; ... dest[MAX_MOVE_REGS-1] = temp; src += MAX_MOVE_REGS; dest += MAX_MOVE_REGS; } while (src != final); This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp registers are needed. Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */ #define MAX_MOVE_REGS 4 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD) static void block_move_loop (dest_reg, src_reg, bytes, align, orig_src) rtx dest_reg; /* register holding destination address */ rtx src_reg; /* register holding source address */ int bytes; /* # bytes to move */ int align; /* alignment */ rtx orig_src; /* original source for making a reg note */ { rtx dest_mem = gen_rtx (MEM, BLKmode, dest_reg); rtx src_mem = gen_rtx (MEM, BLKmode, src_reg); rtx align_rtx = GEN_INT (align); rtx label; rtx final_src; rtx bytes_rtx; int leftover; if (bytes < 2*MAX_MOVE_BYTES) abort (); leftover = bytes % MAX_MOVE_BYTES; bytes -= leftover; label = gen_label_rtx (); final_src = gen_reg_rtx (Pmode); bytes_rtx = GEN_INT (bytes); if (bytes > 0x7fff) { emit_insn (gen_movsi (final_src, bytes_rtx)); emit_insn (gen_addsi3 (final_src, final_src, src_reg)); } else emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx)); emit_label (label); bytes_rtx = GEN_INT (MAX_MOVE_BYTES); emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx)); emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx)); emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx)); emit_insn (gen_cmpsi (src_reg, final_src)); emit_jump_insn (gen_bne (label)); if (leftover) emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover), align_rtx)); } /* Use a library function to move some bytes. */ static void block_move_call (dest_reg, src_reg, bytes_rtx) rtx dest_reg; rtx src_reg; rtx bytes_rtx; { #ifdef TARGET_MEM_FUNCTIONS emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0, VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode, bytes_rtx, SImode); #else emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0, VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode, bytes_rtx, SImode); #endif } /* Expand string/block move operations. operands[0] is the pointer to the destination. operands[1] is the pointer to the source. operands[2] is the number of bytes to move. operands[3] is the alignment. */ void expand_block_move (operands) rtx operands[]; { rtx bytes_rtx = operands[2]; rtx align_rtx = operands[3]; int constp = (GET_CODE (bytes_rtx) == CONST_INT); int bytes = (constp ? INTVAL (bytes_rtx) : 0); int align = INTVAL (align_rtx); rtx orig_src = operands[1]; rtx src_reg; rtx dest_reg; if (constp && bytes <= 0) return; if (align > UNITS_PER_WORD) align = UNITS_PER_WORD; /* Move the address into scratch registers. */ dest_reg = copy_addr_to_reg (XEXP (operands[0], 0)); src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); if (TARGET_MEMCPY) block_move_call (dest_reg, src_reg, bytes_rtx); #if 0 else if (constp && bytes <= 3*align) block_move_sequence (dest_reg, src_reg, bytes, align, orig_src); #endif else if (constp && bytes <= 2*MAX_MOVE_BYTES) emit_insn (gen_movstrsi_internal (gen_rtx (MEM, BLKmode, dest_reg), gen_rtx (MEM, BLKmode, src_reg), bytes_rtx, align_rtx)); else if (constp && align >= UNITS_PER_WORD && optimize) block_move_loop (dest_reg, src_reg, bytes, align, orig_src); else if (constp && optimize) { /* If the alignment is not word aligned, generate a test at runtime, to see whether things wound up aligned, and we can use the faster lw/sw instead ulw/usw. */ rtx temp = gen_reg_rtx (Pmode); rtx aligned_label = gen_label_rtx (); rtx join_label = gen_label_rtx (); int leftover = bytes % MAX_MOVE_BYTES; bytes -= leftover; emit_insn (gen_iorsi3 (temp, src_reg, dest_reg)); emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD-1))); emit_insn (gen_cmpsi (temp, const0_rtx)); emit_jump_insn (gen_beq (aligned_label)); /* Unaligned loop. */ block_move_loop (dest_reg, src_reg, bytes, 1, orig_src); emit_jump_insn (gen_jump (join_label)); emit_barrier (); /* Aligned loop. */ emit_label (aligned_label); block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_src); emit_label (join_label); /* Bytes at the end of the loop. */ if (leftover) { #if 0 if (leftover <= 3*align) block_move_sequence (dest_reg, src_reg, leftover, align, orig_src); else #endif emit_insn (gen_movstrsi_internal (gen_rtx (MEM, BLKmode, dest_reg), gen_rtx (MEM, BLKmode, src_reg), GEN_INT (leftover), GEN_INT (align))); } } else block_move_call (dest_reg, src_reg, bytes_rtx); } /* Emit load/stores for a small constant block_move. operands[0] is the memory address of the destination. operands[1] is the memory address of the source. operands[2] is the number of bytes to move. operands[3] is the alignment. operands[4] is a temp register. operands[5] is a temp register. ... operands[3+num_regs] is the last temp register. The block move type can be one of the following: BLOCK_MOVE_NORMAL Do all of the block move. BLOCK_MOVE_NOT_LAST Do all but the last store. BLOCK_MOVE_LAST Do just the last store. */ char * output_block_move (insn, operands, num_regs, move_type) rtx insn; rtx operands[]; int num_regs; enum block_move_type move_type; { rtx dest_reg = XEXP (operands[0], 0); rtx src_reg = XEXP (operands[1], 0); int bytes = INTVAL (operands[2]); int align = INTVAL (operands[3]); int num = 0; int offset = 0; int use_lwl_lwr = FALSE; int last_operand = num_regs+4; int safe_regs = 4; int i; rtx xoperands[10]; struct { char *load; /* load insn without nop */ char *load_nop; /* load insn with trailing nop */ char *store; /* store insn */ char *final; /* if last_store used: NULL or swr */ char *last_store; /* last store instruction */ int offset; /* current offset */ enum machine_mode mode; /* mode to use on (MEM) */ } load_store[4]; /* Detect a bug in GCC, where it can give us a register the same as one of the addressing registers and reduce the number of registers available. */ for (i = 4; i < last_operand && safe_regs < (sizeof(xoperands) / sizeof(xoperands[0])); i++) { if (!reg_mentioned_p (operands[i], operands[0]) && !reg_mentioned_p (operands[i], operands[1])) xoperands[safe_regs++] = operands[i]; } if (safe_regs < last_operand) { xoperands[0] = operands[0]; xoperands[1] = operands[1]; xoperands[2] = operands[2]; xoperands[3] = operands[3]; return output_block_move (insn, xoperands, safe_regs-4, move_type); } /* If we are given global or static addresses, and we would be emitting a few instructions, try to save time by using a temporary register for the pointer. */ if (num_regs > 2 && (bytes > 2*align || move_type != BLOCK_MOVE_NORMAL)) { if (CONSTANT_P (src_reg)) { if (TARGET_STATS) mips_count_memory_refs (operands[1], 1); src_reg = operands[ 3 + num_regs-- ]; if (move_type != BLOCK_MOVE_LAST) { xoperands[1] = operands[1]; xoperands[0] = src_reg; output_asm_insn ("la\t%0,%1", xoperands); } } if (CONSTANT_P (dest_reg)) { if (TARGET_STATS) mips_count_memory_refs (operands[0], 1); dest_reg = operands[ 3 + num_regs-- ]; if (move_type != BLOCK_MOVE_LAST) { xoperands[1] = operands[0]; xoperands[0] = dest_reg; output_asm_insn ("la\t%0,%1", xoperands); } } } if (num_regs > (sizeof (load_store) / sizeof (load_store[0]))) num_regs = (sizeof (load_store) / sizeof (load_store[0])); else if (num_regs < 1) abort_with_insn (insn, "Cannot do block move, not enough scratch registers"); if (TARGET_GAS && move_type != BLOCK_MOVE_LAST && set_noreorder++ == 0) output_asm_insn (".set\tnoreorder", operands); while (bytes > 0) { load_store[num].offset = offset; if (bytes >= UNITS_PER_WORD && align >= UNITS_PER_WORD) { load_store[num].load = "lw\t%0,%1"; load_store[num].load_nop = "lw\t%0,%1%#"; load_store[num].store = "sw\t%0,%1"; load_store[num].last_store = "sw\t%0,%1"; load_store[num].final = (char *)0; load_store[num].mode = SImode; offset += UNITS_PER_WORD; bytes -= UNITS_PER_WORD; } else if (bytes >= UNITS_PER_WORD) { #if BYTES_BIG_ENDIAN load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2"; load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#"; load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2"; load_store[num].last_store = "swr\t%0,%2"; load_store[num].final = "swl\t%0,%1"; #else load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1"; load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#"; load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1"; load_store[num].last_store = "swr\t%0,%1"; load_store[num].final = "swl\t%0,%2"; #endif load_store[num].mode = SImode; offset += UNITS_PER_WORD; bytes -= UNITS_PER_WORD; use_lwl_lwr = TRUE; } else if (bytes >= UNITS_PER_SHORT && align >= UNITS_PER_SHORT) { load_store[num].load = "lh\t%0,%1"; load_store[num].load_nop = "lh\t%0,%1%#"; load_store[num].store = "sh\t%0,%1"; load_store[num].last_store = "sh\t%0,%1"; load_store[num].final = (char *)0; load_store[num].offset = offset; load_store[num].mode = HImode; offset += UNITS_PER_SHORT; bytes -= UNITS_PER_SHORT; } else { load_store[num].load = "lb\t%0,%1"; load_store[num].load_nop = "lb\t%0,%1%#"; load_store[num].store = "sb\t%0,%1"; load_store[num].last_store = "sb\t%0,%1"; load_store[num].final = (char *)0; load_store[num].mode = QImode; offset++; bytes--; } if (TARGET_STATS && move_type != BLOCK_MOVE_LAST) { dslots_load_total++; dslots_load_filled++; if (CONSTANT_P (src_reg)) mips_count_memory_refs (src_reg, 1); if (CONSTANT_P (dest_reg)) mips_count_memory_refs (dest_reg, 1); } /* Emit load/stores now if we have run out of registers or are at the end of the move. */ if (++num == num_regs || bytes == 0) { /* If only load/store, we need a NOP after the load. */ if (num == 1) { load_store[0].load = load_store[0].load_nop; if (TARGET_STATS && move_type != BLOCK_MOVE_LAST) dslots_load_filled--; } if (move_type != BLOCK_MOVE_LAST) { for (i = 0; i < num; i++) { int offset; if (!operands[i+4]) abort (); if (GET_MODE (operands[i+4]) != load_store[i].mode) operands[i+4] = gen_rtx (REG, load_store[i].mode, REGNO (operands[i+4])); offset = load_store[i].offset; xoperands[0] = operands[i+4]; xoperands[1] = gen_rtx (MEM, load_store[i].mode, plus_constant (src_reg, offset)); if (use_lwl_lwr) xoperands[2] = gen_rtx (MEM, load_store[i].mode, plus_constant (src_reg, UNITS_PER_WORD-1+offset)); output_asm_insn (load_store[i].load, xoperands); } } for (i = 0; i < num; i++) { int last_p = (i == num-1 && bytes == 0); int offset = load_store[i].offset; xoperands[0] = operands[i+4]; xoperands[1] = gen_rtx (MEM, load_store[i].mode, plus_constant (dest_reg, offset)); if (use_lwl_lwr) xoperands[2] = gen_rtx (MEM, load_store[i].mode, plus_constant (dest_reg, UNITS_PER_WORD-1+offset)); if (move_type == BLOCK_MOVE_NORMAL) output_asm_insn (load_store[i].store, xoperands); else if (move_type == BLOCK_MOVE_NOT_LAST) { if (!last_p) output_asm_insn (load_store[i].store, xoperands); else if (load_store[i].final != (char *)0) output_asm_insn (load_store[i].final, xoperands); } else if (last_p) output_asm_insn (load_store[i].last_store, xoperands); } num = 0; /* reset load_store */ use_lwl_lwr = FALSE; /* reset whether or not we used lwl/lwr */ } } if (TARGET_GAS && move_type != BLOCK_MOVE_LAST && --set_noreorder == 0) output_asm_insn (".set\treorder", operands); return ""; } /* Argument support functions. */ /* Initialize CUMULATIVE_ARGS for a function. */ void init_cumulative_args (cum, fntype, libname) CUMULATIVE_ARGS *cum; /* argument info to initialize */ tree fntype; /* tree ptr for function decl */ rtx libname; /* SYMBOL_REF of library name or 0 */ { static CUMULATIVE_ARGS zero_cum; tree param, next_param; if (TARGET_DEBUG_E_MODE) { fprintf (stderr, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype); if (!fntype) fputc ('\n', stderr); else { tree ret_type = TREE_TYPE (fntype); fprintf (stderr, ", fntype code = %s, ret code = %s\n", tree_code_name[ (int)TREE_CODE (fntype) ], tree_code_name[ (int)TREE_CODE (ret_type) ]); } } *cum = zero_cum; /* Determine if this function has variable arguments. This is indicated by the last argument being 'void_type_mode' if there are no variable arguments. The standard MIPS calling sequence passes all arguments in the general purpose registers in this case. */ for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0; param != (tree)0; param = next_param) { next_param = TREE_CHAIN (param); if (next_param == (tree)0 && TREE_VALUE (param) != void_type_node) cum->gp_reg_found = 1; } } /* Advance the argument to the next argument position. */ void function_arg_advance (cum, mode, type, named) CUMULATIVE_ARGS *cum; /* current arg information */ enum machine_mode mode; /* current arg mode */ tree type; /* type of the argument or 0 if lib support */ int named; /* whether or not the argument was named */ { if (TARGET_DEBUG_E_MODE) fprintf (stderr, "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n", cum->gp_reg_found, cum->arg_number, cum->arg_words, GET_MODE_NAME (mode), type, named); cum->arg_number++; switch (mode) { case VOIDmode: break; default: if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) abort (); cum->gp_reg_found = 1; cum->arg_words += (GET_MODE_SIZE (mode) + 3) / 4; break; case BLKmode: cum->gp_reg_found = 1; cum->arg_words += (int_size_in_bytes (type) + 3) / 4; break; case SFmode: cum->arg_words++; break; case DFmode: cum->arg_words += 2; break; case DImode: cum->gp_reg_found = 1; cum->arg_words += 2; break; case QImode: case HImode: case SImode: cum->gp_reg_found = 1; cum->arg_words++; break; } } /* Return a RTL expression containing the register for the given mode, or 0 if the argument is too be passed on the stack. */ struct rtx_def * function_arg (cum, mode, type, named) CUMULATIVE_ARGS *cum; /* current arg information */ enum machine_mode mode; /* current arg mode */ tree type; /* type of the argument or 0 if lib support */ int named; /* != 0 for normal args, == 0 for ... args */ { rtx ret; int regbase = -1; int bias = 0; int struct_p = ((type != (tree)0) && (TREE_CODE (type) == RECORD_TYPE || TREE_CODE (type) == UNION_TYPE)); if (TARGET_DEBUG_E_MODE) fprintf (stderr, "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ", cum->gp_reg_found, cum->arg_number, cum->arg_words, GET_MODE_NAME (mode), type, named); switch (mode) { case SFmode: if (cum->gp_reg_found || cum->arg_number >= 2) regbase = GP_ARG_FIRST; else { regbase = (TARGET_SOFT_FLOAT) ? GP_ARG_FIRST : FP_ARG_FIRST; if (cum->arg_words == 1) /* first arg was float */ bias = 1; /* use correct reg */ } break; case DFmode: cum->arg_words += (cum->arg_words & 1); regbase = (cum->gp_reg_found || TARGET_SOFT_FLOAT || cum->arg_number >= 2 ? GP_ARG_FIRST : FP_ARG_FIRST); break; default: if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) abort (); /* Drops through. */ case BLKmode: if (type != (tree)0 && TYPE_ALIGN (type) > BITS_PER_WORD) cum->arg_words += (cum->arg_words & 1); regbase = GP_ARG_FIRST; break; case VOIDmode: case QImode: case HImode: case SImode: regbase = GP_ARG_FIRST; break; case DImode: cum->arg_words += (cum->arg_words & 1); regbase = GP_ARG_FIRST; } if (cum->arg_words >= MAX_ARGS_IN_REGISTERS) { if (TARGET_DEBUG_E_MODE) fprintf (stderr, "%s\n", struct_p ? ", [struct]" : ""); ret = (rtx)0; } else { if (regbase == -1) abort (); ret = gen_rtx (REG, mode, regbase + cum->arg_words + bias); if (TARGET_DEBUG_E_MODE) fprintf (stderr, "%s%s\n", reg_names[regbase + cum->arg_words + bias], struct_p ? ", [struct]" : ""); /* The following is a hack in order to pass 1 byte structures the same way that the MIPS compiler does (namely by passing the structure in the high byte or half word of the register). This also makes varargs work. If we have such a structure, we save the adjustment RTL, and the call define expands will emit them. For the VOIDmode argument (argument after the last real argument, pass back a parallel vector holding each of the adjustments. */ /* ??? function_arg can be called more than once for each argument. As a result, we compute more adjustments than we need here. See the CUMULATIVE_ARGS definition in mips.h. */ if (struct_p && int_size_in_bytes (type) < 4) { rtx amount = GEN_INT (BITS_PER_WORD - int_size_in_bytes (type) * BITS_PER_UNIT); rtx reg = gen_rtx (REG, SImode, regbase + cum->arg_words + bias); cum->adjust[ cum->num_adjusts++ ] = gen_ashlsi3 (reg, reg, amount); } } if (mode == VOIDmode && cum->num_adjusts > 0) ret = gen_rtx (PARALLEL, VOIDmode, gen_rtvec_v (cum->num_adjusts, cum->adjust)); return ret; } int function_arg_partial_nregs (cum, mode, type, named) CUMULATIVE_ARGS *cum; /* current arg information */ enum machine_mode mode; /* current arg mode */ tree type; /* type of the argument or 0 if lib support */ int named; /* != 0 for normal args, == 0 for ... args */ { if ((mode == BLKmode || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) && cum->arg_words < MAX_ARGS_IN_REGISTERS) { int words; if (mode == BLKmode) words = (int_size_in_bytes (type) + 3) / 4; else words = (GET_MODE_SIZE (mode) + 3) / 4; if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS) return 0; /* structure fits in registers */ if (TARGET_DEBUG_E_MODE) fprintf (stderr, "function_arg_partial_nregs = %d\n", MAX_ARGS_IN_REGISTERS - cum->arg_words); return MAX_ARGS_IN_REGISTERS - cum->arg_words; } else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1) { if (TARGET_DEBUG_E_MODE) fprintf (stderr, "function_arg_partial_nregs = 1\n"); return 1; } return 0; } /* Print the options used in the assembly file. */ static struct {char *name; int value;} target_switches [] = TARGET_SWITCHES; void print_options (out) FILE *out; { int line_len; int len; int j; char **p; int mask = TARGET_DEFAULT; /* Allow assembly language comparisons with -mdebug eliminating the compiler version number and switch lists. */ if (TARGET_DEBUG_MODE) return; fprintf (out, "\n # %s %s", language_string, version_string); #ifdef TARGET_VERSION_INTERNAL TARGET_VERSION_INTERNAL (out); #endif #ifdef __GNUC__ fprintf (out, " compiled by GNU C\n\n"); #else fprintf (out, " compiled by CC\n\n"); #endif fprintf (out, " # Cc1 defaults:"); line_len = 32767; for (j = 0; j < sizeof target_switches / sizeof target_switches[0]; j++) { if (target_switches[j].name[0] != '\0' && target_switches[j].value > 0 && (target_switches[j].value & mask) == target_switches[j].value) { mask &= ~ target_switches[j].value; len = strlen (target_switches[j].name) + 1; if (len + line_len > 79) { line_len = 2; fputs ("\n #", out); } fprintf (out, " -m%s", target_switches[j].name); line_len += len; } } fprintf (out, "\n\n # Cc1 arguments (-G value = %d, Cpu = %s, ISA = %d):", mips_section_threshold, mips_cpu_string, mips_isa); line_len = 32767; for (p = &save_argv[1]; *p != (char *)0; p++) { char *arg = *p; if (*arg == '-') { len = strlen (arg) + 1; if (len + line_len > 79) { line_len = 2; fputs ("\n #", out); } fprintf (out, " %s", *p); line_len += len; } } fputs ("\n\n", out); } /* Abort after printing out a specific insn. */ void abort_with_insn (insn, reason) rtx insn; char *reason; { error (reason); debug_rtx (insn); abort (); } /* Write a message to stderr (for use in macros expanded in files that do not include stdio.h). */ void trace (s, s1, s2) char *s, *s1, *s2; { fprintf (stderr, s, s1, s2); } #ifdef SIGINFO static void siginfo (signo) int signo; { fprintf (stderr, "compiling '%s' in '%s'\n", (current_function_name != (char *)0) ? current_function_name : "", (current_function_file != (char *)0) ? current_function_file : ""); fflush (stderr); } #endif /* SIGINFO */ /* Set up the threshold for data to go into the small data area, instead of the normal data area, and detect any conflicts in the switches. */ void override_options () { register int i, start; register int regno; register enum machine_mode mode; mips_section_threshold = (g_switch_set) ? g_switch_value : MIPS_DEFAULT_GVALUE; /* Identify the processor type */ if (mips_cpu_string == (char *)0 || !strcmp (mips_cpu_string, "default") || !strcmp (mips_cpu_string, "DEFAULT")) { mips_cpu_string = "default"; mips_cpu = PROCESSOR_DEFAULT; } else { char *p = mips_cpu_string; if (*p == 'r' || *p == 'R') p++; /* Since there is no difference between a R2000 and R3000 in terms of the scheduler, we collapse them into just an R3000. */ mips_cpu = PROCESSOR_DEFAULT; switch (*p) { case '2': if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K")) mips_cpu = PROCESSOR_R3000; break; case '3': if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K")) mips_cpu = PROCESSOR_R3000; break; case '4': if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K")) mips_cpu = PROCESSOR_R4000; break; case '6': if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K")) mips_cpu = PROCESSOR_R6000; break; } if (mips_cpu == PROCESSOR_DEFAULT) { error ("bad value (%s) for -mcpu= switch", mips_cpu_string); mips_cpu_string = "default"; } } /* Now get the architectural level. */ if (mips_isa_string == (char *)0) mips_isa = 1; else if (isdigit (*mips_isa_string)) mips_isa = atoi (mips_isa_string); else { error ("bad value (%s) for -mips switch", mips_isa_string); mips_isa = 1; } if (mips_isa < 0 || mips_isa > 3) error ("-mips%d not supported", mips_isa); else if (mips_isa > 1 && (mips_cpu == PROCESSOR_DEFAULT || mips_cpu == PROCESSOR_R3000)) error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa); else if (mips_cpu == PROCESSOR_R6000 && mips_isa > 2) error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa); /* make sure sizes of ints/longs/etc. are ok */ if (mips_isa < 3) { if (TARGET_INT64) fatal ("Only the r4000 can support 64 bit ints"); else if (TARGET_LONG64) fatal ("Only the r4000 can support 64 bit longs"); else if (TARGET_LLONG128) fatal ("Only the r4000 can support 128 bit long longs"); else if (TARGET_FLOAT64) fatal ("Only the r4000 can support 64 bit fp registers"); } else if (TARGET_INT64 || TARGET_LONG64 || TARGET_LLONG128 || TARGET_FLOAT64) warning ("r4000 64/128 bit types not yet supported"); /* Tell halfpic.c that we have half-pic code if we do. */ if (TARGET_HALF_PIC) HALF_PIC_INIT (); if (TARGET_ABICALLS) mips_abicalls = MIPS_ABICALLS_YES; else mips_abicalls = MIPS_ABICALLS_NO; /* -mrnames says to use the MIPS software convention for register names instead of the hardware names (ie, a0 instead of $4). We do this by switching the names in mips_reg_names, which the reg_names points into via the REGISTER_NAMES macro. */ if (TARGET_NAME_REGS) { if (TARGET_GAS) { target_flags &= ~ MASK_NAME_REGS; error ("Gas does not support the MIPS software register name convention."); } else bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names, sizeof (mips_reg_names)); } /* If this is OSF/1, set up a SIGINFO handler so we can see what function is currently being compiled. */ #ifdef SIGINFO if (getenv ("GCC_SIGINFO") != (char *)0) { struct sigaction action; action.sa_handler = siginfo; action.sa_mask = 0; action.sa_flags = SA_RESTART; sigaction (SIGINFO, &action, (struct sigaction *)0); } #endif #if defined(_IOLBF) #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf) /* If -mstats and -quiet, make stderr line buffered. */ if (quiet_flag && TARGET_STATS) setvbuf (stderr, (char *)0, _IOLBF, BUFSIZ); #endif #endif /* Set up the classification arrays now. */ mips_rtx_classify[(int)PLUS] = CLASS_ADD_OP; mips_rtx_classify[(int)MINUS] = CLASS_ADD_OP; mips_rtx_classify[(int)DIV] = CLASS_DIVMOD_OP; mips_rtx_classify[(int)MOD] = CLASS_DIVMOD_OP; mips_rtx_classify[(int)UDIV] = CLASS_DIVMOD_OP | CLASS_UNSIGNED_OP; mips_rtx_classify[(int)UMOD] = CLASS_DIVMOD_OP | CLASS_UNSIGNED_OP; mips_rtx_classify[(int)EQ] = CLASS_CMP_OP | CLASS_EQUALITY_OP | CLASS_FCMP_OP; mips_rtx_classify[(int)NE] = CLASS_CMP_OP | CLASS_EQUALITY_OP | CLASS_FCMP_OP; mips_rtx_classify[(int)GT] = CLASS_CMP_OP | CLASS_FCMP_OP; mips_rtx_classify[(int)GE] = CLASS_CMP_OP | CLASS_FCMP_OP; mips_rtx_classify[(int)LT] = CLASS_CMP_OP | CLASS_FCMP_OP; mips_rtx_classify[(int)LE] = CLASS_CMP_OP | CLASS_FCMP_OP; mips_rtx_classify[(int)GTU] = CLASS_CMP_OP | CLASS_UNSIGNED_OP; mips_rtx_classify[(int)GEU] = CLASS_CMP_OP | CLASS_UNSIGNED_OP; mips_rtx_classify[(int)LTU] = CLASS_CMP_OP | CLASS_UNSIGNED_OP; mips_rtx_classify[(int)LEU] = CLASS_CMP_OP | CLASS_UNSIGNED_OP; mips_print_operand_punct['?'] = TRUE; mips_print_operand_punct['#'] = TRUE; mips_print_operand_punct['&'] = TRUE; mips_print_operand_punct['!'] = TRUE; mips_print_operand_punct['*'] = TRUE; mips_print_operand_punct['@'] = TRUE; mips_print_operand_punct['.'] = TRUE; mips_print_operand_punct['('] = TRUE; mips_print_operand_punct[')'] = TRUE; mips_print_operand_punct['['] = TRUE; mips_print_operand_punct[']'] = TRUE; mips_print_operand_punct['<'] = TRUE; mips_print_operand_punct['>'] = TRUE; mips_print_operand_punct['{'] = TRUE; mips_print_operand_punct['}'] = TRUE; mips_print_operand_punct['^'] = TRUE; mips_char_to_class['d'] = GR_REGS; mips_char_to_class['f'] = ((TARGET_HARD_FLOAT) ? FP_REGS : NO_REGS); mips_char_to_class['h'] = HI_REG; mips_char_to_class['l'] = LO_REG; mips_char_to_class['x'] = MD_REGS; mips_char_to_class['y'] = GR_REGS; mips_char_to_class['z'] = ST_REGS; /* Set up array to map GCC register number to debug register number. Ignore the special purpose register numbers. */ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) mips_dbx_regno[i] = -1; start = GP_DBX_FIRST - GP_REG_FIRST; for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++) mips_dbx_regno[i] = i + start; start = FP_DBX_FIRST - FP_REG_FIRST; for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) mips_dbx_regno[i] = i + start; /* Set up array giving whether a given register can hold a given mode. At present, restrict ints from being in FP registers, because reload is a little enthusiastic about storing extra values in FP registers, and this is not good for things like OS kernels. Also, due to the mandatory delay, it is as fast to load from cached memory as to move from the FP register. */ for (mode = VOIDmode; mode != MAX_MACHINE_MODE; mode = (enum machine_mode)((int)mode + 1)) { register int size = GET_MODE_SIZE (mode); register enum mode_class class = GET_MODE_CLASS (mode); for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) { register int temp; if (mode == CC_FPmode || mode == CC_REV_FPmode) temp = (regno == FPSW_REGNUM); else if (GP_REG_P (regno)) temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD)); else if (FP_REG_P (regno)) temp = ((TARGET_FLOAT64 || ((regno & 1) == 0)) && (class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT || (TARGET_DEBUG_H_MODE && class == MODE_INT))); else if (MD_REG_P (regno)) temp = (mode == SImode || (regno == MD_REG_FIRST && mode == DImode)); else temp = FALSE; mips_hard_regno_mode_ok[(int)mode][regno] = temp; } } } /* * The MIPS debug format wants all automatic variables and arguments * to be in terms of the virtual frame pointer (stack pointer before * any adjustment in the function), while the MIPS 3.0 linker wants * the frame pointer to be the stack pointer after the initial * adjustment. So, we do the adjustment here. The arg pointer (which * is eliminated) points to the virtual frame pointer, while the frame * pointer (which may be eliminated) points to the stack pointer after * the initial adjustments. */ int mips_debugger_offset (addr, offset) rtx addr; int offset; { rtx offset2 = const0_rtx; rtx reg = eliminate_constant_term (addr, &offset2); if (!offset) offset = INTVAL (offset2); if (reg == stack_pointer_rtx || reg == frame_pointer_rtx) { int frame_size = (!current_frame_info.initialized) ? compute_frame_size (get_frame_size ()) : current_frame_info.total_size; offset = offset - frame_size; } /* sdbout_parms does not want this to crash for unrecognized cases. */ #if 0 else if (reg != arg_pointer_rtx) abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer."); #endif return offset; } /* A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand X. X is an RTL expression. CODE is a value that can be used to specify one of several ways of printing the operand. It is used when identical operands must be printed differently depending on the context. CODE comes from the `%' specification that was used to request printing of the operand. If the specification was just `%DIGIT' then CODE is 0; if the specification was `%LTR DIGIT' then CODE is the ASCII code for LTR. If X is a register, this macro should print the register's name. The names can be found in an array `reg_names' whose type is `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. When the machine description has a specification `%PUNCT' (a `%' followed by a punctuation character), this macro is called with a null pointer for X and the punctuation character for CODE. The MIPS specific codes are: 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x", 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x", 'd' output integer constant in decimal, 'z' if the operand is 0, use $0 instead of normal operand. 'D' print second register of double-word register operand. 'L' print low-order register of double-word register operand. 'M' print high-order register of double-word register operand. 'C' print part of opcode for a branch condition. 'N' print part of opcode for a branch condition, inverted. '(' Turn on .set noreorder ')' Turn on .set reorder '[' Turn on .set noat ']' Turn on .set at '<' Turn on .set nomacro '>' Turn on .set macro '{' Turn on .set volatile (not GAS) '}' Turn on .set novolatile (not GAS) '&' Turn on .set noreorder if filling delay slots '*' Turn on both .set noreorder and .set nomacro if filling delay slots '!' Turn on .set nomacro if filling delay slots '#' Print nop if in a .set noreorder section. '?' Print 'l' if we are to use a branch likely instead of normal branch. '@' Print the name of the assembler temporary register (at or $1). '.' Print the name of the register with a hard-wired zero (zero or $0). '^' Print the name of the pic call-through register (t9 or $25). */ void print_operand (file, op, letter) FILE *file; /* file to write to */ rtx op; /* operand to print */ int letter; /* % or 0 */ { register enum rtx_code code; if (PRINT_OPERAND_PUNCT_VALID_P (letter)) { switch (letter) { default: error ("PRINT_OPERAND: Unknown punctuation '%c'", letter); break; case '?': if (mips_branch_likely) putc ('l', file); break; case '@': fputs (reg_names [GP_REG_FIRST + 1], file); break; case '^': fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file); break; case '.': fputs (reg_names [GP_REG_FIRST + 0], file); break; case '&': if (final_sequence != 0 && set_noreorder++ == 0) fputs (".set\tnoreorder\n\t", file); break; case '*': if (final_sequence != 0) { if (set_noreorder++ == 0) fputs (".set\tnoreorder\n\t", file); if (set_nomacro++ == 0) fputs (".set\tnomacro\n\t", file); } break; case '!': if (final_sequence != 0 && set_nomacro++ == 0) fputs ("\n\t.set\tnomacro", file); break; case '#': if (set_noreorder != 0) fputs ("\n\tnop", file); else if (TARGET_GAS || TARGET_STATS) fputs ("\n\t#nop", file); break; case '(': if (set_noreorder++ == 0) fputs (".set\tnoreorder\n\t", file); break; case ')': if (set_noreorder == 0) error ("internal error: %%) found without a %%( in assembler pattern"); else if (--set_noreorder == 0) fputs ("\n\t.set\treorder", file); break; case '[': if (set_noat++ == 0) fputs (".set\tnoat\n\t", file); break; case ']': if (set_noat == 0) error ("internal error: %%] found without a %%[ in assembler pattern"); else if (--set_noat == 0) fputs ("\n\t.set\tat", file); break; case '<': if (set_nomacro++ == 0) fputs (".set\tnomacro\n\t", file); break; case '>': if (set_nomacro == 0) error ("internal error: %%> found without a %%< in assembler pattern"); else if (--set_nomacro == 0) fputs ("\n\t.set\tmacro", file); break; case '{': if (set_volatile++ == 0) fprintf (file, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS) ? "" : "#"); break; case '}': if (set_volatile == 0) error ("internal error: %%} found without a %%{ in assembler pattern"); else if (--set_volatile == 0) fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#"); break; } return; } if (! op) { error ("PRINT_OPERAND null pointer"); return; } code = GET_CODE (op); if (letter == 'C') switch (code) { case EQ: fputs ("eq", file); break; case NE: fputs ("ne", file); break; case GT: fputs ("gt", file); break; case GE: fputs ("ge", file); break; case LT: fputs ("lt", file); break; case LE: fputs ("le", file); break; case GTU: fputs ("gtu", file); break; case GEU: fputs ("geu", file); break; case LTU: fputs ("ltu", file); break; case LEU: fputs ("leu", file); break; default: abort_with_insn (op, "PRINT_OPERAND, illegal insn for %%C"); } else if (letter == 'N') switch (code) { case EQ: fputs ("ne", file); break; case NE: fputs ("eq", file); break; case GT: fputs ("le", file); break; case GE: fputs ("lt", file); break; case LT: fputs ("ge", file); break; case LE: fputs ("gt", file); break; case GTU: fputs ("leu", file); break; case GEU: fputs ("ltu", file); break; case LTU: fputs ("geu", file); break; case LEU: fputs ("gtu", file); break; default: abort_with_insn (op, "PRINT_OPERAND, illegal insn for %%N"); } else if (code == REG) { register int regnum = REGNO (op); if (letter == 'M') regnum += MOST_SIGNIFICANT_WORD; else if (letter == 'L') regnum += LEAST_SIGNIFICANT_WORD; else if (letter == 'D') regnum++; fprintf (file, "%s", reg_names[regnum]); } else if (code == MEM) output_address (XEXP (op, 0)); else if (code == CONST_DOUBLE) { #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT union { double d; int i[2]; } u; u.i[0] = CONST_DOUBLE_LOW (op); u.i[1] = CONST_DOUBLE_HIGH (op); if (GET_MODE (op) == SFmode) { float f; f = u.d; u.d = f; } fprintf (file, "%.20e", u.d); #else fatal ("CONST_DOUBLE found in cross compilation"); #endif } else if ((letter == 'x') && (GET_CODE(op) == CONST_INT)) fprintf (file, "0x%04x", 0xffff & (INTVAL(op))); else if ((letter == 'X') && (GET_CODE(op) == CONST_INT)) fprintf (file, "0x%08x", INTVAL(op)); else if ((letter == 'd') && (GET_CODE(op) == CONST_INT)) fprintf (file, "%d", (INTVAL(op))); else if (letter == 'z' && (GET_CODE (op) == CONST_INT) && INTVAL (op) == 0) fputs (reg_names[GP_REG_FIRST], file); else if (letter == 'd' || letter == 'x' || letter == 'X') fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter); else output_addr_const (file, op); } /* A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand that is a memory reference whose address is ADDR. ADDR is an RTL expression. On some machines, the syntax for a symbolic address depends on the section that the address refers to. On these machines, define the macro `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and then check for it here. */ void print_operand_address (file, addr) FILE *file; rtx addr; { if (!addr) error ("PRINT_OPERAND_ADDRESS, null pointer"); else switch (GET_CODE (addr)) { default: abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, illegal insn #1"); break; case REG: if (REGNO (addr) == ARG_POINTER_REGNUM) abort_with_insn (addr, "Arg pointer not eliminated."); fprintf (file, "0(%s)", reg_names [REGNO (addr)]); break; case PLUS: { register rtx reg = (rtx)0; register rtx offset = (rtx)0; register rtx arg0 = XEXP (addr, 0); register rtx arg1 = XEXP (addr, 1); if (GET_CODE (arg0) == REG) { reg = arg0; offset = arg1; if (GET_CODE (offset) == REG) abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs"); } else if (GET_CODE (arg1) == REG) { reg = arg1; offset = arg0; } else if (CONSTANT_P (arg0) && CONSTANT_P (arg1)) { output_addr_const (file, addr); break; } else abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs"); if (!CONSTANT_P (offset)) abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, illegal insn #2"); if (REGNO (reg) == ARG_POINTER_REGNUM) abort_with_insn (addr, "Arg pointer not eliminated."); output_addr_const (file, offset); fprintf (file, "(%s)", reg_names [REGNO (reg)]); } break; case LABEL_REF: case SYMBOL_REF: case CONST_INT: case CONST: output_addr_const (file, addr); break; } } /* If optimizing for the global pointer, keep track of all of the externs, so that at the end of the file, we can emit the appropriate .extern declaration for them, before writing out the text section. We assume that all names passed to us are in the permanent obstack, so that they will be valid at the end of the compilation. If we have -G 0, or the extern size is unknown, don't bother emitting the .externs. */ int mips_output_external (file, decl, name) FILE *file; tree decl; char *name; { register struct extern_list *p; int len; if (TARGET_GP_OPT && mips_section_threshold != 0 && ((TREE_CODE (decl)) != FUNCTION_DECL) && ((len = int_size_in_bytes (TREE_TYPE (decl))) > 0)) { p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list)); p->next = extern_head; p->name = name; p->size = len; extern_head = p; } return 0; } /* Compute a string to use as a temporary file name. */ static FILE * make_temp_file () { FILE *stream; char *base = getenv ("TMPDIR"); int len; if (base == (char *)0) { #ifdef P_tmpdir if (access (P_tmpdir, R_OK | W_OK) == 0) base = P_tmpdir; else #endif if (access ("/usr/tmp", R_OK | W_OK) == 0) base = "/usr/tmp/"; else base = "/tmp/"; } len = strlen (base); temp_filename = (char *) alloca (len + sizeof("/ccXXXXXX")); strcpy (temp_filename, base); if (len > 0 && temp_filename[len-1] != '/') temp_filename[len++] = '/'; strcpy (temp_filename + len, "ccXXXXXX"); mktemp (temp_filename); stream = fopen (temp_filename, "w+"); if (!stream) pfatal_with_name (temp_filename); unlink (temp_filename); return stream; } /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out for .file's that start within a function. If we are smuggling stabs, try to put out a MIPS ECOFF file and a stab. */ void mips_output_filename (stream, name) FILE *stream; char *name; { static int first_time = TRUE; char ltext_label_name[100]; if (first_time) { first_time = FALSE; SET_FILE_NUMBER (); current_function_file = name; fprintf (stream, "\t.file\t%d ", num_source_filenames); output_quoted_string (stream, name); fprintf (stream, "\n"); /* This tells mips-tfile that stabs will follow. */ if (!TARGET_GAS && write_symbols == DBX_DEBUG) fprintf (stream, "\t#@stabs\n"); } else if (write_symbols == DBX_DEBUG) { ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0); fprintf (stream, "%s ", ASM_STABS_OP); output_quoted_string (stream, name); fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]); } else if (name != current_function_file && strcmp (name, current_function_file) != 0) { if (inside_function && !TARGET_GAS) { if (!file_in_function_warning) { file_in_function_warning = TRUE; ignore_line_number = TRUE; warning ("MIPS ECOFF format does not allow changing filenames within functions with #line"); } fprintf (stream, "\t#.file\t%d ", num_source_filenames); } else { SET_FILE_NUMBER (); current_function_file = name; fprintf (stream, "\t.file\t%d ", num_source_filenames); } output_quoted_string (stream, name); fprintf (stream, "\n"); } } /* Emit a linenumber. For encapsulated stabs, we need to put out a stab as well as a .loc, since it is possible that MIPS ECOFF might not be able to represent the location for inlines that come from a different file. */ void mips_output_lineno (stream, line) FILE *stream; int line; { if (write_symbols == DBX_DEBUG) { ++sym_lineno; fprintf (stream, "$LM%d:\n\t%s %d,0,%d,$LM%d\n", sym_lineno, ASM_STABN_OP, N_SLINE, line, sym_lineno); } else { fprintf (stream, "\n\t%s.loc\t%d %d\n", (ignore_line_number) ? "#" : "", num_source_filenames, line); LABEL_AFTER_LOC (stream); } } /* If defined, a C statement to be executed just prior to the output of assembler code for INSN, to modify the extracted operands so they will be output differently. Here the argument OPVEC is the vector containing the operands extracted from INSN, and NOPERANDS is the number of elements of the vector which contain meaningful data for this insn. The contents of this vector are what will be used to convert the insn template into assembler code, so you can change the assembler output by changing the contents of the vector. We use it to check if the current insn needs a nop in front of it because of load delays, and also to update the delay slot statistics. */ void final_prescan_insn (insn, opvec, noperands) rtx insn; rtx opvec[]; int noperands; { if (dslots_number_nops > 0) { rtx pattern = PATTERN (insn); int length = get_attr_length (insn); /* Do we need to emit a NOP? */ if (length == 0 || (mips_load_reg != (rtx)0 && reg_mentioned_p (mips_load_reg, pattern)) || (mips_load_reg2 != (rtx)0 && reg_mentioned_p (mips_load_reg2, pattern)) || (mips_load_reg3 != (rtx)0 && reg_mentioned_p (mips_load_reg3, pattern)) || (mips_load_reg4 != (rtx)0 && reg_mentioned_p (mips_load_reg4, pattern))) fputs ((set_noreorder) ? "\tnop\n" : "\t#nop\n", asm_out_file); else dslots_load_filled++; while (--dslots_number_nops > 0) fputs ((set_noreorder) ? "\tnop\n" : "\t#nop\n", asm_out_file); mips_load_reg = (rtx)0; mips_load_reg2 = (rtx)0; mips_load_reg3 = (rtx)0; mips_load_reg4 = (rtx)0; if (set_noreorder && --set_noreorder == 0) fputs ("\t.set\treorder\n", asm_out_file); } if (TARGET_STATS) { enum rtx_code code = GET_CODE (insn); if (code == JUMP_INSN || code == CALL_INSN) dslots_jump_total++; } } /* Output at beginning of assembler file. If we are optimizing to use the global pointer, create a temporary file to hold all of the text stuff, and write it out to the end. This is needed because the MIPS assembler is evidently one pass, and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata declaration when the code is processed, it generates a two instruction sequence. */ void mips_asm_file_start (stream) FILE *stream; { ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename); /* Versions of the MIPS assembler before 2.20 generate errors if a branch inside of a .set noreorder section jumps to a label outside of the .set noreorder section. Revision 2.20 just set nobopt silently rather than fixing the bug. */ if (TARGET_MIPS_AS && optimize && flag_delayed_branch) fprintf (stream, "\t.set\tnobopt\n"); /* Generate the pseudo ops that System V.4 wants. */ #ifndef ABICALLS_ASM_OP #define ABICALLS_ASM_OP ".abicalls" #endif if (TARGET_ABICALLS) /* ??? but do not want this (or want pic0) if -non-shared? */ fprintf (stream, "\t%s\n", ABICALLS_ASM_OP); if (TARGET_GP_OPT) { asm_out_data_file = stream; asm_out_text_file = make_temp_file (); } else asm_out_data_file = asm_out_text_file = stream; if (TARGET_NAME_REGS) fprintf (asm_out_file, "#include \n"); print_options (stream); } /* If we are optimizing the global pointer, emit the text section now and any small externs which did not have .comm, etc that are needed. Also, give a warning if the data area is more than 32K and -pic because 3 instructions are needed to reference the data pointers. */ void mips_asm_file_end (file) FILE *file; { char buffer[8192]; tree name_tree; struct extern_list *p; int len; if (HALF_PIC_P ()) HALF_PIC_FINISH (file); if (TARGET_GP_OPT) { if (extern_head) fputs ("\n", file); for (p = extern_head; p != 0; p = p->next) { name_tree = get_identifier (p->name); /* Positively ensure only one .extern for any given symbol. */ if (! TREE_ASM_WRITTEN (name_tree)) { TREE_ASM_WRITTEN (name_tree) = 1; fputs ("\t.extern\t", file); assemble_name (file, p->name); fprintf (file, ", %d\n", p->size); } } fprintf (file, "\n\t.text\n"); rewind (asm_out_text_file); if (ferror (asm_out_text_file)) fatal_io_error (temp_filename); while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0) if (fwrite (buffer, 1, len, file) != len) pfatal_with_name (asm_file_name); if (len < 0) pfatal_with_name (temp_filename); if (fclose (asm_out_text_file) != 0) pfatal_with_name (temp_filename); } } /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol is used, so that we don't emit an .extern for it in mips_asm_file_end. */ void mips_declare_object (stream, name, init_string, final_string, size) FILE *stream; char *name; char *init_string; char *final_string; int size; { fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */ assemble_name (stream, name); fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */ if (TARGET_GP_OPT && mips_section_threshold != 0) { tree name_tree = get_identifier (name); TREE_ASM_WRITTEN (name_tree) = 1; } } /* Output a double precision value to the assembler. If both the host and target are IEEE, emit the values in hex. */ void mips_output_double (stream, value) FILE *stream; REAL_VALUE_TYPE value; { #ifdef REAL_VALUE_TO_TARGET_DOUBLE long value_long[2]; REAL_VALUE_TO_TARGET_DOUBLE (value, value_long); fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n", value_long[0], value, value_long[1]); #else fprintf (stream, "\t.double\t%.20g\n", value); #endif } /* Output a single precision value to the assembler. If both the host and target are IEEE, emit the values in hex. */ void mips_output_float (stream, value) FILE *stream; REAL_VALUE_TYPE value; { #ifdef REAL_VALUE_TO_TARGET_SINGLE long value_long; REAL_VALUE_TO_TARGET_SINGLE (value, value_long); fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value); #else fprintf (stream, "\t.float\t%.12g\n", value); #endif } /* Return TRUE if any register used in the epilogue is used. This to insure any insn put into the epilogue delay slots is safe. */ int epilogue_reg_mentioned_p (insn) rtx insn; { register char *fmt; register int i; register enum rtx_code code; register int regno; if (insn == (rtx)0) return 0; if (GET_CODE (insn) == LABEL_REF) return 0; code = GET_CODE (insn); switch (code) { case REG: regno = REGNO (insn); if (regno == STACK_POINTER_REGNUM) return 1; if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) return 1; if (!call_used_regs[regno]) return 1; if (regno != MIPS_TEMP1_REGNUM && regno != MIPS_TEMP2_REGNUM) return 0; if (!current_frame_info.initialized) compute_frame_size (get_frame_size ()); return (current_frame_info.total_size >= 32768); case SCRATCH: case CC0: case PC: case CONST_INT: case CONST_DOUBLE: return 0; } fmt = GET_RTX_FORMAT (code); for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) { if (fmt[i] == 'E') { register int j; for (j = XVECLEN (insn, i) - 1; j >= 0; j--) if (epilogue_reg_mentioned_p (XVECEXP (insn, i, j))) return 1; } else if (fmt[i] == 'e' && epilogue_reg_mentioned_p (XEXP (insn, i))) return 1; } return 0; } /* Return the bytes needed to compute the frame pointer from the current stack pointer. Mips stack frames look like: Before call After call +-----------------------+ +-----------------------+ high | | | | mem. | | | | | caller's temps. | | caller's temps. | | | | | +-----------------------+ +-----------------------+ | | | | | arguments on stack. | | arguments on stack. | | | | | +-----------------------+ +-----------------------+ | 4 words to save | | 4 words to save | | arguments passed | | arguments passed | | in registers, even | | in registers, even | SP->| if not passed. | VFP->| if not passed. | +-----------------------+ +-----------------------+ | | | fp register save | | | +-----------------------+ | | | gp register save | | | +-----------------------+ | | | local variables | | | +-----------------------+ | | | alloca allocations | | | +-----------------------+ | | | GP save for V.4 abi | | | +-----------------------+ | | | arguments on stack | | | +-----------------------+ | 4 words to save | | arguments passed | | in registers, even | low SP->| if not passed. | memory +-----------------------+ */ long compute_frame_size (size) int size; /* # of var. bytes allocated */ { int regno; long total_size; /* # bytes that the entire frame takes up */ long var_size; /* # bytes that variables take up */ long args_size; /* # bytes that outgoing arguments take up */ long extra_size; /* # extra bytes */ long gp_reg_rounded; /* # bytes needed to store gp after rounding */ long gp_reg_size; /* # bytes needed to store gp regs */ long fp_reg_size; /* # bytes needed to store fp regs */ long mask; /* mask of saved gp registers */ long fmask; /* mask of saved fp registers */ int fp_inc; /* 1 or 2 depending on the size of fp regs */ long fp_bits; /* bitmask to use for each fp register */ gp_reg_size = 0; fp_reg_size = 0; mask = 0; fmask = 0; extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0)); var_size = MIPS_STACK_ALIGN (size); args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size); /* The MIPS 3.0 linker does not like functions that dynamically allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it looks like we are trying to create a second frame pointer to the function, so allocate some stack space to make it happy. */ if (args_size == 0 && current_function_calls_alloca) args_size = 4*UNITS_PER_WORD; total_size = var_size + args_size + extra_size; /* Calculate space needed for gp registers. */ for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) { if (MUST_SAVE_REGISTER (regno)) { gp_reg_size += UNITS_PER_WORD; mask |= 1L << (regno - GP_REG_FIRST); } } /* Calculate space needed for fp registers. */ if (TARGET_FLOAT64) { fp_inc = 1; fp_bits = 1; } else { fp_inc = 2; fp_bits = 3; } for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += fp_inc) { if (regs_ever_live[regno] && !call_used_regs[regno]) { fp_reg_size += 2*UNITS_PER_WORD; fmask |= fp_bits << (regno - FP_REG_FIRST); } } gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size); total_size += gp_reg_rounded + fp_reg_size; if (total_size == extra_size) total_size = extra_size = 0; else if (TARGET_ABICALLS) { /* Add the context-pointer to the saved registers. */ gp_reg_size += UNITS_PER_WORD; mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST); total_size -= gp_reg_rounded; gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size); total_size += gp_reg_rounded; } /* Save other computed information. */ current_frame_info.total_size = total_size; current_frame_info.var_size = var_size; current_frame_info.args_size = args_size; current_frame_info.extra_size = extra_size; current_frame_info.gp_reg_size = gp_reg_size; current_frame_info.fp_reg_size = fp_reg_size; current_frame_info.mask = mask; current_frame_info.fmask = fmask; current_frame_info.initialized = reload_completed; current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD; current_frame_info.num_fp = fp_reg_size / (2*UNITS_PER_WORD); if (mask) { unsigned long offset = args_size + extra_size + var_size + gp_reg_size - UNITS_PER_WORD; current_frame_info.gp_sp_offset = offset; current_frame_info.gp_save_offset = offset - total_size; } else { current_frame_info.gp_sp_offset = 0; current_frame_info.gp_save_offset = 0; } if (fmask) { unsigned long offset = args_size + extra_size + var_size + gp_reg_rounded + fp_reg_size - 2*UNITS_PER_WORD; current_frame_info.fp_sp_offset = offset; current_frame_info.fp_save_offset = offset - total_size + UNITS_PER_WORD; } else { current_frame_info.fp_sp_offset = 0; current_frame_info.fp_save_offset = 0; } /* Ok, we're done. */ return total_size; } /* Common code to emit the insns (or to write the instructions to a file) to save/restore registers. Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg) is not modified within save_restore_insns. */ #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0) static void save_restore_insns (store_p, large_reg, large_offset, file) int store_p; /* true if this is prologue */ rtx large_reg; /* register holding large offset constant or NULL */ long large_offset; /* large constant offset value */ FILE *file; /* file to write instructions to instead of making RTL */ { long mask = current_frame_info.mask; long fmask = current_frame_info.fmask; int regno; rtx base_reg_rtx; long base_offset; long gp_offset; long fp_offset; long end_offset; if (frame_pointer_needed && !BITSET_P (mask, FRAME_POINTER_REGNUM - GP_REG_FIRST)) abort (); if (mask == 0 && fmask == 0) return; /* Save registers starting from high to low. The debuggers prefer at least the return register be stored at func+4, and also it allows us not to need a nop in the epilog if at least one register is reloaded in addition to return address. */ /* Save GP registers if needed. */ if (mask) { /* Pick which pointer to use as a base register. For small frames, just use the stack pointer. Otherwise, use a temporary register. Save 2 cycles if the save area is near the end of a large frame, by reusing the constant created in the prologue/epilogue to adjust the stack frame. */ gp_offset = current_frame_info.gp_sp_offset; end_offset = gp_offset - (current_frame_info.gp_reg_size - UNITS_PER_WORD); if (gp_offset < 0 || end_offset < 0) fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.", gp_offset, end_offset); else if (gp_offset < 32768) { base_reg_rtx = stack_pointer_rtx; base_offset = 0; } else if (large_reg != (rtx)0 && (((unsigned long)(large_offset - gp_offset)) < 32768) && (((unsigned long)(large_offset - end_offset)) < 32768)) { base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); base_offset = large_offset; if (file == (FILE *)0) emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx)); else fprintf (file, "\taddu\t%s,%s,%s\n", reg_names[MIPS_TEMP2_REGNUM], reg_names[REGNO (large_reg)], reg_names[STACK_POINTER_REGNUM]); } else { base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); base_offset = gp_offset; if (file == (FILE *)0) { emit_move_insn (base_reg_rtx, GEN_INT (gp_offset)); emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx)); } else fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n\taddu\t%s,%s,%s\n", reg_names[MIPS_TEMP2_REGNUM], (long)base_offset, (long)base_offset, reg_names[MIPS_TEMP2_REGNUM], reg_names[MIPS_TEMP2_REGNUM], reg_names[STACK_POINTER_REGNUM]); } for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--) { if (BITSET_P (mask, regno - GP_REG_FIRST)) { if (file == (FILE *)0) { rtx reg_rtx = gen_rtx (REG, Pmode, regno); rtx mem_rtx = gen_rtx (MEM, Pmode, gen_rtx (PLUS, Pmode, base_reg_rtx, GEN_INT (gp_offset - base_offset))); if (store_p) emit_move_insn (mem_rtx, reg_rtx); else if (!TARGET_ABICALLS || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)) emit_move_insn (reg_rtx, mem_rtx); } else { if (store_p || !TARGET_ABICALLS || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)) fprintf (file, "\t%s\t%s,%ld(%s)\n", (store_p) ? "sw" : "lw", reg_names[regno], gp_offset - base_offset, reg_names[REGNO(base_reg_rtx)]); } gp_offset -= UNITS_PER_WORD; } } } else { base_reg_rtx = (rtx)0; /* Make sure these are initialzed */ base_offset = 0; } /* Save floating point registers if needed. */ if (fmask) { int fp_inc = (TARGET_FLOAT64) ? 1 : 2; /* Pick which pointer to use as a base register. */ fp_offset = current_frame_info.fp_sp_offset; end_offset = fp_offset - (current_frame_info.fp_reg_size - 2*UNITS_PER_WORD); if (fp_offset < 0 || end_offset < 0) fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.", fp_offset, end_offset); else if (fp_offset < 32768) { base_reg_rtx = stack_pointer_rtx; base_offset = 0; } else if (base_reg_rtx != (rtx)0 && (((unsigned long)(base_offset - fp_offset)) < 32768) && (((unsigned long)(base_offset - end_offset)) < 32768)) { ; /* already set up for gp registers above */ } else if (large_reg != (rtx)0 && (((unsigned long)(large_offset - fp_offset)) < 32768) && (((unsigned long)(large_offset - end_offset)) < 32768)) { base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); base_offset = large_offset; if (file == (FILE *)0) emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx)); else fprintf (file, "\taddu\t%s,%s,%s\n", reg_names[MIPS_TEMP2_REGNUM], reg_names[REGNO (large_reg)], reg_names[STACK_POINTER_REGNUM]); } else { base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); base_offset = fp_offset; if (file == (FILE *)0) { emit_move_insn (base_reg_rtx, GEN_INT (fp_offset)); emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx)); } else fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n\taddu\t%s,%s,%s\n", reg_names[MIPS_TEMP2_REGNUM], (long)base_offset, (long)base_offset, reg_names[MIPS_TEMP2_REGNUM], reg_names[MIPS_TEMP2_REGNUM], reg_names[STACK_POINTER_REGNUM]); } for (regno = FP_REG_LAST-1; regno >= FP_REG_FIRST; regno -= fp_inc) { if (BITSET_P (fmask, regno - FP_REG_FIRST)) { if (file == (FILE *)0) { rtx reg_rtx = gen_rtx (REG, DFmode, regno); rtx mem_rtx = gen_rtx (MEM, DFmode, gen_rtx (PLUS, Pmode, base_reg_rtx, GEN_INT (fp_offset - base_offset))); if (store_p) emit_move_insn (mem_rtx, reg_rtx); else emit_move_insn (reg_rtx, mem_rtx); } else fprintf (file, "\t%s\t%s,%ld(%s)\n", (store_p) ? "s.d" : "l.d", reg_names[regno], fp_offset - base_offset, reg_names[REGNO(base_reg_rtx)]); fp_offset -= 2*UNITS_PER_WORD; } } } } /* Set up the stack and frame (if desired) for the function. */ void function_prologue (file, size) FILE *file; int size; { long tsize = current_frame_info.total_size; ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl)); if (debug_info_level != DINFO_LEVEL_TERSE) ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl)); inside_function = 1; fputs ("\t.ent\t", file); assemble_name (file, current_function_name); fputs ("\n", file); assemble_name (file, current_function_name); fputs (":\n", file); fprintf (file, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n", reg_names[ (frame_pointer_needed) ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ], tsize, reg_names[31 + GP_REG_FIRST], current_frame_info.var_size, current_frame_info.num_gp, current_frame_info.num_fp, current_function_outgoing_args_size, current_frame_info.extra_size); fprintf (file, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n", current_frame_info.mask, current_frame_info.gp_save_offset, current_frame_info.fmask, current_frame_info.fp_save_offset); if (TARGET_ABICALLS) { char *sp_str = reg_names[STACK_POINTER_REGNUM]; fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n", reg_names[PIC_FUNCTION_ADDR_REGNUM]); if (tsize > 0) { fprintf (file, "\tsubu\t%s,%s,%d\n", sp_str, sp_str, tsize); fprintf (file, "\t.cprestore %d\n", current_frame_info.args_size); } } } /* Expand the prologue into a bunch of separate insns. */ void mips_expand_prologue () { int regno; long tsize; rtx tmp_rtx = (rtx)0; char *arg_name = (char *)0; tree fndecl = current_function_decl; tree fntype = TREE_TYPE (fndecl); tree fnargs = (TREE_CODE (fntype) != METHOD_TYPE) ? DECL_ARGUMENTS (fndecl) : 0; rtx next_arg_reg; int i; tree next_arg; tree cur_arg; CUMULATIVE_ARGS args_so_far; /* If struct value address is treated as the first argument, make it so. */ if (aggregate_value_p (DECL_RESULT (fndecl)) && ! current_function_returns_pcc_struct && struct_value_incoming_rtx == 0) { tree type = build_pointer_type (fntype); tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type); DECL_ARG_TYPE (function_result_decl) = type; TREE_CHAIN (function_result_decl) = fnargs; fnargs = function_result_decl; } /* Determine the last argument, and get its name. */ INIT_CUMULATIVE_ARGS (args_so_far, fntype, (rtx)0); regno = GP_ARG_FIRST; for (cur_arg = fnargs; cur_arg != (tree)0; cur_arg = next_arg) { tree type = DECL_ARG_TYPE (cur_arg); enum machine_mode passed_mode = TYPE_MODE (type); rtx entry_parm = FUNCTION_ARG (args_so_far, passed_mode, DECL_ARG_TYPE (cur_arg), 1); if (entry_parm) { int words; /* passed in a register, so will get homed automatically */ if (GET_MODE (entry_parm) == BLKmode) words = (int_size_in_bytes (type) + 3) / 4; else words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4; regno = REGNO (entry_parm) + words - 1; } else { regno = GP_ARG_LAST+1; break; } FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, DECL_ARG_TYPE (cur_arg), 1); next_arg = TREE_CHAIN (cur_arg); if (next_arg == (tree)0) { if (DECL_NAME (cur_arg)) arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg)); break; } } /* In order to pass small structures by value in registers compatibly with the MIPS compiler, we need to shift the value into the high part of the register. Function_arg has encoded a PARALLEL rtx, holding a vector of adjustments to be made as the next_arg_reg variable, so we split up the insns, and emit them separately. */ next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1); if (next_arg_reg != (rtx)0 && GET_CODE (next_arg_reg) == PARALLEL) { rtvec adjust = XVEC (next_arg_reg, 0); int num = GET_NUM_ELEM (adjust); for (i = 0; i < num; i++) { rtx pattern = RTVEC_ELT (adjust, i); if (GET_CODE (pattern) != SET || GET_CODE (SET_SRC (pattern)) != ASHIFT) abort_with_insn (pattern, "Insn is not a shift"); PUT_CODE (SET_SRC (pattern), ASHIFTRT); emit_insn (pattern); } } tsize = compute_frame_size (get_frame_size ()); /* If this function is a varargs function, store any registers that would normally hold arguments ($4 - $7) on the stack. */ if ((TYPE_ARG_TYPES (fntype) != 0 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node)) || (arg_name != (char *)0 && ((arg_name[0] == '_' && strcmp (arg_name, "__builtin_va_alist") == 0) || (arg_name[0] == 'v' && strcmp (arg_name, "va_alist") == 0)))) { int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD; rtx ptr = stack_pointer_rtx; /* If we are doing svr4-abi, sp has already been decremented by tsize. */ if (TARGET_ABICALLS) offset += tsize; for (; regno <= GP_ARG_LAST; regno++) { if (offset != 0) ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset)); emit_move_insn (gen_rtx (MEM, Pmode, ptr), gen_rtx (REG, Pmode, regno)); offset += UNITS_PER_WORD; } } if (tsize > 0) { rtx tsize_rtx = GEN_INT (tsize); /* If we are doing svr4-abi, sp move is done by function_prologue. */ if (!TARGET_ABICALLS) { if (tsize > 32767) { tmp_rtx = gen_rtx (REG, SImode, MIPS_TEMP1_REGNUM); emit_move_insn (tmp_rtx, tsize_rtx); tsize_rtx = tmp_rtx; } emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tsize_rtx)); } save_restore_insns (TRUE, tmp_rtx, tsize, (FILE *)0); if (frame_pointer_needed) emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx)); } /* If we are profiling, make sure no instructions are scheduled before the call to mcount. */ if (profile_flag || profile_block_flag) emit_insn (gen_blockage ()); } /* Do any necessary cleanup after a function to restore stack, frame, and regs. */ #define RA_MASK ((long) 0x80000000) /* 1 << 31 */ #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)) void function_epilogue (file, size) FILE *file; int size; { long tsize; char *sp_str = reg_names[STACK_POINTER_REGNUM]; char *t1_str = reg_names[MIPS_TEMP1_REGNUM]; rtx epilogue_delay = current_function_epilogue_delay_list; int noreorder = !TARGET_MIPS_AS || (epilogue_delay != 0); int noepilogue = FALSE; int load_nop = FALSE; int load_only_r31; rtx tmp_rtx = (rtx)0; rtx restore_rtx; int i; /* The epilogue does not depend on any registers, but the stack registers, so we assume that if we have 1 pending nop, it can be ignored, and 2 it must be filled (2 nops occur for integer multiply and divide). */ if (dslots_number_nops > 0) { if (dslots_number_nops == 1) { dslots_number_nops = 0; dslots_load_filled++; } else { while (--dslots_number_nops > 0) fputs ((set_noreorder) ? "\tnop\n" : "\t#nop\n", asm_out_file); } if (set_noreorder > 0 && --set_noreorder == 0) fputs ("\t.set\treorder\n", file); } if (set_noat != 0) { set_noat = 0; fputs ("\t.set\tat\n", file); error ("internal gcc error: .set noat left on in epilogue"); } if (set_nomacro != 0) { set_nomacro = 0; fputs ("\t.set\tmacro\n", file); error ("internal gcc error: .set nomacro left on in epilogue"); } if (set_noreorder != 0) { set_noreorder = 0; fputs ("\t.set\treorder\n", file); error ("internal gcc error: .set noreorder left on in epilogue"); } if (set_volatile != 0) { set_volatile = 0; fprintf (file, "\t#.set\tnovolatile\n", (TARGET_MIPS_AS) ? "" : "#"); error ("internal gcc error: .set volatile left on in epilogue"); } size = MIPS_STACK_ALIGN (size); tsize = (!current_frame_info.initialized) ? compute_frame_size (size) : current_frame_info.total_size; if (tsize == 0 && epilogue_delay == 0) { rtx insn = get_last_insn (); /* If the last insn was a BARRIER, we don't have to write any code because a jump (aka return) was put there. */ if (GET_CODE (insn) == NOTE) insn = prev_nonnote_insn (insn); if (insn && GET_CODE (insn) == BARRIER) noepilogue = TRUE; noreorder = FALSE; } if (!noepilogue) { /* In the reload sequence, we don't need to fill the load delay slots for most of the loads, also see if we can fill the final delay slot if not otherwise filled by the reload sequence. */ if (noreorder) fprintf (file, "\t.set\tnoreorder\n"); if (tsize > 32767) { fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n", t1_str, (long)tsize, (long)tsize); tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM); } if (frame_pointer_needed) fprintf (file, "\tmove\t%s,%s\t\t\t# sp not trusted here\n", sp_str, reg_names[FRAME_POINTER_REGNUM]); save_restore_insns (FALSE, tmp_rtx, tsize, file); load_only_r31 = (((current_frame_info.mask & ~ (TARGET_ABICALLS ? PIC_OFFSET_TABLE_MASK : 0)) == RA_MASK) && current_frame_info.fmask == 0); if (noreorder) { /* If the only register saved is the return address, we need a nop, unless we have an instruction to put into it. Otherwise we don't since reloading multiple registers doesn't reference the register being loaded. */ if (load_only_r31) { if (epilogue_delay) final_scan_insn (XEXP (epilogue_delay, 0), file, 1, /* optimize */ -2, /* prescan */ 1); /* nopeepholes */ else { fprintf (file, "\tnop\n"); load_nop = TRUE; } } fprintf (file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 31]); if (tsize > 32767) fprintf (file, "\taddu\t%s,%s,%s\n", sp_str, sp_str, t1_str); else if (tsize > 0) fprintf (file, "\taddu\t%s,%s,%d\n", sp_str, sp_str, tsize); else if (!load_only_r31 && epilogue_delay != 0) final_scan_insn (XEXP (epilogue_delay, 0), file, 1, /* optimize */ -2, /* prescan */ 1); /* nopeepholes */ fprintf (file, "\t.set\treorder\n"); } else { if (tsize > 32767) fprintf (file, "\taddu\t%s,%s,%s\n", sp_str, sp_str, t1_str); else if (tsize > 0) fprintf (file, "\taddu\t%s,%s,%d\n", sp_str, sp_str, tsize); fprintf (file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 31]); } } fputs ("\t.end\t", file); assemble_name (file, current_function_name); fputs ("\n", file); if (TARGET_STATS) { int num_gp_regs = current_frame_info.gp_reg_size / 4; int num_fp_regs = current_frame_info.fp_reg_size / 8; int num_regs = num_gp_regs + num_fp_regs; char *name = current_function_name; if (name[0] == '*') name++; dslots_load_total += num_regs; if (!noepilogue) dslots_jump_total++; if (noreorder) { dslots_load_filled += num_regs; /* If the only register saved is the return register, we can't fill this register's delay slot. */ if (load_only_r31 && epilogue_delay == 0) dslots_load_filled--; if (tsize > 0 || (!load_only_r31 && epilogue_delay != 0)) dslots_jump_filled++; } fprintf (stderr, "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d", name, (frame_pointer_needed) ? 'y' : 'n', ((current_frame_info.mask & RA_MASK) != 0) ? 'n' : 'y', (current_function_calls_alloca) ? 'y' : 'n', (current_function_calls_setjmp) ? 'y' : 'n', (long)current_frame_info.total_size, (long)current_function_outgoing_args_size, num_gp_regs, num_fp_regs, dslots_load_total, dslots_load_filled, dslots_jump_total, dslots_jump_filled, num_refs[0], num_refs[1], num_refs[2]); if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs) { fprintf (stderr, " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs); prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS; } if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs) { fprintf (stderr, " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs); prev_half_pic_refs = HALF_PIC_NUMBER_REFS; } fputc ('\n', stderr); } /* Reset state info for each function. */ inside_function = FALSE; ignore_line_number = FALSE; dslots_load_total = 0; dslots_jump_total = 0; dslots_load_filled = 0; dslots_jump_filled = 0; num_refs[0] = 0; num_refs[1] = 0; num_refs[2] = 0; mips_load_reg = (rtx)0; mips_load_reg2 = (rtx)0; current_frame_info = zero_frame_info; /* Restore the output file if optimizing the GP (optimizing the GP causes the text to be diverted to a tempfile, so that data decls come before references to the data). */ if (TARGET_GP_OPT) asm_out_file = asm_out_data_file; } /* Expand the epilogue into a bunch of separate insns. */ void mips_expand_epilogue () { long tsize = current_frame_info.total_size; rtx tsize_rtx = GEN_INT (tsize); rtx tmp_rtx = (rtx)0; if (tsize > 32767) { tmp_rtx = gen_rtx (REG, SImode, MIPS_TEMP1_REGNUM); emit_move_insn (tmp_rtx, tsize_rtx); tsize_rtx = tmp_rtx; } if (tsize > 0) { if (frame_pointer_needed) emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx)); save_restore_insns (FALSE, tmp_rtx, tsize, (FILE *)0); emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, tsize_rtx)); } emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode, GP_REG_FIRST+31))); } /* Define the number of delay slots needed for the function epilogue. On the mips, we need a slot if either no stack has been allocated, or the only register saved is the return register. */ int mips_epilogue_delay_slots () { if (!current_frame_info.initialized) (void) compute_frame_size (get_frame_size ()); if (current_frame_info.total_size == 0) return 1; if (current_frame_info.mask == RA_MASK && current_frame_info.fmask == 0) return 1; return 0; } /* Return true if this function is known to have a null epilogue. This allows the optimizer to omit jumps to jumps if no stack was created. */ int simple_epilogue_p () { if (!reload_completed) return 0; if (current_frame_info.initialized) return current_frame_info.total_size == 0; return (compute_frame_size (get_frame_size ())) == 0; } gcc-2.5.8/config/mips/mips.h100444 22011 13 373016 5471623624 14404 0ustar kenneruser/* Definitions of target machine for GNU compiler. MIPS version. Copyright (C) 1989, 1990, 1991, 1992, 1993 Free Software Foundation, Inc. Contributed by A. Lichnewsky, lich@inria.inria.fr Changed by Michael Meissner, meissner@osf.org This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Make Saber happier on obstack.[ch]. */ #if defined(__mips__) || defined(mips) #define __PTR_TO_INT(P) ((int)(P)) #define __INT_TO_PTR(P) ((char *)(P)) #endif /* Standard GCC variables that we reference. */ extern char *asm_file_name; extern char call_used_regs[]; extern int current_function_calls_alloca; extern int flag_omit_frame_pointer; extern int frame_pointer_needed; extern char *language_string; extern int may_call_alloca; extern int optimize; extern char **save_argv; extern int target_flags; extern char *version_string; /* MIPS external variables defined in mips.c. */ /* comparison type */ enum cmp_type { CMP_SI, /* compare integers */ CMP_SF, /* compare single precision floats */ CMP_DF, /* compare double precision floats */ CMP_MAX /* max comparison type */ }; /* types of delay slot */ enum delay_type { DELAY_NONE, /* no delay slot */ DELAY_LOAD, /* load from memory delay */ DELAY_HILO, /* move from/to hi/lo registers */ DELAY_FCMP /* delay after doing c..{d,s} */ }; /* Which processor to schedule for. Since there is no difference between a R2000 and R3000 in terms of the scheduler, we collapse them into just an R3000. The elements of the enumeration must match exactly the cpu attribute in the mips.md machine description. */ enum processor_type { PROCESSOR_DEFAULT, PROCESSOR_R3000, PROCESSOR_R6000, PROCESSOR_R4000 }; /* Recast the cpu class to be the cpu attribute. */ #define mips_cpu_attr ((enum attr_cpu)mips_cpu) /* Whether to emit abicalls code sequences or not. */ enum mips_abicalls_type { MIPS_ABICALLS_NO, MIPS_ABICALLS_YES }; /* Recast the abicalls class to be the abicalls attribute. */ #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls) /* Which type of block move to do (whether or not the last store is split out so it can fill a branch delay slot). */ enum block_move_type { BLOCK_MOVE_NORMAL, /* generate complete block move */ BLOCK_MOVE_NOT_LAST, /* generate all but last store */ BLOCK_MOVE_LAST /* generate just the last store */ }; extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */ extern char mips_print_operand_punct[]; /* print_operand punctuation chars */ extern char *current_function_name; /* current function being compiled */ extern char *current_function_file; /* filename current function is in */ extern int num_source_filenames; /* current .file # */ extern int inside_function; /* != 0 if inside of a function */ extern int ignore_line_number; /* != 0 if we are to ignore next .loc */ extern int file_in_function_warning; /* warning given about .file in func */ extern int sdb_label_count; /* block start/end next label # */ extern int mips_section_threshold; /* # bytes of data/sdata cutoff */ extern int g_switch_value; /* value of the -G xx switch */ extern int g_switch_set; /* whether -G xx was passed. */ extern int sym_lineno; /* sgi next label # for each stmt */ extern int set_noreorder; /* # of nested .set noreorder's */ extern int set_nomacro; /* # of nested .set nomacro's */ extern int set_noat; /* # of nested .set noat's */ extern int set_volatile; /* # of nested .set volatile's */ extern int mips_branch_likely; /* emit 'l' after br (branch likely) */ extern int mips_dbx_regno[]; /* Map register # to debug register # */ extern char mips_rtx_classify[]; /* classify an RTX code */ extern struct rtx_def *branch_cmp[2]; /* operands for compare */ extern enum cmp_type branch_type; /* what type of branch to use */ extern enum processor_type mips_cpu; /* which cpu are we scheduling for */ extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */ extern int mips_isa; /* architectural level */ extern char *mips_cpu_string; /* for -mcpu= */ extern char *mips_isa_string; /* for -mips{1,2,3} */ extern int dslots_load_total; /* total # load related delay slots */ extern int dslots_load_filled; /* # filled load delay slots */ extern int dslots_jump_total; /* total # jump related delay slots */ extern int dslots_jump_filled; /* # filled jump delay slots */ extern int dslots_number_nops; /* # of nops needed by previous insn */ extern int num_refs[3]; /* # 1/2/3 word references */ extern struct rtx_def *mips_load_reg; /* register to check for load delay */ extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */ extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */ extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */ /* Functions within mips.c that we reference. */ extern void abort_with_insn (); extern int arith32_operand (); extern int arith_operand (); extern int cmp_op (); extern int cmp2_op (); extern long compute_frame_size (); extern int epilogue_reg_mentioned_p (); extern void expand_block_move (); extern int equality_op (); extern int fcmp_op (); extern void final_prescan_insn (); extern int fpsw_register_operand (); extern struct rtx_def * function_arg (); extern void function_arg_advance (); extern int function_arg_partial_nregs (); extern void function_epilogue (); extern void function_prologue (); extern void gen_conditional_branch (); extern struct rtx_def * gen_int_relational (); extern void init_cumulative_args (); extern int large_int (); extern int md_register_operand (); extern int mips_address_cost (); extern void mips_asm_file_end (); extern void mips_asm_file_start (); extern int mips_const_double_ok (); extern void mips_count_memory_refs (); extern int mips_debugger_offset (); extern void mips_declare_object (); extern int mips_epilogue_delay_slots (); extern void mips_expand_epilogue (); extern void mips_expand_prologue (); extern char *mips_fill_delay_slot (); extern char *mips_move_1word (); extern char *mips_move_2words (); extern void mips_output_double (); extern int mips_output_external (); extern void mips_output_float (); extern void mips_output_filename (); extern void mips_output_lineno (); extern char *output_block_move (); extern void override_options (); extern int pc_or_label_operand (); extern void print_operand_address (); extern void print_operand (); extern void print_options (); extern int reg_or_0_operand (); extern int simple_epilogue_p (); extern int simple_memory_operand (); extern int small_int (); extern void trace(); extern int uns_arith_operand (); extern int uns_cmp_op (); /* Recognition functions that return if a condition is true. */ extern int address_operand (); extern int const_double_operand (); extern int const_int_operand (); extern int general_operand (); extern int immediate_operand (); extern int memory_address_p (); extern int memory_operand (); extern int nonimmediate_operand (); extern int nonmemory_operand (); extern int register_operand (); extern int scratch_operand (); /* Functions to change what output section we are using. */ extern void data_section (); extern void rdata_section (); extern void readonly_data_section (); extern void sdata_section (); extern void text_section (); /* Functions in the rest of the compiler that we reference. */ extern void abort_with_insn (); extern void debug_rtx (); extern void fatal_io_error (); extern int get_frame_size (); extern int offsettable_address_p (); extern void output_address (); extern char *permalloc (); extern int reg_mentioned_p (); /* Functions in the standard library that we reference. */ extern int atoi (); extern char *getenv (); extern char *mktemp (); /* Stubs for half-pic support if not OSF/1 reference platform. */ #ifndef HALF_PIC_P #define HALF_PIC_P() 0 #define HALF_PIC_NUMBER_PTRS 0 #define HALF_PIC_NUMBER_REFS 0 #define HALF_PIC_ENCODE(DECL) #define HALF_PIC_DECLARE(NAME) #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.") #define HALF_PIC_ADDRESS_P(X) 0 #define HALF_PIC_PTR(X) X #define HALF_PIC_FINISH(STREAM) #endif /* Run-time compilation parameters selecting different hardware subsets. */ /* Macros used in the machine description to test the flags. */ /* Bits for real switches */ #define MASK_INT64 0x00000001 /* ints are 64 bits */ #define MASK_LONG64 0x00000002 /* longs are 64 bits */ #define MASK_LLONG128 0x00000004 /* long longs are 128 bits */ #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */ #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */ #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */ #define MASK_STATS 0x00000040 /* print statistics to stderr */ #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/ #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */ #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */ #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */ #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/ #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */ #define MASK_UNUSED1 0x00002000 #define MASK_UNUSED2 0x00004000 #define MASK_UNUSED3 0x00008000 #define MASK_UNUSED4 0x00010000 #define MASK_UNUSED5 0x00020000 #define MASK_UNUSED6 0x00040000 #define MASK_UNUSED7 0x00080000 /* Dummy switches used only in spec's*/ #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */ /* Debug switches, not documented */ #define MASK_DEBUG 0x40000000 /* Eliminate version # in .s file */ #define MASK_DEBUG_A 0x20000000 /* don't allow