test: ia64/flush.c File Reference

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# flush.c File Reference

`#include "ki.h"`
`#include "kxia64.h"`

Go to the source code of this file.

## Functions

VOID | KiSweepDcacheTarget (IN PULONG SignalDone, IN PVOID Parameter1, IN PVOID Parameter2, IN PVOID Parameter3)
VOID | KiSweepIcacheTarget (IN PULONG SignalDone, IN PVOID Parameter1, IN PVOID Parameter2, IN PVOID Parameter3)
VOID | KiFlushIoBuffersTarget (IN PKIPI_CONTEXT SignalDone, IN PVOID Mdl, IN PVOID ReadOperation, IN PVOID DmaOperation)
VOID | KiSyncCacheTarget (IN PKIPI_CONTEXT SignalDone, IN PVOID Parameter1, IN PVOID Parameter2, IN PVOID Parameter3)
ULONG_PTR | KiSyncMC_DrainTarget ()
ULONG_PTR | KiSyncMC_Drain (IN BOOLEAN AllProcessors, IN PVOID BaseAddress, IN ULONG Length)
ULONG_PTR | KiSyncPrefetchVisibleTarget ()
ULONG_PTR | KiSyncPrefetchVisible (IN BOOLEAN AllProcessors, IN PVOID BaseAddress, IN ULONG Length)
VOID | KeSweepIcache (IN BOOLEAN AllProcessors)
VOID | KeSweepDcache (IN BOOLEAN AllProcessors)
VOID | KeSweepCacheRange (IN BOOLEAN AllProcessors, IN PVOID BaseAddress, IN ULONG Length)
VOID | KeSweepIcacheRange (IN BOOLEAN AllProcessors, IN PVOID BaseAddress, IN ULONG Length)
VOID | KeSweepDcacheRange (IN BOOLEAN AllProcessors, IN PVOID BaseAddress, IN ULONG Length)
VOID | KeSweepCacheRangeWithDrain (IN BOOLEAN AllProcessors, IN PVOID BaseAddress, IN ULONG Length)

## Variables

ULONG | ProbePalVisibilitySupport = 1
ULONG | NeedPalVisibilitySupport = 1
KSPIN_LOCK | KiCacheFlushLock

## Function Documentation

VOID KeSweepCacheRange | ( | IN BOOLEAN | AllProcessors,
|  | IN PVOID | BaseAddress,
|  | IN ULONG | Length
| ) |

Definition at line 453 of file ia64/flush.c.

References ASSERT, KeActiveProcessors, KeLowerIrql(), KiIpiSendPacket(), KiIpiStallOnPacketTargets(), KiSyncCacheTarget(), and NULL.

Referenced by KeSweepCacheRangeWithDrain().

    00461                    :
    00462
    00463     This function is used to flush a range of virtual addresses from both the
    00464     instruction and data cache on all processors in the system.
    00465
    00466     Irrespective of the length of the range, it should not call SweepIcache
    00467     or SweepDcache. This is because SweepDcache will only sweep D cache and
    00468     not the I cache and Vice versa. Since the caller of KeSweepCacheRange assumes
    00469     both the caches are being swept, one cannot call SweepIcache or SweepDcache
    00470     in trying to optimize.
    00471
    00472
    00473     Arguments:
    00474
    00475     AllProcessors - Not used
    00476
    00477     BaseAddress - Supplies a pointer to the base of the range that is flushed.
    00478
    00479     Length - Supplies the length of the range that is flushed if the base
    00480         address is specified.
    00481
    00482     Return Value:
    00483
    00484         None.
    00485
    00486
    00487 --*/
    00488
    00489 {
    00490      KIRQL OldIrql;
    00491      KAFFINITY TargetProcessors;
    00492
    00493     //
    00494     // We will not raise IRQL to synchronization level so that we can allow
    00495     // a context switch in between Flush Cache. FC need not run in the same processor
    00496     // throughout. It can be context switched. So no binding is done to any processor.
    00497     //
    00498     //
    00499
    00500     HalSweepCacheRange(BaseAddress,Length);
    00501
    00502     ASSERT(KeGetCurrentIrql() <= KiSynchIrql);
    00503
    00504     //
    00505     // Raise IRQL to synchronization level to prevent a context switch.
    00506     //
    00507
    00508 #if !defined(NT_UP)
    00509
    00510     OldIrql = KeRaiseIrqlToSynchLevel();
    00511
    00512     //
    00513     // Compute the set of target processors and send the sync parameters
    00514     // to the target processors, if any, for execution.
    00515     //
    00516
    00517     TargetProcessors = KeActiveProcessors & PCR->NotMember;
    00518     if (TargetProcessors != 0) {
    00519     KiIpiSendPacket(TargetProcessors,
    00520                     KiSyncCacheTarget,
    00521                     NULL,
    00522                     NULL,
    00523                     NULL);
    00524     }
    00525
    00526 #endif
    00527
    00528     //
    00529     // Synchronize the Instruction Prefetch pipe in the local processor.
    00530     //
    00531
    00532     __synci();
    00533     __isrlz();
    00534
    00535     //
    00536     // Wait until all target processors have finished sweeping the their
    00537     // data cache.
    00538     //
    00539
    00540 #if !defined(NT_UP)
    00541
    00542     if (TargetProcessors != 0) {
    00543         KiIpiStallOnPacketTargets(TargetProcessors);
    00544     }
    00545
    00546     //
    00547     // Lower IRQL to its previous level and return.
    00548     //
    00549
    00550     KeLowerIrql(OldIrql);
    00551
    00552 #endif
    00553
    00554     return;
    00555
    00556 }

VOID KeSweepCacheRangeWithDrain | ( | IN BOOLEAN | AllProcessors,
|  | IN PVOID | BaseAddress,
|  | IN ULONG | Length
| ) |

Definition at line 979 of file ia64/flush.c.

References ASSERT, KeSweepCacheRange(), KiSyncMC_Drain(), KiSyncPrefetchVisible(), and Status.

Referenced by MiSweepCacheMachineDependent().

    00987                    :
    00988
    00989     This function is used to drain prefetches,demand references followed by flushing
    00990     the cache followed by draining pending fc cache line evictions to a specified range
    00991     address in all processors in the system.
    00992
    00993
    00994 Arguments:
    00995
    00996     AllProcessors -  All processors in the system.
    00997
    00998     BaseAddress - Supplies a pointer to the base of the range that is flushed and drained.
    00999
    01000     Length - Supplies the length of the range that is flushed and drained for the base
    01001         address is specified.
    01002
    01003 Return Value:
    01004
    01005     None.
    01006
    01007     Note:  This is used when changing attributes of WB pages to UC pages.
    01008
    01009 --*/
    01010
    01011 {
    01012     ULONG_PTR Status;
    01013
    01014     Status = KiSyncPrefetchVisible(
    01015                  AllProcessors,
    01016                  BaseAddress,
    01017                  Length
    01018                  );
    01019
    01020     ASSERT(Status != PAL_STATUS_ERROR);
    01021
    01022
    01023     KeSweepCacheRange (
    01024         AllProcessors,
    01025         BaseAddress,
    01026         Length
    01027         );
    01028
    01029     Status = KiSyncMC_Drain (
    01030                  AllProcessors,
    01031                  BaseAddress,
    01032                  Length
    01033                  );
    01034
    01035     ASSERT(Status == PAL_STATUS_SUCCESS);
    01036
    01037     return;
    01038
    01039
    01040 }

VOID KeSweepDcache | ( | IN BOOLEAN | AllProcessors | ) |

Definition at line 276 of file ia64/flush.c.

References ASSERT, DISPATCH_LEVEL, KeAcquireSpinLock, KeActiveProcessors, KeReleaseSpinLock(), KiCacheFlushLock, KiIpiSendPacket(), KiIpiStallOnPacketTargets(), KiSweepDcacheTarget(), and NULL.

    00282                    :
    00283
    00284     This function flushes the data cache on all processors that are currently
    00285     running threads which are children of the current process or flushes the
    00286     data cache on all processors in the host configuration.
    00287
    00288     N.B. PowerPC maintains cache coherency across processors however
    00289     in this routine, the range of addresses being flushed is unknown
    00290     so we must still broadcast the request to the other processors.
    00291
    00292 Arguments:
    00293
    00294     AllProcessors - Supplies a boolean value that determines which data
    00295         caches are flushed.
    00296
    00297 Return Value:
    00298
    00299     None.
    00300
    00301 --*/
    00302
    00303 {
    00304
    00305     KIRQL OldIrql;
    00306     KAFFINITY TargetProcessors;
    00307
    00308     ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);
    00309
    00310 #if !defined(NT_UP)
    00311     //
    00312     // Acquire cache flush spinlock
    00313     // Cache flush is not MP safe yet
    00314     //
    00315     KeAcquireSpinLock(&KiCacheFlushLock, &OldIrql);
    00316
    00317 #endif
    00318
    00319     HalSweepDcache();
    00320
    00321 #if !defined(NT_UP)
    00322
    00323     //
    00324     // Compute the set of target processors and send the sweep parameters
    00325     // to the target processors, if any, for execution.
    00326     //
    00327
    00328     TargetProcessors = KeActiveProcessors & PCR->NotMember;
    00329     if (TargetProcessors != 0) {
    00330         KiIpiSendPacket(TargetProcessors,
    00331                         KiSweepDcacheTarget,
    00332                         NULL,
    00333                         NULL,
    00334                         NULL);
    00335     }
    00336
    00337
    00338     //
    00339     // Wait until all target processors have finished sweeping their
    00340     // data caches.
    00341     //
    00342
    00343
    00344     if (TargetProcessors != 0) {
    00345         KiIpiStallOnPacketTargets(TargetProcessors);
    00346     }
    00347
    00348     //
    00349     // Lower IRQL to its previous level and return.
    00350     //
    00351
    00352     KeReleaseSpinLock(&KiCacheFlushLock, OldIrql);
    00353
    00354 #endif
    00355
    00356     return;
    00357 }

VOID KeSweepDcacheRange | ( | IN BOOLEAN | AllProcessors,
|  | IN PVOID | BaseAddress,
|  | IN ULONG | Length
| ) |

Definition at line 674 of file ia64/flush.c.

References ASSERT, KeActiveProcessors, KeLowerIrql(), KiIpiSendPacket(), KiIpiStallOnPacketTargets(), KiSyncCacheTarget(), and NULL.

    00682                    :
    00683
    00684     This function is used to flush a range of virtual addresses from the
    00685     primary data cache on all processors in the host configuration.
    00686
    00687      If the length of the range is greater than the size of the
    00688     data cache, then one can call HalSweepDcache which calls
    00689     SAL to flush the entire cache. Since SAL does not take care of MP
    00690     flushing, HalSweepDcache has to use IPI mechanism to execute SAL
    00691     flush from each processor. We need to weight the overhead of all these
    00692     versus using HalSweepDcacheRange and avoiding IPI mechanism since
    00693     HalSweepDcacheRange uses fc instruction and fc instruction takes care of MP.
    00694
    00695 Arguments:
    00696
    00697     AllProcessors -  Not used
    00698
    00699     BaseAddress - Supplies a pointer to the base of the range that is flushed.
    00700
    00701     Length - Supplies the length of the range that is flushed if the base
    00702         address is specified.
    00703
    00704 Return Value:
    00705
    00706     None.
    00707
    00708     Note:  For performance reason, we may update KeSweepDcacheRange to do the following:
    00709            if the range asked to sweep is very large, we may call KeSweepDcache to flush
    00710            the full cache.
    00711
    00712
    00713
    00714 --*/
    00715
    00716 {
    00717     KIRQL OldIrql;
    00718     KAFFINITY TargetProcessors;
    00719
    00720     //
    00721     // We will not raise IRQL to synchronization level so that we can allow
    00722     // a context switch in between Flush Cache. FC need not run in the same processor
    00723     // throughout. It can be context switched. So no binding is done to any processor.
    00724     //
    00725     //
    00726
    00727     HalSweepDcacheRange(BaseAddress,Length);
    00728
    00729     ASSERT(KeGetCurrentIrql() <= KiSynchIrql);
    00730
    00731     //
    00732     // Raise IRQL to synchronization level to prevent a context switch.
    00733     //
    00734
    00735 #if !defined(NT_UP)
    00736
    00737     OldIrql = KeRaiseIrqlToSynchLevel();
    00738
    00739     //
    00740     // Compute the set of target processors and send the sync parameters
    00741     // to the target processors, if any, for execution.
    00742     //
    00743
    00744     TargetProcessors = KeActiveProcessors & PCR->NotMember;
    00745     if (TargetProcessors != 0) {
    00746         KiIpiSendPacket(TargetProcessors,
    00747             KiSyncCacheTarget,
    00748             NULL,
    00749             NULL,
    00750             NULL);
    00751     }
    00752
    00753 #endif
    00754
    00755     //
    00756     // Synchronize the Instruction Prefetch pipe in the local processor.
    00757     //
    00758
    00759     __synci();
    00760     __isrlz();
    00761
    00762     //
    00763     // Wait until all target processors have finished sweeping the their
    00764     // data cache.
    00765     //
    00766
    00767 #if !defined(NT_UP)
    00768
    00769     if (TargetProcessors != 0) {
    00770         KiIpiStallOnPacketTargets(TargetProcessors);
    00771     }
    00772
    00773     //
    00774     // Lower IRQL to its previous level and return.
    00775     //
    00776
    00777     KeLowerIrql(OldIrql);
    00778
    00779 #endif
    00780
    00781     return;
    00782
    00783
    00784 }

VOID KeSweepIcache | ( | IN BOOLEAN | AllProcessors | ) |

Definition at line 143 of file ia64/flush.c.

References ASSERT, DISPATCH_LEVEL, KeAcquireSpinLock, KeActiveProcessors, KeReleaseSpinLock(), KiCacheFlushLock, KiIpiSendPacket(), KiIpiStallOnPacketTargets(), KiSweepIcacheTarget(), and NULL.

    00149                    :
    00150
    00151     This function flushes the instruction cache on all processors that are
    00152     currently running threads which are children of the current process or
    00153     flushes the instruction cache on all processors in the host configuration.
    00154
    00155     N.B. Although PowerPC maintains cache coherency across processors, we
    00156     use the flash invalidate function (h/w) for I-Cache sweeps which doesn't
    00157     maintain coherency so we still do the MP I-Cache flush in s/w.   plj.
    00158
    00159 Arguments:
    00160
    00161     AllProcessors - Supplies a boolean value that determines which instruction
    00162         caches are flushed.
    00163
    00164 Return Value:
    00165
    00166     None.
    00167
    00168 --*/
    00169
    00170 {
    00171
    00172     KIRQL OldIrql;
    00173     KAFFINITY TargetProcessors;
    00174
    00175     ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);
    00176
    00177 #if !defined(NT_UP)
    00178     //
    00179     // Acquire cache flush spinlock
    00180     // Cache flush is not MP safe yet
    00181     //
    00182     KeAcquireSpinLock(&KiCacheFlushLock, &OldIrql);
    00183
    00184 #endif
    00185
    00186     HalSweepDcache();
    00187     HalSweepIcache();
    00188
    00189 #if !defined(NT_UP)
    00190
    00191     //
    00192     // Compute the set of target processors and send the sweep parameters
    00193     // to the target processors, if any, for execution.
    00194     //
    00195
    00196     TargetProcessors = KeActiveProcessors & PCR->NotMember;
    00197     if (TargetProcessors != 0) {
    00198         KiIpiSendPacket(TargetProcessors,
    00199                         KiSweepIcacheTarget,
    00200                         NULL,
    00201                         NULL,
    00202                         NULL);
    00203     }
    00204
    00205
    00206     //
    00207     // Wait until all target processors have finished sweeping their
    00208     // instruction caches.
    00209     //
    00210
    00211
    00212     if (TargetProcessors != 0) {
    00213         KiIpiStallOnPacketTargets(TargetProcessors);
    00214     }
    00215
    00216     //
    00217     // Lower IRQL to its previous level and return.
    00218     //
    00219
    00220     KeReleaseSpinLock(&KiCacheFlushLock, OldIrql);
    00221
    00222 #endif
    00223
    00224     return;
    00225 }

VOID KeSweepIcacheRange | ( | IN BOOLEAN | AllProcessors,
|  | IN PVOID | BaseAddress,
|  | IN ULONG | Length
| ) |

Definition at line 559 of file ia64/flush.c.

References ASSERT, KeActiveProcessors, KeLowerIrql(), KiIpiSendPacket(), KiIpiStallOnPacketTargets(), KiSyncCacheTarget(), and NULL.

    00567                    :
    00568
    00569     This function is used to flush a range of virtual addresses from the
    00570     primary instruction cache on all processors in the host configuration.
    00571
    00572      If the length of the range is greater than the size of the
    00573     instruction cache, then one can call HalSweepIcache which calls
    00574     SAL to flush the entire cache. Since SAL does not take care of MP
    00575     flushing, HalSweepIcache has to use IPI mechanism to execute SAL
    00576     flush from each processor. We need to weight the overhead of all these
    00577     versus using HalSweepIcacheRange and avoiding IPI mechanism since
    00578     HalSweepIcacheRange uses fc instruction and fc instruction takes care of MP.
    00579
    00580 Arguments:
    00581
    00582     AllProcessors -  Not used
    00583
    00584     BaseAddress - Supplies a pointer to the base of the range that is flushed.
    00585
    00586     Length - Supplies the length of the range that is flushed if the base
    00587         address is specified.
    00588
    00589 Return Value:
    00590
    00591     None.
    00592
    00593     Note:  For performance reason, we may update KeSweepIcacheRange to do the following:
    00594            if the range asked to sweep is very large, we may call KeSweepIcache to flush
    00595            the full cache.
    00596
    00597
    00598
    00599 --*/
    00600
    00601 {
    00602     KIRQL OldIrql;
    00603     KAFFINITY TargetProcessors;
    00604
    00605     //
    00606     // We will not raise IRQL to synchronization level so that we can allow
    00607     // a context switch in between Flush Cache. FC need not run in the same processor
    00608     // throughout. It can be context switched. So no binding is done to any processor.
    00609     //
    00610     //
    00611
    00612     HalSweepIcacheRange(BaseAddress,Length);
    00613
    00614     ASSERT(KeGetCurrentIrql() <= KiSynchIrql);
    00615
    00616     //
    00617     // Raise IRQL to synchronization level to prevent a context switch.
    00618     //
    00619
    00620 #if !defined(NT_UP)
    00621
    00622     OldIrql = KeRaiseIrqlToSynchLevel();
    00623
    00624     //
    00625     // Compute the set of target processors and send the sync parameters
    00626     // to the target processors, if any, for execution.
    00627     //
    00628
    00629     TargetProcessors = KeActiveProcessors & PCR->NotMember;
    00630     if (TargetProcessors != 0) {
    00631         KiIpiSendPacket(TargetProcessors,
    00632             KiSyncCacheTarget,
    00633             NULL,
    00634             NULL,
    00635             NULL);
    00636     }
    00637
    00638 #endif
    00639
    00640     //
    00641     // Synchronize the Instruction Prefetch pipe in the local processor.
    00642     //
    00643
    00644     __synci();
    00645     __isrlz();
    00646
    00647     //
    00648     // Wait until all target processors have finished sweeping the their
    00649     // data cache.
    00650     //
    00651
    00652 #if !defined(NT_UP)
    00653
    00654     if (TargetProcessors != 0) {
    00655         KiIpiStallOnPacketTargets(TargetProcessors);
    00656     }
    00657
    00658     //
    00659     // Lower IRQL to its previous level and return.
    00660     //
    00661
    00662     KeLowerIrql(OldIrql);
    00663
    00664 #endif
    00665
    00666     return;
    00667
    00668
    00669 }

VOID KiFlushIoBuffersTarget | ( | IN PKIPI_CONTEXT | SignalDone,
|  | IN PVOID | Mdl,
|  | IN PVOID | ReadOperation,
|  | IN PVOID | DmaOperation
| ) |

VOID KiSweepDcacheTarget | ( | IN PULONG | SignalDone,
|  | IN PVOID | Parameter1,
|  | IN PVOID | Parameter2,
|  | IN PVOID | Parameter3
| ) |

Definition at line 360 of file ia64/flush.c.

References KiIpiSignalPacketDone().

    00369                    :
    00370
    00371     This is the target function for sweeping the data cache on target
    00372     processors.
    00373
    00374 Arguments:
    00375
    00376     SignalDone Supplies a pointer to a variable that is cleared when the
    00377         requested operation has been performed.
    00378
    00379     Parameter1 - Parameter3 - Not used.
    00380
    00381 Return Value:
    00382
    00383     None.
    00384
    00385 --*/
    00386
    00387 {
    00388
    00389     //
    00390     // Sweep the data cache on the current processor and clear the sweep
    00391     // data cache packet address to signal the source to continue.
    00392     //
    00393
    00394 #if !defined(NT_UP)
    00395
    00396     HalSweepDcache();
    00397     KiIpiSignalPacketDone(SignalDone);
    00398
    00399 #endif
    00400
    00401     return;
    00402 }

VOID KiSweepIcacheTarget | ( | IN PULONG | SignalDone,
|  | IN PVOID | Parameter1,
|  | IN PVOID | Parameter2,
|  | IN PVOID | Parameter3
| ) |

Definition at line 228 of file ia64/flush.c.

References KiIpiSignalPacketDone().

    00237                    :
    00238
    00239     This is the target function for sweeping the instruction cache on
    00240     target processors.
    00241
    00242 Arguments:
    00243
    00244     SignalDone Supplies a pointer to a variable that is cleared when the
    00245         requested operation has been performed.
    00246
    00247     Parameter1 - Parameter3 - Not used.
    00248
    00249 Return Value:
    00250
    00251     None.
    00252
    00253 --*/
    00254
    00255 {
    00256
    00257     //
    00258     // Sweep the instruction cache on the current processor and clear
    00259     // the sweep instruction cache packet address to signal the source
    00260     // to continue.
    00261     //
    00262
    00263 #if !defined(NT_UP)
    00264
    00265     HalSweepDcache();
    00266     HalSweepIcache();
    00267
    00268     KiIpiSignalPacketDone(SignalDone);
    00269
    00270 #endif
    00271
    00272     return;
    00273 }

VOID KiSyncCacheTarget | ( | IN PKIPI_CONTEXT | SignalDone,
|  | IN PVOID | Parameter1,
|  | IN PVOID | Parameter2,
|  | IN PVOID | Parameter3
| ) |

Definition at line 103 of file ia64/flush.c.

References KiIpiSignalPacketDone().

Referenced by KeSweepCacheRange(), KeSweepDcacheRange(), and KeSweepIcacheRange().

    00111                    :
    00112
    00113     This function synchronizes the I-fetch pipeline. Typically this routine will be
    00114     executed by every processor in the system in response to an IPI after the cache
    00115     is flushed. Each processor executing RFI while leaving the IPI produces the
    00116     serialization effect that is required after isync to make sure that further
    00117     instruction prefetches wait till the ISYNC completes.
    00118
    00119 Arguements:
    00120
    00121     SignalDone Supplies a pointer to a variable that is cleared when the
    00122     requested operation has been performed.
    00123
    00124     Parameter1 - Parameter3 - Not used.
    00125
    00126 Return Value:
    00127
    00128     Nothing.
    00129 --*/
    00130 {
    00131
    00132 #if !defined(NT_UP)
    00133
    00134     __synci();
    00135     KiIpiSignalPacketDone(SignalDone);
    00136
    00137 #endif
    00138     return;
    00139
    00140 }

ULONG_PTR KiSyncMC_Drain | ( | IN BOOLEAN | AllProcessors,
|  | IN PVOID | BaseAddress,
|  | IN ULONG | Length
| ) |

Definition at line 787 of file ia64/flush.c.

References ASSERT, KiIpiGenericCall(), KiSyncMC_DrainTarget(), NULL, PKIPI_BROADCAST_WORKER, and Status.

Referenced by KeSweepCacheRangeWithDrain().

    00795                    :
    00796
    00797     KiSyncMC_Drain issues  PAL_MC_DRAIN to drain either prefetches, demand references
    00798     or pending fc cache line evictions to all the processors in the system.
    00799     DrainTypePointer points to the variable, DrainType, which determines the type of
    00800     drain to be performed. This is typically used when changing the memory attribute
    00801     from WB to UC.
    00802
    00803 Arguments:
    00804
    00805     AllProcessors - All processors in the system.
    00806
    00807     BaseAddress - Supplies a pointer to the base of the range that is to be drained.
    00808
    00809     Length - Supplies the length of the range that is drained for the base
    00810         address specified.
    00811
    00812 Return Value:
    00813
    00814     Note:  This is used when changing attributes of WB pages to UC pages.
    00815
    00816
    00817 --*/
    00818
    00819 {
    00820     ULONG_PTR Status;
    00821     //
    00822     // KiIpiGenericCall returns ULONG_PTR as the function value of the specified function
    00823     //
    00824
    00825     Status = (KiIpiGenericCall (
    00826                 (PKIPI_BROADCAST_WORKER)KiSyncMC_DrainTarget,
    00827                 (ULONG_PTR)NULL)
    00828                 );
    00829
    00830     ASSERT(Status == PAL_STATUS_SUCCESS);
    00831
    00832     return Status;
    00833
    00834
    00835 }

ULONG_PTR KiSyncMC_DrainTarget | ( |  | ) |

Definition at line 407 of file ia64/flush.c.

References ASSERT, and Status.

Referenced by KiSyncMC_Drain().

    00412                    :
    00413
    00414     This is the target function for issuing PAL_MC_DRAIN to drain
    00415     prefetches, demand references and pending fc cache line evictions on the
    00416     target CPU it executes.
    00417
    00418 Argument:
    00419
    00420     None
    00421
    00422
    00423 Return Value:
    00424
    00425    Returns the status from the function HalCallPal
    00426
    00427 --*/
    00428
    00429 {
    00430     ULONG_PTR Status;
    00431
    00432     //
    00433     // Call HalCallPal to drain.
    00434     //
    00435
    00436     Status = HalCallPal(PAL_MC_DRAIN,
    00437         0,
    00438         0,
    00439         0,
    00440         0,
    00441         0,
    00442         0,
    00443         0);
    00444
    00445     ASSERT(Status == PAL_STATUS_SUCCESS);
    00446
    00447     return Status;
    00448
    00449 }

ULONG_PTR KiSyncPrefetchVisible | ( | IN BOOLEAN | AllProcessors,
|  | IN PVOID | BaseAddress,
|  | IN ULONG | Length
| ) |

Definition at line 885 of file ia64/flush.c.

References ASSERT, KiIpiGenericCall(), KiSyncPrefetchVisibleTarget(), NeedPalVisibilitySupport, NULL, PKIPI_BROADCAST_WORKER, ProbePalVisibilitySupport, and Status.

Referenced by KeSweepCacheRangeWithDrain().

    00893                    :
    00894
    00895     KiSyncPrefetchVisible issues  PAL_PREFETCH_VISIBILITY to cause the processor to make
    00896     all pending prefetches visible to subsequent fc instructions; or does nothing, on
    00897     processor implementations which does not require PAL support for disabling prefetch
    00898     in the architectural sequence. On processors that require PAL support for this
    00899     sequence, the actions performed by this procedure may include any or all
    00900     of the following (or none, as long as the processor guarantees that
    00901     prefetches that were issued prior to this call are not resident in the
    00902     processor's caches after the architected sequence is complete.
    00903     This is typically used when changing the memory attribute from WB to UC.
    00904
    00905 Arguments:
    00906
    00907     AllProcessors - All processors in the system.
    00908
    00909     BaseAddress - Supplies a pointer to the base of the range that is to be drained.
    00910
    00911     Length - Supplies the length of the range that is drained for the base
    00912         address specified.
    00913
    00914 Return Value:
    00915
    00916     Status of the PAL CALL
    00917       0  Success
    00918       1  Call not needed
    00919       -3 Error returned
    00920
    00921     Note:  This is used when changing attributes of WB pages to UC pages.
    00922
    00923
    00924 --*/
    00925
    00926 {
    00927     ULONG_PTR Status;
    00928
    00929     switch (ProbePalVisibilitySupport) {
    00930         case 0:
    00931             if (NeedPalVisibilitySupport == 0)
    00932                return PAL_STATUS_SUPPORT_NOT_NEEDED;
    00933             else {
    00934                Status = (KiIpiGenericCall (
    00935                             (PKIPI_BROADCAST_WORKER)KiSyncPrefetchVisibleTarget,
    00936                             (ULONG_PTR)NULL)
    00937                             );
    00938
    00939                 ASSERT(Status != PAL_STATUS_ERROR);
    00940                 return Status;
    00941
    00942             }
    00943             break;
    00944
    00945         case 1:
    00946             Status = KiSyncPrefetchVisibleTarget();
    00947
    00948             ASSERT(Status != PAL_STATUS_ERROR);
    00949
    00950             ProbePalVisibilitySupport = 0;
    00951
    00952             if (Status == PAL_STATUS_SUPPORT_NOT_NEEDED) {
    00953                 NeedPalVisibilitySupport = 0;
    00954                 return PAL_STATUS_SUPPORT_NOT_NEEDED;
    00955             } else {
    00956
    00957
    00958                 Status = (KiIpiGenericCall (
    00959                             (PKIPI_BROADCAST_WORKER)KiSyncPrefetchVisibleTarget,
    00960                             (ULONG_PTR)NULL)
    00961                             );
    00962
    00963                 ASSERT(Status != PAL_STATUS_ERROR);
    00964
    00965                 return Status;
    00966
    00967             }
    00968
    00969             break;
    00970
    00971     }
    00972
    00973
    00974 }

ULONG_PTR KiSyncPrefetchVisibleTarget | ( |  | ) |

Definition at line 838 of file ia64/flush.c.

References ASSERT, and Status.

Referenced by KiSyncPrefetchVisible().

    00843                    :
    00844
    00845     This is the target function for issuing PAL_PREFETCH VISIBILITY
    00846     on the target CPU it executes.
    00847
    00848 Argument:
    00849
    00850     Not used.
    00851
    00852
    00853 Return Value:
    00854
    00855    Returns the status from the function HalCallPal
    00856
    00857 --*/
    00858
    00859 {
    00860     ULONG_PTR Status;
    00861
    00862     //
    00863     // Call HalCallPal to drain.
    00864     //
    00865
    00866     Status = HalCallPal(PAL_PREFETCH_VISIBILITY,
    00867         0,
    00868         0,
    00869         0,
    00870         0,
    00871         0,
    00872         0,
    00873         0);
    00874
    00875
    00876     ASSERT(Status != PAL_STATUS_ERROR);
    00877
    00878     return Status;
    00879
    00880 }

## Variable Documentation

KSPIN_LOCK KiCacheFlushLock

| Definition at line 39 of file ia64/flush.c. Referenced by KeSweepDcache(), KeSweepIcache(), and KiInitializeKernel().

ULONG NeedPalVisibilitySupport = 1

| Definition at line 38 of file ia64/flush.c. Referenced by KiSyncPrefetchVisible().

ULONG ProbePalVisibilitySupport = 1

| Definition at line 37 of file ia64/flush.c. Referenced by KiSyncPrefetchVisible().