test: axp21066.h Source File

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# axp21066.h

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    00001 /*++ BUILD Version: 0000     Increment this if a change has global effects
    00002
    00003 Copyright (c) 1993 Digital Euipment Corporation
    00004
    00005 Module Name:
    00006
    00007     axp21066.h
    00008
    00009 Abstract:
    00010
    00011     This module defines the DECchip 21066-specific structures that are
    00012     defined in the PAL but must be visible to the HAL.
    00013
    00014 Revision History:
    00015
    00016 --*/
    00017
    00018 #ifndef _AXP21066_
    00019 #define _AXP21066_
    00020
    00021
    00022 #ifndef CORE_21064
    00023 #define CORE_21064
    00024
    00025 //
    00026 // Define the "special" processor bus used by all machines that run a
    00027 // DECchip 21064.  The processor bus is used to access the internal
    00028 // performance counters.
    00029 //
    00030
    00031 #define PROCESSOR_BUS_21064 21064
    00032
    00033 //
    00034 // Define the number of entries for repeated internal processor registers.
    00035 //
    00036
    00037 #define ITB_ENTRIES_21064 12
    00038 #define DTB_ENTRIES_21064 32
    00039 #define PAL_TEMPS_21064   32
    00040
    00041 //
    00042 // Define an interrupt enable table entry.
    00043 //
    00044
    00045 typedef struct _IETEntry_21064{
    00046     ULONG ApcEnable: 1;
    00047     ULONG DispatchEnable: 1;
    00048     ULONG PerformanceCounter0Enable: 1;
    00049     ULONG PerformanceCounter1Enable: 1;
    00050     ULONG CorrectableReadEnable: 1;
    00051     ULONG Irq0Enable: 1;
    00052     ULONG Irq1Enable: 1;
    00053     ULONG Irq2Enable: 1;
    00054     ULONG Irq3Enable: 1;
    00055     ULONG Irq4Enable: 1;
    00056     ULONG Irq5Enable: 1;
    00057     ULONG Reserved: 21;
    00058 } IETEntry_21064, *PIETEntry_21064;
    00059
    00060
    00061 //
    00062 // Define the offsets and sizes of the mask sub-tables within the interrupt
    00063 // mask table in the PCR.
    00064 //
    00065
    00066 #define IRQLMASK_HDW_SUBTABLE_21064 (8)
    00067 #define IRQLMASK_HDW_SUBTABLE_21064_ENTRIES (64)
    00068
    00069 #define IRQLMASK_SFW_SUBTABLE_21064 (0)
    00070 #define IRQLMASK_SFW_SUBTABLE_21064_ENTRIES (4)
    00071
    00072 #define IRQLMASK_PC_SUBTABLE_21064  (4)
    00073 #define IRQLMASK_PC_SUBTABLE_21064_ENTRIES (4)
    00074
    00075 //
    00076 // PALcode Event Counters for the 21064
    00077 // This is the structure of the data returned by the rdcounters call pal.
    00078 //
    00079
    00080 typedef struct _COUNTERS_21064{
    00081     LARGE_INTEGER MachineCheckCount;
    00082     LARGE_INTEGER ArithmeticExceptionCount;
    00083     LARGE_INTEGER InterruptCount;
    00084     LARGE_INTEGER ItbMissCount;
    00085     LARGE_INTEGER NativeDtbMissCount;
    00086     LARGE_INTEGER PalDtbMissCount;
    00087     LARGE_INTEGER ItbAcvCount;
    00088     LARGE_INTEGER DtbAcvCount;
    00089     LARGE_INTEGER UnalignedCount;
    00090     LARGE_INTEGER OpcdecCount;
    00091     LARGE_INTEGER FenCount;
    00092     LARGE_INTEGER ItbTnvCount;
    00093     LARGE_INTEGER DtbTnvCount;
    00094     LARGE_INTEGER PteMissCount;
    00095     LARGE_INTEGER KspMissCount;
    00096     LARGE_INTEGER PdeTnvCount;
    00097     LARGE_INTEGER HaltCount;
    00098     LARGE_INTEGER RestartCount;
    00099     LARGE_INTEGER DrainaCount;
    00100     LARGE_INTEGER InitpalCount;
    00101     LARGE_INTEGER WrentryCount;
    00102     LARGE_INTEGER SwpirqlCount;
    00103     LARGE_INTEGER RdirqlCount;
    00104     LARGE_INTEGER DiCount;
    00105     LARGE_INTEGER EiCount;
    00106     LARGE_INTEGER SwppalCount;
    00107     LARGE_INTEGER SsirCount;
    00108     LARGE_INTEGER CsirCount;
    00109     LARGE_INTEGER RfeCount;
    00110     LARGE_INTEGER RetsysCount;
    00111     LARGE_INTEGER SwpctxCount;
    00112     LARGE_INTEGER SwpprocessCount;
    00113     LARGE_INTEGER RdmcesCount;
    00114     LARGE_INTEGER WrmcesCount;
    00115     LARGE_INTEGER TbiaCount;
    00116     LARGE_INTEGER TbisCount;
    00117     LARGE_INTEGER DtbisCount;
    00118     LARGE_INTEGER RdkspCount;
    00119     LARGE_INTEGER SwpkspCount;
    00120     LARGE_INTEGER RdpsrCount;
    00121     LARGE_INTEGER RdpcrCount;
    00122     LARGE_INTEGER RdthreadCount;
    00123     LARGE_INTEGER RdcountersCount;
    00124     LARGE_INTEGER RdstateCount;
    00125     LARGE_INTEGER WrperfmonCount;
    00126     LARGE_INTEGER InitpcrCount;
    00127     LARGE_INTEGER BptCount;
    00128     LARGE_INTEGER CallsysCount;
    00129     LARGE_INTEGER ImbCount;
    00130     LARGE_INTEGER GentrapCount;
    00131     LARGE_INTEGER RdtebCount;
    00132     LARGE_INTEGER KbptCount;
    00133     LARGE_INTEGER CallkdCount;
    00134     LARGE_INTEGER TbisasnCount;
    00135     LARGE_INTEGER Misc1Count;
    00136     LARGE_INTEGER Misc2Count;
    00137     LARGE_INTEGER Misc3Count;
    00138 } COUNTERS_21064, *PCOUNTERS_21064;
    00139
    00140 typedef enum _AXP21064_PCCOUNTER{
    00141     Ev4PerformanceCounter0 = 0,
    00142     Ev4PerformanceCounter1 = 1
    00143 } AXP21064_PCCOUNTER, *PAXP21064_PCCOUNTER;
    00144
    00145 typedef enum _AXP21064_PCMUXCONTROL{
    00146     Ev4TotalIssues = 0x0,
    00147     Ev4PipelineDry = 0x2,
    00148     Ev4LoadInstruction = 0x4,
    00149     Ev4PipelineFrozen = 0x6,
    00150     Ev4BranchInstructions = 0x8,
    00151     Ev4PalMode = 0xb,
    00152     Ev4TotalCycles = 0xa,
    00153     Ev4TotalNonIssues = 0xc,
    00154     Ev4ExternalCounter0 = 0xe,
    00155     Ev4DcacheMiss = 0x0,
    00156     Ev4IcacheMiss = 0x1,
    00157     Ev4DualIssues = 0x2,
    00158     Ev4BranchMispredicts = 0x3,
    00159     Ev4FPInstructions = 0x4,
    00160     Ev4IntegerOperate = 0x5,
    00161     Ev4StoreInstructions = 0x6,
    00162     Ev4ExternalCounter1 = 0x7
    00163 } AXP21064_PCMUXCONTROL, *PAXP21064_PCMUXCONTROL;
    00164
    00165 typedef enum _AXP21064_PCEVENTCOUNT{
    00166     Ev4CountEvents2xx8 = 0x100,
    00167     Ev4CountEvents2xx12 = 0x1000,
    00168     Ev4CountEvents2xx16 = 0x10000
    00169 } AXP21064_PCEVENTCOUNT, *PAXP21064_PCEVENTCOUNT;
    00170
    00171 typedef enum _AXP21064_EVENTCOUNT{
    00172     Ev4EventCountHigh = 1,
    00173     Ev4EventCountLow = 0
    00174 } AXP21064_EVENTCOUNT, *PAXP21064_EVENTCOUNT;
    00175
    00176 //
    00177 // Internal Processor Register definitions (read format).
    00178 //
    00179
    00180 //
    00181 // Pte formats
    00182 //
    00183
    00184 typedef LARGE_INTEGER ITB_PTE_21064;
    00185 typedef ITB_PTE_21064 *PITB_PTE_21064;
    00186 typedef LARGE_INTEGER DTB_PTE_21064;
    00187 typedef DTB_PTE_21064 *PDTB_PTE_21064;
    00188
    00189 #define PTE_FOR_21064_SHIFT 3
    00190 #define PTE_FOW_21064_SHIFT 4
    00191 #define PTE_KWE_21064_SHIFT 5
    00192 #define PTE_EWE_21064_SHIFT 6
    00193 #define PTE_SWE_21064_SHIFT 7
    00194 #define PTE_UWE_21064_SHIFT 8
    00195 #define PTE_KRE_21064_SHIFT 9
    00196 #define PTE_ERE_21064_SHIFT 10
    00197 #define PTE_SRE_21064_SHIFT 11
    00198 #define PTE_URE_21064_SHIFT 12
    00199 #define PTE_PFN_21064_SHIFT 13
    00200 #define PTE_PFN_21064_SHIFTMASK  0x1FFFF
    00201 #define PTE_ASM_21064_SHIFT 34
    00202
    00203 #define PTE_ALL_21064(itbpte) (itbpte)
    00204 #define PTE_FOR_21064(itbpte) ( (itbpte.LowPart >> PTE_FOR_21064_SHIFT) & 1)
    00205 #define PTE_FOW_21064(itbpte) ( (itbpte.LowPart >> PTE_FOW_21064_SHIFT) & 1)
    00206 #define PTE_KWE_21064(itbpte) ( (itbpte.LowPart >> PTE_KWE_21064_SHIFT) & 1)
    00207 #define PTE_EWE_21064(itbpte) ( (itbpte.LowPart >> PTE_EWE_21064_SHIFT) & 1)
    00208 #define PTE_SWE_21064(itbpte) ( (itbpte.LowPart >> PTE_SWE_21064_SHIFT) & 1)
    00209 #define PTE_UWE_21064(itbpte) ( (itbpte.LowPart >> PTE_UWE_21064_SHIFT) & 1)
    00210 #define PTE_KRE_21064(itbpte) ( (itbpte.LowPart >> PTE_KRE_21064_SHIFT) & 1)
    00211 #define PTE_ERE_21064(itbpte) ( (itbpte.LowPart >> PTE_ERE_21064_SHIFT) & 1)
    00212 #define PTE_SRE_21064(itbpte) ( (itbpte.LowPart >> PTE_SRE_21064_SHIFT) & 1)
    00213 #define PTE_URE_21064(itbpte) ( (itbpte.LowPart >> PTE_URE_21064_SHIFT) & 1)
    00214 #define PTE_ASM_21064(itbpte) ( (itbpte.LowPart >> PTE_ASM_21064_SHIFT) & 1)
    00215 #define PTE_PFN_21064(itbpte) ( (itbpte.LowPart >> PTE_PFN_21064_SHIFT) & PTE_PFN_21064_SHIFTMASK)
    00216
    00217 //
    00218 // Instruction Cache Control and Status Register format
    00219 //
    00220
    00221 typedef LARGE_INTEGER ICCSR_21064;
    00222 typedef ICCSR_21064 *PICCSR_21064;
    00223
    00224 #define ICCSR_PC0_21064_SHIFT   1
    00225 #define ICCSR_PC1_21064_SHIFT   2
    00226 #define ICCSR_PCMUX0_21064_SHIFT 9
    00227 #define ICCSR_PCMUX0_21064_SHIFTMASK 0xF
    00228 #define ICCSR_PCMUX1_21064_SHIFT 13
    00229 #define ICCSR_PCMUX1_21064_SHIFTMASK 0x7
    00230 #define ICCSR_PIPE_21064_SHIFT 16
    00231 #define ICCSR_BPE_21064_SHIFT  17
    00232 #define ICCSR_JSE_21064_SHIFT  18
    00233 #define ICCSR_BHE_21064_SHIFT  19
    00234 #define ICCSR_DI_21064_SHIFT   20
    00235 #define ICCSR_HWE_21064_SHIFT  21
    00236 #define ICCSR_MAP_21064_SHIFT  22
    00237 #define ICCSR_FPE_21064_SHIFT  23
    00238 #define ICCSR_ASN_21064_SHIFT  28
    00239 #define ICCSR_ASN_21064_SHIFTMASK 0x3F
    00240
    00241 #define ICCSR_ALL_21064(iccsr) (iccsr)
    00242 #define ICCSR_PC0_21064(iccsr) ( (iccsr.LowPart >> ICCSR_PC0_21064_SHIFT) & 1)
    00243 #define ICCSR_PC1_21064(iccsr) ( (iccsr.LowPart >> ICCSR_PC1_21064_SHIFT) & 1)
    00244 #define ICCSR_PCMUX0_21064(iccsr) \
    00245     ( (iccsr.LowPart >> ICCSR_PCMUX0_21064_SHIFT) & ICCSR_PCMUX0_21064_SHIFTMASK)
    00246 #define ICCSR_PCMUX1_21064(iccsr) \
    00247     ( (iccsr.LowPart >> ICCSR_PCMUX1_21064_SHIFT) & ICCSR_PCMUX1_21064_SHIFTMASK)
    00248 #define ICCSR_PIPE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_PIPE_21064_SHIFT) & 1)
    00249 #define ICCSR_BPE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_BPE_21064_SHIFT) & 1)
    00250 #define ICCSR_JSE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_JSE_21064_SHIFT) & 1)
    00251 #define ICCSR_BHE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_BHE_21064_SHIFT) & 1)
    00252 #define ICCSR_DI_21064(iccsr)  ( (iccsr.LowPart >> ICCSR_DI_21064_SHIFT) & 1)
    00253 #define ICCSR_HWE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_HWE_21064_SHIFT) & 1)
    00254 #define ICCSR_MAP_21064(iccsr) ( (iccsr.LowPart >> ICCSR_MAP_21064_SHIFT) & 1)
    00255 #define ICCSR_FPE_21064(iccsr) ( (iccsr.LowPart >> ICCSR_FPE_21064_SHIFT) & 1)
    00256 #define ICCSR_ASN_21064(iccsr) \
    00257     (ULONG)( (iccsr.LowPart >> ICCSR_ASN_21064_SHIFT) & ICCSR_ASN_21064_SHIFTMASK)
    00258
    00259 //
    00260 // Processor Status (PS) format.
    00261 //
    00262
    00263 typedef LARGE_INTEGER PS_21064;
    00264 typedef PS_21064 *PPS_21064;
    00265
    00266 #define PS_CM0_21064_SHIFT 1
    00267 #define PS_CM1_21064_SHIFT 34
    00268
    00269 #define PS_ALL_21064(ps) (ps)
    00270 #define PS_CM_21064(ps) \
    00271         ( (((ps).LowPart >> PS_CM0_21064_SHIFT) & 1) || \
    00272           (((ps).LowPart >> (PS_CM1_21064_SHIFT-1)) & 1) )
    00273
    00274 //
    00275 // Exception Summary (EXC_SUM) format.
    00276 //
    00277
    00278 typedef LARGE_INTEGER EXC_SUM_21064;
    00279 typedef EXC_SUM_21064 *PEXC_SUM_21064;
    00280
    00281 #define EXCSUM_SWC_21064_SHIFT 2
    00282 #define EXCSUM_INV_21064_SHIFT 3
    00283 #define EXCSUM_DZE_21064_SHIFT 4
    00284 #define EXCSUM_FOV_21064_SHIFT 5
    00285 #define EXCSUM_UNF_21064_SHIFT 6
    00286 #define EXCSUM_INE_21064_SHIFT 7
    00287 #define EXCSUM_IOV_21064_SHIFT 8
    00288 #define EXCSUM_MSK_21064_SHIFT 33
    00289
    00290 #define EXCSUM_ALL_21064(excsum) (excsum)
    00291 #define EXCSUM_SWC_21064(excsum) ((excsum.LowPart >> EXCSUM_SWC_21064_SHIFT) & 0x1)
    00292 #define EXCSUM_INV_21064(excsum) ( (excsum.LowPart >> EXCSUM_INV_21064_SHIFT) & 0x1)
    00293 #define EXCSUM_DZE_21064(excsum) ( (excsum.LowPart >> EXCSUM_DZE_21064_SHIFT) & 0x1)
    00294 #define EXCSUM_FOV_21064(excsum) ( (excsum.LowPart >> EXCSUM_FOV_21064_SHIFT) & 0x1)
    00295 #define EXCSUM_UNF_21064(excsum) ( (excsum.LowPart >> EXCSUM_UNF_21064_SHIFT) & 0x1)
    00296 #define EXCSUM_INE_21064(excsum) ( (excsum.LowPart >> EXCSUM_INE_21064_SHIFT) & 0x1)
    00297 #define EXCSUM_IOV_21064(excsum) ( (excsum.LowPart >> EXCSUM_IOV_21064_SHIFT) & 0x1)
    00298 #define EXCSUM_MSK_21064(excsum) ( (excsum.LowPart >> EXCSUM_MSK_21064_SHIFT) & 0x1)
    00299
    00300 //
    00301 // Interrupt Request (HIRR, SIRR, ASTRR) format.
    00302 //
    00303
    00304 typedef LARGE_INTEGER IRR_21064;
    00305 typedef IRR_21064 *PIRR_21064;
    00306
    00307 #define IRR_HWR_21064_SHIFT 1
    00308 #define IRR_SWR_21064_SHIFT 2
    00309 #define IRR_ATR_21064_SHIFT 3
    00310 #define IRR_CRR_21064_SHIFT 4
    00311 #define IRR_HIRR53_21064_SHIFT 5
    00312 #define IRR_HIRR53_21064_SHIFTMASK 0x7
    00313 #define IRR_PC1_21064_SHIFT 8
    00314 #define IRR_PC0_21064_SHIFT 9
    00315 #define IRR_HIRR20_21064_SHIFT 10
    00316 #define IRR_HIRR20_21064_SHIFTMASK 0x7
    00317 #define IRR_SLR_21064_SHIFT 13
    00318 #define IRR_SIRR_21064_SHIFT 14
    00319 #define IRR_SIRR_21064_SHIFTMASK 0x7FFF
    00320 #define IRR_ASTRR_21064_SHIFT 29
    00321 #define IRR_ASTRR_21064_SHIFTMASK 0xF
    00322
    00323 #define IRR_ALL_21064(irr) (irr)
    00324 #define IRR_HWR_21064(irr) ( (irr.LowPart >> IRR_HWR_21064_SHIFT) & 0x1)
    00325 #define IRR_SWR_21064(irr) ( (irr.LowPart >> IRR_SWR_21064_SHIFT) & 0x1)
    00326 #define IRR_ATR_21064(irr) ( (irr.LowPart >> IRR_ATR_21064_SHIFT) & 0x1)
    00327 #define IRR_CRR_21064(irr) ( (irr.LowPart >> IRR_CRR_21064_SHIFT) & 0x1)
    00328 #define IRR_HIRR_21064(irr) \
    00329     ( ((irr.LowPart >> (IRR_HIRR53_21064_SHIFT-3)) & IRR_HIRR53_21064_SHIFTMASK) || \
    00330     ( (irr.LowPart >> IRR_HIRR20_21064_SHIFT) & IRR_HIRR20_21064_SHIFTMASK) )
    00331 #define IRR_PC1_21064(irr) ( (irr.LowPart >> IRR_PC1_21064_SHIFT) & 0x1)
    00332 #define IRR_PC0_21064(irr) ( (irr.LowPart >> IRR_PC0_21064_SHIFT) & 0x1)
    00333 #define IRR_SLR_21064(irr) ( (irr.LowPart >> IRR_SLR_21064_SHIFT) & 0x1)
    00334 #define IRR_SIRR_21064(irr) \
    00335     ( (irr.LowPart >> IRR_SIRR_21064_SHIFT) & IRR_SIRR_21064_SHIFTMASK)
    00336 #define IRR_ASTRR_21064(irr) \
    00337     ( (irr.LowPart >> IRR_ASTRR_21064_SHIFT) & IRR_ASTRR_21064_SHIFTMASK)
    00338
    00339 //
    00340 // Interrupt Enable (HIER, SIER, ASTER) format.
    00341 //
    00342
    00343 typedef LARGE_INTEGER IER_21064;
    00344 typedef IER_21064 *PIER_21064;
    00345
    00346 #define IER_CRR_21064_SHIFT 4
    00347 #define IER_HIER53_21064_SHIFT 5
    00348 #define IER_HIER53_21064_SHIFTMASK 0x7
    00349 #define IER_PC1_21064_SHIFT 8
    00350 #define IER_PC0_21064_SHIFT 9
    00351 #define IER_HIER20_21064_SHIFT 10
    00352 #define IER_HIER20_21064_SHIFTMASK 0x7
    00353 #define IER_SLR_21064_SHIFT 13
    00354 #define IER_SIER_21064_SHIFT 14
    00355 #define IER_SIER_21064_SHIFTMASK 0x7FFF
    00356 #define IER_ASTER_21064_SHIFT 29
    00357 #define IER_ASTER_21064_SHIFTMASK 0xF
    00358
    00359 #define IER_ALL_21064(ier) (ier)
    00360 #define IER_CRR_21064(ier) ( (ier.LowPart >> IER_CRR_21064_SHIFT) & 0x1)
    00361 #define IER_HIER_21064(ier) \
    00362     ( ( (ier.LowPart >> (IER_HIER53_21064_SHIFT-3)) & IER_HIER53_21064_SHIFTMASK) || \
    00363       ( (ier.LowPart >> IER_HIER20_21064_SHIFT) & IER_HIER20_21064_SHIFTMASK) )
    00364 #define IER_PC1_21064(ier) ( (ier.LowPart >> IER_PC1_21064_SHIFT) & 0x1)
    00365 #define IER_PC0_21064(ier) ( (ier.LowPart >> IER_PC0_21064_SHIFT) & 0x1)
    00366 #define IER_SLR_21064(ier) ( (ier.LowPart >> IER_SLR_21064_SHIFT) & 0x1)
    00367 #define IER_SIER_21064(ier) \
    00368     ( (ier.LowPart >> IER_SIER_21064_SHIFT) & IER_SIER_21064_SHIFTMASK)
    00369 #define IER_ASTER_21064(ier) \
    00370     ( (ier.LowPart >> IER_ASTER_21064_SHIFT) & IER_ASTER_21064_SHIFTMASK)
    00371
    00372 //
    00373 // Abox Control Register (ABOX_CTL) format.
    00374 //
    00375
    00376 typedef union _ABOX_CTL_21064{
    00377     struct {
    00378         ULONG wb_dis: 1;
    00379         ULONG mchk_en: 1;
    00380         ULONG crd_en: 1;
    00381         ULONG ic_sbuf_en: 1;
    00382         ULONG spe_1: 1;
    00383         ULONG spe_2: 1;
    00384         ULONG emd_en: 1;
    00385         ULONG mbz1: 3;
    00386         ULONG dc_ena: 1;
    00387         ULONG dc_fhit: 1;
    00388     } bits;
    00389     LARGE_INTEGER all;
    00390 } ABOX_CTL_21064, *PABOX_CTL_21064;
    00391
    00392 #define ABOXCTL_ALL_21064(aboxctl) ((aboxctl).all)
    00393 #define ABOXCTL_WBDIS_21064(aboxctl) ((aboxctl).bits.wb_dis)
    00394 #define ABOXCTL_MCHKEN_21064(aboxctl) ((aboxctl).bits.mchk_en)
    00395 #define ABOXCTL_CRDEN_21064(aboxctl) ((aboxctl).bits.crd_en)
    00396 #define ABOXCTL_ICSBUFEN_21064(aboxctl) ((aboxctl).bits.ic_sbuf_en)
    00397 #define ABOXCTL_SPE1_21064(aboxctl) ((aboxctl).bits.spe_1)
    00398 #define ABOXCTL_SPE2_21064(aboxctl) ((aboxctl).bits.spe_2)
    00399 #define ABOXCTL_EMDEN_21064(aboxctl) ((aboxctl).bits.emd_en)
    00400 #define ABOXCTL_DCENA_21064(aboxctl) ((aboxctl).bits.dc_ena)
    00401 #define ABOXCTL_DCFHIT_21064(aboxctl) ((aboxctl).bits.dc_fhit)
    00402
    00403 //
    00404 // Memory Management Control and Status Register (MMCSR) format.
    00405 //
    00406
    00407 typedef union _MMCSR_21064{
    00408     struct {
    00409         ULONG Wr: 1;
    00410         ULONG Acv: 1;
    00411         ULONG For: 1;
    00412         ULONG Fow: 1;
    00413         ULONG Ra: 5;
    00414         ULONG Opcode: 6;
    00415     } bits;
    00416     LARGE_INTEGER all;
    00417 } MMCSR_21064, *PMMCSR_21064;
    00418
    00419 #define MMCSR_ALL_21064(mmcsr) ((mmcsr).all)
    00420 #define MMCSR_WR_21064(mmcsr) ((mmcsr).bits.Wr)
    00421 #define MMCSR_ACV_21064(mmcsr) ((mmcsr).bits.Acv)
    00422 #define MMCSR_FOR_21064(mmcsr) ((mmcsr).bits.For)
    00423 #define MMCSR_FOW_21064(mmcsr) ((mmcsr).bits.Fow)
    00424 #define MMCSR_RA_21064(mmcsr) ((mmcsr).bits.Ra)
    00425 #define MMCSR_OPCODE_21064(mmcsr) ((mmcsr).bits.Opcode)
    00426
    00427 //
    00428 // Dcache Status (DC_STAT) format.
    00429 //
    00430 typedef union _DC_STAT_21064{
    00431     struct {
    00432         ULONG Reserved: 3;
    00433         ULONG DcHit: 1;
    00434         ULONG DCacheParityError: 1;
    00435         ULONG ICacheParityError: 1;
    00436     } bits;
    00437     LARGE_INTEGER all;
    00438 } DC_STAT_21064, *PDC_STAT_21064;
    00439
    00440 #define DCSTAT_ALL_21064(dcstat) ((dcstat).all)
    00441 #define DCSTAT_DCHIT_21064(dcstat) ((dcstat).bits.DcHit)
    00442 #define DCSTAT_DCPARITY_ERROR_21064(dcstat) ((dcstat).bits.DCacheParityError)
    00443 #define DCSTAT_ICPARITY_ERROR_21064(dcstat) ((dcstat).bits.ICacheParityError)
    00444
    00445 #endif
    00446
    00447 //end_axp21064
    00448
    00449 //
    00450 // Define the number of banks in the memory controller.
    00451 //
    00452
    00453 #define MEMORY_BANKS_21066 (4)
    00454
    00455 //
    00456 // Define the base physical addresses for the integrated
    00457 // memory and I/O controllers.
    00458 //
    00459
    00460 #define MEMORY_CONTROLLER_PHYSICAL_21066 (0x120000000)
    00461 #define IO_CONTROLLER_PHYSICAL_21066 (0x180000000)
    00462
    00463 //
    00464 // Define the memory controller CSR structure.
    00465 //
    00466
    00467 typedef struct _MEMC_CSRS_21066{
    00468     LARGE_INTEGER Bcr0;
    00469     LARGE_INTEGER Bcr1;
    00470     LARGE_INTEGER Bcr2;
    00471     LARGE_INTEGER Bcr3;
    00472     LARGE_INTEGER Bmr0;
    00473     LARGE_INTEGER Bmr1;
    00474     LARGE_INTEGER Bmr2;
    00475     LARGE_INTEGER Bmr3;
    00476     LARGE_INTEGER Btr0;
    00477     LARGE_INTEGER Btr1;
    00478     LARGE_INTEGER Btr2;
    00479     LARGE_INTEGER Btr3;
    00480     LARGE_INTEGER Gtr;
    00481     LARGE_INTEGER Esr;
    00482     LARGE_INTEGER Ear;
    00483     LARGE_INTEGER Car;
    00484     LARGE_INTEGER Vgr;
    00485     LARGE_INTEGER Plm;
    00486     LARGE_INTEGER For;
    00487 } MEMC_CSRS_21066, *PMEMC_CSRS_21066;
    00488
    00489 //
    00490 // Define the i/o controller CSR structure.
    00491 //
    00492
    00493 typedef struct _IOC_CSRS_21066{
    00494     LARGE_INTEGER Hae;
    00495     LARGE_INTEGER Filler1[3];
    00496     LARGE_INTEGER Cct;
    00497     LARGE_INTEGER Filler2[3];
    00498     LARGE_INTEGER IoStat0;
    00499     LARGE_INTEGER Filler3[3];
    00500     LARGE_INTEGER IoStat1;
    00501     LARGE_INTEGER Filler4[3];
    00502     LARGE_INTEGER Tbia;
    00503     LARGE_INTEGER Filler5[3];
    00504     LARGE_INTEGER Tben;
    00505     LARGE_INTEGER Filler6[3];
    00506     LARGE_INTEGER PciSoftReset;
    00507     LARGE_INTEGER Filler7[3];
    00508     LARGE_INTEGER PciParityDisable;
    00509     LARGE_INTEGER Filler8[3];
    00510     LARGE_INTEGER Wbase0;
    00511     LARGE_INTEGER Filler9[3];
    00512     LARGE_INTEGER Wbase1;
    00513     LARGE_INTEGER Filler10[3];
    00514     LARGE_INTEGER Wmask0;
    00515     LARGE_INTEGER Filler11[3];
    00516     LARGE_INTEGER Wmask1;
    00517     LARGE_INTEGER Filler12[3];
    00518     LARGE_INTEGER Tbase0;
    00519     LARGE_INTEGER Filler13[3];
    00520     LARGE_INTEGER Tbase1;
    00521     LARGE_INTEGER Filler14[3];
    00522 } IOC_CSRS_21066, *PIOC_CSRS_21066;
    00523
    00524
    00525 //
    00526 // Bank Configuration Registers (BCR0 - BCR3)
    00527 //
    00528
    00529 typedef union _BCR_21066{
    00530     struct {
    00531         ULONG Reserved1: 6;
    00532         ULONG Ras: 4;
    00533         ULONG Erm: 1;
    00534         ULONG Wrm: 1;
    00535         ULONG Bwe: 1;
    00536         ULONG Sbe: 1;
    00537         ULONG Bav: 1;
    00538         ULONG Reserved2: 5;
    00539         ULONG BankBase: 9;
    00540         ULONG Reserved3: 3;
    00541     } ;
    00542     LARGE_INTEGER all;
    00543 } BCR_21066, *PBCR_21066;
    00544
    00545 //
    00546 // Bank Address Mask Registers (BMR0 - BMR3)
    00547 //
    00548
    00549 typedef union _BMR_21066{
    00550     struct {
    00551         ULONG Reserved1: 20;
    00552         ULONG BankAddressMask: 9;
    00553         ULONG Reserved2: 3;
    00554     } ;
    00555     LARGE_INTEGER all;
    00556 } BMR_21066, *PBMR_21066;
    00557
    00558 //
    00559 // Global Timing Register (GTR)
    00560 //
    00561
    00562 typedef union _GTR_21066{
    00563     struct {
    00564         ULONG Precharge: 5;
    00565         ULONG MinimumRas: 5;
    00566         ULONG MaximumRas: 8;
    00567         ULONG RefreshEnable: 1;
    00568         ULONG RefreshInterval: 8;
    00569         ULONG RefreshDivideSelect: 1;
    00570         ULONG Setup: 4;
    00571     } ;
    00572     LARGE_INTEGER all;
    00573 } GTR_21066, *PGTR_21066;
    00574
    00575 //
    00576 // Error Status Register (ESR)
    00577 //
    00578
    00579 typedef union _ESR_21066{
    00580     struct {
    00581         ULONG Eav: 1;
    00582         ULONG Cee: 1;
    00583         ULONG Uee: 1;
    00584         ULONG Wre: 1;
    00585         ULONG Sor: 1;
    00586         ULONG Reserved1: 2;
    00587         ULONG Cte: 1;
    00588         ULONG Reserved2: 1;
    00589         ULONG Mse: 1;
    00590         ULONG Mhe: 1;
    00591         ULONG Ice: 1;
    00592         ULONG Nxm: 1;
    00593         ULONG Reserved3: 19;
    00594         ULONG Ecc0: 1;
    00595         ULONG Wec6: 1;
    00596         ULONG Wec3: 1;
    00597         ULONG Reserved4: 1;
    00598         ULONG Ecc1: 1;
    00599         ULONG Reserved5: 3;
    00600         ULONG Wec7: 1;
    00601         ULONG Ecc2: 1;
    00602         ULONG Wec2: 1;
    00603         ULONG Reserved6: 2;
    00604         ULONG Ecc3: 1;
    00605         ULONG Reserved7: 2;
    00606         ULONG Wec4: 1;
    00607         ULONG Wec1: 1;
    00608         ULONG Ecc4: 1;
    00609         ULONG Wec0: 1;
    00610         ULONG Reserved8: 2;
    00611         ULONG Ecc5: 1;
    00612         ULONG Reserved9: 4;
    00613         ULONG Ecc6: 1;
    00614         ULONG Wec5: 1;
    00615         ULONG Reserved10: 2;
    00616         ULONG Ecc7: 1;
    00617     } ;
    00618     LARGE_INTEGER all;
    00619 } ESR_21066, *PESR_21066;
    00620
    00621 //
    00622 // Error Address Register (EAR)
    00623 //
    00624
    00625 typedef union _EAR_21066{
    00626     struct {
    00627         ULONG PerfCntMux0: 3;
    00628         ULONG ErrorAddress: 26;
    00629         ULONG PerfCntMux1: 3;
    00630     } ;
    00631     LARGE_INTEGER all;
    00632 } EAR_21066, *PEAR_21066;
    00633
    00634
    00635 //
    00636 // Cache Register (CAR)
    00637 //
    00638
    00639 typedef union _CAR_21066{
    00640     struct {
    00641         ULONG Bce: 1;
    00642         ULONG Reserved1: 1;
    00643         ULONG Etp: 1;
    00644         ULONG Wwp: 1;
    00645         ULONG Ece: 1;
    00646         ULONG BCacheSize: 3;
    00647         ULONG ReadCycles: 3;
    00648         ULONG WriteCycles: 3;
    00649         ULONG Whd: 1;
    00650         ULONG Pwr: 1;
    00651         ULONG Tag: 15;
    00652         ULONG Hit: 1;
    00653     } ;
    00654     LARGE_INTEGER all;
    00655 } CAR_21066, *PCAR_21066;
    00656
    00657
    00658 //
    00659 // IOC Status 0 Registers (IOC_STAT0)
    00660 //
    00661
    00662 typedef union _IOC_STAT0_21066{
    00663     struct {
    00664         ULONG Cmd: 4;
    00665         ULONG Err: 1;
    00666         ULONG Lost: 1;
    00667         ULONG Thit: 1;
    00668         ULONG Tref: 1;
    00669         ULONG Code: 3;
    00670         ULONG Reserved1: 2;
    00671         ULONG PageNumber: 19;
    00672     } ;
    00673     LARGE_INTEGER all;
    00674 } IOC_STAT0_21066, *PIOC_STAT0_21066;
    00675
    00676
    00677 //
    00678 // IOC Status 1 Register (IOC_STAT1)
    00679 //
    00680
    00681 typedef union _IOC_STAT1_21066{
    00682     struct {
    00683         ULONG Address: 32;
    00684     } ;
    00685     LARGE_INTEGER all;
    00686 } IOC_STAT1_21066, *PIOC_STAT1_21066;
    00687
    00688
    00689 //
    00690 // Internal Processor State record.
    00691 // This is the structure of the data returned by the rdstate call pal.
    00692 //
    00693
    00694 typedef struct _PROCESSOR_STATE_21066{
    00695     ABOX_CTL_21064 AboxCtl;
    00696     IER_21064 Aster;
    00697     IRR_21064 Astrr;
    00698     BCR_21066 BankConfig[ MEMORY_BANKS_21066 ];
    00699     BMR_21066 BankMask[ MEMORY_BANKS_21066 ];
    00700     DC_STAT_21064 DcStat;
    00701     DTB_PTE_21064 DtbPte[ DTB_ENTRIES_21064 ];
    00702     EXC_SUM_21064 ExcSum;
    00703     IER_21064 Hier;
    00704     IRR_21064 Hirr;
    00705     ICCSR_21064 Iccsr;
    00706     ITB_PTE_21064 ItbPte[ ITB_ENTRIES_21064 ];
    00707     MMCSR_21064 MmCsr;
    00708     LARGE_INTEGER PalBase;
    00709     LARGE_INTEGER PalTemp[ PAL_TEMPS_21064 ];
    00710     PS_21064 Ps;
    00711     IER_21064 Sier;
    00712     IRR_21064 Sirr;
    00713     LARGE_INTEGER Va;
    00714 } PROCESSOR_STATE_21066, *PPROCESSOR_STATE_21066;
    00715
    00716 //
    00717 // Machine-check logout frame.
    00718 //
    00719
    00720 typedef struct _LOGOUT_FRAME_21066{
    00721     ABOX_CTL_21064 AboxCtl;
    00722     BCR_21066 BankConfig[ MEMORY_BANKS_21066 ];
    00723     BMR_21066 BankMask[ MEMORY_BANKS_21066 ];
    00724     DC_STAT_21064 DcStat;
    00725     LARGE_INTEGER ExcAddr;
    00726     EXC_SUM_21064 ExcSum;
    00727     IER_21064 Hier;
    00728     IRR_21064 Hirr;
    00729     ICCSR_21064 Iccsr;
    00730     MMCSR_21064 MmCsr;
    00731     LARGE_INTEGER PalBase;
    00732     LARGE_INTEGER PalTemp[ PAL_TEMPS_21064 ];
    00733     PS_21064 Ps;
    00734     LARGE_INTEGER Va;
    00735 } LOGOUT_FRAME_21066, *PLOGOUT_FRAME_21066;
    00736
    00737 //
    00738 // Correctable Machine-check logout frame.
    00739 //
    00740
    00741 typedef struct _CORRECTABLE_FRAME_21066{
    00742     BCR_21066 BankConfig[ MEMORY_BANKS_21066 ];
    00743     BMR_21066 BankMask[ MEMORY_BANKS_21066 ];
    00744     DC_STAT_21064 DcStat;
    00745 } CORRECTABLE_FRAME_21066;
    00746
    00747 //
    00748 // Define the physical and virtual address bits
    00749 //
    00750
    00751 #define LCA_PHYSICAL_ADDRESS_BITS     34
    00752 #define LCA_VIRTUAL_ADDRESS_BITS      43
    00753
    00754 #endif