test: duodma.h Source File

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# duodma.h

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    00001 /*++ BUILD Version: 0001    // Increment this if a change has global effects
    00002
    00003 Copyright (c) 1992  Microsoft Corporation
    00004
    00005 Module Name:
    00006
    00007     duodma.h
    00008
    00009 Abstract:
    00010
    00011     This module is the header file that describes the DMA control register
    00012     structure for the Duo system.
    00013
    00014 Author:
    00015
    00016     David N. Cutler (davec) 13-Nov-1990
    00017
    00018 Revision History:
    00019
    00020 --*/
    00021
    00022 #ifndef _DUODMA_
    00023 #define _DUODMA_
    00024
    00025 //
    00026 // Define DMA register structures.
    00027 //
    00028
    00029 typedef struct _DMA_REGISTER {
    00030     ULONG Long;
    00031     ULONG Fill;
    00032 } DMA_REGISTER, *PDMA_REGISTER;
    00033
    00034 typedef struct _DMA_LARGE_REGISTER {
    00035     union {
    00036         LARGE_INTEGER LargeInteger;
    00037         double Double;
    00038     } u;
    00039 } DMA_LARGE_REGISTER, *PDMA_LARGE_REGISTER;
    00040
    00041 //
    00042 // Define DMA channel register structure.
    00043 //
    00044
    00045 typedef struct _DMA_CHANNEL {
    00046     DMA_REGISTER Mode;
    00047     DMA_REGISTER Enable;
    00048     DMA_REGISTER ByteCount;
    00049     DMA_REGISTER Address;
    00050 } DMA_CHANNEL, *PDMA_CHANNEL;
    00051
    00052 //
    00053 // Define DMA control register structure.
    00054 //
    00055
    00056 typedef volatile struct _DMA_REGISTERS {
    00057     DMA_REGISTER Configuration;
    00058     DMA_REGISTER RevisionLevel;
    00059     DMA_REGISTER RemoteFailedAddress;
    00060     DMA_REGISTER MemoryFailedAddress;
    00061     DMA_REGISTER InvalidAddress;
    00062     DMA_REGISTER TranslationBase;
    00063     DMA_REGISTER TranslationLimit;
    00064     DMA_REGISTER TranslationInvalidate;
    00065     DMA_REGISTER ChannelInterruptAcknowledge;
    00066     DMA_REGISTER LocalInterruptAcknowledge;
    00067     DMA_REGISTER EisaInterruptAcknowledge;
    00068     DMA_REGISTER TimerInterruptAcknowledge;
    00069     DMA_REGISTER IpInterruptAcknowledge;
    00070     DMA_REGISTER Reserved1;
    00071     DMA_REGISTER WhoAmI;
    00072     DMA_REGISTER NmiSource;
    00073     DMA_REGISTER RemoteSpeed[15];
    00074     DMA_REGISTER InterruptEnable;
    00075     DMA_CHANNEL Channel[4];
    00076     DMA_REGISTER ArbitrationControl;
    00077     DMA_REGISTER Errortype;
    00078     DMA_REGISTER RefreshRate;
    00079     DMA_REGISTER RefreshCounter;
    00080     DMA_REGISTER SystemSecurity;
    00081     DMA_REGISTER InterruptInterval;
    00082     DMA_REGISTER IntervalTimer;
    00083     DMA_REGISTER IpInterruptRequest;
    00084     DMA_REGISTER InterruptDiagnostic;
    00085     DMA_LARGE_REGISTER EccDiagnostic;
    00086     DMA_REGISTER MemoryConfig[4];
    00087     DMA_REGISTER Reserved2;
    00088     DMA_REGISTER Reserved3;
    00089     DMA_LARGE_REGISTER IoCacheBuffer[64];
    00090     DMA_REGISTER IoCachePhysicalTag[8];
    00091     DMA_REGISTER IoCacheLogicalTag[8];
    00092     DMA_REGISTER IoCacheLowByteMask[8];
    00093     DMA_REGISTER IoCacheHighByteMask[8];
    00094 } DMA_REGISTERS, *PDMA_REGISTERS;
    00095
    00096 //
    00097 // Configuration Register values.
    00098 //
    00099
    00100 #define LOAD_CLEAN_EXCLUSIVE 0x20
    00101 #define DISABLE_EISA_MEMORY 0x10
    00102 #define ENABLE_PROCESSOR_B 0x08
    00103 #define MAP_PROM 0x04
    00104
    00105 //
    00106 // Interrupt Enable bits.
    00107 //
    00108 #define ENABLE_CHANNEL_INTERRUPTS (1 << 0)
    00109 #define ENABLE_DEVICE_INTERRUPTS (1 << 1)
    00110 #define ENABLE_EISA_INTERRUPTS (1 << 2)
    00111 #define ENABLE_TIMER_INTERRUPTS (1 << 3)
    00112 #define ENABLE_IP_INTERRUPTS (1 << 4)
    00113
    00114 //
    00115 // Eisa Interupt Acknowledge Register values.
    00116 //
    00117
    00118 #define EISA_NMI_VECTOR 0x8000
    00119
    00120 //
    00121 // DMA_NMI_SRC register bit definitions.
    00122 //
    00123
    00124 #define NMI_SRC_MEMORY_ERROR        1
    00125 #define NMI_SRC_R4000_ADDRESS_ERROR 2
    00126 #define NMI_SRC_IO_CACHE_ERROR      4
    00127 #define NMI_SRC_ADR_NMI             8
    00128
    00129 //
    00130 // Define DMA channel mode register structure.
    00131 //
    00132
    00133 typedef struct _DMA_CHANNEL_MODE {
    00134     ULONG AccessTime : 3;
    00135     ULONG TransferWidth : 2;
    00136     ULONG InterruptEnable : 1;
    00137     ULONG BurstMode : 1;
    00138     ULONG Reserved1 : 25;
    00139 } DMA_CHANNEL_MODE, *PDMA_CHANNEL_MODE;
    00140
    00141 //
    00142 // Define access time values.
    00143 //
    00144
    00145 #define ACCESS_40NS 0x0                 // 40ns access time
    00146 #define ACCESS_80NS 0x1                 // 80ns access time
    00147 #define ACCESS_120NS 0x2                // 120ns access time
    00148 #define ACCESS_160NS 0x3                // 160ns access time
    00149 #define ACCESS_200NS 0x4                // 200ns access time
    00150 #define ACCESS_240NS 0x5                // 240ns access time
    00151 #define ACCESS_280NS 0x6                // 280ns access time
    00152 #define ACCESS_320NS 0x7                // 320ns access time
    00153
    00154 //
    00155 // Define transfer width values.
    00156 //
    00157
    00158 #define WIDTH_8BITS 0x1                 // 8-bit transfer width
    00159 #define WIDTH_16BITS 0x2                // 16-bit transfer width
    00160 #define WIDTH_32BITS 0x3                // 32-bit transfer width
    00161
    00162 //
    00163 // Define DMA channel enable register structure.
    00164 //
    00165
    00166 typedef struct _DMA_CHANNEL_ENABLE {
    00167     ULONG ChannelEnable : 1;
    00168     ULONG TransferDirection : 1;
    00169     ULONG Reserved1 : 6;
    00170     ULONG TerminalCount : 1;
    00171     ULONG MemoryError : 1;
    00172     ULONG TranslationError : 1;
    00173     ULONG Reserved2 : 21;
    00174 } DMA_CHANNEL_ENABLE, *PDMA_CHANNEL_ENABLE;
    00175
    00176 //
    00177 // Define transfer direction values.
    00178 //
    00179
    00180 #define DMA_READ_OP 0x0                 // read from device
    00181 #define DMA_WRITE_OP 0x1                // write to device
    00182
    00183 //
    00184 // Define translation table entry structure.
    00185 //
    00186
    00187 typedef volatile struct _TRANSLATION_ENTRY {
    00188     ULONG PageFrame;
    00189     ULONG Fill;
    00190 } TRANSLATION_ENTRY, *PTRANSLATION_ENTRY;
    00191
    00192 //
    00193 // Error Type Register values
    00194 //
    00195
    00196 #define SONIC_ADDRESS_ERROR 4
    00197 #define SONIC_MEMORY_ERROR 0x40
    00198 #define EISA_ADDRESS_ERROR 1
    00199 #define EISA_MEMORY_ERROR 2
    00200
    00201 //
    00202 // Address Mask definitions.
    00203 //
    00204
    00205 #define LFAR_ADDRESS_MASK 0xfffff000
    00206 #define RFAR_ADDRESS_MASK 0x00ffffc0
    00207 #define MFAR_ADDRESS_MASK 0x1ffffff0
    00208
    00209 //
    00210 // ECC Register Definitions.
    00211 //
    00212
    00213 #define ECC_SINGLE_BIT_DP0 0x02000000
    00214 #define ECC_SINGLE_BIT_DP1 0x20000000
    00215 #define ECC_SINGLE_BIT ( ECC_SINGLE_BIT_DP0 | ECC_SINGLE_BIT_DP1 )
    00216 #define ECC_DOUBLE_BIT_DP0 0x04000000
    00217 #define ECC_DOUBLE_BIT_DP1 0x40000000
    00218 #define ECC_DOUBLE_BIT ( ECC_DOUBLE_BIT_DP0 | ECC_DOUBLE_BIT_DP1 )
    00219 #define ECC_MULTIPLE_BIT_DP0 0x08000000
    00220 #define ECC_MULTIPLE_BIT_DP1 0x80000000
    00221
    00222 #define ECC_FORCE_DP0 0x010000
    00223 #define ECC_FORCE_DP1 0x100000
    00224 #define ECC_DISABLE_SINGLE_DP0 0x020000
    00225 #define ECC_DISABLE_SINGLE_DP1 0x200000
    00226 #define ECC_ENABLE_DP0 0x040000
    00227 #define ECC_ENABLE_DP1 0x400000
    00228
    00229 //
    00230 // LED/DIAG Register Definitions.
    00231 //
    00232
    00233 #define DIAG_NMI_SWITCH 2
    00234
    00235 //
    00236 // Common error bit definitions
    00237 //
    00238
    00239 #define SINGLE_ERROR   1
    00240 #define MULTIPLE_ERROR 2
    00241 #define RFAR_CACHE_FLUSH 4
    00242
    00243 #endif // _DUODMA_