test: ncr53c94.h Source File

Main Page | Class Hierarchy | Class List | File List | Class Members | File Members

# ncr53c94.h

Go to the documentation of this file.

    00001 /*++
    00002
    00003 Copyright (c) 1990  Microsoft Corporation
    00004
    00005 Module Name:
    00006
    00007     ncr53C94.h
    00008
    00009 Abstract:
    00010
    00011     The module defines the structures, defines and functions for the NCR 53C94
    00012     host bus adapter chip.
    00013
    00014 Author:
    00015
    00016     Jeff Havens  (jhavens) 28-Feb-1991
    00017
    00018 Revision History:
    00019
    00020     R.D. Lanser  (DEC)     05-Oct-1991
    00021         Copied SCSI_REGISTER structure from d3scsidd.c and added check for
    00022         DECSTATION.  Changed the UCHAR's in the read/write register structures
    00023         with SCSI_REGISTER, and added the dot Byte member reference to
    00024         SCSI_WRITE and SCSI_READ macros.
    00025
    00026
    00027
    00028 --*/
    00029
    00030 #ifndef _NCR53C94_
    00031 #define _NCR53C94_
    00032
    00033
    00034 //
    00035 // Define SCSI Protocol Chip register format.
    00036 //
    00037
    00038 #if defined(DECSTATION)
    00039
    00040 typedef struct _SCSI_REGISTER {
    00041     UCHAR Byte;
    00042     UCHAR Fill[3];
    00043 } SCSI_REGISTER, *PSCSI_REGISTER;
    00044
    00045 #else
    00046
    00047 #define SCSI_REGISTER UCHAR
    00048
    00049 #endif // DECSTATION
    00050
    00051 //
    00052 // SCSI Protocol Chip Definitions.
    00053 //
    00054 // Define SCSI Protocol Chip Read registers structure.
    00055 //
    00056
    00057 typedef struct _SCSI_READ_REGISTERS {
    00058     SCSI_REGISTER TransferCountLow;
    00059     SCSI_REGISTER TransferCountHigh;
    00060     SCSI_REGISTER Fifo;
    00061     SCSI_REGISTER Command;
    00062     SCSI_REGISTER ScsiStatus;
    00063     SCSI_REGISTER ScsiInterrupt;
    00064     SCSI_REGISTER SequenceStep;
    00065     SCSI_REGISTER FifoFlags;
    00066     SCSI_REGISTER Configuration1;
    00067     SCSI_REGISTER Reserved1;
    00068     SCSI_REGISTER Reserved2;
    00069     SCSI_REGISTER Configuration2;
    00070     SCSI_REGISTER Configuration3;
    00071     SCSI_REGISTER Reserved;
    00072     SCSI_REGISTER TransferCountPage;
    00073     SCSI_REGISTER FifoBottem;
    00074 } SCSI_READ_REGISTERS, *PSCSI_READ_REGISTERS;
    00075
    00076 //
    00077 // Define SCSI Protocol Chip Write registers structure.
    00078 //
    00079
    00080 typedef struct _SCSI_WRITE_REGISTERS {
    00081     SCSI_REGISTER TransferCountLow;
    00082     SCSI_REGISTER TransferCountHigh;
    00083     SCSI_REGISTER Fifo;
    00084     SCSI_REGISTER Command;
    00085     SCSI_REGISTER DestinationId;
    00086     SCSI_REGISTER SelectTimeOut;
    00087     SCSI_REGISTER SynchronousPeriod;
    00088     SCSI_REGISTER SynchronousOffset;
    00089     SCSI_REGISTER Configuration1;
    00090     SCSI_REGISTER ClockConversionFactor;
    00091     SCSI_REGISTER TestMode;
    00092     SCSI_REGISTER Configuration2;
    00093     SCSI_REGISTER Configuration3;
    00094     SCSI_REGISTER Reserved;
    00095     SCSI_REGISTER TransferCountPage;
    00096     SCSI_REGISTER FifoBottem;
    00097 } SCSI_WRITE_REGISTERS, *PSCSI_WRITE_REGISTERS;
    00098
    00099 typedef union _SCSI_REGISTERS {
    00100     SCSI_READ_REGISTERS  ReadRegisters;
    00101     SCSI_WRITE_REGISTERS WriteRegisters;
    00102 } SCSI_REGISTERS, *PSCSI_REGISTERS;
    00103
    00104 //
    00105 // Define SCSI Command Codes.
    00106 //
    00107
    00108 #define NO_OPERATION_DMA 0x80
    00109 #define FLUSH_FIFO 0x1
    00110 #define RESET_SCSI_CHIP 0x2
    00111 #define RESET_SCSI_BUS 0x3
    00112 #define TRANSFER_INFORMATION 0x10
    00113 #define TRANSFER_INFORMATION_DMA 0x90
    00114 #define COMMAND_COMPLETE 0x11
    00115 #define MESSAGE_ACCEPTED 0x12
    00116 #define TRANSFER_PAD 0x18
    00117 #define SET_ATTENTION 0x1a
    00118 #define RESET_ATTENTION 0x1b
    00119 #define RESELECT 0x40
    00120 #define SELECT_WITHOUT_ATTENTION 0x41
    00121 #define SELECT_WITH_ATTENTION 0x42
    00122 #define SELECT_WITH_ATTENTION_STOP 0x43
    00123 #define ENABLE_SELECTION_RESELECTION 0x44
    00124 #define DISABLE_SELECTION_RESELECTION 0x45
    00125 #define SELECT_WITH_ATTENTION3 0x46
    00126
    00127 //
    00128 // Define SCSI Status Register structure.
    00129 //
    00130 typedef struct _SCSI_STATUS {
    00131     UCHAR Phase : 3;
    00132     UCHAR ValidGroup : 1;
    00133     UCHAR TerminalCount : 1;
    00134     UCHAR ParityError : 1;
    00135     UCHAR GrossError : 1;
    00136     UCHAR Interrupt : 1;
    00137 } SCSI_STATUS, *PSCSI_STATUS;
    00138
    00139 //
    00140 // Define SCSI Phase Codes.
    00141 //
    00142
    00143 #define DATA_OUT 0x0
    00144 #define DATA_IN 0x1
    00145 #define COMMAND_OUT 0x2
    00146 #define STATUS_IN 0x3
    00147 #define MESSAGE_OUT 0x6
    00148 #define MESSAGE_IN 0x7
    00149
    00150 //
    00151 // Define SCSI Interrupt Register structure.
    00152 //
    00153
    00154 typedef struct _SCSI_INTERRUPT {
    00155     UCHAR Selected : 1;
    00156     UCHAR SelectedWithAttention : 1;
    00157     UCHAR Reselected : 1;
    00158     UCHAR FunctionComplete : 1;
    00159     UCHAR BusService : 1;
    00160     UCHAR Disconnect : 1;
    00161     UCHAR IllegalCommand : 1;
    00162     UCHAR ScsiReset : 1;
    00163 } SCSI_INTERRUPT, *PSCSI_INTERRUPT;
    00164
    00165 //
    00166 // Define SCSI Sequence Step Register structure.
    00167 //
    00168
    00169 typedef struct _SCSI_SEQUENCE_STEP {
    00170     UCHAR Step : 3;
    00171     UCHAR MaximumOffset : 1;
    00172     UCHAR Reserved : 4;
    00173 } SCSI_SEQUENCE_STEP, *PSCSI_SEQUENCE_STEP;
    00174
    00175 //
    00176 // Define SCSI Fifo Flags Register structure.
    00177 //
    00178
    00179 typedef struct _SCSI_FIFO_FLAGS {
    00180     UCHAR ByteCount : 5;
    00181     UCHAR FifoStep : 3;
    00182 } SCSI_FIFO_FLAGS, *PSCSI_FIFO_FLAGS;
    00183
    00184 //
    00185 // Define SCSI Configuration 1 Register structure.
    00186 //
    00187
    00188 typedef struct _SCSI_CONFIGURATION1 {
    00189     UCHAR HostBusId : 3;
    00190     UCHAR ChipTestEnable : 1;
    00191     UCHAR ParityEnable : 1;
    00192     UCHAR ParityTestMode : 1;
    00193     UCHAR ResetInterruptDisable : 1;
    00194     UCHAR SlowCableMode : 1;
    00195 } SCSI_CONFIGURATION1, *PSCSI_CONFIGURATION1;
    00196
    00197 //
    00198 // Define SCSI Configuration 2 Register structure.
    00199 //
    00200
    00201 typedef struct _SCSI_CONFIGURATION2 {
    00202     UCHAR DmaParityEnable : 1;
    00203     UCHAR RegisterParityEnable : 1;
    00204     UCHAR TargetBadParityAbort : 1;
    00205     UCHAR Scsi2 : 1;
    00206     UCHAR HighImpedance : 1;
    00207     UCHAR EnableByteControl : 1;
    00208     UCHAR EnablePhaseLatch : 1;
    00209     UCHAR ReserveFifoByte : 1;
    00210 } SCSI_CONFIGURATION2, *PSCSI_CONFIGURATION2;
    00211
    00212 //
    00213 // Define SCSI Configuration 3 Register structure.
    00214 //
    00215
    00216 typedef struct _SCSI_CONFIGURATION3 {
    00217     UCHAR Threshold8 : 1;
    00218     UCHAR AlternateDmaMode : 1;
    00219     UCHAR SaveResidualByte : 1;
    00220     UCHAR FastClock : 1;
    00221     UCHAR FastScsi : 1;
    00222     UCHAR EnableCdb10 : 1;
    00223     UCHAR EnableQueue : 1;
    00224     UCHAR CheckIdMessage : 1;
    00225 } SCSI_CONFIGURATION3, *PSCSI_CONFIGURATION3;
    00226
    00227 //
    00228 // Define Emulex FAS 218 unique part Id code.
    00229 //
    00230
    00231 typedef struct _NCR_PART_CODE {
    00232     UCHAR RevisionLevel : 3;
    00233     UCHAR ChipFamily : 5;
    00234 }NCR_PART_CODE, *PNCR_PART_CODE;
    00235
    00236 #define EMULEX_FAS_216 2
    00237
    00238 //
    00239 // SCSI Protocol Chip Control read and write macros.
    00240 //
    00241
    00242 #if defined(DECSTATION)
    00243
    00244 #define SCSI_READ(ChipAddr, Register) \
    00245     (READ_REGISTER_UCHAR (&((ChipAddr)->ReadRegisters.Register.Byte)))
    00246
    00247 #define SCSI_WRITE(ChipAddr, Register, Value) \
    00248     WRITE_REGISTER_UCHAR(&((ChipAddr)->WriteRegisters.Register.Byte), (Value))
    00249
    00250 #else
    00251
    00252 #define SCSI_READ(ChipAddr, Register) \
    00253     (READ_REGISTER_UCHAR (&((ChipAddr)->ReadRegisters.Register)))
    00254
    00255 #define SCSI_WRITE(ChipAddr, Register, Value) \
    00256     WRITE_REGISTER_UCHAR(&((ChipAddr)->WriteRegisters.Register), (Value))
    00257
    00258 #endif
    00259
    00260
    00261 #endif