test: nec98.h Source File

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# nec98.h

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    00001 /*++
    00002
    00003 Copyright (c) 1994  NEC Corporation
    00004 Copyright (c) 1994  NEC Software, Ltd.
    00005
    00006 Module Name:
    00007
    00008     nec98.h (cf. eisa.h)
    00009
    00010 Abstract:
    00011
    00012     The module defines the structures, and defines  for the NEC PC98 chip set.
    00013
    00014 Author:
    00015
    00016     Michio Nakamura        20-Sep-1994
    00017
    00018 Revision History:
    00019
    00020     Takaaki Tochizawa      13-Mar-1998 Add 2nd DMA for FIR.
    00021
    00022 --*/
    00023
    00024 #ifndef _EISA_
    00025 #define _EISA_
    00026
    00027 //
    00028 // Define the DMA page register structure.
    00029 //
    00030
    00031 #define DMA_BANK_A31_A24_DR0   0xe05
    00032 #define DMA_BANK_A31_A24_DR1   0xe07
    00033 #define DMA_BANK_A31_A24_DR2   0xe09
    00034 #define DMA_BANK_A31_A24_DR3   0xe0b
    00035 #define DMA_INC_ENABLE_A31_A24 0xe0f
    00036
    00037 //
    00038 // Define the DMA 2 page register structure.
    00039 //
    00040
    00041 #define DMA2_BANK_A31_A24_DR5   0xf07
    00042 #define DMA2_BANK_A31_A24_DR6   0xf09
    00043 #define DMA2_BANK_A31_A24_DR7   0xf0b
    00044 #define DMA2_INC_ENABLE_A31_A24 0xf0f
    00045
    00046 //
    00047 // Define the DMA 2 mode change register
    00048 //
    00049 #define DMA2_MODE_CHANGE      0xf4
    00050 #define DMA2_MODE_8237_COMP   0x0
    00051 #define DMA2_MODE_71037_A     0x1
    00052 #define DMA2_MODE_71037_B     0x2
    00053 #define DMA2_MODE_71037_C     0x3
    00054
    00055 #define DMA_STATUS 0xc8
    00056 #define DMA_COMMAND 0xc8
    00057 #define SINGLE_MASK 0xca
    00058 #define MODE 0xcb
    00059 #define CLEAR_BYTE_POINTER 0xcc
    00060 #define CLEAR_MASK 0xce
    00061
    00062 typedef struct _DMA_PAGE{
    00063     UCHAR Reserved1;            // offset 0x20
    00064     UCHAR Channel1;             // offset 0x21
    00065     UCHAR Reserved2;
    00066     UCHAR Channel2;             // offset 0x23
    00067     UCHAR Reserved3;
    00068     UCHAR Channel3;             // offset 0x25
    00069     UCHAR Reserved4;
    00070     UCHAR Channel0;             // offset 0x27
    00071     UCHAR Reserved5[0x120-0x27];// offset 0x120
    00072     UCHAR Channel5;             // offset 0x121
    00073     UCHAR Reserved6;
    00074     UCHAR Channel6;             // offset 0x123
    00075     UCHAR Reserved7;
    00076     UCHAR Channel7;             // offset 0x125
    00077     UCHAR Reserved8[4];
    00078 }DMA_PAGE, *PDMA_PAGE;
    00079
    00080 //
    00081 // Define the DMA stop register structure.
    00082 //
    00083
    00084 typedef struct _DMA_CHANNEL_STOP {
    00085     UCHAR ChannelLsb;
    00086     UCHAR ChannelMsb;
    00087     UCHAR ChannelHsb;
    00088     UCHAR Reserved;
    00089 }DMA_CHANNEL_STOP, *PDMA_CHANNEL_STOP;
    00090
    00091 //
    00092 // Define DMA 1 address and count structure.
    00093 //
    00094
    00095 typedef struct _DMA1_ADDRESS_COUNT {
    00096     UCHAR Reserved1;
    00097     UCHAR DmaBaseAddress;
    00098     UCHAR Reserved2;
    00099     UCHAR DmaBaseCount;
    00100 }DMA1_ADDRESS_COUNT, *PDMA1_ADDRESS_COUNT;
    00101
    00102
    00103 //
    00104 // Define DMA 2 address and count structure.
    00105 //
    00106
    00107 typedef struct _DMA2_ADDRESS_COUNT {
    00108     UCHAR Reserved1;
    00109     UCHAR DmaBaseAddress;
    00110     UCHAR Reserved2;
    00111     UCHAR DmaBaseCount;
    00112 }DMA2_ADDRESS_COUNT, *PDMA2_ADDRESS_COUNT;
    00113
    00114 //
    00115 // Define DMA 1 control register structure.
    00116 //
    00117
    00118 typedef struct _DMA1_CONTROL {
    00119     DMA1_ADDRESS_COUNT DmaAddressCount[4];
    00120     UCHAR Reserved1;
    00121     UCHAR DmaStatus;            //offset 0x11
    00122     UCHAR Reserved2;
    00123     UCHAR DmaRequest;           //offset 0x13
    00124     UCHAR Reserved3;
    00125     UCHAR SingleMask;           //offset 0x15
    00126     UCHAR Reserved4;
    00127     UCHAR Mode;                 //offset 0x17
    00128     UCHAR Reserved5;
    00129     UCHAR ClearBytePointer;     //offset 0x19
    00130     UCHAR Reserved6;
    00131     UCHAR MasterClear;          //offset 0x1b
    00132     UCHAR Reserved7;
    00133     UCHAR ClearMask;            //offset 0x1d
    00134     UCHAR Reserved;
    00135     UCHAR AllMask;              //offset 0x1f
    00136 }DMA1_CONTROL, *PDMA1_CONTROL;
    00137
    00138 //
    00139 // Define DMA 2 control register structure.
    00140 //
    00141
    00142 typedef struct _DMA2_CONTROL {
    00143     UCHAR Reserved8[0x100-0x20];//offset 0x20
    00144     DMA2_ADDRESS_COUNT DmaAddressCount[4]; //offset 0x100
    00145     UCHAR Reserved1;
    00146     UCHAR DmaStatus;            //offset 0x111
    00147     UCHAR Reserved2;
    00148     UCHAR DmaRequest;           //offset 0x113
    00149     UCHAR Reserved3;
    00150     UCHAR SingleMask;           //offset 0x115
    00151     UCHAR Reserved4;
    00152     UCHAR Mode;                 //offset 0x117
    00153     UCHAR Reserved5;
    00154     UCHAR ClearBytePointer;     //offset 0x119
    00155     UCHAR Reserved6;
    00156     UCHAR MasterClear;          //offset 0x11b
    00157     UCHAR Reserved7;
    00158     UCHAR ClearMask;            //offset 0x11d
    00159     UCHAR Reserved;
    00160     UCHAR AllMask;              //offset 0x11f
    00161     UCHAR Reserved9[10];        //offset 0x120
    00162 }DMA2_CONTROL, *PDMA2_CONTROL;
    00163
    00164 //
    00165 // Define Timer control register structure.
    00166 //
    00167
    00168 typedef struct _TIMER_CONTROL {
    00169     UCHAR BcdMode : 1;
    00170     UCHAR Mode : 3;
    00171     UCHAR SelectByte : 2;
    00172     UCHAR SelectCounter : 2;
    00173 }TIMER_CONTROL, *PTIMER_CONTROL;
    00174
    00175 //
    00176 // Define Timer status register structure.
    00177 //
    00178
    00179 typedef struct _TIMER_STATUS {
    00180     UCHAR BcdMode : 1;
    00181     UCHAR Mode : 3;
    00182     UCHAR SelectByte : 2;
    00183     UCHAR CrContentsMoved : 1;
    00184     UCHAR OutPin : 1;
    00185 }TIMER_STATUS, *PTIMER_STATUS;
    00186
    00187 //
    00188 // Define Mode values.
    00189 //
    00190
    00191 #define TM_SIGNAL_END_OF_COUNT  0
    00192 #define TM_ONE_SHOT             1
    00193 #define TM_RATE_GENERATOR       2
    00194 #define TM_SQUARE_WAVE          3
    00195 #define TM_SOFTWARE_STROBE      4
    00196 #define TM_HARDWARE_STROBE      5
    00197
    00198 //
    00199 // Define SelectByte values
    00200 //
    00201
    00202 #define SB_COUNTER_LATCH        0
    00203 #define SB_LSB_BYTE             1
    00204 #define SB_MSB_BYTE             2
    00205 #define SB_LSB_THEN_MSB         3
    00206
    00207 //
    00208 // Define SelectCounter values.
    00209 //
    00210
    00211 #define SELECT_COUNTER_0        0
    00212 #define SELECT_COUNTER_1        1
    00213 #define SELECT_COUNTER_2        2
    00214 #define SELECT_READ_BACK        3
    00215
    00216 //
    00217 // Define Timer clock for speaker.
    00218 //
    00219
    00220 #define TIMER_CLOCK_IN  1193167     // 1.193Mhz
    00221
    00222 //
    00223 // Define NMI Status/Control register structure.
    00224 //
    00225
    00226 typedef struct _NMI_STATUS {
    00227     UCHAR SpeakerGate : 1;
    00228     UCHAR SpeakerData : 1;
    00229     UCHAR DisableEisaParity : 1;
    00230     UCHAR DisableNmi : 1;
    00231     UCHAR RefreshToggle : 1;
    00232     UCHAR SpeakerTimer : 1;
    00233     UCHAR IochkNmi : 1;
    00234     UCHAR ParityNmi : 1;
    00235 }NMI_STATUS, *PNMI_STATUS;
    00236
    00237 //
    00238 // Define NMI Enable register structure.
    00239 //
    00240
    00241 typedef struct _NMI_ENABLE {
    00242    UCHAR RtClockAddress : 7;
    00243    UCHAR NmiDisable : 1;
    00244 }NMI_ENABLE, *PNMI_ENABLE;
    00245 //
    00246 // Define the NMI extended status and control register structure.
    00247 //
    00248
    00249 typedef struct _NMI_EXTENDED_CONTROL {
    00250     UCHAR BusReset : 1;
    00251     UCHAR EnableNmiPort : 1;
    00252     UCHAR EnableFailSafeNmi : 1;
    00253     UCHAR EnableBusMasterTimeout : 1;
    00254     UCHAR Reserved1 : 1;
    00255     UCHAR PendingPortNmi : 1;
    00256     UCHAR PendingBusMasterTimeout : 1;
    00257     UCHAR PendingFailSafeNmi : 1;
    00258 }NMI_EXTENDED_CONTROL, *PNMI_EXTENDED_CONTROL;
    00259
    00260 //
    00261 // Define 82357 register structure.
    00262 //
    00263
    00264 typedef struct _EISA_CONTROL {
    00265     union   {
    00266         DMA1_CONTROL Dma1BasePort;          // Offset 0x00
    00267         struct  {
    00268             UCHAR Interrupt1ControlPort0;   // Offset 0x00
    00269             UCHAR Reserved1;
    00270             UCHAR Interrupt1ControlPort1;   // Offset 0x02
    00271             UCHAR Reserved2[5];
    00272             UCHAR Interrupt2ControlPort0;   // Offset 0x08
    00273             UCHAR Reserved3;
    00274             UCHAR Interrupt2ControlPort1;   // Offset 0x0A
    00275             UCHAR Reserved4[sizeof(DMA1_CONTROL)-11];
    00276
    00277         };
    00278     };
    00279     union {
    00280         DMA_PAGE DmaPageLowPort;                    // Offset 0x20
    00281         DMA2_CONTROL Dma2BasePort;                  // Offset 0x20
    00282         struct {
    00283             UCHAR Reserved20[9];                    // Offset 0x20
    00284             UCHAR PageIncrementMode;                // Offset 0x29
    00285             UCHAR Reserved21;
    00286             UCHAR InDirectAddress;                  // Offset 0x2b
    00287             UCHAR Reserved22;
    00288             UCHAR InDirectData;                     // Offset 0x2d
    00289             UCHAR Reserved23[0x7f - 0x2e];
    00290             UCHAR PageIncrementMode2;               // Offset 0x7f
    00291             UCHAR Reserved24[0x129 - 0x80];
    00292             UCHAR DMA2PageIncrementMode;            // Offset 0x129
    00293         };
    00294     };
    00295     UCHAR Reserved25[0xfffc - 0x130];               // Offset 0x130
    00296     //
    00297     // No NEC PC98 have 2nd DMA controller. But PC/AT has one. Therefore there are some valuable
    00298     // refer to 2nd DMA in ixisasup.c.
    00299     // I add it following valuable so that HAL builds. HAL of NEC PC98 doesn't use it.
    00300     //
    00301     UCHAR Dma1ExtendedModePort;
    00302     UCHAR Dma2ExtendedModePort;
    00303     UCHAR DmaPageHighPort;
    00304     UCHAR Interrupt1EdgeLevel;
    00305     UCHAR Interrupt2EdgeLevel;
    00306
    00307 } EISA_CONTROL, *PEISA_CONTROL;
    00308
    00309 //
    00310 // Define initialization command word 1 structure.
    00311 //
    00312
    00313 typedef struct _INITIALIZATION_COMMAND_1 {
    00314     UCHAR Icw4Needed : 1;
    00315     UCHAR CascadeMode : 1;
    00316     UCHAR Unused1 : 2;
    00317     UCHAR InitializationFlag : 1;
    00318     UCHAR Unused2 : 3;
    00319 }INITIALIZATION_COMMAND_1, *PINITIALIZATION_COMMAND_1;
    00320
    00321 //
    00322 // Define initialization command word 4 structure.
    00323 //
    00324
    00325 typedef struct _INITIALIZATION_COMMAND_4 {
    00326     UCHAR I80x86Mode : 1;
    00327     UCHAR AutoEndOfInterruptMode : 1;
    00328     UCHAR Unused1 : 2;
    00329     UCHAR SpecialFullyNested : 1;
    00330     UCHAR Unused2 : 3;
    00331 }INITIALIZATION_COMMAND_4, *PINITIALIZATION_COMMAND_4;
    00332
    00333 //
    00334 // Define EISA interrupt controller operational command values.
    00335 // Define operation control word 2 commands.
    00336 //
    00337
    00338 #define NONSPECIFIC_END_OF_INTERRUPT 0x20
    00339 #define SPECIFIC_END_OF_INTERRUPT    0x60
    00340
    00341 //
    00342 // Define external EISA interupts
    00343 //
    00344
    00345 #define EISA_EXTERNAL_INTERRUPTS_1  0xf8
    00346 #define EISA_EXTERNAL_INTERRUPTS_2  0xbe
    00347
    00348 //
    00349 // Define the DMA mode register structure.
    00350 //
    00351
    00352 typedef struct _DMA_EISA_MODE {
    00353     UCHAR Channel : 2;
    00354     UCHAR TransferType : 2;
    00355     UCHAR AutoInitialize : 1;
    00356     UCHAR AddressDecrement : 1;
    00357     UCHAR RequestMode : 2;
    00358 }DMA_EISA_MODE, *PDMA_EISA_MODE;
    00359
    00360 //
    00361 // Define TransferType values.
    00362 //
    00363
    00364 #define VERIFY_TRANSFER     0x00
    00365 #define READ_TRANSFER       0x01        // Read from the device.
    00366 #define WRITE_TRANSFER      0x02        // Write to the device.
    00367
    00368 //
    00369 // Define RequestMode values.
    00370 //
    00371
    00372 #define DEMAND_REQUEST_MODE         0x00
    00373 #define SINGLE_REQUEST_MODE         0x01
    00374 #define BLOCK_REQUEST_MODE          0x02
    00375 #define CASCADE_REQUEST_MODE        0x03
    00376
    00377 //
    00378 // Define the DMA extended mode register structure.
    00379 //
    00380
    00381 typedef struct _DMA_EXTENDED_MODE {
    00382     UCHAR ChannelNumber : 2;
    00383     UCHAR TransferSize : 2;
    00384     UCHAR TimingMode : 2;
    00385     UCHAR EndOfPacketInput : 1;
    00386     UCHAR StopRegisterEnabled : 1;
    00387 }DMA_EXTENDED_MODE, *PDMA_EXTENDED_MODE;
    00388
    00389 //
    00390 // Define the DMA extended mode register transfer size values.
    00391 //
    00392
    00393 #define BY_BYTE_8_BITS      0
    00394 #define BY_WORD_16_BITS     1
    00395 #define BY_BYTE_32_BITS     2
    00396 #define BY_BYTE_16_BITS     3
    00397
    00398 //
    00399 // Define the DMA extended mode timing mode values.
    00400 //
    00401
    00402 #define COMPATIBLITY_TIMING 0
    00403 #define TYPE_A_TIMING       1
    00404 #define TYPE_B_TIMING       2
    00405 #define BURST_TIMING        3
    00406
    00407 #ifndef DMA1_COMMAND_STATUS
    00408
    00409
    00410 //
    00411 // Define constants used by Intel 8237A DMA chip
    00412 //
    00413
    00414 #define DMA_SETMASK     4
    00415 #define DMA_CLEARMASK       0
    00416 #define DMA_READ            4  // These two appear backwards, but I think
    00417 #define DMA_WRITE           8  // the DMA docs have them mixed up
    00418 #define DMA_SINGLE_TRANSFER 0x40
    00419 #define DMA_AUTO_INIT       0x10 // Auto initialization mode
    00420 #endif
    00421
    00422
    00423 //
    00424 // This structure is drive layout and partition information
    00425 // for NEC PC-98xx series.
    00426 //
    00427
    00428 typedef struct _PARTITION_INFORMATION_NEC {
    00429     UCHAR PartitionType;
    00430     BOOLEAN RecognizedPartition;
    00431     BOOLEAN RewritePartition;
    00432     ULONG PartitionNumber;
    00433     LARGE_INTEGER IplStartOffset;
    00434     LARGE_INTEGER StartingOffset;
    00435     LARGE_INTEGER PartitionLength;
    00436     UCHAR BootableFlag;
    00437     UCHAR PartitionName[16];
    00438 } PARTITION_INFORMATION_NEC, *PPARTITION_INFORMATION_NEC;
    00439
    00440 typedef struct _DRIVE_LAYOUT_INFORMATION_NEC {
    00441     ULONG PartitionCount;
    00442     ULONG Signature;
    00443     UCHAR BootRecordNec[8];
    00444     PARTITION_INFORMATION_NEC PartitionEntry[1];
    00445 } DRIVE_LAYOUT_INFORMATION_NEC, *PDRIVE_LAYOUT_INFORMATION_NEC;
    00446
    00447 //
    00448 // The system has memory over 16MB ?
    00449 //
    00450 extern UCHAR Over16MBMemoryFlag;
    00451
    00452 //
    00453 // We can't use DMA between 15MB and 16MB.
    00454 //
    00455 #define NOTDMA_MINIMUM_PHYSICAL_ADDRESS 0x0f00000
    00456
    00457 //
    00458 //
    00459 //
    00460 VOID
    00461 FASTCALL
    00462 xHalExamineMBR(
    00463     IN PDEVICE_OBJECT DeviceObject,
    00464     IN ULONG SectorSize,
    00465     IN ULONG MBRTypeIdentifier,
    00466     OUT PVOID *Buffer
    00467     );
    00468
    00469 VOID
    00470 FASTCALL
    00471 xHalIoAssignDriveLetters(
    00472     IN struct _LOADER_PARAMETER_BLOCK *LoaderBlock,
    00473     IN PSTRING NtDeviceName,
    00474     OUT PUCHAR NtSystemPath,
    00475     OUT PSTRING NtSystemPathString
    00476     );
    00477
    00478 NTSTATUS
    00479 FASTCALL
    00480 xHalIoReadPartitionTable(
    00481     IN PDEVICE_OBJECT DeviceObject,
    00482     IN ULONG SectorSize,
    00483     IN BOOLEAN ReturnRecognizedPartitions,
    00484     OUT struct _DRIVE_LAYOUT_INFORMATION **PartitionBuffer
    00485     );
    00486
    00487 NTSTATUS
    00488 FASTCALL
    00489 xHalIoSetPartitionInformation(
    00490     IN PDEVICE_OBJECT DeviceObject,
    00491     IN ULONG SectorSize,
    00492     IN ULONG PartitionNumber,
    00493     IN ULONG PartitionType
    00494     );
    00495
    00496 NTSTATUS
    00497 FASTCALL
    00498 xHalIoWritePartitionTable(
    00499     IN PDEVICE_OBJECT DeviceObject,
    00500     IN ULONG SectorSize,
    00501     IN ULONG SectorsPerTrack,
    00502     IN ULONG NumberOfHeads,
    00503     IN struct _DRIVE_LAYOUT_INFORMATION *PartitionBuffer
    00504     );
    00505
    00506 #endif //_EISA_