test: vga.h Source File

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# vga.h

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    00001 /*++
    00002
    00003 Copyright (c) 1992  Microsoft Corporation
    00004
    00005 Module Name:
    00006
    00007     vga.h
    00008
    00009 Abstract:
    00010
    00011     This module contains the definitions for the code that implements the
    00012     VGA device driver.
    00013
    00014 Author:
    00015
    00016 Environment:
    00017
    00018     Kernel mode
    00019
    00020 Revision History:
    00021
    00022
    00023 --*/
    00024
    00025
    00026
    00027
    00028 //
    00029 // Base address of VGA memory range.  Also used as base address of VGA
    00030 // memory when loading a font, which is done with the VGA mapped at A0000.
    00031 //
    00032
    00033 #define MEM_VGA      0xA0000
    00034 #define MEM_VGA_SIZE 0x20000
    00035
    00036 //
    00037 // Index in the access range sturture for video memory
    00038 // !!! This must match the VgaAccessRange structure    !!!
    00039 // !!! Memory is in the structure, index 2 (3rd entry) !!!
    00040
    00041 #define VGA_MEMORY  2
    00042
    00043
    00044 //
    00045 // VGA port-related definitions.
    00046 //
    00047 //
    00048 // Port definitions for filling the ACCSES_RANGES structure in the miniport
    00049 // information, defines the range of I/O ports the VGA spans.
    00050 // There is a break in the IO ports - a few ports are used for the parallel
    00051 // port. Those cannot be defined in the ACCESS_RANGE, but are still mapped
    00052 // so all VGA ports are in one address range.
    00053 //
    00054
    00055 #define VGA_BASE_IO_PORT      0x000003B0
    00056 #define VGA_START_BREAK_PORT  0x000003BB
    00057 #define VGA_END_BREAK_PORT    0x000003C0
    00058 #define VGA_MAX_IO_PORT       0x000003DF
    00059
    00060 //
    00061 // VGA register definitions
    00062 //
    00063                                             // ports in monochrome mode
    00064 #define CRTC_ADDRESS_PORT_MONO      0x0004  // CRT Controller Address and
    00065 #define CRTC_DATA_PORT_MONO         0x0005  // Data registers in mono mode
    00066 #define FEAT_CTRL_WRITE_PORT_MONO   0x000A  // Feature Control write port
    00067                                             // in mono mode
    00068 #define INPUT_STATUS_1_MONO         0x000A  // Input Status 1 register read
    00069                                             // port in mono mode
    00070 #define ATT_INITIALIZE_PORT_MONO    INPUT_STATUS_1_MONO
    00071                                             // Register to read to reset
    00072                                             // Attribute Controller index/data
    00073
    00074 #define ATT_ADDRESS_PORT            0x0010  // Attribute Controller Address and
    00075 #define ATT_DATA_WRITE_PORT         0x0010  // Data registers share one port
    00076                                             // for writes, but only Address is
    00077                                             // readable at 0x3C0
    00078 #define ATT_DATA_READ_PORT          0x0011  // Attribute Controller Data reg is
    00079                                             // readable here
    00080 #define MISC_OUTPUT_REG_WRITE_PORT  0x0012  // Miscellaneous Output reg write
    00081                                             // port
    00082 #define INPUT_STATUS_0_PORT         0x0012  // Input Status 0 register read
    00083                                             // port
    00084 #define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013  // Bit 0 enables/disables the
    00085                                             // entire VGA subsystem
    00086 #define SEQ_ADDRESS_PORT            0x0014  // Sequence Controller Address and
    00087 #define SEQ_DATA_PORT               0x0015  // Data registers
    00088 #define DAC_PIXEL_MASK_PORT         0x0016  // DAC pixel mask reg
    00089 #define DAC_ADDRESS_READ_PORT       0x0017  // DAC register read index reg,
    00090                                             // write-only
    00091 #define DAC_STATE_PORT              0x0017  // DAC state (read/write),
    00092                                             // read-only
    00093 #define DAC_ADDRESS_WRITE_PORT      0x0018  // DAC register write index reg
    00094 #define DAC_DATA_REG_PORT           0x0019  // DAC data transfer reg
    00095 #define FEAT_CTRL_READ_PORT         0x001A  // Feature Control read port
    00096 #define MISC_OUTPUT_REG_READ_PORT   0x001C  // Miscellaneous Output reg read
    00097                                             // port
    00098 #define GRAPH_ADDRESS_PORT          0x001E  // Graphics Controller Address
    00099 #define GRAPH_DATA_PORT             0x001F  // and Data registers
    00100
    00101 #define CRTC_ADDRESS_PORT_COLOR     0x0024  // CRT Controller Address and
    00102 #define CRTC_DATA_PORT_COLOR        0x0025  // Data registers in color mode
    00103 #define FEAT_CTRL_WRITE_PORT_COLOR  0x002A  // Feature Control write port
    00104 #define INPUT_STATUS_1_COLOR        0x002A  // Input Status 1 register read
    00105                                             // port in color mode
    00106 #define ATT_INITIALIZE_PORT_COLOR   INPUT_STATUS_1_COLOR
    00107                                             // Register to read to reset
    00108                                             // Attribute Controller index/data
    00109                                             // toggle in color mode
    00110
    00111
    00112 //
    00113 // VGA indexed register indexes.
    00114 //
    00115
    00116 #define IND_CURSOR_START        0x0A    // index in CRTC of the Cursor Start
    00117 #define IND_CURSOR_END          0x0B    //  and End registers
    00118 #define IND_CURSOR_HIGH_LOC     0x0E    // index in CRTC of the Cursor Location
    00119 #define IND_CURSOR_LOW_LOC      0x0F    //  High and Low Registers
    00120 #define IND_VSYNC_END           0x11    // index in CRTC of the Vertical Sync
    00121                                         //  End register, which has the bit
    00122                                         //  that protects/unprotects CRTC
    00123                                         //  index registers 0-7
    00124 #define IND_SET_RESET_ENABLE    0x01    // index of Set/Reset Enable reg in GC
    00125 #define IND_DATA_ROTATE         0x03    // index of Data Rotate reg in GC
    00126 #define IND_READ_MAP            0x04    // index of Read Map reg in Graph Ctlr
    00127 #define IND_GRAPH_MODE          0x05    // index of Mode reg in Graph Ctlr
    00128 #define IND_GRAPH_MISC          0x06    // index of Misc reg in Graph Ctlr
    00129 #define IND_BIT_MASK            0x08    // index of Bit Mask reg in Graph Ctlr
    00130 #define IND_SYNC_RESET          0x00    // index of Sync Reset reg in Seq
    00131 #define IND_MAP_MASK            0x02    // index of Map Mask in Sequencer
    00132 #define IND_MEMORY_MODE         0x04    // index of Memory Mode reg in Seq
    00133 #define IND_CRTC_PROTECT        0x11    // index of reg containing regs 0-7 in
    00134                                         //  CRTC
    00135 #define IND_START_ADRS_H        0x0C    // index in CRTC of Start Address (high)
    00136 #define IND_START_ADRS_L        0x0D    // index in CRTC of Start Address (low)
    00137 #define IND_LINE_COMPARE        0x18    // index in CRTC of Line Compare (bit7-0)
    00138 #define IND_LINE_COMPARE8       0x07    // index in CRTC of Line Compare (bit8)
    00139 #define IND_LINE_COMPARE9       0x09    // index in CRTC of Line Compare (bit9)
    00140 #define IND_SET_RESET           0x00    // index of Set/Reset Plane Color Register in Graph Ctrl
    00141 #define IND_COLOR_DONT_CARE     0x07    // index of Color Don't Care Register in Graph Ctrl
    00142
    00143 #define START_SYNC_RESET_VALUE  0x01    // value for Sync Reset reg to start
    00144                                         //  synchronous reset
    00145 #define END_SYNC_RESET_VALUE    0x03    // value for Sync Reset reg to end
    00146                                         //  synchronous reset
    00147
    00148 //
    00149 // Values for Attribute Controller Index register to turn video off
    00150 // and on, by setting bit 5 to 0 (off) or 1 (on).
    00151 //
    00152
    00153 #define VIDEO_DISABLE 0
    00154 #define VIDEO_ENABLE  0x20
    00155
    00156 //
    00157 // Value written to the Read Map register when identifying the existence of
    00158 // a VGA in VgaInitialize. This value must be different from the final test
    00159 // value written to the Bit Mask in that routine.
    00160 //
    00161
    00162 #define READ_MAP_TEST_SETTING 0x03
    00163
    00164 //
    00165 // Masks to keep only the significant bits of the Graphics Controller and
    00166 // Sequencer Address registers. Masking is necessary because some VGAs, such
    00167 // as S3-based ones, don't return unused bits set to 0, and some SVGAs use
    00168 // these bits if extensions are enabled.
    00169 //
    00170
    00171 #define GRAPH_ADDR_MASK 0x0F
    00172 #define SEQ_ADDR_MASK   0x07
    00173
    00174 //
    00175 // IND_DATA_ROTATE : index of Data Rotate reg in GC
    00176 //
    00177 #define DR_ROT_CNT      0x07   // Data Rotate Count
    00178 #define DR_SET          0x00   // Data Unmodified
    00179 #define DR_AND          0x08   // Data ANDed with latches
    00180 #define DR_OR           0x10   // Data ORed    with latches
    00181 #define DR_XOR          0x18   // Data XORed with latches
    00182
    00183 //
    00184 // IND_GRAPH_MODE : index of Mode reg in Graph Ctlr
    00185 //
    00186 #define M_PROC_WRITE    0x00   // Write processor data rotated
    00187 #define M_LATCH_WRITE   0x01   // Write latched data
    00188 #define M_COLOR_WRITE   0x02   // Write processor data as color
    00189 #define M_AND_WRITE     0x03   // Write (procdata AND bitmask)
    00190 #define M_DATA_READ     0x00   // Read selected plane
    00191 #define M_COLOR_READ    0x08   // Read color compare
    00192
    00193 //
    00194 // Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register.
    00195 //
    00196
    00197 #define CHAIN4_MASK 0x08
    00198
    00199 //
    00200 // Default text mode setting for various registers, used to restore their
    00201 // states if VGA detection fails after they've been modified.
    00202 //
    00203
    00204 #define MEMORY_MODE_TEXT_DEFAULT 0x02
    00205 #define BIT_MASK_DEFAULT 0xFF
    00206 #define READ_MAP_DEFAULT 0x00
    00207
    00208 //
    00209 // Palette-related info.
    00210 //
    00211
    00212 //
    00213 // Highest valid DAC color register index.
    00214 //
    00215
    00216 #define VIDEO_MAX_COLOR_REGISTER  0xFF
    00217
    00218 //
    00219 // Highest valid palette register index
    00220 //
    00221
    00222 #define VIDEO_MAX_PALETTE_REGISTER 0x0F
    00223