===========================================================================================
QUANTA Computer Inc. BIOS RELEASE NOTES for S2S/S2SP+/S2SD/S2SR
===========================================================================================
Project Name      : S2S/S2SP+/S2SD/S2SR
BIOS Version      : S2S_3B06.03
Build Date        : 2016/08/22
Update BootBlock  : YES
Clear NVRAM       : YES
BIN Checksum(16MB): CBE53708
ROM Checksum(8MB) : 565A3401
BIN MD5(16MB)     : 01256f603ad2220ab3868d3665457640
ROM MD5(8MB)      : 59fbf8b4fe5b48f06fe5a0e372fc8ef7
===========================================================================================
                             HARDWARE REQUIREMENTS/REVISIONS
===========================================================================================
System hardware revision supported: S2S FAB5 or FAB6 board. 

===========================================================================================
                             INTEL PROCESSOR MICROCODE REVISIONS
===========================================================================================
----------------------+---------------------------------------------+----------------------
Filename              | Description                                 | Stepping(s)     
----------------------+---------------------------------------------+----------------------
M6F306F2_00000036.mcb | Protein Data Bank format, Revision 00000036 | C-0       (Haswell EP)
M6F306F2_00000036.mcb | Protein Data Bank format, Revision 00000036 | C-1 / M-1 (Haswell EP)
M6F306F2_00000036.mcb | Protein Data Bank format, Revision 00000036 | R-2       (Haswell EP)
MEF406F0_00000014.mcb | Protein Data Bank format, Revision 00000014 | A-0 / A-1 (Broadwell EP)
MEF406F0_00000014.mcb | Protein Data Bank format, Revision 00000014 | L-0       (Broadwell EP)
MEF406F1_0B000014.mcb | Protein Data Bank format, Revision 0B000014 | M-0 / R-0 (Broadwell EP)
MEF406F1_0B000014.mcb | Protein Data Bank format, Revision 0B000014 | B-0       (Broadwell EP)
----------------------+---------------------------------------------+----------------------
===========================================================================================
                             SYSTEM FIRMWARE REQUIREMENTS/REVISIONS
===========================================================================================
BIOS Core Version                : 5.11
BIOS Compliancy                  : UEFI 2.4.0; PI 1.3
VGA (embedded in AST2400)        : 1.00.07
Intel(R) PCH SATA/sSATA RAID     : 4.3.0.1018
Intel(R) SPS F/W (ME)            : SPS_E5_03.01.03.021.0
Quanta ME Configuration          : v3.01.03.021, vendor label (0x0000011)
Intel(R) QPI and MRC             : 3.00
Intel(R) PCH RC                  : 3.00
Intel(R) BIOS ACM                : PW 3.0.2
Intel(R) SINIT ACM               : PW 3.0.1

===========================================================================================
                             IMPORTANT INSTALLATION NOTES
===========================================================================================
WARNING:
   It is very important to follow the flash option provided in the batch file 
   BIOS_efi64.nsh/ME_efi64.nsh for EFI, 
   BIOS_win64.cmd/ME_win64.cmd for Windows, 
   BIOS_lnx64.sh/ME_lnx64.sh for Linux. 
   Using incorrect flash option to flash BIOS may cause damage to your system.

   There are two way to flash BIOS image.
   1. Burn S2S_xxxx.BIN via fixture or,

   2. Update BIOS region by AFU tool:
   For EFI environment, follow below steps to update both BIOS and ME FW:
   (1) Unzip the release package to the same folder in a HDD or USB Flash Drive with bootable DOS.
   (2) Insert the USB Flash Drive or HDD mentioned in step (1).
   (3) Power on the system and boot into this build-in UEFI SHELL, and enter the update file location of the USB Flash Drive or HDD.
   (4) Execute batch file BIOS_efi64.nsh to update BIOS.
   (5) Execute batch file ME_efi64.nsh to update ME FW.
   (6) After the update finished, perform an DC cycle, the new BIOS/ME FW runs.
   (7) Then, please enter setup, press <F9> to load default and save before any test run.

   For x64 Windows environment, follow below steps to update both BIOS and ME FW:
   (1) Power on the system and boot into Windows OS.
   (2) Unzip the release package to the same folder in the HDD.
   (3) Open Command Prompt, change to the folder with release package located.
   (4) Execute batch file BIOS_win64.cmd to update BIOS.
   (5) Execute batch file ME_win64.cmd to update ME FW.
   (6) After the update finished, perform an DC cycle, the new BIOS/ME FW runs.
   (7) Then, please enter setup, press <F9> to load default and save before any test run.
   
   For x64 Linux environment, follow below steps to update both BIOS and ME FW:
   (1) Power on the system and boot into Linux OS.
   (2) Unzip the release package to the same folder in the HDD.
   (3) Open Terminal, change to the folder with release package located.
   (4) Execute batch file BIOS_lnx64.sh to update BIOS.
   (5) Execute batch file ME_lnx64.sh to update ME FW.
   (6) After the update finished, perform an DC cycle, the new BIOS/ME FW runs.
   (7) Then, please enter setup, press <F9> to load default and save before any test run.
   
Note:
- Current AFU tool version: v5.08.02.1189(EFI), v5.08.02.1200(LNX,WIN)
- BIOS_efi64.nsh/BIOS_win64.cmd/BIOS_lnx64.sh updates BIOS regions only.
- ME_efi64.nsh/ME_win64.cmd/ME_lnx64.sh updates ME firmware regions only.
- S2S_xxxx.BIN, S2S_xxxx.ROM, "xxxx" is version name as 3B06.03.....
- BIOS update script will use '/N' by default, please note that this parameter will clear all BIOS Setup setting,
  this is for avoid NV structure be changed after RC/Module updated.
  If you can make sure the RC version is the same, you can remove 'N' parameter by yourself.
- In RHEL7.0 must use chmod 755 to change privilege of afulnx_64, BIOS_lnx64.sh, ME_lnx64.sh, otherwise
  flash BIOS can not start.  
  
===========================================================================================
                             KNOWN ISSUES/WORKAROUNDS
===========================================================================================
- Please update CPLD first to support Broadwell two CPU configuration, or it may not boot up.
- From previous BIOS 2BXX update to version after 3B02, it would need to add /X to avoid ROMID issue.
===========================================================================================
                             FEATURES ADDED/MODIFY
===========================================================================================
S2S_3B06.03:
- N/A.

S2S_3B06.02:
- Follow EA provided data to modify PCH SATA setting for re-spain S2S/S2SP MB.
- Modify customer setting and Show "Pending operation" setup option.
- Correct the "Pwr/Perf Profiles" related "Enforce POR" option to Enforce Stretch Goal
  and also update DDR4 Stretch Goal table frequency as Intel POR design.
- Update S2SD MB PCIe CTLE for HSW port3AB.
- Limit MMIO to 42bit for memory BARs for ESXi.

S2S_3B06.01:
- Show "4G above decoding" setup option for S2SD projects.
- Implement QCT leaky bucket parameter for about 15mins.
- Change QCT default "Spare Error/Memory Correctable Threshold" value to 1000.

S2S_3B06:
- N/A.

S2S_3B05:
- Follow EA measure to update S2S MB PCIe CTLE for HSW CPU.
- Based on MB position to set NTB USD_DSP/DSD_USP automatically for S2SR sku.
- Change PCIE SSC default to disable and Enable the ICC Override function in POST for S2S/S2SP but keep disable for S2SR/S2SD.
- Sync from HSW trunk for support new Memory CAParity error SEL.
- Update Broadwell-EP B0/M0/R0 stepping CPU Microcode to version "MEF406F1_0B000014.mcb".
- Update "TCG2" module to TCG2_08 from TCG2_07.

S2S_3B04:
- Sync to CRB 5.011_MayanCity_0ACFL022 for MRC v3.00 and Microcode update.
- Update ME config to 03.01.03.021.0
  
S2S_3B03:
- Sync to CRB 5.011_MayanCity_0ACFL021 for MRC v2.95 and Microcode update.
- Update ME config to 03.01.03.018.0
- Update PCH SATA controller RX GEN3 setting for HDD missing issue for S2SP Plus.
- Fix the ECC Error Disable Threshold function with Haswell CPU.
- POR update: Add 1R RDIMM and UDIMM configs.
- Grayout setup options of device BBS Priorities for User Access Level.
- Implement PPR feature for SEL log and IPMI control
- Implement Power LED when BMC is Disabled for S2S serious.
- Follow EA mesure to set S2S MB PCIe CTLE for BDW/HSW CPU.

S2S_3B02:
- Sync to CRB 5.011_MayanCity_0ACFL018 for MRC v2.40 and Microcode update.
- Update ME config to 03.01.03.005.0
- Changed "Enter Setup" hot-key from F12 to F2 for some post error messages. 
- Fixed that IPv6 IP Address have incorrect strings when input error address.
- Let AFU only chack 4 characters of BIOS version instead of 5 when update BIOS without /X.
- Adding PW ACM 3.0.1 support.
- Default enable token "LSI_CORRECTABLE_ERRORS_MASK" for all projects.
- Follow SI standard revision 2.25 to supress "Authorized TimeStamps" in setup.
- Update SATA/sSATA RSTe to version 4.3.0.1018.
- Change the asset tag of "DMI Type 3" mapping to asset tag of BMC FRU ID 1
- Refer S2V_vivi039 to Follow EA mesure to set S2S MB IIO DMI/PCIe CTLE for BDW/HSW CPU.
- Fix incorrect parameter for getting variable in ChgStdDefault.
- Correct the SMBIOS Type 8 "XTP" to "XDP" string.

S2S_2B03:
- Sync to CRB 5.011_MayanCity_0ACFL016 for MRC v1.90 and Microcode update.
- Update ME config to 03.01.03.001.0
- Follow IPMI spec to modify event data field formats.

S2S_2B02:
- Dynamically disable "Link L1 Enable" based on CPUID
- PCIe ECRC error handling for BDW CPU.
- Modify logdata to obey MRC error debug led format
- Follow SI to set setup item "Enable ADR" to default disable.
- Workaround when using 2400 1DPC Configuration MRC may fail advanced training
- Sync to CRB 5.011_MayanCity_0ACFL013a for MRC v1.80 and microcode 12(BDW) / 31(HSW).
- Update ME config to 03.01.02.005.0

S2S_2C01:
- Initial release for Broadwell CPU.

===========================================================================================
                             FEATURES REMOVED
===========================================================================================
S2S_3B06.03:
- N/A.

S2S_3B06.02:
- N/A.

S2S_3B06.01:
- N/A.

S2S_3B06:
- N/A.

S2S_3B05:
- N/A.

S2S_3B04:
- N/A.

S2S_3B03:
- N/A.

S2S_3B02:
- N/A.

S2S_2B03:
- N/A.

S2S_2B02:
- N/A.

S2S_2C01:
- N/A.
===========================================================================================
                             ISSUES FIXED
===========================================================================================
S2S_3B06.03:
- Fix the wrong "Enforce POR" setting for customer.

S2S_3B06.02:
- Modify BMC Revision Major Number to Decimal format.
- Fix When "No Bootable Device Detected" message show up and wait in POST, the FRB-2 Watchdog still trigger after time-out
- Tracker #182815:[S2S HSX/BDX] TPM status didn't change after VMware 6.0 installation
- Tracker #165059:[SMBIOS] [REG10]There are some SMBIOS info incorrect
- Tracker #167870:[OOB651] (Reg29)(MTK)There are some SMBIOS info incorrect
- Tracker #183218:SMBIOS-Type 8 Port Connector Information some of External Reference Designator strings mismatched with HW spec v05 Silkscreen list.
- Tracker #183161:SMBIOS Type9 Designation string have row data. (should be meet silkscreen table)
- Correct the SMBIOS Type 16 Memory Array - Error Correction Types
- Fix the hang postcode 0x9a issue in QSMC when using Debug module to boot up.

S2S_3B06.01:
- N/A.

S2S_3B06:
- Tracker #170645: [Certification]The system occurs SEL "Machine Check Exception(MCERR)-Asserted" and hang up during WHEAHCT Logo(WHCK) test
- Tracker #176759: [PVT]The system can't boot into QS 3008 Legacy RH 7.1 successfully with BIOS 3B05
- Tracker #176813: [PVT]The system can't boot into QS 3008 Legacy RH 7.1 successfully under BIOS 3B05
- Correct the "Pwr/Perf Profiles" desired default by F9 hotkey per different board ID images.
- Fix 2 Dual-port Intel SSD D3X00 can't boot up issue.
- Tracker #177278: [PVT]The bus address on SMBIOS Type 41 is incorrect
- Correct the "CAP ERR FLOW feature Control" option Auto Behavior to fix Memory Cap Error Hang in HSW.

S2S_3B05:
- Tracker #171431: BIOS version name won't change after downgrade/upgrade/reflash the BIOS under RHEL7 by script after use amidelnx to modify BIOS version name.
- Tracker #171335: The Front Panel Power LED doesn't change to Blue/Amber blinking when system power on and error occurs
- Tracker #173060: [S2S/BDW/PVT] The Front Panel power LED is not Blue/Amber blinking when system error log occur.
- Tracker #173443: Boot override doesn't have EFI shell option after enable secure boot.
- Tracker #171234: The "Ports number of PCIe SSD" doesn't show under Boot order/Override/Popup menu on S2SP Plus
- Tracker #173163: The POST still show "0xA104 : CMOS/NVRAM configuration cleared" message after replace battery then reboot under BIOS (msg shows twice)
- Tracker #174623: Help text of the Hyper-Threading [ALL] missing symbol ")". 
- Tracker #175258: [BIOS Sanity] The parameter of BIOS 3B04.LNK01 doesn't meet standard rule (doesn't define /X) , but this BIOS adds parameter ''/X''

S2S_3B04:
- Tracker #160278: [OOB395]The MD5 of Release note are different from the actual reading of x.BIN and x.ROM file.
- Tracker #165059: [REG10]There are some SMBIOS info incorrect
- Tracker #167870: [OOB651] (Reg29)(MTK)There are some SMBIOS info incorrect

S2S_3B03:
- Tracker #169544: [S2S/BDW/DVT] TPM provision is failed under UEFI Shell. (S2B: 161819)
- Tracker #169557: Typo "S2S" on S2SP Plus BIOS 2B02 README.TXT.
- Tracker #169977: SymptomS2SP Plus doesn't support BDW CPU now but BIOS item name under VRC is BIOS_BDW and Release Note also show supports, it will confuse users.
- Tracker #170194: [SMBIOS] Incorrect SMBIOS port type 8 info "SATA" for several onboard connectors.
- Tracker #170204: [SMBIOS] Incorrect SMBIOS port type "SAS" for the port "KR/MNGNT".
- Tracker #170271: BIOS 2B02 README file mismatch to rule "BIOS Readme should define the impact about flash parameter /N."
- Tracker #170539: BIOS 2B02 ReadMe file only mentions "supported FAB3/4", but currently our MB is FAB5/6
         
S2S_3B02:
- Tracker #163712: [REG17]The BIOS 2B02 Setup menu doesn't meet BIOS Standard Spec
- Tracker #163715: [REG17]The FRB-2 Timer Policy default value under BIOS 2B02 is incorrect, it should be ''Do Nothing'' not ''Reset''
- Tracker #163956: [REG17]The system will hang up when press Discard Changes and Exit under BIOS
- Tracker #163960: [REG17]The System MAC under BMC WebUI only shows 1 port of QN 40GbE CX3 Mezz(36S4ELB0010) but QN 40GbE CX3 Mezz has two ports
- Tracker #164067: [REG17]The TPM 2.0 items are different among "BIOS Advanced page", "Project BIOS SPEC" and "Std_BIOS SPEC".
- Tracker #164219: [REG17]There are several failed and warning items about SelfTest items with IDK tests
- Tracker #166818: [Reg 17] (BDW DVT) The system can't boot successfully and SEL will show Watchdog timeout SEL if TXT is enabled under BIOS

S2S_2B03:
- Tracker #163127: [REG17]The Core Version and BIOS Compliancy under BIOS menu don't meet BIOS Spec
- Tracker #163131: [REG17]The Altitude under BIOS/IntelRCSetup/General ME Configuration is gray out and can't set up
- Tracker #163587: [REG17]The USB Port screen under BIOS doesn't meet BIOS Standard Spec
- Tracker #163643: [REG17]The item ''Set Max Allowed CPU P-state/T-state'' is failed under ME test
- Tracker #163734: [REG17]The option ''2400'' for DDR4 Memory Frequency will miss after press F9 to load default (S4P: 162828)
- Tracker #163740: [REG17]CPU ID and Update Revision don't match BIOS README file of all CPU Micorcode revision
- Tracker #163773: [REG17]The system can't boot into OS successfully when Hyper-Threading is disabled and CPU Socket x Configuration-Cores Enabled sets to ''1''
- Tracker #163815: [REG17]The system can't boot into OS successfully and SEL will show FRB2 Watchdog timeout when system installs QN 10GbE X540 Mezz and disable ''PCI-Ex Error Enable'' under BIOS
- Tracker #163900: [REG17]The USB string of Mass Storage Devices doesn't show completely under S2S (S2B eTrack: 163250)
- Tracker #163960: [REG17]The System MAC under BMC WebUI only shows 1 port of QN 40GbE CX3 Mezz(36S4ELB0010) but QN 40GbE CX3 Mezz has two ports
- Tracker #163976: [REG17]The system will hang up at BIOS POST code 92 when press F2 to boot into BIOS
- Tracker #163991: [REG17]The window of typing passwd is abnormal after setting passwd for HDD security erase(S2P eTrack:151118)
- Tracker #164017: [REG17]Some BIOS items could be changed with User Access level(S2B eTrack:163241)
- Tracker #164045: [REG17]COM port A miss under W2012 R2 on S2S
- Fix the items of PCIe "Corrected/Uncorrected/Fatal Error Enable" are disable that can work abnormally.
- Fix incorrect NULL register descriptor for _CPC.

S2S_2B02:
- Tracker #158627 - Run UEFI iPXE DC cycle(IPv6 only) with dual port CX3, system fail to boot into iPXE at loop 15 with "PXE-E99: Unexpected network error" message.
- Correct the SMI clear status process for Correctable ECC
- Fix AFU ME update do NOT update DER region
- Tracker #161386 - [BDW-EP] SEL will not log "Correctable ECC Logging Limit Reached" and "Correctable Memory Error Logging Disabled" event after SEL log 10 correctable ECC events.        
- Fix debug mode will fail when boot to DOS or install PCIe lan card.
- Tracker #155829 - The value of "Number Of Power Cords" and "Height" in SMBIOS Type 3 is incorrect
- Tracker #155834 - SMBIOS Type8 info ("External Connector Type" and "Port Type") for VGA is not consistent with SPEC definition.
- Tracker #155896 - System slots information within SMBIOS is not consisten with HW designation
- Tracker #151954 - [AVL][ONi350]There are no NIC number and chipset info for UEFI PXE boot device in BIOS setup utility.
- Tracker #154583 - The Intel PCIe SSD (FW1.10) cannot initialization and will show "GPT Protective Partition" under Windows 2012 R2 Datacenter (FW54 passed)
- Tracker #155830 - After safety remove Samsung PCIe SSD(IPM0CB3Z), the OS log do not have "Device is Prepared for Safe Removal" log 
                    and the device controller will disappear one second then show again with error in Device Managerment
- Tracker #159845 - [2015 Q2] CSM function still Enable after setting Secure Boot to enable.(BIOS Help shows it should CSM function should be disable)
- Tracker #159534 - [2015 Q2]The OCP Mezz/Quanta Mezz MAC miss under BMC WebUI when Disabled "Legacy OpRom Support" (S2B:158542)
- Correct the "Altitude" option help string for "sea level"
- Tracker #155736 - [MTK OOB] E5-2643 V3 QGSR CPU L3 Cache size is 40960KB under BIOS 3B01, mismatch to DCL definition 20480KB.
- Tracker #158445: [OOB239](3108 AVL) The BIOS "Help" page of QS3108 does not slide smoothly and has some garbage words.
- Tracker #159513: [Customer report]Failed to Set boot device to PXE with BIOS legacy mode by using IPMI command
- Fix wrong for loop condition while printing onboard/mezz Lan device information.
- Fix PCIe CTLE values don't work on BDW
- Fix system would hang after booting into Linux while disabled "BMC support"
- Fix QPI CTLE value for BDW CPU
                   
S2S_2C01:
- N/A.

[END OF RELEASE NOTES]
