===========================================================================================
Hitachi Vantara BIOS RELEASE NOTES for S5BH/S5BVH
===========================================================================================
Project Name      : S5BH/S5BVH
BIOS Version      : S5BH3B27.H00
Build Date        : 2023/09/21
Update BootBlock  : YES
Clear NVRAM       : YES
BIN Checksum(32MB): 5925B033
ROM Checksum(16MB): A410BF87
BIN_enc Checksum  : 5925F8B2
BIN MD5(32MB)     : 1319D375F198FE41BDE9372C9598AA3A
ROM MD5(16MB)     : D5A79D99D962FA0A6B144D5CF806B3A7
BIN_enc MD5       : 395B2DE518A2EED1AB648A69608DC240

===========================================================================================
                             HARDWARE REQUIREMENTS/REVISIONS
===========================================================================================
System hardware revision supported: S5BH (1U/2U)/S5BVH motherboard. (B0/B1/S0 PCH)

===========================================================================================
                             INTEL PROCESSOR MICROCODE REVISIONS
===========================================================================================
----------------------+----------------------------------------------------+---------------
Filename              | Description                                        | Stepping(s)
----------------------+----------------------------------------------------+---------------
MB750654_02007006.mcb | H-0/M-0/U-0 stepping processor signature 00050654  | H-0/M-0/U-0 (Skylake Server)
MB750655_03000012.mcb | A-0         stepping processor signature 00050655  | A-0 (CascadeLake Server)
MBf50656_04003604.mcb | B-0/L-0/R-0 stepping processor signature 00050656  | B-0/L-0/R-0 (CascadeLake Server)
MBf50657_05003604.mcb | B-1/L-1/R-1 stepping processor signature 00050657  | B-1/L-1/R-1 (CascadeLake Server)
----------------------+----------------------------------------------------+---------------

===========================================================================================
                             SYSTEM FIRMWARE REQUIREMENTS/REVISIONS
===========================================================================================
BIOS Core Version                 : 5.14
BIOS Compliancy                   : UEFI 2.7.0; PI 1.6
AMI BIOS Label                    : 5.14_PurleyCrb_0ACLA060
VGA (embedded in AST2500)         : 1.08.00
Intel(R) SPS F/W (ME)             : SPS_E5_04.01.05.002.0
PTT version                       : 302.8
Intel(R) SPS F/W OEM Vendor Label : v21 (Override)
Intel(R) RC                       : 0628.P50
Intel(R) BIOS ACM                 : v1.7.54 (PW)
Intel(R) SINIT ACM                : v1.7.55 (PW)
Intel(R) RSTe PreOS Components    : v8.0.0.4006
HFI1 UEFI Driver                  : v1.9.2.0
FPK X722 GbE FW                   : LBG_B1_PHY_Auto_Detect_NCSI_LED_ACT_QCTv004_v3.45_80000B4B.bin
Lewisburg X722 GbE UEFI driver    : 2.5.07
Lewisburg X722 GbE PXE OPROM      : 1.0.66
Lewisburg X722 GbE iSCSI OPROM    : 3.1.29
EEPROM version of NVM image       : 0004
AFU version                       : v5.11.06.1854
Intel BKC Version                 : KIT #777696
QS DCPMM Module Firmware          : fw_ekvb0_1.2.0.5446_rel.bin

===========================================================================================
                             IMPORTANT INSTALLATION NOTES
===========================================================================================
WARNING:
A. It is very important to follow the flash option provided in the batch file (BIOS_efi64.nsh/
   ME_efi64.nsh for UEFI Shell, BIOS_win64.cmd/ME_win64.cmd for Windows 64 bits, BIOS_lnx64.sh/ME_lnx64.sh for Linux 64 bits). 
   Using incorrect flash option to flash BIOS may cause damage to your system.

B. After BIOS S5BH3B10, system will not support DCPMM(or AEP) DIMM firmware 01.00.00.4707(BKC WW17) or earlier version.
   Please update your DCPMM firmware to BKC WW20 or later before flashing BIOS S5BH3B10 or later.

C. Please update to the corresponding version of BIOS prior to the update of the DCPMM FW.

1. Burn S5BH3Bxx.BIN via fixture

2. For UEFI  Shell environment, follow below steps to update BIOS:
   (1) Unzip the release package to the same folder in a HDD or USB Flash Drive.
   (2) Insert the USB Flash Drive or HDD mentioned in step (1).
   (3) Power on the system and boot into "Build-in EFI Shell"
   (4) Execute batch file BIOS_efi64.nsh to update BIOS.
   (5) Execute batch file ME_efi64.nsh to update ME FW.
   (6) After the update finished, reboot the system, the new BIOS/ME FW runs.
   (7) Enter BIOS setup, press <F9> to load default and save before any test run.
 
3. For x64 Windows environment, follow below steps to update BIOS:
   (1) Power on the system and boot into Windows OS.
   (2) Unzip the release package to the same folder in the HDD.
   (3) Open Command Prompt, change to the folder with release package located.
   (4) Execute batch file BIOS_win64.cmd to update BIOS.
   (5) Execute batch file ME_win64.cmd to update ME FW.
   (6) After the update finished, reboot the system, the new BIOS/ME FW runs.
   (7) Enter BIOS setup, press <F9> to load default and save before any test run.
   
4. For x64 Linux environment, follow below steps to update BIOS:
   (1) Power on the system and boot into Linux OS.
   (2) Unzip the release package to the same folder in the HDD.
   (3) Open Terminal, change to the folder with release package located.
   (4) Type "chmod -R 777 *" to change privilege for all files and folders.
   (5) Execute batch file BIOS_lnx64.sh to update BIOS.
   (6) Execute batch file ME_lnx64.sh to update ME FW.
   (7) After the update finished, reboot the system, the new BIOS/ME FW runs.
   (8) Enter BIOS setup, press <F9> to load default and save before any test run.
   
5. If update BIOS from version before 3A10.HXX (include 3A10.HXX) to S5BH3Bxx, please use fixture to udpate or
   BIOS package update to S5BH3B13.H01 first and then update to later version. Since in S5BH3B13.H01 package, afu update script added parameter /X,
   that will skip ROM ID check. If /X is not added, update from 3A10.HXX or older versions to S5BH3B13.H01 will fail because ROM ID had changed.

6. It is not recommended to downgrade CLX BIOS (S5BH3BXX) to SKX BIOS (3A10.HXX) since SKX BIOS can't support CLX CPU.
   If you have to downgrade to SKX BIOS (3A10.HXX), please use fixture to update or follow the steps as below
   (1) Confirm you are using SKX CPU
   (2) Copy BIOS 3A10.HXX image to S5BH3BXX BIOS relates package folder which can support parameter /RLC:E updating entire BIOS region.
   (3) add parameter "/X" to skip ROM ID check when update BIOS 3A10.HXX via AFU tool.
   ex. In x64 Linux environment, "./afulnx64\Afulnx_64 3A10.HXX.BIN /P /B /K /N /L /X /RLC:E
       In UEFI Shell environment, "afuefi64\AfuEfi64.efi 3A10.HXX.BIN /P /B /K /N /L /X /RLC:E
       In x64 Windows environment, "afuwin64\afuwinx64.exe 3A10.HXX.BIN /P /B /K /N /L /X /RLC:E

Note:
- Before BMC 3.62, it may have 'PHY MAC restore to default'/'PHY become busy under OS' by inband/outband YAFUFLASH flash BIOS.
- After BMC 4.22, please use BIOS *.enc file to update BIOS by BMC outband support.
- BIOS_efi64.nsh/BIOS_win64.cmd/BIOS_lnx64.sh updates BIOS region only.
- ME_efi64.nsh/ME_win64.cmd/ME_lnx64.sh updates non-BIOS regions (include 10GbE/ME/PDR ...).
- AFUDOS tool is no longer supported, we provide UEFI/Windows/Linux environment tool for upgrade firmware.
- This BIOS already enable Security Flash feature, please make sure the BIOS image signed when you want upgrade it.
  Or it will report security check fail then upgrade fail.
- Please make sure the PHY ID match with the current system run NVM image, or X722 device will only left one and can't work.
- BIOS has support PLDM function to keep the setting after flashing BIOS, please confirm updated parameters include "/N /CLRCFG",
  if need to back to the default setting.
  ex. In x64 Linux environment, after BIOS_lnx64.sh execution for BIOS udpated, "./afulnx64\Afulnx_64 S5BH3Bxx.BIN /N /CLRCFG" to load default.
      In UEFI Shell enviro5nment, after BIOS_efi64.nsh execution for BIOS udpated, "afuefi64\AfuEfi64.efi S5BH3Bxx.BIN /N /CLRCFG" to load default.
      In x64 Windows environment, after BIOS_win64.cmd execution for BIOS udpated, "afuwin64\afuwinx64.exe S5BH3Bxx.BIN /N /CLRCFG" to load default.
- The Lewisburg X722 controller use 40 GbE driver, the ctrl+S function was removed after UEFI driver 1.6.20 version.
- BIOS will not support to update Lewisburg X722 NVM image in AFU updating process.
  Please use "NVM update tool" to update this image manually in OS.
- POST error "CMOS/NVRAM configuration cleared" will not present in POST screen due to multi-default setting, but it will be logged into SEL.
- Configuration rules related with DCPMM "must be followed":
  1. DCPMMs of capacities, firmware and stepping must be the same.
  2. DCPMMs of firmware need matching BKC version.
  3. DCPMMs of population recommend to follow INTEL's suggest.
  4. DCPMMs controller stepping must be same. If no follow, it will result in UEFI Fatal Error “DIMM controller revision mismatch”.
  5. Each DCPMM in the system must have the same SKU(ES or QS) with respect to the operating modes and features supported.
     If the DCPMM software detects that the system is populated with DCPMM with incompatible SKUs, it will operate in read-only mode.
     In this case, it will not allow changes to the DCPMMs and their associated capacity.
- Starting from WW46 BKC, Intel do NOT validate on RHEL 7.5.
- From BIOS S5BH3B10, BIOS use the Production Worth(PW) ACM Binary and "must" use production CPU samples.
  If TXT feature with PW ACM used on a platform with engineering samples, system may reset.
- According to Intel datasheet #556488 – Intel® Optane™ DC Persistent Memory Module Firmware Interface Specification, Revision 1.13,
  if Revision Number(RN) of DCPMM firmware is updated, DCPMM cannot be downgraded to a FW version whose RN is less than present version.
  Firmware version    01.02.00.5318
                       |  |  |    +--- 4-digit Build Number
                       |  |  +-------- 2-digit Security Revision Number (SV)
                       |  +----------- 2-digit Revision Number (RN)
                       +-------------- 2-digit Product Number (PN)
- After BKC 2018WW50, ES2 firmware is no longer updating.
- Performing a full SPI chip or Direct Firmware Update downgrade to SPS_E5_04.00.04.294.0 or 
  earlier requires a full AC cycle at the end of the downgrade process.
- Starting from WW08 BKC, BIOS enabled Short ARS on boot. Please wait for ARS to complete before updating the DCPMM FW.
- After BIOS S5BH3B13.H00, start supporting redfish version 1.5.a, must also update BMC to 4.57.06 or later which can support redfish version 1.5.a.
- If user need to update both BMC and BIOS via BMC webUI, will need to update BMC FW first, then update BIOS FW. 
  That is because before BIOS update, BMC will copy BIOS current setting to BIOS future setting. 
  If update BIOS first, BMC will loss BIOS future setting after BMC finish update.
- Do not downgrade DCPMM DIMMs to a version of DCPMM FW below PV/PRQ FW 1.2.0.5355 (WW08 BKC).
  Older DCPMM FW will not be supported and DIMMs could enter an undesired state effecting usability.
- Starting from S5BH3B14.H00, must also update BMC to 4.62.06, otherwise sending inventory data via redfish might be failed.

===========================================================================================
                             KNOWN ISSUES/WORKAROUNDS
===========================================================================================  
- According to Intel security advisory, BIOS is default disabled DCI interface by SPS ME xml and BIOS setup.
  This is a notice from Intel eMOW WW08, and TXT only works when DCI disable and no ITP connected.
  Also, DCI related setup has been removed since BIOS S5BH3B10 per security concern.
  
- Because RSD feature already implemented, it will send whole SMBIOS table with all system information to BMC. At the first new configuration 
  environment, BIOS will take a lot of time to send data while boot into OS or Shell.
  
- Please notice that if you execute BIOS online upgrade script continuous twice (after flash completely then execute again).
  The PLDM module will override the BIOS default again. It's current PLDM limitation, please do not execute BIOS upgrade script continuous.

- BIOS would skip flashing Lewisburg X722 GbE region in AFU ME update, please use addiotnal Intel nvmupdate tool to update 
  Lewisburg X722 GbE region when flash BIOS by AFU tool. But using WebUI can update BIOS version and Lewisburg X722 GbE region at the same time.

- The device strings of each boot option in Setup pop-up screen are limited to one line temporarily.
  Therefore some long device strings may be cut out in the end.

- "The ROM file information does not match with the system BIOS!" warning messages will appear when using 
  AFU tool to flash BIOS with rom layout change.
  Please add "/RLC:E" parameter in AFU scripts to flash BIOS image, or press "E" if ROM layout change warning messages appear.

- BIOS cannot detect MAC address in legacy boot mode on Mellanox LAN card ConnectX-4, ConnectX-5 in IB mode.

- Cascade Lake Server Qual (Intel® Xeon® Processor Scalable Family A0) has several issues that either limit or prevent 
  some capabilities of DCPMM from being evaluated. The Intel® Optane™ DC Persistent Memory Technology Sightings Report, 
  Doc #569957, contains details on features and functionality that are known to be blocked or affected by UEFI FW, 
  DCPMM Firmware, and other parts of the software stack.

- Apache Pass in Appdirect Mode when used with Windows RS5 may go into an non-reconfigurable state. Under investigation EIP-433841 IPS-00387013.

- Since BIOS rom layout changes between 3A10.HXX to S5BH3BXX, adding parameter "/RLC:E" to flash entire BIOS region.

- BCP region used to preserve BIOS setting would be flashed through AFU update including parameter "/RLC:E".
  Therefore, when updating BIOS to CLX BIOS from SKX BIOS, BIOS setting is not able to be preserved
  since the preserved region is flashsed 

- After S5BH3B13.H00 supporting redfish 1.5.a, the system inventory data implemented method is different from old version of redfish,
  hence some data including WWPN/WWNN of FiberChannel card in system inventory data is not ready.
  Please check WWPN/WWNN in SMBIOS type 165 or check it via IPMI command as a workaround.

===========================================================================================
                             FEATURES ADDED/MODIFY
===========================================================================================
S5BH3B27.H00:
- Follow 5.14_PurleyCrb_0ACLA060 to update related modules RC0628.P50 (2023.3 IPU PV)
- Update SKX CPU H0 stepping microcode to MB750654_02007006.
- Update CLX CPU B0 stepping microcode to MBF50656_04003604.
- Update CLX CPU B1 stepping microcode to MBF50657_05003604.
- Update Intel(R) SPS F/W to SPS_E5_04_01_05_002_0.
- Implement WA for sSATA device boot option would disappear after change AHCI mode to RAID mode

S5BH3B26.H00:
- Follow 5.14_PurleyCrb_0ACLA058 to update related modules RC0626.P01 (2023.1 IPU PV)
- Update CLX CPU B0 stepping microcode to MBF50656_04003303.
- Update CLX CPU B1 stepping microcode to MBF50657_05003303.
- Update Intel(R) SPS F/W to SPS_E5_04_01_04_901_0.
- Setup modify: Hide "CAT Opportunistic Tuning" option
- Support PPR feature and unhidden BIOS PPR Type option.

S5BH3B25.H00:
- Follow 5.14_PurleyCrb_0ACLA057 to update related modules RC0623.D09 (2022.3 IPU PV)
- Update SKX CPU H0 stepping microcode to MB750654_02006E05.
- Update Intel(R) SPS F/W to SPS_E5_04_01_04_804_0.
- Follow latest Intel SPI program guide spec "intel-c620-pch-spi-program-guide-559021-rev1-3.pdf" 
  Table 4-1 to disable CPU/BIOS Write/Read Device Expansion Region.

S5BH3B24.H00:
- Follow Purley snapshot to update SMBIOS type 4 Max Speed for Skylake
- Follow 5.14_PurleyCrb_0ACLA055 to update related modules RC0618.D03 (2022.1 IPU PV)
- Update SKX CPU H0 stepping microcode to MB750654_02006d05.
- Update CLX CPU B0 stepping microcode to MBF50656_04003302.
- Update CLX CPU B1 stepping microcode to MBF50657_05003302.
- Update Intel(R) SPS F/W to SPS_E5_04_01_04_700_0.

S5BH3B23.H00:
- Update DBX binary that UEFI web posted on April 29, 2021.

S5BH3B22.H00:
- Follow 5.14_PurleyCrb_0ACLA053 to update related modules RC0612.D02 (2021.1 IPU PV)
- Update CLX CPU B0 stepping microcode to MBF50656_04003103
- Update CLX CPU B1 stepping microcode to MBF50657_05003103
- Modify option "tRFC Performance Enable" default to [Enable] for better result of performance testing.
- Update SMBIOS type 4 Max Speed for Skylake.
- Modify Security Vulnerability (CVE-2021-28211 / CVE-2021-28210 / CVE-2019-14584)
- [Redfish] Add NVMe PCIe 4.0 transfer data rate to display via redfish and fix the unit from GT/s to Gbps

S5BH3B21.H01:
- Update ME SPS_E5_04_01_04_505_0 XML file.

S5BH3B21.H00:
- Implement power cycle after SCE import with /ni parameter in PowerCyclePolicy OEM module.
- Implement latest USB2 PP1/PP2 EA settings.
- Show virtual disk info when using redfish "/redfish/v1/Systems/Self/Storage/1/Volumes"
- Update ME to SPS_E5_04_01_04_505_0 from SPS_E5_04_01_04_423_0.
- Modify riser type 1~3 of Riser 3.
- Update SKX CPU H0 stepping microcode to MB750654_02006B06.
- Update CLX CPU B0 stepping microcode to MBF50656_04003102.
- Update CLX CPU B1 stepping microcode to MBF50657_05003102.

S5BH3B20.H00:
- Display option EPP profile.
- Make bad bar work only if boot in legacy mode.
- Correct UPI corrected error threshold setup maximum to 32767

S5BH3B19.H00:
- Follow 5.14_PurleyCrb_0ACLA052 to update related modules  RC0610.D02 (2020.2 IPU PV)
- Update SKX CPU H0 stepping microcode to MB750654_02006a08.
- Update CLX CPU B0 stepping microcode to MBF50656_04003003.
- Update CLX CPU B1 stepping microcode to MBF50657_05003003.
- Update Intel(R) SPS F/W to SPS_E5_04_01_04_423_0.
- Update Intel(R) RSTe PreOS Components to v6.3.
- Update SMBIOS type 4 Max Speed for Cascadelake.
- Modify behavior of input invalid IP on IPv6 address to remain previous valid IP instead of replaced by :::::::.
- Add token to control sent Emulex Fiber Channel WWNN WWPN info to BMC
- Add multiple NICs to the blacklist.
- Follow Standard conclusion to let IPv4 related address back to previous valid address while input invalid address.
- Add Virtual Slot ID VSLOT_RISER3_ID0 back and remove VSLOT_RISER3_ID1,2,3 for SMBIOS type 9 Riser 3.

S5BH3B18.H00:
- Follow 5.14_PurleyCrb_0ACLA051 to update related modules (RC0602.D02 IPU PV)
- Implement Clearing Ppr Data Consumed bit in CMOS.
- Implement skip to check reserved IPv6 addresses.
- Improve the condition rule of getting MAC from Mellanox CX series card.
- Add new SKU "20x SAS/SATA + 4x U.2" support.
- [Redfish] Redfish MTU set it to 1400.

S5BH3B17.H01:
- Update Microcode to 02006906 for SKX H0 stepping.
- Update Microcode to 04002F01 for CLX B0 stepping.
- Update Microcode to 05002F01 for CLX B1 stepping.

S5BH3B17.H00:
- Follow 5.14_PurleyCrb_0ACLA050 to update related modules (RC0602.D02 2020.1 IPU PV)
- Update ME SPS FW to SPS_E5_04_01_04_381_0 from SPS_E5_04_01_04_339_0.
- Update Microcode to 02006901 for SKX H0 stepping.
- Update Microcode to 04002F00 for CLX B0 stepping.
- Update Microcode to 05002F00 for CLX B1 stepping.
- Update Microcode module to Microcode_273 from Microcode_267 for INTEL-SA-00329.
- Update IScsi module from label 20 to 28.
- Update for enable the case sensitive for HDD password.
- Follow SI Standard to set "Extended Type 17 Structure" as enable.
- Follow SI standard to show "Config TDP" Setup option.
- Grayout iSCSI and RAMDisk Configuration operation in user access level.
- Correct the help text string of PL1 Limit.
- Follow PCIe SPEC to check if Pcie Extended Next Capability Offset is invalid.
- [Redfish] Add x-AMI of "MCTP Bus Owner" Option (hidden option)
- [Redfish] Add x-AMI of "SNC" Option
- [Redfish] Modify "Hynix" to "SK Hynix" in SMBIOS and Redfish 
- [Redfish] Update the Subnet Mask default setting that sync from the BMC.

S5BH3B16.H01:
- Set memory correctable error threshold to 5000 and memory leaky bucket timer period to 16.11 sec.
- Make the default value FRU data in BIOS setup menu and SMBIOS be the same.

S5BH3B16.H00:
- Follow 5.14_PurleyCrb_0ACLA049 to update related modules (RC0595.D04 IPU)
- Update ME SPS FW to SPS_E5_04_01_04_339_0 from SPS_E5_04_01_04_296_0.
- Update Microcode to 02000065 for SKX H0 stepping.
- Update Microcode to 03000012 for SKX A0 stepping.
- Update Microcode to 0400002c for CLX B0 stepping.
- Update Microcode to 0500002c for CLX B1 stepping.
- Modify BIOS settings and SMBIOS type 3/8/9/41 for S5BH/S5BH_2U/S5BVH respectively.
- Add "OCP MEZZ SLOT 2(KRx4)" SMBIOS type 9 data.
- Implement GPGPU SKU support. 
- Implement GPGPU SKU new PCIe hot-plug settings.
- Implement POST error "(0xA109) FP FRU - PD Custom Field 1 not implement"
- Follow SI_Std SPEC to hide "Stale AtoS" and "LLC dead line alloc".
- Ignore hot plug IIO ports IO resource padding.
- Implement Send NVME SSD Information IPMI command to BMC.
- Add DIMM Manufacturing Location/DateCode into OEM IPMI CMD Set DIMM Information Param 7.
- Define more detail memory type on OemIPMI command.
- [Redfish] Update Redfish Host/Basic/Advanced eModules to label 12/10/10 for Redfish 1.5.c support.
- [Redfish] Move sending system inventory data to ready to boot phase.
- [Redfish] Implement setting Pwr and Perf Profile to Custom when any related setting is set to conflict with Pwr and Perf Profile via Redfish.
- [Redfish] Update x-AMI language for RC options we show in Setup.
- [RSD] Update RSD related module to 07.1.
- [RSD] Implement Send RSD provision done to BMC even if no NIC been detected on system.
- [RSD] Follow RSD SW request to modify RSD OEM type 210. (SST config)
- [RSD] Filter out PCH Root Ports from type 192/165, and correct Slot ID of type 192 for devices under PCH Root Port.

S5BH3B14.H01:
- Add retry mechanism to handle the case of redfish would be not workable when redfish connection is failed.
- Always send Redfish inventory info to BMC if it supports one-shot method.
- Use firmware version of SATA HDD for "Revision" information of "Drive" in Redfish API.

S5BH3B14.H00:
- Follow 5.14_PurleyCrb_0ACLA046_BETA to update related modules (RC0584.D01 PLR1)
- Update SKX CPU H0 stepping microcode to MB750654_0200005E.
- Update CLX CPU B0 stepping microcode to MBF50656_04000024.
- Update CLX CPU B1 stepping microcode to MBF50657_05000024.
- Update Intel(R) SPS F/W to SPS_E5_04_01_04_296_0.
- Improve the 1st boot time after BIOS upgrade with BIOS setting preserve condition.
- Implement Move BMC USB virtual CDROM disable command' from exitbootservice to POST end.
- [RSD] Modify the Socket Designation in SMBIOS Type 193.
- [Redfish] Modify "ChassisType" from "Sub Chassis" to "Sled" in BMC Redfish.
- [Redfish] Do not send DHCPv4 and DHCPv6 to BMC via Redfish.
- Disable Autonomous Core C-State to improve performance for S5BVH

S5BH3B13.H01:
- Add parameter /X /RLC:E in BIOS update script.

S5BH3B13.H00:
- Sync to 3B13 BIOS code base.
- Update to Redfish 1.5.a and use Host Interface.

S5BH3B10:
- Initial official released version.

===========================================================================================
                             FEATURES REMOVED
===========================================================================================
S5BH3B27.H00:
- N/A.

S5BH3B26.H00:
- N/A.

S5BH3B25.H00:
- N/A.

S5BH3B24.H00:
- Remove the fix of system will reboot multiple times when CPU0/CPU1 "Core Disable Bitmap(Hex)" are set to different values.

S5BH3B23.H00:
- N/A.

S5BH3B22.H00:
- N/A.

S5BH3B21.H01:
- N/A.

S5BH3B21.H00:
- N/A.

S5BH3B20.H00:
- N/A.

S5BH3B19.H00:
- N/A.

S5BH3B18.H00:
- Disable NeonCity setting that forced PCH PCIe root port 6 (1-based) present.

S5BH3B17.H01:
- N/A.

S5BH3B17.H00:
- Remove x-AMI that related with BMC LAN configuration
- Disable to send related information of SetupData.xml to redfish.

S5BH3B16.H01:
- Follow QCT to disable to send detail memory type to BMC.

S5BH3B16.H00:
- [Redfish] To gray out "Network Stack" option and remove it from Redfsih.
- [Redfish] Remove LinkStatus/SignalDetected from inventory data in NetworkPorts.
- [Redfish] Remove the CRB Asset Tag information of Inventory Storage Device.

S5BH3B14.H01:
- N/A.

S5BH3B14.H00:
- N/A.

S5BH3B13.H01:
- N/A.

S5BH3B13.H00:
- N/A.

S5BH3B10:
- N/A.

===========================================================================================
                             ISSUES FIXED
===========================================================================================
S5BH3B27.H00:
- N/A.

S5BH3B26.H00:
- Fix SATA device string below FIXED BOOT ORDER Priorities is mismatch in Legacy mode issue

S5BH3B25.H00:
- Fix #404871 Run "Hardware Security Testability Interface Test" failed.
- Fix #398283 SMASH show duplicate MAC address of E810XXVDA2G1P5 NIC card after switch BIOS to Legacy mode.(MCS ID:4519.1)
- Fix #328227 The description and Severity of ''Correctable Memory Error Logging Disabled'' and ''Correctable ECC Error Logging Limit Reached'' events are not meet event log table v4.58 definition.

S5BH3B24.H00:
- Fix #384565 that there are 2 Debian OS options shown in Boot Override after install Debian 10.11.
- Fix PPR event is not correct when bad DIMM is used in CPU1.
- Fix that PPR events will be recorded even if PPR is not executed.
- Fix system cannot boot into USB via Redfish/IPMI persistent command in first boot when MB is mounted CD/DVD.
- Fix system cannot record other non-ECC memory errors when Correctable ECC Error logging is disabled.
- Fix #387294 WebUI display duplicate MAC address of Mellanox MCX631102AC-ADAT(MCS ID:4555.1) NIC card.
- Fix #387646 SMBIOS type17 info "Type Detail" is wrong.
- Fix the "Administrator Password" help text incorrect with the full Samsung PM983 drives.
- Fix that Debian 10 boot fail when secure boot is enable.

S5BH3B23.H00:
- Fix #377997 When boot to PXE via IPMI and Boot Option#1 not set to network, it will jump over to next Boot Option, if first port cannot boot into PXE
- Fix security issues by enabling flash descriptor region Lock.

S5BH3B22.H00:
- Fix #365304 After flash with preserve by WEBUI, BIOS ''Boot override'' show UEFI: PXE/HTTP IPv4.../PXE/HTTP IPv6 information(Legacy Mode).
- Fix #366805 The F11 function key messages dispalyed 'Press <F11> to enter boot option', but it should be 'Press <F11> for BBS POPUP menu'
- Fix #367011 The BIOS item "PTT Support" was gray out and also cannot change the setting.

S5BH3B21.H01:
- Fix #368683 The BMC can't detect all temperature sensors of processor.
- Fix #368766 The BMC can't detect temperature sensors of NVMe device.

S5BH3B21.H00:
- Fix POST screen can not display "CMOS/NVRAM configuration cleared" after clear CMOS.
- Fix Riser 3 Type 2 info at S5BH_2U SMBIOS type 9 not match with the latest silkscreen.

S5BH3B20.H00:
- Fix #344128 After install RHEL8.3 with QS-3516B-R6-PD32_4G(FW 5.140.00-3319),system log has error log ''FuPluginUefi failed to add /sys/firmware/efi/esrt/entries/entry0: ESRT GUID'',
- Fix #345143 After install AEP DCPMM ,no "Intel Optane DC Persistent Memory" option in BIOS Advance page
- Fix #345192 PCIe SLOT number in SMBIOS/BIOS Boot override doesn't match silkscreen
- Fix #345572 SMBIOS Type9 Riser3 M.2 Slot is not match with Riser3 silkscreen.
- Fix If there is one "0" or two consecutive "0" within IPv6 address, the display format will be inconsistent between POST and Setup.
- Fix #341596 BIOS item "Dirty warm reset" can't switch to enable.
- Fix 3 abnormal "44975" string on setup menu issue. Fix iSCSI driver option cannot grayout by .vfr issue.
- Fix E810 don't list under Boot Override when the system is the legacy mode.
- Fix CVE-2019-14560 base on the modification provided by AMI.

S5BH3B19.H00:
- Fix #283156 Slot Designation string of SMBIOS Type 9 doesn't match HW silkscreen
- Fix #329619 When enable ''Disable Block Sid'', the password is invalid when keying correct NVME SSD Password
- Fix CurrIpmiOverLan won't be updated when GetPortFirewall status is failed.
- Fix BIOS fail to send firmware version to BMC by IPMI command.

S5BH3B18.H00:
- Fix #321628 BMC SEL record "Bus Correctable Error" during the BIOS FW flash.
- Fix #321996 When inject UCE via APEI and trigger memory disable function, it will have system hang after reset.
- Fix #322723 Stream result "Triad" value can't reach 98% of previous BIOS version Stream Triad at least.
- Fix #322138 Micron 64G dimm performance can't reach expect pass value with BIOS hyper threading disable.
- Fix #324344 "Multi Rank Sparing" is not present in AMISCE dump file when dump with prameters /lang.
- Fix Memory Topology shows incorrect Dimm size when "Memory Rank Sparing" is enabled.
- Fix system will reboot multiple times when CPU0/CPU1 "Core Disable Bitmap(Hex)" are set to different values.
- [Redfish] Fix some options need to communicate BMC can not be set via Redfish and SCE.
- [Redfish] Fix "BMC Console Redirection Enable", "BMC SOL Bits per second", and "BMC LAN Port Configuration" can not be modified by Redfish and SCE.

S5BH3B17.H01:
- N/A.

S5BH3B17.H00:
- Fix #295484, ME Altitude will not preserve after update BIOS with AFU
- Fix #313155, some error ID of PCIE correctable/uncorrectable error is 0xFF in SEL when use Keysight card to trigger.
- Fix #314280, Add DID=0x1750 case for Broadcom P2100G LAN card to get MAC address in legacy mode.
- Fix #299723, Add SAS with RAID card and use postman to enter command /redfish/v1/Systems/Self/Storage/1/Volumes get a .json file, the volume count is 0
- Fix #299697, S5BH SMBIOS type 9 strings do not match HW silverscreen.
- Fix #318037, Set ARI to Enable for NVIDIA requirements. (GPGPU SKUs)
- Fix that ProductInfo fields in setup FRU is inconsistent to others while FRU fields are empty.
- Fix CVE-2019-14575 base on the modification provided by AMI.
- Fix ipmi boot with persistent mode function fail when set the BIOS admin password. 

S5BH3B16.H01:
- Fix #307299, The system mode should changed to User after Restore Factory Keys, actually the system mode show "Deployed".
- Fix #301532, BIOS setup display "Save & Reset" string in pop-up message after pressing F1 and F10.
- Fix #259057, BIOS Setup UI will show abnormal after create VROC RAID Volume via BIOS Setup.
- Fix #302747, SCE tool can modify BIOS setting without password when BIOS is set administrator password.
- Fix #302780, There are some items can be changed via SCE without password when administrator password in BIOS setup is set.
- Fix #300111, The all items in the Network Stack Configuration will not load default after flash BIOS with /N /CLRCFG.
- Fix #308809, Using Yafuflash to flash BIOS with preserve_nvram command, SHA384 PCR Bank will not preserve.
- Fix #304364, The system MAC cannot display under dashboard of WEBUI.
- Fix #304558, The system MAC(UEFI/Legacy) cannot display via SMASH.
- Fix #301253, The "Boot mode" and "Boot Order Priorities" in BIOS setup did not load default after press F9 and system reboot.
- Fix #309736, There are two format in ACPI Table "OEM Table ID"
- Fix system cannot enter AMI Virtual CDROM after BMC mount two or more same image.
- Fix that system need to sign the driver again in Linux OS when "Secure Boot"=Enabled during BIOS update in the second time.
- Fix incorrect Scsi Device capacity in /redfish/v1/Systems/Self/Storage/1/Drives/[Device]
- Fix the reversed TPM Vendor ID name in SMBios Type 43
- Fix there is no event log in SEL for the hot removal case

S5BH3B16.H00:
- Fix #276832, The GPU ''Unidirectional P2P=Enabled Bandwidth Matrix'' test result of T4 is FAIL.
- Fix #295175, Set BIOS Correctable Error Threshold value to ''1000'' , but the BMC record Correctable ECC error log after inject few times ECC error via ITP.
- Fix #285286, Administrator Password didn't preserve successful after use YAFUFlash2 Update BIOS with Preserve)
- Fix #292234, BIOS password not preserved after update BIOS via YAFUFlash2 tool with Preserve NVRAM
- Fix #283156, Slot Designation string of SMBIOS Type 9 doesn't match HW silkscreen
- Fix #296495, Riser 3 B0 slot port will change via ITP (slot1 and 3).
- Fix #281173, Lack "(DDR4)" string in "usable memory" of Main page.
- Fix When sysyem install PCIe SSD(Intel P4510), legacy device should not show on Boot Override.
- Fix User shouldn't change iSCSI Configuration and Driver Health on BIOS Setup with user privilege.
- Fix HDD Data information is incorrect in QSM 1.8.3.5.
- Fix The riser 3 slot 1/2 information should be x8/x16 not x16/x8 via smbios.
- Fix SMBIOS type 210 information not match SMBIOS SPEC definition.
- Fix The PCIe SlotNo of Extended PCIe Error event doesn't match BIOS Boot Override display.
- Fix BIOS setup menu will show ''PCI OUT OF RESOURCES CONDITION'' message when install three of the Tesla M10 GPU card.
- Fix SecureBootSetup variable not preserved when flash BIOS with /CLRCFG.
- Fix OS boot option on USB will be treated as Hard Disk in FBO Priority.
- Fix that system hang at post code 0x92 when boot up system with HBA card.
- Fix "Contained Element Record Length" value mismatch with SMBIOS SPEC.
- Fix SMBIOS type 9 of riser will be created when no install riser.
- [Redfish] Fix PCIeDevices does not list USB device for VirtualNic in Redfish system inventory data.
- [Redfish] Fix Redfish HI settings will be preserved by PLDM after update BIOS between Redfish v1.2 and v1.5 via AFU.
- [Redfish] Fix FirmwareRevision/FirmwareApiVersion sent incorrect to BMC via Redfish
- [Redfish] Fix MemorySubsystemControllerProductID cause DMTF Redfish Service Validator fail.
- [RSD] Fix NVMe type 194 miss "Port Designation" string when SlotID is 0xFF.
- [RSD] Fix BIOS not send LLDP packet when system do RSD provision.
- [RSD] Fix RSD provision fail when set parameter UpdateMdr to true.

S5BH3B14.H01:
- Fix many zero after Device Model string in SMBIOS Type 194.
- Fix Skip retrying to send Inventory data to BMC via HI while connecting failed.
- Fix SMBIOS type42 will not be created when Redfish HI connection fail during POST.
- Fix the incorrect value of FirmwareVersion of NVMe device.
- Fix BIOS may not do Redfish communication with BMC permanently until next BIOS upgrade action.
- Fix missing Controllers item in Redfish NetworkAdapters info after AMI Redfish 1.5.a.

S5BH3B14.H00:
- Fix #242007 Memory Rank information is not match between MCS and SMBIOS table.
- Fix #271782 When set "security boot" to enable and "Factory Key Provision" to Enabled, "EFI Shell" will disappear in boot override.
- Fix #271383 When set "Enable Intel TXT" to disable , dump SMBIOS via command "dmidecode -t 196" will keep on "01" instead of "00".
- Fix #265448 The SMBIOS Type 9 record M.2 Slot , but ''PCIe Riser Interface'' did not have M.2 slot on HW SPEC.
- Fix BMC WedUI don't show any MAC address when send the seventeenth MAC to BMC.
- Fix 128GB and 256GB AEP will show rank 4 in SMBIOS type 17.
- Fix AEP rank in memory topology is not match with SMBIOS type 17.
- [Redfish] Fix the incorrect value of StatusIndicator of NVMe device.
- [Redfish] Fix VirtualNic of inventory information is not exist if no any LAN card in the system.
- Fix #272982 SM3_256 PCR Bank function will disappear in BIOS menu after BIOS load default setting.

S5BH3B13.H01:
- N/A.

S5BH3B13.H00:
- Fix Rank info show 1Rank in BIOS setup menu, but shows 4R in SMBIOS Type 17(dmidecode). (eTrack #272630)
- Fix VirtualNic of inventory information is not exist if no any LAN card in the system. (eTrack #274436, 274422 and 274378)
- Fix AEP DIMM Memory Rank information is not match between MCS and SMBIOS table. (eTrack #242007)

S5BH3B10:
- N/A.

[END OF RELEASE NOTES]
